From 0a00a6aaa846b695a7a750cf40079d56a9bb94d6 Mon Sep 17 00:00:00 2001
From: azidar
Date: Fri, 1 May 2015 11:02:46 -0700
Subject: Fixed bug where the enable was looked at for lowering MUX.

---
 test/chisel3/ModuleVec.fir | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'test/chisel3/ModuleVec.fir')

diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir
index a4617267..a53c9549 100644
--- a/test/chisel3/ModuleVec.fir
+++ b/test/chisel3/ModuleVec.fir
@@ -21,9 +21,9 @@ circuit ModuleVec :
     
     inst T_37 of PlusOne
     inst T_38 of PlusOne_25
-    wire pluses : { in : UInt<32>, flip out : UInt<32>}[2]
-    pluses[0] := Pad(T_37,?)
-    pluses[1] := Pad(T_38,?)
+    wire pluses : { flip in : UInt<32>, out : UInt<32>}[2]
+    pluses[0] := T_37
+    pluses[1] := T_38
     pluses[0].in := Pad(ins[0],?)
     outs[0] := Pad(pluses[0].out,?)
     pluses[1].in := Pad(ins[1],?)
-- 
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