diff options
| author | azidar | 2015-04-28 17:32:19 -0700 |
|---|---|---|
| committer | azidar | 2015-04-28 17:32:19 -0700 |
| commit | 1644ed195522cd7343aaaa047e6669529907de9f (patch) | |
| tree | 250d34e3bf5616e01b4629ee6497cdd1ce9647b8 /test/chisel3/MemorySearch.fir | |
| parent | d6d630e6dbe3e5dd3c335cc8bd65a81d9dcb0f5f (diff) | |
Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec.fir doesn't work because incorrecly generated?
Diffstat (limited to 'test/chisel3/MemorySearch.fir')
| -rw-r--r-- | test/chisel3/MemorySearch.fir | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/test/chisel3/MemorySearch.fir b/test/chisel3/MemorySearch.fir index a2df4671..e62f35ba 100644 --- a/test/chisel3/MemorySearch.fir +++ b/test/chisel3/MemorySearch.fir @@ -2,43 +2,43 @@ ; CHECK: Done! circuit MemorySearch : module MemorySearch : - input target : UInt(4) - output address : UInt(3) - input en : UInt(1) - output odone : UInt(1) + input target : UInt<4> + output address : UInt<3> + input en : UInt<1> + output odone : UInt<1> - node T_35 = UInt(0, 3) - reg index : UInt(3) - index.init := T_35 - node T_36 = UInt(0, 1) - node T_37 = UInt(4, 3) - node T_38 = UInt(15, 4) - node T_39 = UInt(14, 4) - node T_40 = UInt(2, 2) - node T_41 = UInt(5, 3) - node T_42 = UInt(13, 4) - wire elts : UInt(1)[7] - elts.0 := T_36 - elts.1 := T_37 - elts.2 := T_38 - elts.3 := T_39 - elts.4 := T_40 - elts.5 := T_41 - elts.6 := T_42 + node T_35 = UInt<3>(0) + reg index : UInt<3> + on-reset index := T_35 + node T_36 = UInt<1>(0) + node T_37 = UInt<3>(4) + node T_38 = UInt<4>(15) + node T_39 = UInt<4>(14) + node T_40 = UInt<2>(2) + node T_41 = UInt<3>(5) + node T_42 = UInt<4>(13) + wire elts : UInt<1>[7] + elts[0] := T_36 + elts[1] := T_37 + elts[2] := T_38 + elts[3] := T_39 + elts[4] := T_40 + elts[5] := T_41 + elts[6] := T_42 accessor elt = elts[index] node T_43 = bit-not(en) node T_44 = eq(elt, target) - node T_45 = UInt(7, 3) + node T_45 = UInt<3>(7) node T_46 = eq(index, T_45) node T_47 = bit-or(T_44, T_46) node done = bit-and(T_43, T_47) when en : - node T_48 = UInt(0, 1) + node T_48 = UInt<1>(0) index := T_48 else : node T_49 = bit-not(done) when T_49 : - node T_50 = UInt(1, 1) + node T_50 = UInt<1>(1) node T_51 = add(index, T_50) index := T_51 odone := done |