diff options
| author | azidar | 2015-04-28 17:32:19 -0700 |
|---|---|---|
| committer | azidar | 2015-04-28 17:32:19 -0700 |
| commit | 1644ed195522cd7343aaaa047e6669529907de9f (patch) | |
| tree | 250d34e3bf5616e01b4629ee6497cdd1ce9647b8 /test/chisel3/LFSR16.fir | |
| parent | d6d630e6dbe3e5dd3c335cc8bd65a81d9dcb0f5f (diff) | |
Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec.fir doesn't work because incorrecly generated?
Diffstat (limited to 'test/chisel3/LFSR16.fir')
| -rw-r--r-- | test/chisel3/LFSR16.fir | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/test/chisel3/LFSR16.fir b/test/chisel3/LFSR16.fir index a8857882..b635e4bf 100644 --- a/test/chisel3/LFSR16.fir +++ b/test/chisel3/LFSR16.fir @@ -3,12 +3,12 @@ circuit LFSR16 : module LFSR16 : - output out : UInt(16) - input inc : UInt(1) + output out : UInt<16> + input inc : UInt<1> - node T_16 = UInt(1, 16) - reg res : UInt(16) - res.init := T_16 + node T_16 = UInt<16>(1) + reg res : UInt<16> + on-reset res := T_16 when inc : node T_17 = bit(res, 0) node T_18 = bit(res, 2) |