diff options
| author | azidar | 2015-04-16 17:05:46 -0700 |
|---|---|---|
| committer | azidar | 2015-04-16 17:05:46 -0700 |
| commit | 06ff7f7dddcb479d9d4d775a55cbb18d873b35b9 (patch) | |
| tree | 5023aa9aa4e944d9b3911a8dddf43ece6f6f1455 /test/chisel3/EnableShiftRegister.fir | |
| parent | 5dfc741fd04c7fa357b976b57086d67244d3d22a (diff) | |
Updated parser to correctly read empty statements
Diffstat (limited to 'test/chisel3/EnableShiftRegister.fir')
| -rw-r--r-- | test/chisel3/EnableShiftRegister.fir | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/test/chisel3/EnableShiftRegister.fir b/test/chisel3/EnableShiftRegister.fir index aa7d36ae..732e1dbc 100644 --- a/test/chisel3/EnableShiftRegister.fir +++ b/test/chisel3/EnableShiftRegister.fir @@ -1,19 +1,21 @@ +;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s +;CHECK: To Flo circuit EnableShiftRegister : module EnableShiftRegister : input in : UInt(4) output out : UInt(4) input shift : UInt(1) - node T_14 : UInt(4) = UInt(0, 4) + node T_14 = UInt(0, 4) reg r0 : UInt(4) r0.init := T_14 - node T_15 : UInt(4) = UInt(0, 4) + node T_15 = UInt(0, 4) reg r1 : UInt(4) r1.init := T_15 - node T_16 : UInt(4) = UInt(0, 4) + node T_16 = UInt(0, 4) reg r2 : UInt(4) r2.init := T_16 - node T_17 : UInt(4) = UInt(0, 4) + node T_17 = UInt(0, 4) reg r3 : UInt(4) r3.init := T_17 when shift : @@ -21,4 +23,5 @@ circuit EnableShiftRegister : r1 := r0 r2 := r1 r3 := r2 - out := r3
\ No newline at end of file + out := r3 +;CHECK: Finished To Flo |