diff options
| author | jackbackrack | 2015-06-02 08:47:40 -0700 |
|---|---|---|
| committer | jackbackrack | 2015-06-02 08:47:40 -0700 |
| commit | b178ca42fd9d4f7b94d80c01cd810bf18da9ebc8 (patch) | |
| tree | 033e197aa2e297187e21712faf1957eb405b435b /test/chisel3/ComplexAssign.fir | |
| parent | e668a13b285c87678a708a8af5bee2cfa0f7645b (diff) | |
| parent | 8fc826a2770f46d63d8d7b1bccf14d2bf6e6b7cd (diff) | |
merge + fix trim to use correct bits operands
Diffstat (limited to 'test/chisel3/ComplexAssign.fir')
| -rw-r--r-- | test/chisel3/ComplexAssign.fir | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/test/chisel3/ComplexAssign.fir b/test/chisel3/ComplexAssign.fir new file mode 100644 index 00000000..c1dc41cd --- /dev/null +++ b/test/chisel3/ComplexAssign.fir @@ -0,0 +1,16 @@ +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +;CHECK: Done! + +circuit ComplexAssign : + module ComplexAssign : + input in : {re : UInt<10>, im : UInt<10>} + output out : {re : UInt<10>, im : UInt<10>} + input e : UInt<1> + when e : + wire T_18 : {re : UInt<10>, im : UInt<10>} + T_18 := in + out.re := T_18.re + out.im := T_18.im + else : + out.re := UInt<1>(0) + out.im := UInt<1>(0) |