From cf80ff9c83c2fedd42ec186a3e342520c89f91ab Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 26 May 2015 17:33:40 -0700
Subject: Added <>. Added additional checks for primops. Added new chisel3
 files.

---
 test/chisel3/ComplexAssign.fir | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 test/chisel3/ComplexAssign.fir

(limited to 'test/chisel3/ComplexAssign.fir')

diff --git a/test/chisel3/ComplexAssign.fir b/test/chisel3/ComplexAssign.fir
new file mode 100644
index 00000000..c1dc41cd
--- /dev/null
+++ b/test/chisel3/ComplexAssign.fir
@@ -0,0 +1,16 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit ComplexAssign : 
+  module ComplexAssign : 
+    input in : {re : UInt<10>, im : UInt<10>}
+    output out : {re : UInt<10>, im : UInt<10>}
+    input e : UInt<1>
+    when e : 
+      wire T_18 : {re : UInt<10>, im : UInt<10>}
+      T_18 := in
+      out.re := T_18.re
+      out.im := T_18.im
+    else : 
+      out.re := UInt<1>(0)
+      out.im := UInt<1>(0)
-- 
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