diff options
| author | azidar | 2015-04-16 17:05:46 -0700 |
|---|---|---|
| committer | azidar | 2015-04-16 17:05:46 -0700 |
| commit | 06ff7f7dddcb479d9d4d775a55cbb18d873b35b9 (patch) | |
| tree | 5023aa9aa4e944d9b3911a8dddf43ece6f6f1455 /test/chisel3/ComplexAssign.fir | |
| parent | 5dfc741fd04c7fa357b976b57086d67244d3d22a (diff) | |
Updated parser to correctly read empty statements
Diffstat (limited to 'test/chisel3/ComplexAssign.fir')
| -rw-r--r-- | test/chisel3/ComplexAssign.fir | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/test/chisel3/ComplexAssign.fir b/test/chisel3/ComplexAssign.fir index 2cf52370..14cb063c 100644 --- a/test/chisel3/ComplexAssign.fir +++ b/test/chisel3/ComplexAssign.fir @@ -1,15 +1,18 @@ +;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s +;CHECK: To Flo circuit ComplexAssign : module ComplexAssign : - input in : {output re : UInt(10), output im : UInt(10)} - output out : {output re : UInt(10), output im : UInt(10)} + input in : {re : UInt(10), im : UInt(10)} + output out : {re : UInt(10), im : UInt(10)} input e : UInt(1) when e : - wire T_19 : {output re : UInt(10), output im : UInt(10)} + wire T_19 : {re : UInt(10), im : UInt(10)} T_19 := in out.re := T_19.re out.im := T_19.im else : - node T_20 : UInt(1) = UInt(0, 1) + node T_20 = UInt(0, 1) out.re := T_20 - node T_21 : UInt(1) = UInt(0, 1) - out.im := T_21
\ No newline at end of file + node T_21 = UInt(0, 1) + out.im := T_21 +;CHECK: Finished To Flo |