merge + fix trim to use correct bits operands

1 files changed, 17 insertions, 0 deletions

diff --git a/test/chisel3/BundleWire.fir b/test/chisel3/BundleWire.fir
new file mode 100644
index 00000000..2c2ad772
--- /dev/null
+++ b/test/chisel3/BundleWire.fir
@@ -0,0 +1,17 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit BundleWire : 
+  module BundleWire : 
+    input in : {x : UInt<32>, y : UInt<32>}
+    output outs : {x : UInt<32>, y : UInt<32>}[4]
+    
+    wire coords : {x : UInt<32>, y : UInt<32>}[4]
+    coords[0] := in
+    outs[0] := coords[0]
+    coords[1] := in
+    outs[1] := coords[1]
+    coords[2] := in
+    outs[2] := coords[2]
+    coords[3] := in
+    outs[3] := coords[3]