diff options
| author | azidar | 2015-04-16 17:05:46 -0700 |
|---|---|---|
| committer | azidar | 2015-04-16 17:05:46 -0700 |
| commit | 06ff7f7dddcb479d9d4d775a55cbb18d873b35b9 (patch) | |
| tree | 5023aa9aa4e944d9b3911a8dddf43ece6f6f1455 /test/chisel3/BundleWire.fir | |
| parent | 5dfc741fd04c7fa357b976b57086d67244d3d22a (diff) | |
Updated parser to correctly read empty statements
Diffstat (limited to 'test/chisel3/BundleWire.fir')
| -rw-r--r-- | test/chisel3/BundleWire.fir | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/test/chisel3/BundleWire.fir b/test/chisel3/BundleWire.fir index 72d3061e..86ffa4e8 100644 --- a/test/chisel3/BundleWire.fir +++ b/test/chisel3/BundleWire.fir @@ -1,9 +1,11 @@ +;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s +;CHECK: To Flo circuit BundleWire : module BundleWire : - output in : {input y : UInt(32), input x : UInt(32)} - output outs : {output y : UInt(32), output x : UInt(32)}[4] + output in : {flip y : UInt(32), flip x : UInt(32)} + output outs : {y : UInt(32), x : UInt(32)}[4] - wire coords : {output y : UInt(32), output x : UInt(32)}[4] + wire coords : {y : UInt(32), x : UInt(32)}[4] coords.0 := in outs.0 := coords.0 coords.1 := in @@ -11,4 +13,5 @@ circuit BundleWire : coords.2 := in outs.2 := coords.2 coords.3 := in - outs.3 := coords.3
\ No newline at end of file + outs.3 := coords.3 +;CHECK: Finished To Flo |