diff options
| author | azidar | 2015-04-16 17:05:46 -0700 |
|---|---|---|
| committer | azidar | 2015-04-16 17:05:46 -0700 |
| commit | 06ff7f7dddcb479d9d4d775a55cbb18d873b35b9 (patch) | |
| tree | 5023aa9aa4e944d9b3911a8dddf43ece6f6f1455 /test/chisel3/BitsOps.fir | |
| parent | 5dfc741fd04c7fa357b976b57086d67244d3d22a (diff) | |
Updated parser to correctly read empty statements
Diffstat (limited to 'test/chisel3/BitsOps.fir')
| -rw-r--r-- | test/chisel3/BitsOps.fir | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/test/chisel3/BitsOps.fir b/test/chisel3/BitsOps.fir index 5fa56b60..7e6c260d 100644 --- a/test/chisel3/BitsOps.fir +++ b/test/chisel3/BitsOps.fir @@ -1,3 +1,5 @@ +;RUN: firrtl %s abcefghipjklmno cw | tee %s.out | FileCheck %s +;CHECK: To Flo circuit BitsOps : module BitsOps : input b : UInt(16) @@ -7,11 +9,12 @@ circuit BitsOps : output orout : UInt(16) output xorout : UInt(16) - node T_13 : UInt = bit-not(a) + node T_13 = bit-not(a) notout := T_13 - node T_14 : UInt = bit-and(a, b) + node T_14 = bit-and(a, b) andout := T_14 - node T_15 : UInt = bit-or(a, b) + node T_15 = bit-or(a, b) orout := T_15 - node T_16 : UInt = bit-xor(a, b) - xorout := T_16
\ No newline at end of file + node T_16 = bit-xor(a, b) + xorout := T_16 +;CHECK: Finished To Flo |