Remove stanza (#231)

* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)

3 files changed, 0 insertions, 96 deletions

diff --git a/test/chirrtl/infer-mport-dir.fir b/test/chirrtl/infer-mport-dir.fir
deleted file mode 100644
index 50baeff2..00000000
--- a/test/chirrtl/infer-mport-dir.fir
+++ /dev/null
@@ -1,22 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; CHECK: Done!
-circuit top :
-   module top :
-      input clk : Clock
-      wire p : UInt
-      wire q : UInt
-      cmem m : {a:UInt<4>,b:UInt<4>}[10]
-      p <= UInt(1)
-      q <= UInt(1)
-      wire x : {a:UInt<4>,b:UInt<4>}
-      x.a <= UInt(1)
-      x.b <= UInt(1)
-      when p :
-         infer mport a = m[UInt(3)],clk
-         infer mport b = m[UInt(3)],clk
-         infer mport c = m[UInt(3)],clk
-         when q :
-            a <= x
-            x <= b
-            c <= x
-            x <= c
diff --git a/test/chirrtl/mask-bug.fir b/test/chirrtl/mask-bug.fir
deleted file mode 100644
index b580c075..00000000
--- a/test/chirrtl/mask-bug.fir
+++ /dev/null
@@ -1,20 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; CHECK: Done!
-circuit top :
-   module top :
-      input clk : Clock
-      wire p : UInt
-      wire q : UInt
-      cmem m : {a:UInt<4>,b:{c: UInt<4>,d:UInt<4>}}[10]
-      p <= UInt(1)
-      q <= UInt(1)
-      wire x : {a:UInt<4>,b:{c: UInt<4>,d:UInt<4>}}
-      x.a <= UInt(1)
-      x.b.c <= UInt(1)
-      x.b.d <= UInt(1)
-      when p :
-         write mport a = m[UInt(3)],clk
-         when q :
-            a <- x
-
-
diff --git a/test/chirrtl/wacc-wdc.fir b/test/chirrtl/wacc-wdc.fir
deleted file mode 100644
index 3cb5141d..00000000
--- a/test/chirrtl/wacc-wdc.fir
+++ /dev/null
@@ -1,54 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-circuit top :
-   module top :
-      input clk : Clock
-      wire p : UInt
-      wire q : UInt
-      cmem m : {a:UInt<4>,b:UInt<4>}[10]
-      p <= UInt(1)
-      q <= UInt(1)
-      wire x : {a:UInt<4>,b:UInt<4>}
-      x.a <= UInt(1)
-      x.b <= UInt(1)
-      when p :
-         write mport a = m[UInt(3)],clk
-         when q :
-            a <= x
-
-
-; CHECK: Remove CHIRRTL
-
-; CHECK: circuit top :
-; CHECK:    module top :
-; CHECK:       input clk : Clock
-; CHECK:       wire p : UInt
-; CHECK:       wire q : UInt
-; CHECK:       mem m :          
-; CHECK:          data-type => { a : UInt<4>,  b : UInt<4>}
-; CHECK:          depth => 10
-; CHECK:          write-latency => 1
-; CHECK:          read-latency => 0
-; CHECK:          writer => a
-; CHECK:       m.a.addr is invalid
-; CHECK:       m.a.clk <= clk
-; CHECK:       m.a.en <= UInt<1>("h0")
-; CHECK:       m.a.data is invalid
-; CHECK:       m.a.mask.a <= UInt<1>("h0")
-; CHECK:       m.a.mask.b <= UInt<1>("h0")
-; CHECK:       p <= UInt<1>("h1")
-; CHECK:       q <= UInt<1>("h1")
-; CHECK:       wire x : { a : UInt<4>,  b : UInt<4>}
-; CHECK:       x.a <= UInt<1>("h1")
-; CHECK:       x.b <= UInt<1>("h1")
-; CHECK:       when p :
-; CHECK:          m.a.addr <= UInt<2>("h3")
-; CHECK:          m.a.en <= UInt<1>("h1")
-; CHECK:          when q :
-; CHECK:             m.a.data <= x
-; CHECK:             m.a.mask.a <= UInt<1>("h1")
-; CHECK:             m.a.mask.b <= UInt<1>("h1")   
-
-; CHECK: Finished Remove CHIRRTL
-; CHECK: Done!
-
-