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authorDavid Biancolin2021-10-18 11:18:31 -0700
committerGitHub2021-10-18 11:18:31 -0700
commit1796f37ee36d722df71bd3f580cee9d01be6f4e9 (patch)
tree1f9394fda9fbb132f1bb09d9d9bb69884308f25a /src
parentef1d27a84addc46353884eb06ea18f4c68e6a808 (diff)
Favor os-lib write.over in WriteEmitted (#2389)
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/stage/phases/WriteEmitted.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/stage/phases/WriteEmitted.scala b/src/main/scala/firrtl/stage/phases/WriteEmitted.scala
index 90b0e123..647921d5 100644
--- a/src/main/scala/firrtl/stage/phases/WriteEmitted.scala
+++ b/src/main/scala/firrtl/stage/phases/WriteEmitted.scala
@@ -45,13 +45,13 @@ class WriteEmitted extends Phase {
annotations.flatMap {
case a: EmittedModuleAnnotation[_] =>
val target = FileUtils.getPath(sopts.getBuildFileName(a.value.name, Some(a.value.outputSuffix)))
- os.write(target, a.value.value)
+ os.write.over(target, a.value.value)
None
case a: EmittedCircuitAnnotation[_] =>
val target = FileUtils.getPath(
sopts.getBuildFileName(fopts.outputFileName.getOrElse(a.value.name), Some(a.value.outputSuffix))
)
- os.write(target, a.value.value)
+ os.write.over(target, a.value.value)
None
case a => Some(a)
}