From 1796f37ee36d722df71bd3f580cee9d01be6f4e9 Mon Sep 17 00:00:00 2001
From: David Biancolin
Date: Mon, 18 Oct 2021 11:18:31 -0700
Subject: Favor os-lib write.over in WriteEmitted (#2389)

---
 src/main/scala/firrtl/stage/phases/WriteEmitted.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/stage/phases/WriteEmitted.scala b/src/main/scala/firrtl/stage/phases/WriteEmitted.scala
index 90b0e123..647921d5 100644
--- a/src/main/scala/firrtl/stage/phases/WriteEmitted.scala
+++ b/src/main/scala/firrtl/stage/phases/WriteEmitted.scala
@@ -45,13 +45,13 @@ class WriteEmitted extends Phase {
     annotations.flatMap {
       case a: EmittedModuleAnnotation[_] =>
         val target = FileUtils.getPath(sopts.getBuildFileName(a.value.name, Some(a.value.outputSuffix)))
-        os.write(target, a.value.value)
+        os.write.over(target, a.value.value)
         None
       case a: EmittedCircuitAnnotation[_] =>
         val target = FileUtils.getPath(
           sopts.getBuildFileName(fopts.outputFileName.getOrElse(a.value.name), Some(a.value.outputSuffix))
         )
-        os.write(target, a.value.value)
+        os.write.over(target, a.value.value)
         None
       case a => Some(a)
     }
-- 
cgit v1.2.3