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authorchick2020-08-14 19:47:53 -0700
committerJack Koenig2020-08-14 19:47:53 -0700
commit6fc742bfaf5ee508a34189400a1a7dbffe3f1cac (patch)
tree2ed103ee80b0fba613c88a66af854ae9952610ce /src/test/scala/firrtlTests/execution/VerilogExecution.scala
parentb516293f703c4de86397862fee1897aded2ae140 (diff)
All of src/ formatted with scalafmt
Diffstat (limited to 'src/test/scala/firrtlTests/execution/VerilogExecution.scala')
-rw-r--r--src/test/scala/firrtlTests/execution/VerilogExecution.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/execution/VerilogExecution.scala b/src/test/scala/firrtlTests/execution/VerilogExecution.scala
index 89f27609..913cfc71 100644
--- a/src/test/scala/firrtlTests/execution/VerilogExecution.scala
+++ b/src/test/scala/firrtlTests/execution/VerilogExecution.scala
@@ -30,7 +30,7 @@ trait VerilogExecution extends TestExecution {
// Make and run Verilog simulation
verilogToCpp(c.main, testDir, Nil, harness) #&&
- cppToExe(c.main, testDir) ! loggingProcessLogger
+ cppToExe(c.main, testDir) ! loggingProcessLogger
assert(executeExpectingSuccess(c.main, testDir))
}
}