All of src/ formatted with scalafmt

4 files changed, 20 insertions, 22 deletions

diff --git a/src/test/scala/firrtlTests/execution/ExecutionTestHelper.scala b/src/test/scala/firrtlTests/execution/ExecutionTestHelper.scala
index 7d250664..0a50e53e 100644
--- a/src/test/scala/firrtlTests/execution/ExecutionTestHelper.scala
+++ b/src/test/scala/firrtlTests/execution/ExecutionTestHelper.scala
@@ -31,18 +31,18 @@ object ExecutionTestHelper {
 
     // Generate test step counter, create ExecutionTestHelper that represents initial test state
     val cnt = DefRegister(NoInfo, DUTRules.counter.name, counterType, DUTRules.clock, DUTRules.reset, Utils.zero)
-    val inc = Connect(NoInfo, DUTRules.counter, DoPrim(PrimOps.Add, Seq(DUTRules.counter, UIntLiteral(1)), Nil, UnknownType))
+    val inc =
+      Connect(NoInfo, DUTRules.counter, DoPrim(PrimOps.Add, Seq(DUTRules.counter, UIntLiteral(1)), Nil, UnknownType))
     ExecutionTestHelper(c, Seq(cnt, inc), Map.empty[Expression, Expression], Nil, Nil)
   }
 }
 
 case class ExecutionTestHelper(
-  dut: Circuit,
-  setup: Seq[Statement],
-  pokeRegs: Map[Expression, Expression],
+  dut:            Circuit,
+  setup:          Seq[Statement],
+  pokeRegs:       Map[Expression, Expression],
   completedSteps: Seq[Conditionally],
-  activeStep: Seq[Statement]
-) {
+  activeStep:     Seq[Statement]) {
 
   def step(n: Int): ExecutionTestHelper = {
     require(n > 0, "Step length must be positive")
@@ -52,9 +52,7 @@ case class ExecutionTestHelper(
   def poke(expString: String, value: Literal): ExecutionTestHelper = {
     val pokeExp = ParseExpression(expString)
     val pokeable = ensurePokeable(pokeExp)
-    pokeable.addStatements(
-      Connect(NoInfo, pokeExp, value),
-      Connect(NoInfo, pokeable.pokeRegs(pokeExp), value))
+    pokeable.addStatements(Connect(NoInfo, pokeExp, value), Connect(NoInfo, pokeable.pokeRegs(pokeExp), value))
   }
 
   def invalidate(expString: String): ExecutionTestHelper = {
@@ -85,7 +83,7 @@ case class ExecutionTestHelper(
   }
 
   private def top: Module = {
-    dut.modules.collectFirst({ case m: Module if m.name == dut.main  => m }).get
+    dut.modules.collectFirst({ case m: Module if m.name == dut.main => m }).get
   }
 
   private[execution] def emit: Circuit = {
diff --git a/src/test/scala/firrtlTests/execution/ParserHelpers.scala b/src/test/scala/firrtlTests/execution/ParserHelpers.scala
index 3472c19c..1f74d634 100644
--- a/src/test/scala/firrtlTests/execution/ParserHelpers.scala
+++ b/src/test/scala/firrtlTests/execution/ParserHelpers.scala
@@ -14,10 +14,10 @@ object ParseStatement {
     val indent = "    "
     val indented = stmtStr.split("\n").mkString(indent, s"\n${indent}", "")
     s"""circuit ${DUTRules.dutName} :
-         |  module ${DUTRules.dutName} :
-         |    input clock : Clock
-         |    input reset : UInt<1>
-         |${indented}""".stripMargin
+       |  module ${DUTRules.dutName} :
+       |    input clock : Clock
+       |    input reset : UInt<1>
+       |${indented}""".stripMargin
   }
 
   private def parse(stmtStr: String): Circuit = {
diff --git a/src/test/scala/firrtlTests/execution/SimpleExecutionTest.scala b/src/test/scala/firrtlTests/execution/SimpleExecutionTest.scala
index 2654f476..911f7485 100644
--- a/src/test/scala/firrtlTests/execution/SimpleExecutionTest.scala
+++ b/src/test/scala/firrtlTests/execution/SimpleExecutionTest.scala
@@ -20,19 +20,19 @@ trait TestExecution {
 
 /**
   * A class that makes it easier to write execution-driven tests.
-  * 
+  *
   * By combining a DUT body (supplied as a string without an enclosing
   * module or circuit) with a sequence of test operations, an
   * executable, self-contained Verilog testbench may be automatically
   * created and checked.
-  * 
+  *
   * @note It is necessary to mix in a trait extending TestExecution
   * @note The DUT has two implicit ports, "clock" and "reset"
   * @note Execution of the command sequences begins after reset is deasserted
-  * 
+  *
   * @see [[firrtlTests.execution.TestExecution]]
   * @see [[firrtlTests.execution.VerilogExecution]]
-  * 
+  *
   * @example {{{
   * class AndTester extends SimpleExecutionTest with VerilogExecution {
   *   val body = "reg r : UInt<32>, clock with: (reset => (reset, UInt<32>(0)))"
@@ -64,9 +64,9 @@ abstract class SimpleExecutionTest extends FirrtlPropSpec {
   def commands: Seq[SimpleTestCommand]
 
   private def interpretCommand(eth: ExecutionTestHelper, cmd: SimpleTestCommand) = cmd match {
-    case Step(n) => eth.step(n)
-    case Invalidate(expStr) => eth.invalidate(expStr)
-    case Poke(expStr, value) => eth.poke(expStr, UIntLiteral(value))
+    case Step(n)               => eth.step(n)
+    case Invalidate(expStr)    => eth.invalidate(expStr)
+    case Poke(expStr, value)   => eth.poke(expStr, UIntLiteral(value))
     case Expect(expStr, value) => eth.expect(expStr, UIntLiteral(value))
   }
 
diff --git a/src/test/scala/firrtlTests/execution/VerilogExecution.scala b/src/test/scala/firrtlTests/execution/VerilogExecution.scala
index 89f27609..913cfc71 100644
--- a/src/test/scala/firrtlTests/execution/VerilogExecution.scala
+++ b/src/test/scala/firrtlTests/execution/VerilogExecution.scala
@@ -30,7 +30,7 @@ trait VerilogExecution extends TestExecution {
 
     // Make and run Verilog simulation
     verilogToCpp(c.main, testDir, Nil, harness) #&&
-    cppToExe(c.main, testDir) ! loggingProcessLogger
+      cppToExe(c.main, testDir) ! loggingProcessLogger
     assert(executeExpectingSuccess(c.main, testDir))
   }
 }