From 6fc742bfaf5ee508a34189400a1a7dbffe3f1cac Mon Sep 17 00:00:00 2001
From: chick
Date: Fri, 14 Aug 2020 19:47:53 -0700
Subject: All of src/ formatted with scalafmt

---
 src/test/scala/firrtlTests/execution/VerilogExecution.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/test/scala/firrtlTests/execution/VerilogExecution.scala')

diff --git a/src/test/scala/firrtlTests/execution/VerilogExecution.scala b/src/test/scala/firrtlTests/execution/VerilogExecution.scala
index 89f27609..913cfc71 100644
--- a/src/test/scala/firrtlTests/execution/VerilogExecution.scala
+++ b/src/test/scala/firrtlTests/execution/VerilogExecution.scala
@@ -30,7 +30,7 @@ trait VerilogExecution extends TestExecution {
 
     // Make and run Verilog simulation
     verilogToCpp(c.main, testDir, Nil, harness) #&&
-    cppToExe(c.main, testDir) ! loggingProcessLogger
+      cppToExe(c.main, testDir) ! loggingProcessLogger
     assert(executeExpectingSuccess(c.main, testDir))
   }
 }
-- 
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