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| author | Albert Magyar | 2019-10-01 14:16:58 -0700 |
|---|---|---|
| committer | GitHub | 2019-10-01 14:16:58 -0700 |
| commit | 1ced6cf929b436380364e9b893e8de7edc3205fd (patch) | |
| tree | c0998198ebc9036308754826ffb863e43259f3fa /src/test/scala/firrtlTests/ExtModuleTests.scala | |
| parent | 4ca2b859473e0a88723463eac2821cfbd3249c43 (diff) | |
| parent | 082bc994457cc5f6780b58fb914a6ab3eb8a021f (diff) | |
Merge pull request #1183 from freechipsproject/mem-read-under-write
Implement read-first memory behavior in Verilog
Diffstat (limited to 'src/test/scala/firrtlTests/ExtModuleTests.scala')
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