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| author | Albert Magyar | 2019-09-12 17:06:01 -0700 |
|---|---|---|
| committer | Albert Magyar | 2019-09-30 16:22:01 -0700 |
| commit | 082bc994457cc5f6780b58fb914a6ab3eb8a021f (patch) | |
| tree | c0998198ebc9036308754826ffb863e43259f3fa /src/test/scala/firrtlTests/ExtModuleTests.scala | |
| parent | 01399dd00ba18b1e4d5c1f773ca33f077c53c534 (diff) | |
Implement read-first memories in VerilogMemDelays
* Corrects behavior under write collisions
* Avoids heavily refactoring pass
Diffstat (limited to 'src/test/scala/firrtlTests/ExtModuleTests.scala')
0 files changed, 0 insertions, 0 deletions