Merge pull request #1183 from freechipsproject/mem-read-under-write

Implement read-first memory behavior in Verilog

2 files changed, 64 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/ProtoBufSpec.scala b/src/test/scala/firrtlTests/ProtoBufSpec.scala
index 2f347c6d..7f41fb26 100644
--- a/src/test/scala/firrtlTests/ProtoBufSpec.scala
+++ b/src/test/scala/firrtlTests/ProtoBufSpec.scala
@@ -176,6 +176,21 @@ class ProtoBufSpec extends FirrtlFlatSpec {
     oldCMem should equal (cmem)
   }
 
+  // readunderwrite support
+  it should "support readunderwrite parameters" in {
+    val m1 = DefMemory(NoInfo, "m", UIntType(IntWidth(8)), 128, 1, 1, List("r"), List("w"), Nil, ir.ReadUnderWrite.Old)
+    FromProto.convert(ToProto.convert(m1).head.build) should equal (m1)
+
+    val m2 = m1.copy(readUnderWrite = ir.ReadUnderWrite.New)
+    FromProto.convert(ToProto.convert(m2).head.build) should equal (m2)
+
+    val cm1 = CDefMemory(NoInfo, "m", UIntType(IntWidth(8)), 128, true, ir.ReadUnderWrite.Old)
+    FromProto.convert(ToProto.convert(cm1).head.build) should equal (cm1)
+
+    val cm2 = cm1.copy(readUnderWrite = ir.ReadUnderWrite.New)
+    FromProto.convert(ToProto.convert(cm2).head.build) should equal (cm2)
+  }
+
   it should "support AsyncResetTypes" in {
     val port = ir.Port(ir.NoInfo, "reset", ir.Input, ir.AsyncResetType)
     FromProto.convert(ToProto.convert(port).build) should equal (port)
diff --git a/src/test/scala/firrtlTests/VerilogMemDelaySpec.scala b/src/test/scala/firrtlTests/VerilogMemDelaySpec.scala
index 405f5ab5..e7f27d0e 100644
--- a/src/test/scala/firrtlTests/VerilogMemDelaySpec.scala
+++ b/src/test/scala/firrtlTests/VerilogMemDelaySpec.scala
@@ -49,4 +49,53 @@ class VerilogMemDelaySpec extends FreeSpec with Matchers {
     CheckHighForm.run(result2)
     //result.circuit.serialize.length > 0 should be (true)
   }
+
+  "Using a read-first memory should be allowed in VerilogMemDelays" in {
+    val input =
+      """
+        |circuit Test :
+        |  module Test :
+        |    input clock : Clock
+        |    input waddr : UInt<5>
+        |    input wdata : UInt<32>
+        |    input raddr : UInt<5>
+        |    input rw_wen : UInt<1>
+        |    output rdata : UInt<32>
+        |    output rw_rdata : UInt<32>
+        |    mem m :
+        |      data-type => UInt<32>
+        |      depth => 32
+        |      read-latency => 1
+        |      write-latency => 1
+        |      read-under-write => old
+        |      reader => read
+        |      writer => write
+        |      readwriter => rw
+        |    m.read.clk <= clock
+        |    m.read.en <= UInt<1>(1)
+        |    m.read.addr <= raddr
+        |    rdata <= m.read.data
+        |
+        |    m.write.clk <= clock
+        |    m.write.en <= UInt<1>(1)
+        |    m.write.mask <= UInt<1>(1)
+        |    m.write.addr <= waddr
+        |    m.write.data <= wdata
+        |
+        |    m.rw.clk <= clock
+        |    m.rw.en <= UInt<1>(1)
+        |    m.rw.wmode <= rw_wen
+        |    m.rw.wmask <= UInt<1>(1)
+        |    m.rw.addr <= waddr
+        |    m.rw.wdata <= wdata
+        |    rw_rdata <= m.rw.rdata
+      """.stripMargin
+
+    val circuit = Parser.parse(input)
+    val compiler = new LowFirrtlCompiler
+
+    val result = compiler.compile(CircuitState(circuit, ChirrtlForm), Seq.empty)
+    val result2 = VerilogMemDelays.run(result.circuit)
+    CheckHighForm.run(result2)
+  }
 }