Clk2clock - rename the implicit "clk" module input "clock" (#387)

* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.

* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.

1 files changed, 5 insertions, 5 deletions

diff --git a/src/test/resources/features/Printf.fir b/src/test/resources/features/Printf.fir
index a19e2493..5e065b9c 100644
--- a/src/test/resources/features/Printf.fir
+++ b/src/test/resources/features/Printf.fir
@@ -1,17 +1,17 @@
 ; See LICENSE for license details.
 circuit Printf : 
   module Printf : 
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
-    reg count : UInt<10>, clk with :
+    reg count : UInt<10>, clock with :
       reset => (reset, UInt<6>(0))
-    reg const : UInt<32> clk with :
+    reg const : UInt<32> clock with :
       reset => (reset, UInt(123456))
 
     node notReset = not(reset)
     count <= add(count, UInt(1))
-    printf(clk, notReset, "\tcount = %d 0x%x b%b\\\'%d%%\'\n", count, count, count, const)
+    printf(clock, notReset, "\tcount = %d 0x%x b%b\\\'%d%%\'\n", count, count, count, const)
 
     when eq(count, UInt(255)) :
-      stop(clk, UInt(1), 0)
+      stop(clock, UInt(1), 0)