Clk2clock - rename the implicit "clk" module input "clock" (#387)

* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.

* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.

1 files changed, 4 insertions, 4 deletions

diff --git a/src/test/resources/features/NestedSubAccessTester.fir b/src/test/resources/features/NestedSubAccessTester.fir
index c40da6a0..84b4cfbe 100644
--- a/src/test/resources/features/NestedSubAccessTester.fir
+++ b/src/test/resources/features/NestedSubAccessTester.fir
@@ -12,7 +12,7 @@ circuit NestedSubAccessTester :
     out <= vec[foo[index]]
 
   module NestedSubAccessTester :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     inst dut of NestedSubAccess
@@ -22,9 +22,9 @@ circuit NestedSubAccessTester :
     dut.foo[2] <= UInt(1)
 
     when neq(dut.out, UInt(4)) :
-      printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-      stop(clk, not(reset), 1)
+      printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+      stop(clock, not(reset), 1)
     else :
-      stop(clk, not(reset), 0)
+      stop(clock, not(reset), 0)