Clk2clock - rename the implicit "clk" module input "clock" (#387)

* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.

* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.

1 files changed, 4 insertions, 4 deletions

diff --git a/src/test/resources/blackboxes/RenamedExtModuleTester.fir b/src/test/resources/blackboxes/RenamedExtModuleTester.fir
index 9e807813..37338c9f 100644
--- a/src/test/resources/blackboxes/RenamedExtModuleTester.fir
+++ b/src/test/resources/blackboxes/RenamedExtModuleTester.fir
@@ -7,7 +7,7 @@ circuit RenamedExtModuleTester :
     defname = SimpleExtModule
 
   module RenamedExtModuleTester :
-    input clk : Clock
+    input clock : Clock
     input reset : UInt<1>
 
     inst dut of ThisIsJustTheFirrtlName
@@ -16,8 +16,8 @@ circuit RenamedExtModuleTester :
 
     when not(reset) :
       when neq(dut.bar, UInt(1234)) :
-        printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
-        stop(clk, not(reset), 1)
+        printf(clock, not(reset), "Assertion failed\nTest Failed!\n")
+        stop(clock, not(reset), 1)
       else :
-        stop(clk, not(reset), 0)
+        stop(clock, not(reset), 0)