diff options
| author | azidar | 2015-07-06 17:45:44 -0700 |
|---|---|---|
| committer | azidar | 2015-07-14 11:29:55 -0700 |
| commit | 3c8f283b445ca99d4ed4c1e04e2bc8bdcdbd72f6 (patch) | |
| tree | bf659befff5521bc51a6e1a3ec5ef72fb52310c5 /notes | |
| parent | 68f7ac42d01c88bcc0c77c919587618673658c76 (diff) | |
Added chisel feedback to firrtl spec. Datapath_new triggers too large a width error
Diffstat (limited to 'notes')
| -rw-r--r-- | notes/chisel-feedback-7.6.15.txt | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/notes/chisel-feedback-7.6.15.txt b/notes/chisel-feedback-7.6.15.txt new file mode 100644 index 00000000..5f5bc8cc --- /dev/null +++ b/notes/chisel-feedback-7.6.15.txt @@ -0,0 +1,8 @@ +Firrtl spec feedback + +add limited support for zero width wires? + +Add more explanation for what types of passes +spec of what chisel3/firrtl whole compiler toolchain looks like + +Why is verilog generation unreadable and slow for chisel 2.0? |