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Diffstat (limited to 'notes/chisel-feedback-7.6.15.txt')
| -rw-r--r-- | notes/chisel-feedback-7.6.15.txt | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/notes/chisel-feedback-7.6.15.txt b/notes/chisel-feedback-7.6.15.txt new file mode 100644 index 00000000..5f5bc8cc --- /dev/null +++ b/notes/chisel-feedback-7.6.15.txt @@ -0,0 +1,8 @@ +Firrtl spec feedback + +add limited support for zero width wires? + +Add more explanation for what types of passes +spec of what chisel3/firrtl whole compiler toolchain looks like + +Why is verilog generation unreadable and slow for chisel 2.0? |