From 3c8f283b445ca99d4ed4c1e04e2bc8bdcdbd72f6 Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 6 Jul 2015 17:45:44 -0700
Subject: Added chisel feedback to firrtl spec. Datapath_new triggers too large
 a width error

---
 notes/chisel-feedback-7.6.15.txt | 8 ++++++++
 1 file changed, 8 insertions(+)
 create mode 100644 notes/chisel-feedback-7.6.15.txt

(limited to 'notes')

diff --git a/notes/chisel-feedback-7.6.15.txt b/notes/chisel-feedback-7.6.15.txt
new file mode 100644
index 00000000..5f5bc8cc
--- /dev/null
+++ b/notes/chisel-feedback-7.6.15.txt
@@ -0,0 +1,8 @@
+Firrtl spec feedback
+
+add limited support for zero width wires?
+
+Add more explanation for what types of passes
+spec of what chisel3/firrtl whole compiler toolchain looks like
+
+Why is verilog generation unreadable and slow for chisel 2.0?
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