76 files changed, 0 insertions, 58136 deletions

diff --git a/cc3200/hal/adc.c b/cc3200/hal/adc.c
deleted file mode 100644
index 23d219e1d..000000000
--- a/cc3200/hal/adc.c
+++ /dev/null
@@ -1,692 +0,0 @@
-//*****************************************************************************
-//
-//  adc.c
-//
-//  Driver for the ADC module.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup ADC_Analog_to_Digital_Converter_api
-//! @{
-//
-//*****************************************************************************
-#include "inc/hw_types.h"
-#include "inc/hw_memmap.h"
-#include "inc/hw_ints.h"
-#include "inc/hw_adc.h"
-#include "inc/hw_apps_config.h"
-#include "interrupt.h"
-#include "adc.h"
-
-
-//*****************************************************************************
-//
-//! Enables the ADC
-//!
-//! \param ulBase is the base address of the ADC
-//!
-//! This function sets the ADC global enable
-//!
-//! \return None.
-//
-//*****************************************************************************
-void ADCEnable(unsigned long ulBase)
-{
-  //
-  // Set the global enable bit in the control register.
-  //
-  HWREG(ulBase + ADC_O_ADC_CTRL) |= 0x1;
-}
-
-//*****************************************************************************
-//
-//! Disable the ADC
-//!
-//! \param ulBase is the base address of the ADC
-//!
-//! This function clears the ADC global enable
-//!
-//! \return None.
-//
-//*****************************************************************************
-void ADCDisable(unsigned long ulBase)
-{
-  //
-  // Clear the global enable bit in the control register.
-  //
-  HWREG(ulBase + ADC_O_ADC_CTRL) &= ~0x1 ;
-}
-
-//*****************************************************************************
-//
-//! Enables specified ADC channel
-//!
-//! \param ulBase is the base address of the ADC
-//! \param ulChannel is one of the valid ADC channels
-//!
-//! This function enables specified ADC channel and configures the
-//! pin as analog pin.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void ADCChannelEnable(unsigned long ulBase, unsigned long ulChannel)
-{
-  unsigned long ulCh;
-
-  ulCh =  (ulChannel == ADC_CH_0)? 0x02 :
-          (ulChannel == ADC_CH_1)? 0x04 :
-          (ulChannel == ADC_CH_2)? 0x08 : 0x10;
-
-  HWREG(ulBase + ADC_O_ADC_CH_ENABLE) |= ulCh;
-}
-
-//*****************************************************************************
-//
-//! Disables specified ADC channel
-//!
-//! \param ulBase is the base address of the ADC
-//! \param ulChannel is one of the valid ADC channelsber
-//!
-//! This function disables specified ADC channel.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void ADCChannelDisable(unsigned long ulBase, unsigned long ulChannel)
-{
-  unsigned long ulCh;
-
-  ulCh =  (ulChannel == ADC_CH_0)? 0x02 :
-          (ulChannel == ADC_CH_1)? 0x04 :
-          (ulChannel == ADC_CH_2)? 0x08 : 0x10;
-
-  HWREG(ulBase + ADC_O_ADC_CH_ENABLE) &= ~ulCh;
-}
-
-//*****************************************************************************
-//
-//! Enables and registers ADC interrupt handler for specified channel
-//!
-//! \param ulBase is the base address of the ADC
-//! \param ulChannel is one of the valid ADC channels
-//! \param pfnHandler is a pointer to the function to be called when the
-//! ADC channel interrupt occurs.
-//!
-//! This function enables and registers ADC interrupt handler for specified
-//! channel. Individual interrupt for each channel should be enabled using
-//! \sa ADCIntEnable(). It is the interrupt handler's responsibility to clear
-//! the interrupt source.
-//!
-//! The parameter \e ulChannel should be one of the following
-//!
-//! - \b ADC_CH_0 for channel 0
-//! - \b ADC_CH_1 for channel 1
-//! - \b ADC_CH_2 for channel 2
-//! - \b ADC_CH_3 for channel 3
-//!
-//! \return None.
-//
-//*****************************************************************************
-void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel,
-                    void (*pfnHandler)(void))
-{
-  unsigned long ulIntNo;
-
-  //
-  // Get the interrupt number associted with the specified channel
-  //
-  ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 :
-            (ulChannel == ADC_CH_1)? INT_ADCCH1 :
-            (ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3;
-
-  //
-  // Register the interrupt handler
-  //
-  IntRegister(ulIntNo,pfnHandler);
-
-  //
-  // Enable ADC interrupt
-  //
-  IntEnable(ulIntNo);
-}
-
-
-//*****************************************************************************
-//
-//! Disables and unregisters ADC interrupt handler for specified channel
-//!
-//! \param ulBase is the base address of the ADC
-//! \param ulChannel is one of the valid ADC channels
-//!
-//! This function disables and unregisters ADC interrupt handler for specified
-//! channel. This function also masks off the interrupt in the interrupt
-//! controller so that the interrupt handler no longer is called.
-//!
-//! The parameter \e ulChannel should be one of the following
-//!
-//! - \b ADC_CH_0 for channel 0
-//! - \b ADC_CH_1 for channel 1
-//! - \b ADC_CH_2 for channel 2
-//! - \b ADC_CH_3 for channel 3
-//!
-//! \return None.
-//
-//*****************************************************************************
-void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel)
-{
-  unsigned long ulIntNo;
-
-  //
-  // Get the interrupt number associted with the specified channel
-  //
-  ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 :
-            (ulChannel == ADC_CH_1)? INT_ADCCH1 :
-            (ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3;
-
-  //
-  // Disable ADC interrupt
-  //
-  IntDisable(ulIntNo);
-
-  //
-  // Unregister the interrupt handler
-  //
-  IntUnregister(ulIntNo);
-}
-
-//*****************************************************************************
-//
-//! Enables individual interrupt sources for specified channel
-//!
-//!
-//! \param ulBase is the base address of the ADC
-//! \param ulChannel is one of the valid ADC channels
-//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
-//!
-//! This function enables the indicated ADC interrupt sources.  Only the
-//! sources that are enabled can be reflected to the processor interrupt;
-//! disabled sources have no effect on the processor.
-//!
-//! The parameter \e ulChannel should be one of the following
-//!
-//! - \b ADC_CH_0 for channel 0
-//! - \b ADC_CH_1 for channel 1
-//! - \b ADC_CH_2 for channel 2
-//! - \b ADC_CH_3 for channel 3
-//!
-//! The \e ulIntFlags parameter is the logical OR of any of the following:
-//! - \b ADC_DMA_DONE for DMA done
-//! - \b ADC_FIFO_OVERFLOW for FIFO over flow
-//! - \b ADC_FIFO_UNDERFLOW for FIFO under flow
-//! - \b ADC_FIFO_EMPTY for FIFO empty
-//! - \b ADC_FIFO_FULL for FIFO full
-//!
-//! \return None.
-//
-//*****************************************************************************
-void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel,
-                  unsigned long ulIntFlags)
-{
-  unsigned long ulOffset;
-  unsigned long ulDmaMsk;
-
-  //
-  // Enable DMA Done interrupt
-  //
-  if(ulIntFlags & ADC_DMA_DONE)
-  {
-     ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
-                (ulChannel == ADC_CH_1)?0x00002000:
-                (ulChannel == ADC_CH_2)?0x00004000:0x00008000;
-
-     HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk;
-  }
-
-  ulIntFlags = ulIntFlags &  0x0F;
-  //
-  // Get the interrupt enable register offset for specified channel
-  //
-  ulOffset = ADC_O_adc_ch0_irq_en + ulChannel;
-
-  //
-  // Unmask the specified interrupts
-  //
-  HWREG(ulBase + ulOffset) |= (ulIntFlags & 0xf);
-}
-
-
-//*****************************************************************************
-//
-//! Disables individual interrupt sources for specified channel
-//!
-//!
-//! \param ulBase is the base address of the ADC.
-//! \param ulChannel is one of the valid ADC channels
-//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
-//!
-//! This function disables the indicated ADC interrupt sources.  Only the
-//! sources that are enabled can be reflected to the processor interrupt;
-//! disabled sources have no effect on the processor.
-//!
-//! The parameters\e ulIntFlags and \e ulChannel should be as explained in
-//! ADCIntEnable().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel,
-                  unsigned long ulIntFlags)
-{
-  unsigned long ulOffset;
-  unsigned long ulDmaMsk;
-
-  //
-  // Disable DMA Done interrupt
-  //
-  if(ulIntFlags & ADC_DMA_DONE)
-  {
-     ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
-                (ulChannel == ADC_CH_1)?0x00002000:
-                (ulChannel == ADC_CH_2)?0x00004000:0x00008000;
-
-     HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk;
-  }
-
-  //
-  // Get the interrupt enable register offset for specified channel
-  //
-  ulOffset = ADC_O_adc_ch0_irq_en + ulChannel;
-
-  //
-  // Unmask the specified interrupts
-  //
-  HWREG(ulBase + ulOffset) &= ~ulIntFlags;
-}
-
-
-//*****************************************************************************
-//
-//! Gets the current channel interrupt status
-//!
-//! \param ulBase is the base address of the ADC
-//! \param ulChannel is one of the valid ADC channels
-//!
-//! This function returns the interrupt status of the specified ADC channel.
-//!
-//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable().
-//!
-//! \return Return the ADC channel interrupt status,  enumerated as a bit
-//! field of values described in ADCIntEnable()
-//
-//*****************************************************************************
-unsigned long ADCIntStatus(unsigned long ulBase, unsigned long ulChannel)
-{
-  unsigned long ulOffset;
-  unsigned long ulDmaMsk;
-  unsigned long ulIntStatus;
-
-  //
-  // Get DMA Done interrupt status
-  //
-  ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
-            (ulChannel == ADC_CH_1)?0x00002000:
-            (ulChannel == ADC_CH_2)?0x00004000:0x00008000;
-
-  ulIntStatus = HWREG(APPS_CONFIG_BASE +
-                     APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED)& ulDmaMsk;
-
-
-  //
-  // Get the interrupt enable register offset for specified channel
-  //
-  ulOffset = ADC_O_adc_ch0_irq_status + ulChannel;
-
-  //
-  // Read ADC interrupt status
-  //
-  ulIntStatus |= HWREG(ulBase + ulOffset) & 0xf;
-
-  //
-  // Return the current interrupt status
-  //
-  return(ulIntStatus);
-}
-
-
-//*****************************************************************************
-//
-//! Clears the current channel interrupt sources
-//!
-//! \param ulBase is the base address of the ADC
-//! \param ulChannel is one of the valid ADC channels
-//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
-//!
-//! This function clears individual interrupt source for the specified
-//! ADC channel.
-//!
-//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void ADCIntClear(unsigned long ulBase, unsigned long ulChannel,
-                  unsigned long ulIntFlags)
-{
-  unsigned long ulOffset;
-  unsigned long ulDmaMsk;
-
-  //
-  // Clear DMA Done interrupt
-  //
-  if(ulIntFlags & ADC_DMA_DONE)
-  {
-     ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
-                (ulChannel == ADC_CH_1)?0x00002000:
-                (ulChannel == ADC_CH_2)?0x00004000:0x00008000;
-
-     HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk;
-  }
-
-  //
-  // Get the interrupt enable register offset for specified channel
-  //
-  ulOffset = ADC_O_adc_ch0_irq_status + ulChannel;
-
-  //
-  // Clear the specified interrupts
-  //
-  HWREG(ulBase + ulOffset) = (ulIntFlags & ~(ADC_DMA_DONE));
-}
-
-//*****************************************************************************
-//
-//! Enables the ADC DMA operation for specified channel
-//!
-//! \param ulBase is the base address of the ADC
-//! \param ulChannel is one of the valid ADC channels
-//!
-//! This function enables the DMA operation for specified ADC channel
-//!
-//! The parameter \e ulChannel should be one of the following
-//!
-//! - \b ADC_CH_0 for channel 0
-//! - \b ADC_CH_1 for channel 1
-//! - \b ADC_CH_2 for channel 2
-//! - \b ADC_CH_3 for channel 3
-//!
-//! \return None.
-//
-//*****************************************************************************
-void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel)
-{
-  unsigned long ulBitMask;
-
-  //
-  // Get the bit mask for enabling DMA for specified channel
-  //
-  ulBitMask = (ulChannel == ADC_CH_0)?0x01:
-              (ulChannel == ADC_CH_1)?0x04:
-              (ulChannel == ADC_CH_2)?0x10:0x40;
-
-  //
-  // Enable DMA request for the specified channel
-  //
-  HWREG(ulBase + ADC_O_adc_dma_mode_en) |= ulBitMask;
-}
-
-//*****************************************************************************
-//
-//! Disables the ADC DMA operation for specified channel
-//!
-//! \param ulBase is the base address of the ADC
-//! \param ulChannel is one of the valid ADC channels
-//!
-//! This function disables the DMA operation for specified ADC channel
-//!
-//! The parameter \e ulChannel should be one of the following
-//!
-//! - \b ADC_CH_0 for channel 0
-//! - \b ADC_CH_1 for channel 1
-//! - \b ADC_CH_2 for channel 2
-//! - \b ADC_CH_3 for channel 3
-//!
-//! \return None.
-//
-//*****************************************************************************
-void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel)
-{
-  unsigned long ulBitMask;
-
-  //
-  // Get the bit mask for disabling DMA for specified channel
-  //
-  ulBitMask = (ulChannel == ADC_CH_0)?0x01:
-              (ulChannel == ADC_CH_1)?0x04:
-              (ulChannel == ADC_CH_2)?0x10:0x40;
-
-  //
-  // Disable DMA request for the specified channel
-  //
-  HWREG(ulBase + ADC_O_adc_dma_mode_en) &= ~ulBitMask;
-}
-
-//*****************************************************************************
-//
-//! Configures the ADC internal timer
-//!
-//! \param ulBase is the base address of the ADC
-//! \param ulValue is wrap arround value of the timer
-//!
-//! This function Configures the ADC internal timer. The ADC timer is a 17 bit
-//! used to timestamp the ADC data samples internally.
-//! User can read the timestamp along with the sample from the FIFO register(s).
-//! Each sample in the FIFO contains 14 bit actual data and 18 bit timestamp
-//!
-//! The parameter \e ulValue can take any value between 0 - 2^17
-//!
-//! \returns None.
-//
-//*****************************************************************************
-void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue)
-{
-  unsigned long ulReg;
-
-  //
-  // Read the currrent config
-  //
-  ulReg =  HWREG(ulBase + ADC_O_adc_timer_configuration);
-
-  //
-  // Mask and set timer count field
-  //
-  ulReg = ((ulReg & ~0x1FFFF) | (ulValue & 0x1FFFF));
-
-  //
-  // Set the timer count value
-  //
-  HWREG(ulBase + ADC_O_adc_timer_configuration) = ulReg;
-}
-
-//*****************************************************************************
-//
-//! Resets ADC internal timer
-//!
-//! \param ulBase is the base address of the ADC
-//!
-//! This function resets 17-bit ADC internal timer
-//!
-//! \returns None.
-//
-//*****************************************************************************
-void ADCTimerReset(unsigned long ulBase)
-{
-  //
-  // Reset the timer
-  //
-  HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 24);
-}
-
-//*****************************************************************************
-//
-//! Enables ADC internal timer
-//!
-//! \param ulBase is the base address of the ADC
-//!
-//! This function enables 17-bit ADC internal timer
-//!
-//! \returns None.
-//
-//*****************************************************************************
-void ADCTimerEnable(unsigned long ulBase)
-{
-  //
-  // Enable the timer
-  //
-  HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 25);
-}
-
-//*****************************************************************************
-//
-//! Disables ADC internal timer
-//!
-//! \param ulBase is the base address of the ADC
-//!
-//! This function disables 17-bit ADC internal timer
-//!
-//! \returns None.
-//
-//*****************************************************************************
-void ADCTimerDisable(unsigned long ulBase)
-{
-  //
-  // Disable the timer
-  //
-  HWREG(ulBase + ADC_O_adc_timer_configuration) &= ~(1 << 25);
-}
-
-//*****************************************************************************
-//
-//! Gets the current value of ADC internal timer
-//!
-//! \param ulBase is the base address of the ADC
-//!
-//! This function the current value of 17-bit ADC internal timer
-//!
-//! \returns Return the current value of ADC internal timer.
-//
-//*****************************************************************************
-unsigned long ADCTimerValueGet(unsigned long ulBase)
-{
-  return(HWREG(ulBase + ADC_O_adc_timer_current_count));
-}
-
-//*****************************************************************************
-//
-//! Gets the current FIFO level for specified ADC channel
-//!
-//! \param ulBase is the base address of the ADC
-//! \param ulChannel is one of the valid ADC channels.
-//!
-//! This function returns the current FIFO level for specified ADC channel.
-//!
-//! The parameter \e ulChannel should be one of the following
-//!
-//! - \b ADC_CH_0 for channel 0
-//! - \b ADC_CH_1 for channel 1
-//! - \b ADC_CH_2 for channel 2
-//! - \b ADC_CH_3 for channel 3
-//!
-//! \returns Return the current FIFO level for specified channel
-//
-//*****************************************************************************
-unsigned char ADCFIFOLvlGet(unsigned long ulBase, unsigned long ulChannel)
-{
-  unsigned long ulOffset;
-
-  //
-  // Get the fifo level register offset for specified channel
-  //
-  ulOffset = ADC_O_adc_ch0_fifo_lvl + ulChannel;
-
-  //
-  // Return FIFO level
-  //
-  return(HWREG(ulBase + ulOffset) & 0x7);
-}
-
-//*****************************************************************************
-//
-//! Reads FIFO for specified ADC channel
-//!
-//! \param ulBase is the base address of the ADC
-//! \param ulChannel is one of the valid ADC channels.
-//!
-//! This function returns one data sample from the channel fifo as specified by
-//! \e ulChannel parameter.
-//!
-//! The parameter \e ulChannel should be one of the following
-//!
-//! - \b ADC_CH_0 for channel 0
-//! - \b ADC_CH_1 for channel 1
-//! - \b ADC_CH_2 for channel 2
-//! - \b ADC_CH_3 for channel 3
-//!
-//! \returns Return one data sample from the channel fifo.
-//
-//*****************************************************************************
-unsigned long ADCFIFORead(unsigned long ulBase, unsigned long ulChannel)
-{
-  unsigned long ulOffset;
-
-  //
-  // Get the fifo register offset for specified channel
-  //
-  ulOffset = ADC_O_channel0FIFODATA + ulChannel;
-
-  //
-  // Return FIFO level
-  //
-  return(HWREG(ulBase + ulOffset));
-}
-
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
diff --git a/cc3200/hal/adc.h b/cc3200/hal/adc.h
deleted file mode 100644
index 03e0ea52c..000000000
--- a/cc3200/hal/adc.h
+++ /dev/null
@@ -1,117 +0,0 @@
-//*****************************************************************************
-//
-//  adc.h
-//
-//  Defines and Macros for the ADC.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __ADC_H__
-#define __ADC_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-// Values that can be passed to APIs as ulChannel parameter
-//*****************************************************************************
-#define ADC_CH_0   0x00000000
-#define ADC_CH_1   0x00000008
-#define ADC_CH_2   0x00000010
-#define ADC_CH_3   0x00000018
-
-
-//*****************************************************************************
-//
-// Values that can be passed to ADCIntEnable(), ADCIntDisable()
-// and ADCIntClear() as ulIntFlags, and returned from ADCIntStatus()
-//
-//*****************************************************************************
-#define ADC_DMA_DONE        0x00000010
-#define ADC_FIFO_OVERFLOW   0x00000008
-#define ADC_FIFO_UNDERFLOW  0x00000004
-#define ADC_FIFO_EMPTY      0x00000002
-#define ADC_FIFO_FULL       0x00000001
-
-
-//*****************************************************************************
-//
-// API Function prototypes
-//
-//*****************************************************************************
-extern void ADCEnable(unsigned long ulBase);
-extern void ADCDisable(unsigned long ulBase);
-extern void ADCChannelEnable(unsigned long ulBase,unsigned long ulChannel);
-extern void ADCChannelDisable(unsigned long ulBase,unsigned long ulChannel);
-extern void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel,
-                    void (*pfnHandler)(void));
-extern void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel);
-extern void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel,
-                  unsigned long ulIntFlags);
-extern void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel,
-                  unsigned long ulIntFlags);
-extern unsigned long ADCIntStatus(unsigned long ulBase,unsigned long ulChannel);
-extern void ADCIntClear(unsigned long ulBase, unsigned long ulChannel,
-                  unsigned long ulIntFlags);
-extern void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel);
-extern void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel);
-extern void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue);
-extern void ADCTimerEnable(unsigned long ulBase);
-extern void ADCTimerDisable(unsigned long ulBase);
-extern void ADCTimerReset(unsigned long ulBase);
-extern unsigned long ADCTimerValueGet(unsigned long ulBase);
-extern unsigned char ADCFIFOLvlGet(unsigned long ulBase,
-                                   unsigned long ulChannel);
-extern unsigned long ADCFIFORead(unsigned long ulBase,
-                                   unsigned long ulChannel);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __ADC_H__
-
diff --git a/cc3200/hal/aes.c b/cc3200/hal/aes.c
deleted file mode 100644
index e0e129ef5..000000000
--- a/cc3200/hal/aes.c
+++ /dev/null
@@ -1,1360 +0,0 @@
-//*****************************************************************************

-//

-//  aes.c

-//

-//  Driver for the AES module.

-//

-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/

-//

-//

-//  Redistribution and use in source and binary forms, with or without

-//  modification, are permitted provided that the following conditions

-//  are met:

-//

-//    Redistributions of source code must retain the above copyright

-//    notice, this list of conditions and the following disclaimer.

-//

-//    Redistributions in binary form must reproduce the above copyright

-//    notice, this list of conditions and the following disclaimer in the

-//    documentation and/or other materials provided with the

-//    distribution.

-//

-//    Neither the name of Texas Instruments Incorporated nor the names of

-//    its contributors may be used to endorse or promote products derived

-//    from this software without specific prior written permission.

-//

-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-//

-//*****************************************************************************

-

-//*****************************************************************************

-//

-//! \addtogroup AES_Advanced_Encryption_Standard_api

-//! @{

-//

-//*****************************************************************************

-

-#include <stdbool.h>

-#include <stdint.h>

-#include "inc/hw_aes.h"

-#include "inc/hw_dthe.h"

-#include "inc/hw_ints.h"

-#include "inc/hw_memmap.h"

-#include "inc/hw_nvic.h"

-#include "inc/hw_types.h"

-#include "aes.h"

-#include "debug.h"

-#include "interrupt.h"

-

-#define AES_BLOCK_SIZE_IN_BYTES 16

-

-//*****************************************************************************

-//

-//! Configures the AES module.

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param ui32Config is the configuration of the AES module.

-//!

-//! This function configures the AES module based on the specified parameters.

-//! It does not change any DMA- or interrupt-related parameters.

-//!

-//! The ui32Config parameter is a bit-wise OR of a number of configuration

-//! flags. The valid flags are grouped based on their function.

-//!

-//! The direction of the operation is specified with only of following flags:

-//!

-//! - \b AES_CFG_DIR_ENCRYPT - Encryption mode

-//! - \b AES_CFG_DIR_DECRYPT - Decryption mode

-//!

-//! The key size is specified with only one of the following flags:

-//!

-//! - \b AES_CFG_KEY_SIZE_128BIT - Key size of 128 bits

-//! - \b AES_CFG_KEY_SIZE_192BIT - Key size of 192 bits

-//! - \b AES_CFG_KEY_SIZE_256BIT - Key size of 256 bits

-//!

-//! The mode of operation is specified with only one of the following flags.

-//!

-//! - \b AES_CFG_MODE_ECB - Electronic codebook mode

-//! - \b AES_CFG_MODE_CBC - Cipher-block chaining mode

-//! - \b AES_CFG_MODE_CFB - Cipher feedback mode

-//! - \b AES_CFG_MODE_CTR - Counter mode

-//! - \b AES_CFG_MODE_ICM - Integer counter mode

-//! - \b AES_CFG_MODE_XTS - Ciphertext stealing mode

-//! - \b AES_CFG_MODE_XTS_TWEAKJL - XEX-based tweaked-codebook mode with

-//! ciphertext stealing with previous/intermediate tweak value and j loaded

-//! - \b AES_CFG_MODE_XTS_K2IJL - XEX-based tweaked-codebook mode with

-//! ciphertext stealing with key2, i and j loaded

-//! - \b AES_CFG_MODE_XTS_K2ILJ0 - XEX-based tweaked-codebook mode with

-//! ciphertext stealing with key2 and i loaded, j = 0

-//! - \b AES_CFG_MODE_F8 - F8 mode

-//! - \b AES_CFG_MODE_F9 - F9 mode

-//! - \b AES_CFG_MODE_CBCMAC - Cipher block chaining message authentication

-//! code mode

-//! - \b AES_CFG_MODE_GCM - Galois/counter mode

-//! - \b AES_CFG_MODE_GCM_HLY0ZERO - Galois/counter mode with GHASH with H

-//! loaded and Y0-encrypted forced to zero

-//! - \b AES_CFG_MODE_GCM_HLY0CALC - Galois/counter mode with GHASH with H

-//! loaded and Y0-encrypted calculated internally

-//! - \b AES_CFG_MODE_GCM_HY0CALC - Galois/Counter mode with autonomous GHASH

-//! (both H and Y0-encrypted calculated internally)

-//! - \b AES_CFG_MODE_CCM - Counter with CBC-MAC mode

-//!

-//! The following defines are used to specify the counter width.  It is only

-//! required to be defined when using CTR, CCM, or GCM modes, only one of the

-//! following defines must be used to specify the counter width length:

-//!

-//! - \b AES_CFG_CTR_WIDTH_32 - Counter is 32 bits

-//! - \b AES_CFG_CTR_WIDTH_64 - Counter is 64 bits

-//! - \b AES_CFG_CTR_WIDTH_96 - Counter is 96 bits

-//! - \b AES_CFG_CTR_WIDTH_128 - Counter is 128 bits

-//!

-//! Only one of the following defines must be used to specify the length field

-//! for CCM operations (L):

-//!

-//! - \b AES_CFG_CCM_L_2 - 2 bytes

-//! - \b AES_CFG_CCM_L_4 - 4 bytes

-//! - \b AES_CFG_CCM_L_8 - 8 bytes

-//!

-//! Only one of the following defines must be used to specify the length of the

-//! authentication field for CCM operations (M) through the \e ui32Config

-//! argument in the AESConfigSet() function:

-//!

-//! - \b AES_CFG_CCM_M_4 - 4 bytes

-//! - \b AES_CFG_CCM_M_6 - 6 bytes

-//! - \b AES_CFG_CCM_M_8 - 8 bytes

-//! - \b AES_CFG_CCM_M_10 - 10 bytes

-//! - \b AES_CFG_CCM_M_12 - 12 bytes

-//! - \b AES_CFG_CCM_M_14 - 14 bytes

-//! - \b AES_CFG_CCM_M_16 - 16 bytes

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-AESConfigSet(uint32_t ui32Base, uint32_t ui32Config)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-    ASSERT((ui32Config & AES_CFG_DIR_ENCRYPT) ||

-           (ui32Config & AES_CFG_DIR_DECRYPT));

-    ASSERT((ui32Config & AES_CFG_KEY_SIZE_128BIT) ||

-           (ui32Config & AES_CFG_KEY_SIZE_192BIT) ||

-           (ui32Config & AES_CFG_KEY_SIZE_256BIT));

-    ASSERT((ui32Config & AES_CFG_MODE_ECB) ||

-           (ui32Config & AES_CFG_MODE_CBC) ||

-           (ui32Config & AES_CFG_MODE_CTR) ||

-           (ui32Config & AES_CFG_MODE_ICM) ||

-           (ui32Config & AES_CFG_MODE_CFB) ||

-           (ui32Config & AES_CFG_MODE_XTS_TWEAKJL) ||

-           (ui32Config & AES_CFG_MODE_XTS_K2IJL) ||

-           (ui32Config & AES_CFG_MODE_XTS_K2ILJ0) ||

-           (ui32Config & AES_CFG_MODE_F8) ||

-           (ui32Config & AES_CFG_MODE_F9) ||

-           (ui32Config & AES_CFG_MODE_CTR) ||

-           (ui32Config & AES_CFG_MODE_CBCMAC) ||

-           (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) ||

-           (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) ||

-           (ui32Config & AES_CFG_MODE_GCM_HY0CALC) ||

-           (ui32Config & AES_CFG_MODE_CCM));

-    ASSERT(((ui32Config & AES_CFG_MODE_CTR) ||

-            (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) ||

-            (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) ||

-            (ui32Config & AES_CFG_MODE_GCM_HY0CALC) ||

-            (ui32Config & AES_CFG_MODE_CCM)) &&

-           ((ui32Config & AES_CFG_CTR_WIDTH_32) ||

-            (ui32Config & AES_CFG_CTR_WIDTH_64) ||

-            (ui32Config & AES_CFG_CTR_WIDTH_96) ||

-            (ui32Config & AES_CFG_CTR_WIDTH_128)));

-    ASSERT((ui32Config & AES_CFG_MODE_CCM) &&

-           ((ui32Config & AES_CFG_CCM_L_2) ||

-            (ui32Config & AES_CFG_CCM_L_4) ||

-            (ui32Config & AES_CFG_CCM_L_8)) &&

-           ((ui32Config & AES_CFG_CCM_M_4) ||

-            (ui32Config & AES_CFG_CCM_M_6) ||

-            (ui32Config & AES_CFG_CCM_M_8) ||

-            (ui32Config & AES_CFG_CCM_M_10) ||

-            (ui32Config & AES_CFG_CCM_M_12) ||

-            (ui32Config & AES_CFG_CCM_M_14) ||

-            (ui32Config & AES_CFG_CCM_M_16)));

-

-    //

-    // Backup the save context field before updating the register.

-    //

-    if(HWREG(ui32Base + AES_O_CTRL) & AES_CTRL_SAVE_CONTEXT)

-    {

-        ui32Config |= AES_CTRL_SAVE_CONTEXT;

-    }

-

-    //

-    // Write the CTRL register with the new value

-    //

-    HWREG(ui32Base + AES_O_CTRL) = ui32Config;

-}

-

-//*****************************************************************************

-//

-//! Writes the key 1 configuration registers, which are used for encryption or

-//! decryption.

-//!

-//! \param ui32Base is the base address for the AES module.

-//! \param pui8Key is an array of bytes, containing the key to be

-//! configured.  The least significant word in the 0th index.

-//! \param ui32Keysize is the size of the key, which must be one of the

-//! following values:  \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or

-//! \b AES_CFG_KEY_SIZE_256.

-//!

-//! This function writes key 1 configuration registers based on the key

-//! size.  This function is used in all modes.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-AESKey1Set(uint32_t ui32Base, uint8_t *pui8Key, uint32_t ui32Keysize)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-    ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) ||

-           (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) ||

-           (ui32Keysize == AES_CFG_KEY_SIZE_256BIT));

-

-    //

-    // With all key sizes, the first 4 words are written.

-    //

-    HWREG(ui32Base + AES_O_KEY1_0) = * ((uint32_t *)(pui8Key + 0));

-    HWREG(ui32Base + AES_O_KEY1_1) = * ((uint32_t *)(pui8Key + 4));

-    HWREG(ui32Base + AES_O_KEY1_2) = * ((uint32_t *)(pui8Key + 8));

-    HWREG(ui32Base + AES_O_KEY1_3) = * ((uint32_t *)(pui8Key + 12));

-

-    //

-    // The key is 192 or 256 bits.  Write the next 2 words.

-    //

-    if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT)

-    {

-        HWREG(ui32Base + AES_O_KEY1_4) = * ((uint32_t *)(pui8Key + 16));

-        HWREG(ui32Base + AES_O_KEY1_5) = * ((uint32_t *)(pui8Key + 20));

-    }

-

-    //

-    // The key is 256 bits.  Write the last 2 words.

-    //

-    if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT)

-    {

-        HWREG(ui32Base + AES_O_KEY1_6) = * ((uint32_t *)(pui8Key + 24));

-        HWREG(ui32Base + AES_O_KEY1_7) = * ((uint32_t *)(pui8Key + 28));

-    }

-}

-

-//*****************************************************************************

-//

-//! Writes the key 2 configuration registers, which are used for encryption or

-//! decryption.

-//!

-//! \param ui32Base is the base address for the AES module.

-//! \param pui8Key is an array of bytes, containing the key to be

-//! configured.  The least significant word in the 0th index.

-//! \param ui32Keysize is the size of the key, which must be one of the

-//! following values:  \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or

-//! \b AES_CFG_KEY_SIZE_256.

-//!

-//! This function writes the key 2 configuration registers based on the key

-//! size.  This function is used in the F8, F9, XTS, CCM, and CBC-MAC modes.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-AESKey2Set(uint32_t ui32Base, uint8_t *pui8Key, uint32_t ui32Keysize)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-    ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) ||

-           (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) ||

-           (ui32Keysize == AES_CFG_KEY_SIZE_256BIT));

-

-    //

-    // With all key sizes, the first 4 words are written.

-    //

-    HWREG(ui32Base + AES_O_KEY2_0) = * ((uint32_t *)(pui8Key + 0));

-    HWREG(ui32Base + AES_O_KEY2_1) = * ((uint32_t *)(pui8Key + 4));

-    HWREG(ui32Base + AES_O_KEY2_2) = * ((uint32_t *)(pui8Key + 8));

-    HWREG(ui32Base + AES_O_KEY2_3) = * ((uint32_t *)(pui8Key + 12));

-

-    //

-    // The key is 192 or 256 bits.  Write the next 2 words.

-    //

-    if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT)

-    {

-        HWREG(ui32Base + AES_O_KEY2_4) = * ((uint32_t *)(pui8Key + 16));

-        HWREG(ui32Base + AES_O_KEY2_5) = * ((uint32_t *)(pui8Key + 20));

-    }

-

-    //

-    // The key is 256 bits.  Write the last 2 words.

-    //

-    if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT)

-    {

-        HWREG(ui32Base + AES_O_KEY2_6) = * ((uint32_t *)(pui8Key + 24));

-        HWREG(ui32Base + AES_O_KEY2_7) = * ((uint32_t *)(pui8Key + 28));

-    }

-}

-

-//*****************************************************************************

-//

-//! Writes key 3 configuration registers, which are used for encryption or

-//! decryption.

-//!

-//! \param ui32Base is the base address for the AES module.

-//! \param pui8Key is a pointer to an array bytes, containing

-//! the key to be configured. The least significant word is in the 0th index.

-//!

-//! This function writes the key 2 configuration registers with key 3 data

-//! used in CBC-MAC and F8 modes.  This key is always 128 bits.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-AESKey3Set(uint32_t ui32Base, uint8_t *pui8Key)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-

-    //

-    // Write the key into the upper 4 key registers

-    //

-    HWREG(ui32Base + AES_O_KEY2_4) = * ((uint32_t *)(pui8Key + 0));

-    HWREG(ui32Base + AES_O_KEY2_5) = * ((uint32_t *)(pui8Key + 4));

-    HWREG(ui32Base + AES_O_KEY2_6) = * ((uint32_t *)(pui8Key + 8));

-    HWREG(ui32Base + AES_O_KEY2_7) = * ((uint32_t *)(pui8Key + 12));

-}

-

-//*****************************************************************************

-//

-//! Writes the Initial Vector (IV) register, needed in some of the AES Modes.

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param pui8IVdata is an array of 16 bytes (128 bits), containing the IV

-//! value to be configured. The least significant word is in the 0th index.

-//!

-//! This functions writes the initial vector registers in the AES module.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-AESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-

-    //

-    // Write the initial vector registers.

-    //

-    HWREG(ui32Base + AES_O_IV_IN_0) = *((uint32_t *)(pui8IVdata+0));

-    HWREG(ui32Base + AES_O_IV_IN_1) = *((uint32_t *)(pui8IVdata+4));

-    HWREG(ui32Base + AES_O_IV_IN_2) = *((uint32_t *)(pui8IVdata+8));

-    HWREG(ui32Base + AES_O_IV_IN_3) = *((uint32_t *)(pui8IVdata+12));

-}

-

-

-//*****************************************************************************

-//

-//! Reads the Initial Vector (IV) register, needed in some of the AES Modes.

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param pui8IVdata is pointer to an array of 16 bytes.

-//!

-//! This functions reads the initial vector registers in the AES module.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-AESIVGet(uint32_t ui32Base, uint8_t *pui8IVdata)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-

-    //

-    // Write the initial vector registers.

-    //

-    *((uint32_t *)(pui8IVdata+ 0)) = HWREG(ui32Base + AES_O_IV_IN_0);

-    *((uint32_t *)(pui8IVdata+ 4)) = HWREG(ui32Base + AES_O_IV_IN_1);

-    *((uint32_t *)(pui8IVdata+ 8)) = HWREG(ui32Base + AES_O_IV_IN_2);

-    *((uint32_t *)(pui8IVdata+12)) = HWREG(ui32Base + AES_O_IV_IN_3);

-}

-

-//*****************************************************************************

-//

-//! Saves the tag registers to a user-defined location.

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param pui8TagData is pointer to the location that stores the tag data.

-//!

-//! This function stores the tag data for use authenticated encryption and

-//! decryption operations.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-AESTagRead(uint32_t ui32Base, uint8_t *pui8TagData)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-

-    //

-    // Read the tag data.

-    //

-    *((uint32_t *)(pui8TagData+0)) = HWREG((ui32Base + AES_O_TAG_OUT_0));

-    *((uint32_t *)(pui8TagData+4)) = HWREG((ui32Base + AES_O_TAG_OUT_1));

-    *((uint32_t *)(pui8TagData+8)) = HWREG((ui32Base + AES_O_TAG_OUT_2));

-    *((uint32_t *)(pui8TagData+12)) = HWREG((ui32Base + AES_O_TAG_OUT_3));

-}

-

-//*****************************************************************************

-//

-//! Used to set the write crypto data length in the AES module.

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param ui64Length is the crypto data length in bytes.

-//!

-//! This function stores the cryptographic data length in blocks for all modes.

-//! Data lengths up to (2^61 - 1) bytes are allowed.  For GCM, any value up

-//! to (2^36 - 2) bytes are allowed because a 32-bit block counter is used.  For

-//! basic modes (ECB/CBC/CTR/ICM/CFB128), zero can be programmed into the

-//! length field, indicating that the length is infinite.

-//!

-//! When this function is called, the engine is triggered to start using

-//! this context.

-//!

-//! \note This length does not include the authentication-only data used in

-//! some modes.  Use the AESAuthLengthSet() function to specify the

-//! authentication data length.

-//!

-//! \return None

-//

-//*****************************************************************************

-void

-AESDataLengthSet(uint32_t ui32Base, uint64_t ui64Length)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-

-    //

-    // Write the length register by shifting the 64-bit ui64Length.

-    //

-    HWREG(ui32Base + AES_O_C_LENGTH_0) = (uint32_t)(ui64Length);

-    HWREG(ui32Base + AES_O_C_LENGTH_1) = (uint32_t)(ui64Length >> 32);

-}

-

-//*****************************************************************************

-//

-//! Sets the optional additional authentication data (AAD) length.

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param ui32Length is the length in bytes.

-//!

-//! This function is only used to write the authentication data length in the

-//! combined modes (GCM or CCM) and XTS mode.  Supported AAD lengths for CCM

-//! are from 0 to (2^16 - 28) bytes.  For GCM, any value up to (2^32 - 1) can

-//! be used.  For XTS mode, this register is used to load j.  Loading of j is

-//! only required if j != 0.  j represents the sequential number of the 128-bit

-//! blocks inside the data unit.  Consequently, j must be multiplied by 16

-//! when passed to this function, thereby placing the block number in

-//! bits [31:4] of the register.

-//!

-//! When this function is called, the engine is triggered to start using

-//! this context for GCM and CCM.

-//!

-//! \return None

-//

-//*****************************************************************************

-void

-AESAuthDataLengthSet(uint32_t ui32Base, uint32_t ui32Length)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-

-    //

-    // Write the length into the register.

-    //

-    HWREG(ui32Base + AES_O_AUTH_LENGTH) = ui32Length;

-}

-

-//*****************************************************************************

-//

-//! Reads plaintext/ciphertext from data registers without blocking.

-//! This api writes data in blocks

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param pui8Dest is a pointer to an array of words of data.

-//! \param ui8Length the length can be from 1 to 16

-//!

-//! This function reads a block of either plaintext or ciphertext out of the

-//! AES module.  If the output data is not ready, the function returns

-//! false.  If the read completed successfully, the function returns true.

-//! A block is 16 bytes or 4 words.

-//!

-//! \return true or false.

-//

-//*****************************************************************************

-bool

-AESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length)

-{

-	volatile uint32_t pui32Dest[4];

-	uint8_t ui8BytCnt;

-	uint8_t *pui8DestTemp;

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-    if((ui8Length == 0)||(ui8Length>16))

-    {

-       	return(false);

-    }

-

-    //

-    // Check if the output is ready before reading the data.  If it not ready,

-    // return false.

-    //

-    if((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0)

-    {

-        return(false);

-    }

-

-    //

-    // Read a block of data from the data registers

-    //

-    pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3);

-    pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2);

-    pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1);

-    pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0);

-

-    //

-    //Copy the data to a block memory

-    //

-    pui8DestTemp = (uint8_t *)pui32Dest;

-    for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)

-    {

-     	*(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt);

-    }

-    //

-    // Read successful, return true.

-    //

-    return(true);

-}

-

-

-//*****************************************************************************

-//

-//! Reads plaintext/ciphertext from data registers with blocking.

-//! This api writes data in blocks

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param pui8Dest is a pointer to an array of words.

-//! \param ui8Length is the length of data in bytes to be read.

-//!        ui8Length can be from 1 to 16

-//!

-//! This function reads a block of either plaintext or ciphertext out of the

-//! AES module.  If the output is not ready, the function waits until it

-//! is ready. A block is 16 bytes or 4 words.

-//!

-//! \return None.

-//

-//*****************************************************************************

-

-void

-AESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length)

-{

-	volatile uint32_t pui32Dest[4];

-	uint8_t ui8BytCnt;

-	uint8_t *pui8DestTemp;

-

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-    if((ui8Length == 0)||(ui8Length>16))

-   	{

-       	return;

-    }

-

-

-    //

-    // Wait for the output to be ready before reading the data.

-    //

-    while((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0)

-    {

-    }

-

-    //

-    // Read a block of data from the data registers

-    //

-    pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3);

-    pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2);

-    pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1);

-    pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0);

-    //

-    //Copy the data to a block memory

-    //

-    pui8DestTemp = (uint8_t *)pui32Dest;

-    for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)

-   	{

-    	*(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt);

-   	}

-

-    return;

-}

-

-//*****************************************************************************

-//

-//! Writes plaintext/ciphertext to data registers without blocking.

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param pui8Src is a pointer to an array of words of data.

-//! \param ui8Length the length can be from 1 to 16

-//!

-//! This function writes a block of either plaintext or ciphertext into the

-//! AES module.  If the input is not ready, the function returns false

-//! If the write completed successfully, the function returns true.

-//!

-//! \return True or false.

-//

-//*****************************************************************************

-bool

-AESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length)

-{

-	volatile uint32_t pui32Src[4]={0,0,0,0};

-	uint8_t ui8BytCnt;

-	uint8_t *pui8SrcTemp;

-

-	//

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-    if((ui8Length == 0)||(ui8Length>16))

-   	{

-      	return(false);

-    }

-

-    //

-    // Check if the input is ready.  If not, then return false.

-    //

-    if(!(AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL))))

-    {

-        return(false);

-    }

-

-

-    //

-    //Copy the data to a block memory

-    //

-    pui8SrcTemp = (uint8_t *)pui32Src;

-    for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)

-	{

-		*(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt);

-	}

-    //

-    // Write a block of data into the data registers.

-    //

-    HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0];

-    HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1];

-    HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2];

-    HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3];

-

-    //

-    // Write successful, return true.

-    //

-    return(true);

-}

-

-

-//*****************************************************************************

-//

-//! Writes plaintext/ciphertext to data registers with blocking.

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param pui8Src is a pointer to an array of bytes.

-//! \param ui8Length the length can be from 1 to 16

-//!

-//! This function writes a block of either plaintext or ciphertext into the

-//! AES module.  If the input is not ready, the function waits until it is

-//! ready before performing the write.

-//!

-//! \return None.

-//

-//*****************************************************************************

-

-void

-AESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length)

-{

-	volatile uint32_t pui32Src[4]={0,0,0,0};

-	uint8_t ui8BytCnt;

-	uint8_t *pui8SrcTemp;

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-    if((ui8Length == 0)||(ui8Length>16))

-	{

-    	return;

-	}

-    //

-    // Wait for input ready.

-    //

-    while((AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0)

-    {

-    }

-

-    //

-    //Copy the data to a block memory

-    //

-    pui8SrcTemp = (uint8_t *)pui32Src;

-    for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)

-   	{

-   		*(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt);

-   	}

-

-    //

-    // Write a block of data into the data registers.

-    //

-    HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0];

-    HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1];

-    HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2];

-    HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3];

-}

-

-

-//*****************************************************************************

-//

-//! Used to process(transform) blocks of data, either encrypt or decrypt it.

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param pui8Src is a pointer to the memory location where the input data

-//! is stored.

-//! \param pui8Dest is a pointer to the memory location output is written.

-//! \param ui32Length is the length of the cryptographic data in bytes.

-//!

-//! This function iterates the encryption or decryption mechanism number over

-//! the data length.  Before calling this function, ensure that the AES

-//! module is properly configured the key, data size, mode, etc.  Only ECB,

-//! CBC, CTR, ICM, CFB, XTS and F8 operating modes should be used.  The data

-//! is processed in 4-word (16-byte) blocks.

-//!

-//! \note This function only supports values of \e ui32Length less than 2^32,

-//! because the memory size is restricted to between 0 to 2^32 bytes.

-//!

-//! \return Returns true if data was processed successfully.  Returns false

-//! if data processing failed.

-//

-//*****************************************************************************

-bool

-AESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest,

-               uint32_t ui32Length)

-{

-    uint32_t ui32Count, ui32BlkCount, ui32ByteCount;

-

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-

-    //

-    // Write the length register first, which triggers the engine to start

-    // using this context.

-    //

-    AESDataLengthSet(AES_BASE, (uint64_t) ui32Length);

-

-    //

-    // Now loop until the blocks are written.

-    //

-    ui32BlkCount = ui32Length/16;

-    for(ui32Count = 0; ui32Count < ui32BlkCount; ui32Count += 1)

-    {

-        //

-        // Write the data registers.

-        //

-        AESDataWrite(ui32Base, pui8Src + (ui32Count*16) ,16);

-

-        //

-        // Read the data registers.

-        //

-        AESDataRead(ui32Base, pui8Dest + (ui32Count*16) ,16);

-

-    }

-

-    //

-    //Now handle the residue bytes

-    //

-    ui32ByteCount = ui32Length%16;

-    if(ui32ByteCount)

-    {

-    	//

-    	// Write the data registers.

-    	//

-    	AESDataWrite(ui32Base, pui8Src + (16*ui32BlkCount) ,ui32ByteCount);

-

-    	//

-    	// Read the data registers.

-    	//

-        AESDataRead(ui32Base, pui8Dest + (16*ui32BlkCount) ,ui32ByteCount);

-    }

-

-

-

-    //

-    // Return true to indicate successful completion of the function.

-    //

-    return(true);

-}

-//*****************************************************************************

-//

-//! Used to generate message authentication code (MAC) using CBC-MAC and F9 mode.

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param pui8Src is a pointer to the memory location where the input data

-//! is stored.

-//! \param ui32Length  is the length of the cryptographic data in bytes.

-//! \param pui8Tag is a pointer to a 4-word array where the hash tag is

-//! written.

-//!

-//! This function processes data to produce a hash tag that can be used tor

-//! authentication.   Before calling this function, ensure that the AES

-//! module is properly configured the key, data size, mode, etc.  Only

-//! CBC-MAC and F9 modes should be used.

-//!

-//! \return Returns true if data was processed successfully.  Returns false

-//! if data processing failed.

-//

-//*****************************************************************************

-bool

-AESDataMAC(uint32_t ui32Base, uint8_t *pui8Src, uint32_t ui32Length,

-            uint8_t *pui8Tag)

-{

-    uint32_t ui32Count, ui32BlkCount, ui32ByteCount;

-	//

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-

-    //

-    // Write the length register first, which triggers the engine to start

-    // using this context.

-    //

-    AESDataLengthSet(AES_BASE, (uint64_t) ui32Length);

-

-    //

-    // Write the data registers.

-    //

-

-    //

-    // Now loop until the blocks are written.

-    //

-    ui32BlkCount = ui32Length/16;

-    for(ui32Count = 0; ui32Count < ui32BlkCount; ui32Count += 1)

-    {

-	   //

-	   // Write the data registers.

-	   //

-	   AESDataWrite(ui32Base, pui8Src + ui32Count*16 ,16);

-    }

-

-    //

-    //Now handle the residue bytes

-    //

-    ui32ByteCount = ui32Length%16;

-    if(ui32ByteCount)

-    {

-	   //

-	   // Write the data registers.

-	   //

-	   AESDataWrite(ui32Base, pui8Src + (ui32Count*ui32BlkCount) ,ui32ByteCount);

-    }

-

-    //

-    // Wait for the context data regsiters to be ready.

-    //

-    while((AES_CTRL_SVCTXTRDY & (HWREG(AES_BASE + AES_O_CTRL))) == 0)

-    {

-    }

-

-    //

-    // Read the hash tag value.

-    //

-    AESTagRead(AES_BASE, pui8Tag);

-

-    //

-    // Return true to indicate successful completion of the function.

-    //

-    return(true);

-}

-

-//*****************************************************************************

-//

-//! Used for Authenticated encryption (AE) of the data. Processes and authenticates blocks of data,

-//! either encrypt the data or decrypt the data.

-//!

-//! \param ui32Base  is the base address of the AES module.

-//! \param pui8Src is a pointer to the memory location where the input data

-//! is stored. The data must be padded to the 16-byte boundary.

-//! \param pui8Dest is a pointer to the memory location output is written.

-//! The space for written data must be rounded up to the 16-byte boundary.

-//! \param ui32Length is the length of the cryptographic data in bytes.

-//! \param pui8AuthSrc is a pointer to the memory location where the

-//! additional authentication data is stored.  The data must be padded to the

-//! 16-byte boundary.

-//! \param ui32AuthLength is the length of the additional authentication

-//! data in bytes.

-//! \param pui8Tag is a pointer to a 4-word array where the hash tag is

-//! written.

-//!

-//! This function encrypts or decrypts blocks of data in addition to

-//! authentication data.  A hash tag is also produced.  Before calling this

-//! function, ensure that the AES module is properly configured the key,

-//! data size, mode, etc.  Only CCM and GCM modes should be used.

-//!

-//! \return Returns true if data was processed successfully.  Returns false

-//! if data processing failed.

-//

-//*****************************************************************************

-bool

-AESDataProcessAE(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest,

-                   uint32_t ui32Length, uint8_t *pui8AuthSrc,

-                   uint32_t ui32AuthLength, uint8_t *pui8Tag)

-{

-    uint32_t ui32Count;

-

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-

-    //

-    // Set the data length.

-    //

-    AESDataLengthSet(AES_BASE, (uint64_t) ui32Length);

-

-    //

-    // Set the additional authentication data length.

-    //

-    AESAuthDataLengthSet(AES_BASE, ui32AuthLength);

-

-    //

-    // Now loop until the authentication data blocks are written.

-    //

-    for(ui32Count = 0; ui32Count < ui32AuthLength; ui32Count += 16)

-    {

-        //

-        // Write the data registers.

-        //

-        AESDataWrite(ui32Base, pui8AuthSrc + (ui32Count),16);

-    }

-

-    //

-    // Now loop until the data blocks are written.

-    //

-    for(ui32Count = 0; ui32Count < ui32Length; ui32Count += 16)

-    {

-        //

-        // Write the data registers.

-        //

-        AESDataWrite(ui32Base, pui8Src + (ui32Count),16);

-

-        //

-        //

-        // Read the data registers.

-        //

-        AESDataRead(ui32Base, pui8Dest + (ui32Count),16);

-    }

-

-    //

-    // Wait for the context data regsiters to be ready.

-    //

-    while((AES_CTRL_SVCTXTRDY & (HWREG(AES_BASE + AES_O_CTRL))) == 0)

-    {

-    }

-

-    //

-    // Read the hash tag value.

-    //

-    AESTagRead(AES_BASE, pui8Tag);

-

-    //

-    // Return true to indicate successful completion of the function.

-    //

-    return(true);

-}

-

-//*****************************************************************************

-//

-//! Returns the current AES module interrupt status.

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param bMasked is \b false if the raw interrupt status is required and

-//! \b true if the masked interrupt status is required.

-//!

-//! \return Returns a bit mask of the interrupt sources, which is a logical OR

-//! of any of the following:

-//!

-//! - \b AES_INT_CONTEXT_IN - Context interrupt

-//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt.

-//! - \b AES_INT_DATA_IN - Data input interrupt

-//! - \b AES_INT_DATA_OUT - Data output interrupt

-//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt

-//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done

-//! interrupt

-//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt

-//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt

-//

-//*****************************************************************************

-uint32_t

-AESIntStatus(uint32_t ui32Base, bool bMasked)

-{

-    uint32_t ui32Temp;

-    uint32_t ui32IrqEnable;

-

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-

-    //

-    // Read the IRQ status register and return the value.

-    //

-    if(bMasked)

-    {

-        ui32Temp = HWREG(DTHE_BASE + DTHE_O_AES_MIS);

-        ui32IrqEnable = HWREG(ui32Base + AES_O_IRQENABLE);

-        return((HWREG(ui32Base + AES_O_IRQSTATUS) &

-                ui32IrqEnable) | ((ui32Temp & 0x0000000F) << 16));

-    }

-    else

-    {

-        ui32Temp = HWREG(DTHE_BASE + DTHE_O_AES_RIS);

-        return(HWREG(ui32Base + AES_O_IRQSTATUS) |

-               ((ui32Temp & 0x0000000F) << 16));

-    }

-}

-

-//*****************************************************************************

-//

-//! Enables AES module interrupts.

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param ui32IntFlags is a bit mask of the interrupt sources to enable.

-//!

-//! This function enables the interrupts in the AES module. The \e ui32IntFlags

-//! parameter is the logical OR of any of the following:

-//!

-//! - \b AES_INT_CONTEXT_IN - Context interrupt

-//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt

-//! - \b AES_INT_DATA_IN - Data input interrupt

-//! - \b AES_INT_DATA_OUT - Data output interrupt

-//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt

-//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done

-//! interrupt

-//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt

-//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt

-//!

-//! \note Interrupts that have been previously been enabled are not disabled

-//! when this function is called.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-    ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) ||

-           (ui32IntFlags == AES_INT_CONTEXT_OUT) ||

-           (ui32IntFlags == AES_INT_DATA_IN) ||

-           (ui32IntFlags == AES_INT_DATA_OUT) ||

-           (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) ||

-           (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) ||

-           (ui32IntFlags == AES_INT_DMA_DATA_IN) ||

-           (ui32IntFlags == AES_INT_DMA_DATA_OUT));

-

-    //

-    // Set the flags.

-    //

-    HWREG(DTHE_BASE + DTHE_O_AES_IM) &= ~((ui32IntFlags & 0x000F0000) >> 16);

-    HWREG(ui32Base + AES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff;

-}

-

-//*****************************************************************************

-//

-//! Disables AES module interrupts.

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param ui32IntFlags is a bit mask of the interrupt sources to disable.

-//!

-//! This function disables the interrupt sources in the AES module. The

-//! \e ui32IntFlags parameter is the logical OR of any of the following:

-//!

-//! - \b AES_INT_CONTEXT_IN - Context interrupt

-//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt

-//! - \b AES_INT_DATA_IN - Data input interrupt

-//! - \b AES_INT_DATA_OUT - Data output interrupt

-//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt

-//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done

-//! interrupt

-//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt

-//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt

-//!

-//! \note The DMA done interrupts are the only interrupts that can be cleared.

-//! The remaining interrupts can be disabled instead using AESIntDisable().

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-    ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) ||

-           (ui32IntFlags == AES_INT_CONTEXT_OUT) ||

-           (ui32IntFlags == AES_INT_DATA_IN) ||

-           (ui32IntFlags == AES_INT_DATA_OUT) ||

-           (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) ||

-           (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) ||

-           (ui32IntFlags == AES_INT_DMA_DATA_IN) ||

-           (ui32IntFlags == AES_INT_DMA_DATA_OUT));

-

-    //

-    // Clear the flags.

-    //

-    HWREG(DTHE_BASE + DTHE_O_AES_IM) |= ((ui32IntFlags & 0x000F0000) >> 16);

-    HWREG(ui32Base + AES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff);

-}

-

-//*****************************************************************************

-//

-//! Clears AES module interrupts.

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param ui32IntFlags is a bit mask of the interrupt sources to disable.

-//!

-//! This function clears the interrupt sources in the AES module.  The

-//! \e ui32IntFlags parameter is the logical OR of any of the following:

-//!

-//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt

-//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done

-//! interrupt

-//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt

-//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt

-//!

-//! \note Only the DMA done interrupts can be cleared.  The remaining

-//! interrupts should be disabled with AESIntDisable().

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-    ASSERT((ui32IntFlags == AES_INT_DMA_CONTEXT_IN) ||

-           (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) ||

-           (ui32IntFlags == AES_INT_DMA_DATA_IN) ||

-           (ui32IntFlags == AES_INT_DMA_DATA_OUT));

-

-    HWREG(DTHE_BASE + DTHE_O_AES_IC) = ((ui32IntFlags >> 16) & 0x0000000F);

-}

-

-//*****************************************************************************

-//

-//! Registers an interrupt handler for the AES module.

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param pfnHandler is a pointer to the function to be called when the

-//! enabled AES interrupts occur.

-//!

-//! This function registers the interrupt handler in the interrupt vector

-//! table, and enables AES interrupts on the interrupt controller; specific AES

-//! interrupt sources must be enabled using AESIntEnable().  The interrupt

-//! handler being registered must clear the source of the interrupt using

-//! AESIntClear().

-//!

-//! If the application is using a static interrupt vector table stored in

-//! flash, then it is not necessary to register the interrupt handler this way.

-//! Instead, IntEnable() is used to enable AES interrupts on the

-//! interrupt controller.

-//!

-//! \sa IntRegister() for important information about registering interrupt

-//! handlers.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-AESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void))

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-

-    //

-    // Register the interrupt handler.

-    //

-    IntRegister(INT_AES, pfnHandler);

-

-    //

-    // Enable the interrupt

-    //

-    IntEnable(INT_AES);

-}

-

-//*****************************************************************************

-//

-//! Unregisters an interrupt handler for the AES module.

-//!

-//! \param ui32Base is the base address of the AES module.

-//!

-//! This function unregisters the previously registered interrupt handler and

-//! disables the interrupt in the interrupt controller.

-//!

-//! \sa IntRegister() for important information about registering interrupt

-//! handlers.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-AESIntUnregister(uint32_t ui32Base)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-

-    //

-    // Disable the interrupt.

-    //

-    IntDisable(INT_AES);

-

-    //

-    // Unregister the interrupt handler.

-    //

-    IntUnregister(INT_AES);

-}

-

-//*****************************************************************************

-//

-//! Enables uDMA requests for the AES module.

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param ui32Flags is a bit mask of the uDMA requests to be enabled.

-//!

-//! This function enables the uDMA request sources in the AES module.

-//! The \e ui32Flags parameter is the logical OR of any of the following:

-//!

-//! - \b AES_DMA_DATA_IN

-//! - \b AES_DMA_DATA_OUT

-//! - \b AES_DMA_CONTEXT_IN

-//! - \b AES_DMA_CONTEXT_OUT

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-    ASSERT((ui32Flags == AES_DMA_DATA_IN) ||

-           (ui32Flags == AES_DMA_DATA_OUT) ||

-           (ui32Flags == AES_DMA_CONTEXT_IN) ||

-           (ui32Flags == AES_DMA_CONTEXT_OUT));

-

-    //

-    // Set the flags in the current register value.

-    //

-    HWREG(ui32Base + AES_O_SYSCONFIG) |= ui32Flags;

-}

-

-//*****************************************************************************

-//

-//! Disables uDMA requests for the AES module.

-//!

-//! \param ui32Base is the base address of the AES module.

-//! \param ui32Flags is a bit mask of the uDMA requests to be disabled.

-//!

-//! This function disables the uDMA request sources in the AES module.

-//! The \e ui32Flags parameter is the logical OR of any of the

-//! following:

-//!

-//! - \b AES_DMA_DATA_IN

-//! - \b AES_DMA_DATA_OUT

-//! - \b AES_DMA_CONTEXT_IN

-//! - \b AES_DMA_CONTEXT_OUT

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == AES_BASE);

-    ASSERT((ui32Flags == AES_DMA_DATA_IN) ||

-           (ui32Flags == AES_DMA_DATA_OUT) ||

-           (ui32Flags == AES_DMA_CONTEXT_IN) ||

-           (ui32Flags == AES_DMA_CONTEXT_OUT));

-

-    //

-    // Clear the flags in the current register value.

-    //

-    HWREG(ui32Base + AES_O_SYSCONFIG) &= ~ui32Flags;

-}

-

-//*****************************************************************************

-//

-// Close the Doxygen group.

-//! @}

-//

-//*****************************************************************************

diff --git a/cc3200/hal/aes.h b/cc3200/hal/aes.h
deleted file mode 100644
index 766d3587e..000000000
--- a/cc3200/hal/aes.h
+++ /dev/null
@@ -1,218 +0,0 @@
-//*****************************************************************************

-//

-//  aes.h

-//

-//  Defines and Macros for the AES module.

-//

-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/

-//

-//

-//  Redistribution and use in source and binary forms, with or without

-//  modification, are permitted provided that the following conditions

-//  are met:

-//

-//    Redistributions of source code must retain the above copyright

-//    notice, this list of conditions and the following disclaimer.

-//

-//    Redistributions in binary form must reproduce the above copyright

-//    notice, this list of conditions and the following disclaimer in the

-//    documentation and/or other materials provided with the

-//    distribution.

-//

-//    Neither the name of Texas Instruments Incorporated nor the names of

-//    its contributors may be used to endorse or promote products derived

-//    from this software without specific prior written permission.

-//

-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-//

-//*****************************************************************************

-

-#ifndef __DRIVERLIB_AES_H__

-#define __DRIVERLIB_AES_H__

-

-//*****************************************************************************

-//

-// If building with a C++ compiler, make all of the definitions in this header

-// have a C binding.

-//

-//*****************************************************************************

-#ifdef __cplusplus

-extern "C"

-{

-#endif

-

-//*****************************************************************************

-//

-// The following defines are used to specify the operation direction in the

-// ui32Config argument in the AESConfig function.  Only one is permitted.

-//

-//*****************************************************************************

-#define AES_CFG_DIR_ENCRYPT     0x00000004

-#define AES_CFG_DIR_DECRYPT     0x00000000

-

-//*****************************************************************************

-//

-// The following defines are used to specify the key size in the ui32Config

-// argument in the AESConfig function.  Only one is permitted.

-//

-//*****************************************************************************

-#define AES_CFG_KEY_SIZE_128BIT 0x00000008

-#define AES_CFG_KEY_SIZE_192BIT 0x00000010

-#define AES_CFG_KEY_SIZE_256BIT 0x00000018

-

-//*****************************************************************************

-//

-// The following defines are used to specify the mode of operation in the

-// ui32Config argument in the AESConfig function.  Only one is permitted.

-//

-//*****************************************************************************

-#define AES_CFG_MODE_M          0x2007fe60

-#define AES_CFG_MODE_ECB        0x00000000

-#define AES_CFG_MODE_CBC        0x00000020

-#define AES_CFG_MODE_CTR        0x00000040

-#define AES_CFG_MODE_ICM        0x00000200

-#define AES_CFG_MODE_CFB        0x00000400

-#define AES_CFG_MODE_XTS_TWEAKJL \

-                                0x00000800

-#define AES_CFG_MODE_XTS_K2IJL \

-                                0x00001000

-#define AES_CFG_MODE_XTS_K2ILJ0 \

-                                0x00001800

-#define AES_CFG_MODE_F8         0x00002000

-#define AES_CFG_MODE_F9         0x20004000

-#define AES_CFG_MODE_CBCMAC     0x20008000

-#define AES_CFG_MODE_GCM_HLY0ZERO \

-                                0x20010040

-#define AES_CFG_MODE_GCM_HLY0CALC \

-                                0x20020040

-#define AES_CFG_MODE_GCM_HY0CALC \

-                                0x20030040

-#define AES_CFG_MODE_CCM        0x20040040

-

-//*****************************************************************************

-//

-// The following defines are used to specify the counter width in the

-// ui32Config argument in the AESConfig function.  It is only required to

-// be defined when using CTR, CCM, or GCM modes. Only one length is permitted.

-//

-//*****************************************************************************

-#define AES_CFG_CTR_WIDTH_32    0x00000000

-#define AES_CFG_CTR_WIDTH_64    0x00000080

-#define AES_CFG_CTR_WIDTH_96    0x00000100

-#define AES_CFG_CTR_WIDTH_128   0x00000180

-

-//*****************************************************************************

-//

-// The following defines are used to define the width of the length field for

-// CCM operation through the ui32Config argument in the AESConfig function.

-// This value is also known as L.  Only one is permitted.

-//

-//*****************************************************************************

-#define AES_CFG_CCM_L_2         0x00080000

-#define AES_CFG_CCM_L_4         0x00180000

-#define AES_CFG_CCM_L_8         0x00380000

-

-//*****************************************************************************

-//

-// The following defines are used to define the length of the authentication

-// field for CCM operations through the ui32Config argument in the AESConfig

-// function.  This value is also known as M.  Only one is permitted.

-//

-//*****************************************************************************

-#define AES_CFG_CCM_M_4         0x00400000

-#define AES_CFG_CCM_M_6         0x00800000

-#define AES_CFG_CCM_M_8         0x00c00000

-#define AES_CFG_CCM_M_10        0x01000000

-#define AES_CFG_CCM_M_12        0x01400000

-#define AES_CFG_CCM_M_14        0x01800000

-#define AES_CFG_CCM_M_16        0x01c00000

-

-//*****************************************************************************

-//

-// Interrupt flags for use with the AESIntEnable, AESIntDisable, and

-// AESIntStatus functions.

-//

-//*****************************************************************************

-#define AES_INT_CONTEXT_IN      0x00000001

-#define AES_INT_CONTEXT_OUT     0x00000008

-#define AES_INT_DATA_IN         0x00000002

-#define AES_INT_DATA_OUT        0x00000004

-#define AES_INT_DMA_CONTEXT_IN  0x00010000

-#define AES_INT_DMA_CONTEXT_OUT 0x00020000

-#define AES_INT_DMA_DATA_IN     0x00040000

-#define AES_INT_DMA_DATA_OUT    0x00080000

-

-//*****************************************************************************

-//

-// Defines used when enabling and disabling DMA requests in the

-// AESEnableDMA and AESDisableDMA functions.

-//

-//*****************************************************************************

-#define AES_DMA_DATA_IN         0x00000040

-#define AES_DMA_DATA_OUT        0x00000020

-#define AES_DMA_CONTEXT_IN      0x00000080

-#define AES_DMA_CONTEXT_OUT     0x00000100

-

-//*****************************************************************************

-//

-// Function prototypes.

-//

-//*****************************************************************************

-extern void AESConfigSet(uint32_t ui32Base, uint32_t ui32Config);

-extern void AESKey1Set(uint32_t ui32Base, uint8_t *pui8Key,

-                       uint32_t ui32Keysize);

-extern void AESKey2Set(uint32_t ui32Base, uint8_t *pui8Key,

-                       uint32_t ui32Keysize);

-extern void AESKey3Set(uint32_t ui32Base, uint8_t *pui8Key);

-extern void AESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata);

-extern void AESIVGet(uint32_t ui32Base, uint8_t *pui8IVdata);

-extern void AESTagRead(uint32_t ui32Base, uint8_t *pui8TagData);

-extern void AESDataLengthSet(uint32_t ui32Base, uint64_t ui64Length);

-extern void AESAuthDataLengthSet(uint32_t ui32Base, uint32_t ui32Length);

-extern bool AESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest,

-                                   uint8_t ui8Length);

-extern void AESDataRead(uint32_t ui32Base, uint8_t *pui8Dest,

-                        uint8_t ui8Length);

-extern bool AESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src,

-                                    uint8_t ui8Length);

-extern void AESDataWrite(uint32_t ui32Base, uint8_t *pui8Src,

-                         uint8_t ui8Length);

-extern bool AESDataProcess(uint32_t ui32Base, uint8_t *pui8Src,

-                           uint8_t *pui8Dest,

-               uint32_t ui32Length);

-extern bool AESDataMAC(uint32_t ui32Base, uint8_t *pui8Src,

-                       uint32_t ui32Length,

-            uint8_t *pui8Tag);

-extern bool AESDataProcessAE(uint32_t ui32Base, uint8_t *pui8Src,

-                             uint8_t *pui8Dest, uint32_t ui32Length,

-                             uint8_t *pui8AuthSrc, uint32_t ui32AuthLength,

-                             uint8_t *pui8Tag);

-extern uint32_t AESIntStatus(uint32_t ui32Base, bool bMasked);

-extern void AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);

-extern void AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);

-extern void AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);

-extern void AESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void));

-extern void AESIntUnregister(uint32_t ui32Base);

-extern void AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);

-extern void AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);

-

-//*****************************************************************************

-//

-// Mark the end of the C bindings section for C++ compilers.

-//

-//*****************************************************************************

-#ifdef __cplusplus

-}

-#endif

-

-#endif //  __DRIVERLIB_AES_H__

diff --git a/cc3200/hal/cc3200_asm.h b/cc3200/hal/cc3200_asm.h
deleted file mode 100644
index 742c9a6f7..000000000
--- a/cc3200/hal/cc3200_asm.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * This file is part of the MicroPython project, http://micropython.org/
- *
- * The MIT License (MIT)
- *
- * Copyright (c) 2015 Daniel Campora
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef CC3200_ASM_H_
-#define CC3200_ASM_H_
-
-// We have inlined IRQ functions for efficiency (they are generally
-// 1 machine instruction).
-//
-// Note on IRQ state: you should not need to know the specific
-// value of the state variable, but rather just pass the return
-// value from disable_irq back to enable_irq.  If you really need
-// to know the machine-specific values, see irq.h.
-
-#ifndef __disable_irq
-#define __disable_irq() __asm__ volatile ("cpsid i");
-#endif
-
-#ifndef DEBUG
-__attribute__(( always_inline ))
-static inline void __WFI(void) {
-    __asm volatile ("    dsb      \n"
-                    "    isb      \n"
-                    "    wfi      \n");
-}
-#else
-// For some reason the debugger gets disconnected when entering any of the sleep modes
-__attribute__(( always_inline ))
-static inline void __WFI(void) {
-    __asm volatile ("    dsb      \n"
-                    "    isb      \n");
-}
-#endif
-
-__attribute__(( always_inline ))
-static inline uint32_t __get_PRIMASK(void) {
-    uint32_t result;
-    __asm volatile ("mrs %0, primask" : "=r" (result));
-    return(result);
-}
-
-__attribute__(( always_inline ))
-static inline void __set_PRIMASK(uint32_t priMask) {
-    __asm volatile ("msr primask, %0" : : "r" (priMask) : "memory");
-}
-
-__attribute__(( always_inline ))
-static inline uint32_t __get_BASEPRI(void) {
-    uint32_t result;
-    __asm volatile ("mrs %0, basepri" : "=r" (result));
-    return(result);
-}
-
-__attribute__(( always_inline ))
-static inline void __set_BASEPRI(uint32_t value) {
-    __asm volatile ("msr basepri, %0" : : "r" (value) : "memory");
-}
-
-__attribute__(( always_inline ))
-static inline void enable_irq(mp_uint_t state) {
-    __set_PRIMASK(state);
-}
-
-__attribute__(( always_inline ))
-static inline mp_uint_t disable_irq(void) {
-    mp_uint_t state = __get_PRIMASK();
-    __disable_irq();
-    return state;
-}
-
-#endif /* CC3200_ASM_H_ */
diff --git a/cc3200/hal/cc3200_hal.c b/cc3200/hal/cc3200_hal.c
deleted file mode 100644
index 9718980e7..000000000
--- a/cc3200/hal/cc3200_hal.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
- * This file is part of the MicroPython project, http://micropython.org/
- *
- * The MIT License (MIT)
- *
- * Copyright (c) 2015 Daniel Campora
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-
- /******************************************************************************
- IMPORTS
- ******************************************************************************/
-#include <stdio.h>
-#include <stdint.h>
-#include <string.h>
-
-
-#include "py/mpstate.h"
-#include "py/mphal.h"
-#include "py/runtime.h"
-#include "py/objstr.h"
-#include "inc/hw_types.h"
-#include "inc/hw_ints.h"
-#include "inc/hw_nvic.h"
-#include "hw_memmap.h"
-#include "rom_map.h"
-#include "interrupt.h"
-#include "systick.h"
-#include "prcm.h"
-#include "pin.h"
-#include "mpexception.h"
-#include "telnet.h"
-#include "pybuart.h"
-#include "utils.h"
-#include "irq.h"
-#include "moduos.h"
-
-#ifdef USE_FREERTOS
-#include "FreeRTOS.h"
-#include "task.h"
-#include "semphr.h"
-#endif
-
-
-/******************************************************************************
- DECLARE PRIVATE FUNCTIONS
- ******************************************************************************/
-#ifndef USE_FREERTOS
-static void hal_TickInit (void);
-#endif
-
-/******************************************************************************
- DECLARE LOCAL DATA
- ******************************************************************************/
-static volatile uint32_t HAL_tickCount;
-
-/******************************************************************************
- DECLARE IMPORTED DATA
- ******************************************************************************/
-extern void (* const g_pfnVectors[256])(void);
-
-/******************************************************************************
- DEFINE PUBLIC FUNCTIONS
- ******************************************************************************/
-
-__attribute__ ((section (".boot")))
-void HAL_SystemInit (void) {
-    MAP_IntVTableBaseSet((unsigned long)&g_pfnVectors[0]);
-
-    // in the case of a release image, these steps are already performed by
-    // the bootloader so we can skip it and gain some code space
-#ifdef DEBUG
-    MAP_IntMasterEnable();
-    PRCMCC3200MCUInit();
-#endif
-
-#ifndef USE_FREERTOS
-    hal_TickInit();
-#endif
-}
-
-void HAL_SystemDeInit (void) {
-}
- 
-void HAL_IncrementTick(void) {
-    HAL_tickCount++;
-}
-
-mp_uint_t mp_hal_ticks_ms(void) {
-    return HAL_tickCount;
-}
-
-// The SysTick timer counts down at HAL_FCPU_HZ, so we can use that knowledge
-// to grab a microsecond counter.
-mp_uint_t mp_hal_ticks_us(void) {
-    mp_uint_t irq_state = disable_irq();
-    uint32_t counter = SysTickValueGet();
-    uint32_t milliseconds = mp_hal_ticks_ms();
-    enable_irq(irq_state);
-
-    uint32_t load = SysTickPeriodGet();
-    counter = load - counter; // Convert from decrementing to incrementing
-    return (milliseconds * 1000) + ((counter * 1000) / load);
-}
-
-void mp_hal_delay_ms(mp_uint_t delay) {
-    // only if we are not within interrupt context and interrupts are enabled
-    if ((HAL_NVIC_INT_CTRL_REG & HAL_VECTACTIVE_MASK) == 0 && query_irq() == IRQ_STATE_ENABLED) {
-        MP_THREAD_GIL_EXIT();
-        #ifdef USE_FREERTOS
-            vTaskDelay (delay / portTICK_PERIOD_MS);
-        #else
-            uint32_t start = HAL_tickCount;
-            // wraparound of tick is taken care of by 2's complement arithmetic.
-            while (HAL_tickCount - start < delay) {
-                // enter sleep mode, waiting for (at least) the SysTick interrupt.
-                __WFI();
-            }
-        #endif
-        MP_THREAD_GIL_ENTER();
-    } else {
-        for (int ms = 0; ms < delay; ms++) {
-            UtilsDelay(UTILS_DELAY_US_TO_COUNT(1000));
-        }
-    }
-}
-
-void mp_hal_stdout_tx_str(const char *str) {
-    mp_hal_stdout_tx_strn(str, strlen(str));
-}
-
-void mp_hal_stdout_tx_strn(const char *str, size_t len) {
-    if (MP_STATE_PORT(os_term_dup_obj)) {
-        if (MP_OBJ_IS_TYPE(MP_STATE_PORT(os_term_dup_obj)->stream_o, &pyb_uart_type)) {
-            uart_tx_strn(MP_STATE_PORT(os_term_dup_obj)->stream_o, str, len);
-        } else {
-            MP_STATE_PORT(os_term_dup_obj)->write[2] = mp_obj_new_str_of_type(&mp_type_str, (const byte *)str, len);
-            mp_call_method_n_kw(1, 0, MP_STATE_PORT(os_term_dup_obj)->write);
-        }
-    }
-    // and also to telnet
-    telnet_tx_strn(str, len);
-}
-
-void mp_hal_stdout_tx_strn_cooked (const char *str, size_t len) {
-    int32_t nslen = 0;
-    const char *_str = str;
-
-    for (int i = 0; i < len; i++) {
-        if (str[i] == '\n') {
-            mp_hal_stdout_tx_strn(_str, nslen);
-            mp_hal_stdout_tx_strn("\r\n", 2);
-            _str += nslen + 1;
-            nslen = 0;
-        } else {
-            nslen++;
-        }
-    }
-    if (_str < str + len) {
-        mp_hal_stdout_tx_strn(_str, nslen);
-    }
-}
-
-int mp_hal_stdin_rx_chr(void) {
-    for ( ;; ) {
-        // read telnet first
-        if (telnet_rx_any()) {
-            return telnet_rx_char();
-        } else if (MP_STATE_PORT(os_term_dup_obj)) { // then the stdio_dup
-            if (MP_OBJ_IS_TYPE(MP_STATE_PORT(os_term_dup_obj)->stream_o, &pyb_uart_type)) {
-                if (uart_rx_any(MP_STATE_PORT(os_term_dup_obj)->stream_o)) {
-                    return uart_rx_char(MP_STATE_PORT(os_term_dup_obj)->stream_o);
-                }
-            } else {
-                MP_STATE_PORT(os_term_dup_obj)->read[2] = mp_obj_new_int(1);
-                mp_obj_t data = mp_call_method_n_kw(1, 0, MP_STATE_PORT(os_term_dup_obj)->read);
-                // data len is > 0
-                if (mp_obj_is_true(data)) {
-                    mp_buffer_info_t bufinfo;
-                    mp_get_buffer_raise(data, &bufinfo, MP_BUFFER_READ);
-                    return ((int *)(bufinfo.buf))[0];
-                }
-            }
-        }
-        mp_hal_delay_ms(1);
-    }
-}
-
-/******************************************************************************
- DEFINE PRIVATE FUNCTIONS
- ******************************************************************************/
-
-#ifndef USE_FREERTOS
-static void hal_TickInit (void) {
-    HAL_tickCount = 0;
-    MAP_SysTickIntRegister(HAL_IncrementTick);
-    MAP_IntEnable(FAULT_SYSTICK);
-    MAP_SysTickIntEnable();
-    MAP_SysTickPeriodSet(HAL_FCPU_HZ / HAL_SYSTICK_PERIOD_US);
-    // Force a reload of the SysTick counter register
-    HWREG(NVIC_ST_CURRENT) = 0;
-    MAP_SysTickEnable();
-}
-#endif
diff --git a/cc3200/hal/cc3200_hal.h b/cc3200/hal/cc3200_hal.h
deleted file mode 100644
index 71e245eeb..000000000
--- a/cc3200/hal/cc3200_hal.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the MicroPython project, http://micropython.org/
- *
- * The MIT License (MIT)
- *
- * Copyright (c) 2015 Daniel Campora
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "hal/utils.h"
-#include "hal/systick.h"
-
-/******************************************************************************
- DEFINE CONSTANTS
- ******************************************************************************/
-
-#define HAL_FCPU_MHZ                        80U
-#define HAL_FCPU_HZ                         (1000000U * HAL_FCPU_MHZ)
-#define HAL_SYSTICK_PERIOD_US               1000U
-#define UTILS_DELAY_US_TO_COUNT(us)         (((us) * HAL_FCPU_MHZ) / 6)
-
-#define HAL_NVIC_INT_CTRL_REG               (*((volatile uint32_t *) 0xE000ED04 ) )
-#define HAL_VECTACTIVE_MASK                 (0x1FUL)
-
-/******************************************************************************
- DEFINE TYPES
- ******************************************************************************/
-
-/******************************************************************************
- DEFINE FUNCTION-LIKE MACROS
- ******************************************************************************/
-
-#define HAL_INTRODUCE_SYNC_BARRIER() {                      \
-                                        __asm(" dsb \n"     \
-                                              " isb \n");   \
-                                     }
-
-/******************************************************************************
- DECLARE PUBLIC FUNCTIONS
- ******************************************************************************/
-
-extern void HAL_SystemInit (void);
-extern void HAL_SystemDeInit (void);
-extern void HAL_IncrementTick(void);
-extern void mp_hal_set_interrupt_char (int c);
-
-#define mp_hal_delay_us(usec) UtilsDelay(UTILS_DELAY_US_TO_COUNT(usec))
-#define mp_hal_ticks_cpu() (SysTickPeriodGet() - SysTickValueGet())
diff --git a/cc3200/hal/cpu.c b/cc3200/hal/cpu.c
deleted file mode 100644
index 29d10afb2..000000000
--- a/cc3200/hal/cpu.c
+++ /dev/null
@@ -1,412 +0,0 @@
-//*****************************************************************************
-//
-//  cpu.c
-//
-//  Instruction wrappers for special CPU instructions needed by the
-//  drivers.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-#include "cpu.h"
-
-//*****************************************************************************
-//
-// Wrapper function for the CPSID instruction.  Returns the state of PRIMASK
-// on entry.
-//
-//*****************************************************************************
-#if defined(gcc)
-unsigned long __attribute__((naked))
-CPUcpsid(void)
-{
-    unsigned long ulRet;
-
-    //
-    // Read PRIMASK and disable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    cpsid   i\n"
-          "    dsb      \n"
-          "    isb      \n"
-          "    bx      lr\n"
-          : "=r" (ulRet));
-
-    //
-    // The return is handled in the inline assembly, but the compiler will
-    // still complain if there is not an explicit return here (despite the fact
-    // that this does not result in any code being produced because of the
-    // naked attribute).
-    //
-    return(ulRet);
-}
-#endif
-#if defined(ewarm)
-unsigned long
-CPUcpsid(void)
-{
-    //
-    // Read PRIMASK and disable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    cpsid   i\n"
-          "    dsb      \n"
-          "    isb      \n");
-
-    //
-    // "Warning[Pe940]: missing return statement at end of non-void function"
-    // is suppressed here to avoid putting a "bx lr" in the inline assembly
-    // above and a superfluous return statement here.
-    //
-#pragma diag_suppress=Pe940
-}
-#pragma diag_default=Pe940
-#endif
-#if defined(ccs)
-unsigned long
-CPUcpsid(void)
-{
-    //
-    // Read PRIMASK and disable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    cpsid   i\n"
-          "    dsb      \n"
-          "    isb      \n"
-          "    bx      lr\n");
-
-    //
-    // The following keeps the compiler happy, because it wants to see a
-    // return value from this function.  It will generate code to return
-    // a zero.  However, the real return is the "bx lr" above, so the
-    // return(0) is never executed and the function returns with the value
-    // you expect in R0.
-    //
-    return(0);
-}
-#endif
-
-//*****************************************************************************
-//
-// Wrapper function returning the state of PRIMASK (indicating whether
-// interrupts are enabled or disabled).
-//
-//*****************************************************************************
-#if defined(gcc)
-unsigned long __attribute__((naked))
-CPUprimask(void)
-{
-    unsigned long ulRet;
-
-    //
-    // Read PRIMASK and disable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    bx      lr\n"
-          : "=r" (ulRet));
-
-    //
-    // The return is handled in the inline assembly, but the compiler will
-    // still complain if there is not an explicit return here (despite the fact
-    // that this does not result in any code being produced because of the
-    // naked attribute).
-    //
-    return(ulRet);
-}
-#endif
-#if defined(ewarm)
-unsigned long
-CPUprimask(void)
-{
-    //
-    // Read PRIMASK and disable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n");
-
-    //
-    // "Warning[Pe940]: missing return statement at end of non-void function"
-    // is suppressed here to avoid putting a "bx lr" in the inline assembly
-    // above and a superfluous return statement here.
-    //
-#pragma diag_suppress=Pe940
-}
-#pragma diag_default=Pe940
-#endif
-#if defined(ccs)
-unsigned long
-CPUprimask(void)
-{
-    //
-    // Read PRIMASK and disable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    bx      lr\n");
-
-    //
-    // The following keeps the compiler happy, because it wants to see a
-    // return value from this function.  It will generate code to return
-    // a zero.  However, the real return is the "bx lr" above, so the
-    // return(0) is never executed and the function returns with the value
-    // you expect in R0.
-    //
-    return(0);
-}
-#endif
-
-//*****************************************************************************
-//
-// Wrapper function for the CPSIE instruction.  Returns the state of PRIMASK
-// on entry.
-//
-//*****************************************************************************
-#if defined(gcc)
-unsigned long __attribute__((naked))
-CPUcpsie(void)
-{
-    unsigned long ulRet;
-
-    //
-    // Read PRIMASK and enable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    cpsie   i\n"
-          "    dsb      \n"
-          "    isb      \n"
-          "    bx      lr\n"
-          : "=r" (ulRet));
-
-    //
-    // The return is handled in the inline assembly, but the compiler will
-    // still complain if there is not an explicit return here (despite the fact
-    // that this does not result in any code being produced because of the
-    // naked attribute).
-    //
-    return(ulRet);
-}
-#endif
-#if defined(ewarm)
-unsigned long
-CPUcpsie(void)
-{
-    //
-    // Read PRIMASK and enable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    cpsie   i\n"
-          "    dsb      \n"
-          "    isb      \n");
-
-    //
-    // "Warning[Pe940]: missing return statement at end of non-void function"
-    // is suppressed here to avoid putting a "bx lr" in the inline assembly
-    // above and a superfluous return statement here.
-    //
-#pragma diag_suppress=Pe940
-}
-#pragma diag_default=Pe940
-#endif
-#if defined(ccs)
-unsigned long
-CPUcpsie(void)
-{
-    //
-    // Read PRIMASK and enable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    cpsie   i\n"
-          "    dsb      \n"
-          "    isb      \n"
-          "    bx      lr\n");
-
-    //
-    // The following keeps the compiler happy, because it wants to see a
-    // return value from this function.  It will generate code to return
-    // a zero.  However, the real return is the "bx lr" above, so the
-    // return(0) is never executed and the function returns with the value
-    // you expect in R0.
-    //
-    return(0);
-}
-#endif
-
-//*****************************************************************************
-//
-// Wrapper function for the WFI instruction.
-//
-//*****************************************************************************
-#if defined(gcc)
-void __attribute__((naked))
-CPUwfi(void)
-{
-    //
-    // Wait for the next interrupt.
-    //
-    __asm("    dsb      \n"
-          "    isb      \n"
-          "    wfi      \n"
-          "    bx      lr\n");
-}
-#endif
-#if defined(ewarm)
-void
-CPUwfi(void)
-{
-    //
-    // Wait for the next interrupt.
-    //
-    __asm("    dsb      \n"
-          "    isb      \n"
-          "    wfi      \n");
-}
-#endif
-#if defined(ccs)
-void
-CPUwfi(void)
-{
-    //
-    // Wait for the next interrupt.
-    //
-    __asm("    dsb      \n"
-          "    isb      \n"
-          "    wfi      \n");
-}
-#endif
-
-//*****************************************************************************
-//
-// Wrapper function for writing the BASEPRI register.
-//
-//*****************************************************************************
-#if defined(gcc)
-void __attribute__((naked))
-CPUbasepriSet(unsigned long ulNewBasepri)
-{
-
-    //
-    // Set the BASEPRI register
-    //
-    __asm("    msr     BASEPRI, r0\n"
-          "    dsb      \n"
-          "    isb      \n"
-          "    bx      lr\n");
-}
-#endif
-#if defined(ewarm)
-void
-CPUbasepriSet(unsigned long ulNewBasepri)
-{
-    //
-    // Set the BASEPRI register
-    //
-    __asm("    msr     BASEPRI, r0\n"
-          "    dsb      \n"
-          "    isb      \n");
-}
-#endif
-#if defined(ccs)
-void
-CPUbasepriSet(unsigned long ulNewBasepri)
-{
-    //
-    // Set the BASEPRI register
-    //
-    __asm("    msr     BASEPRI, r0\n"
-          "    dsb      \n"
-          "    isb      \n");
-}
-#endif
-
-//*****************************************************************************
-//
-// Wrapper function for reading the BASEPRI register.
-//
-//*****************************************************************************
-#if defined(gcc)
-unsigned long __attribute__((naked))
-CPUbasepriGet(void)
-{
-    unsigned long ulRet;
-
-    //
-    // Read BASEPRI
-    //
-    __asm("    mrs     r0, BASEPRI\n"
-          "    bx      lr\n"
-          : "=r" (ulRet));
-
-    //
-    // The return is handled in the inline assembly, but the compiler will
-    // still complain if there is not an explicit return here (despite the fact
-    // that this does not result in any code being produced because of the
-    // naked attribute).
-    //
-    return(ulRet);
-}
-#endif
-#if defined(ewarm)
-unsigned long
-CPUbasepriGet(void)
-{
-    //
-    // Read BASEPRI
-    //
-    __asm("    mrs     r0, BASEPRI\n");
-
-    //
-    // "Warning[Pe940]: missing return statement at end of non-void function"
-    // is suppressed here to avoid putting a "bx lr" in the inline assembly
-    // above and a superfluous return statement here.
-    //
-#pragma diag_suppress=Pe940
-}
-#pragma diag_default=Pe940
-#endif
-#if defined(ccs)
-unsigned long
-CPUbasepriGet(void)
-{
-    //
-    // Read BASEPRI
-    //
-    __asm("    mrs     r0, BASEPRI\n"
-          "    bx      lr\n");
-
-    //
-    // The following keeps the compiler happy, because it wants to see a
-    // return value from this function.  It will generate code to return
-    // a zero.  However, the real return is the "bx lr" above, so the
-    // return(0) is never executed and the function returns with the value
-    // you expect in R0.
-    //
-    return(0);
-}
-#endif
diff --git a/cc3200/hal/cpu.h b/cc3200/hal/cpu.h
deleted file mode 100644
index 4a0fc0dcc..000000000
--- a/cc3200/hal/cpu.h
+++ /dev/null
@@ -1,75 +0,0 @@
-//*****************************************************************************
-//
-//  cpu.h
-//
-//  Prototypes for the CPU instruction wrapper functions.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __CPU_H__
-#define __CPU_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Prototypes.
-//
-//*****************************************************************************
-extern unsigned long CPUcpsid(void);
-extern unsigned long CPUcpsie(void);
-extern unsigned long CPUprimask(void);
-extern void CPUwfi(void);
-extern unsigned long CPUbasepriGet(void);
-extern void CPUbasepriSet(unsigned long ulNewBasepri);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __CPU_H__
diff --git a/cc3200/hal/crc.c b/cc3200/hal/crc.c
deleted file mode 100644
index 9ccb92c38..000000000
--- a/cc3200/hal/crc.c
+++ /dev/null
@@ -1,305 +0,0 @@
-//*****************************************************************************
-//
-//  crc.c
-//
-//  Driver for the CRC module.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup CRC_Cyclic_Redundancy_Check_api
-//! @{
-//
-//*****************************************************************************
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "inc/hw_dthe.h"
-#include "inc/hw_memmap.h"
-#include "inc/hw_types.h"
-#include "crc.h"
-#include "debug.h"
-
-//*****************************************************************************
-//
-//! Set the configuration of CRC functionality with the EC module.
-//!
-//! \param ui32Base is the base address of the EC module.
-//! \param ui32CRCConfig is the configuration of the CRC engine.
-//!
-//! This function configures the operation of the CRC engine within the EC
-//! module.  The configuration is specified with the \e ui32CRCConfig argument.
-//! It is the logical OR of any of the following options:
-//!
-//! CRC Initialization Value
-//! - \b EC_CRC_CFG_INIT_SEED - Initialize with seed value
-//! - \b EC_CRC_CFG_INIT_0 - Initialize to all '0s'
-//! - \b EC_CRC_CFG_INIT_1 - Initialize to all '1s'
-//!
-//! Input Data Size
-//! - \b EC_CRC_CFG_SIZE_8BIT - Input data size of 8 bits
-//! - \b EC_CRC_CFG_SIZE_32BIT - Input data size of 32 bits
-//!
-//! Post Process Reverse/Inverse
-//! - \b EC_CRC_CFG_RESINV - Result inverse enable
-//! - \b EC_CRC_CFG_OBR - Output reverse enable
-//!
-//! Input Bit Reverse
-//! - \b EC_CRC_CFG_IBR - Bit reverse enable
-//!
-//! Endian Control
-//! - \b EC_CRC_CFG_ENDIAN_SBHW - Swap byte in half-word
-//! - \b EC_CRC_CFG_ENDIAN_SHW - Swap half-word
-//!
-//! Operation Type
-//! - \b EC_CRC_CFG_TYPE_P8005 - Polynomial 0x8005
-//! - \b EC_CRC_CFG_TYPE_P1021 - Polynomial 0x1021
-//! - \b EC_CRC_CFG_TYPE_P4C11DB7 - Polynomial 0x4C11DB7
-//! - \b EC_CRC_CFG_TYPE_P1EDC6F41 - Polynomial 0x1EDC6F41
-//! - \b EC_CRC_CFG_TYPE_TCPCHKSUM - TCP checksum
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == DTHE_BASE);
-    ASSERT((ui32CRCConfig & CRC_CFG_INIT_SEED) ||
-           (ui32CRCConfig & CRC_CFG_INIT_0) ||
-           (ui32CRCConfig & CRC_CFG_INIT_1) ||
-           (ui32CRCConfig & CRC_CFG_SIZE_8BIT) ||
-           (ui32CRCConfig & CRC_CFG_SIZE_32BIT) ||
-           (ui32CRCConfig & CRC_CFG_RESINV) ||
-           (ui32CRCConfig & CRC_CFG_OBR) ||
-           (ui32CRCConfig & CRC_CFG_IBR) ||
-           (ui32CRCConfig & CRC_CFG_ENDIAN_SBHW) ||
-           (ui32CRCConfig & CRC_CFG_ENDIAN_SHW) ||
-           (ui32CRCConfig & CRC_CFG_TYPE_P8005) ||
-           (ui32CRCConfig & CRC_CFG_TYPE_P1021) ||
-           (ui32CRCConfig & CRC_CFG_TYPE_P4C11DB7) ||
-           (ui32CRCConfig & CRC_CFG_TYPE_P1EDC6F41) ||
-           (ui32CRCConfig & CRC_CFG_TYPE_TCPCHKSUM));
-
-    //
-    // Write the control register with the configuration.
-    //
-    HWREG(ui32Base + DTHE_O_CRC_CTRL) = ui32CRCConfig;
-}
-
-//*****************************************************************************
-//
-//! Write the seed value for CRC operations in the EC module.
-//!
-//! \param ui32Base is the base address of the EC module.
-//! \param ui32Seed is the seed value.
-//!
-//! This function writes the seed value for use with CRC operations in the
-//! EC module.  This value is the start value for CRC operations.  If this
-//! value is not written, then the residual seed from the previous operation
-//! is used as the starting value.
-//!
-//! \note The seed must be written only if \b EC_CRC_CFG_INIT_SEED is
-//! set with the CRCConfigSet() function.
-//
-//*****************************************************************************
-void
-CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == DTHE_BASE);
-
-    //
-    // Write the seed value to the seed register.
-    //
-    HWREG(ui32Base + DTHE_O_CRC_SEED) = ui32Seed;
-}
-
-//*****************************************************************************
-//
-//! Write data into the EC module for CRC operations.
-//!
-//! \param ui32Base is the base address of the EC module.
-//! \param ui32Data is the data to be written.
-//!
-//! This function writes either 8 or 32 bits of data into the EC module for
-//! CRC operations.  The distinction between 8 and 32 bits of data is made
-//! when the \b EC_CRC_CFG_SIZE_8BIT or \b EC_CRC_CFG_SIZE_32BIT flag
-//! is set using the CRCConfigSet() function.
-//!
-//! When writing 8 bits of data, ensure the data is in the least signficant
-//! byte position.  The remaining bytes should be written with zero.  For
-//! example, when writing 0xAB, \e ui32Data should be 0x000000AB.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == DTHE_BASE);
-
-    //
-    // Write the data
-    //
-    HWREG(DTHE_BASE + DTHE_O_CRC_DIN) = ui32Data;
-}
-
-//*****************************************************************************
-//
-//! Reads the result of a CRC operation in the EC module.
-//!
-//! \param ui32Base is the base address of the EC module.
-//!
-//! This function reads either the unmodified CRC result or the post
-//! processed CRC result from the EC module.  The post-processing options
-//! are selectable through \b EC_CRC_CFG_RESINV and \b EC_CRC_CFG_OBR
-//! parameters in the CRCConfigSet() function.
-//!
-//! \return The CRC result.
-//
-//*****************************************************************************
-uint32_t
-CRCResultRead(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == DTHE_BASE);
-
-    //
-    // return value.
-    //
-    return(HWREG(DTHE_BASE + DTHE_O_CRC_RSLT_PP));
-
-}
-
-//*****************************************************************************
-//
-//! Process data to generate a CRC with the EC module.
-//!
-//! \param ui32Base is the base address of the EC module.
-//! \param puiDataIn is a pointer to an array of data that is processed.
-//! \param ui32DataLength is the number of data items that are processed
-//! to produce the CRC.
-//! \param ui32Config the config parameter to determine the CRC mode
-//!
-//! This function processes an array of data to produce a CRC result.
-//! This function takes the CRC mode as the parameter.
-//!
-//! The data in the array pointed to be \e pui32DataIn is either an array
-//! of bytes or an array or words depending on the selection of the input
-//! data size options \b EC_CRC_CFG_SIZE_8BIT and
-//! \b EC_CRC_CFG_SIZE_32BIT.
-//!
-//! This function returns either the unmodified CRC result or the
-//! post- processed CRC result from the EC module.  The post-processing
-//! options are selectable through \b EC_CRC_CFG_RESINV and
-//! \b EC_CRC_CFG_OBR parameters.
-//!
-//! \return The CRC result.
-//
-//*****************************************************************************
-uint32_t
-CRCDataProcess(uint32_t ui32Base, void *puiDataIn,
-               uint32_t ui32DataLength, uint32_t ui32Config)
-{
-    uint8_t *pui8DataIn;
-    uint32_t *pui32DataIn;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == DTHE_BASE);
-
-    //
-    // See if the CRC is operating in 8-bit or 32-bit mode.
-    //
-    if(ui32Config & DTHE_CRC_CTRL_SIZE)
-    {
-        //
-        // The CRC is operating in 8-bit mode, so create an 8-bit pointer to
-        // the data.
-        //
-        pui8DataIn = (uint8_t *)puiDataIn;
-
-        //
-        // Loop through the input data.
-        //
-        while(ui32DataLength--)
-        {
-            //
-            // Write the next data byte.
-            //
-            HWREG(ui32Base + DTHE_O_CRC_DIN) = *pui8DataIn++;
-        }
-    }
-    else
-    {
-        //
-        // The CRC is operating in 32-bit mode, so loop through the input data.
-        //
-    	pui32DataIn = (uint32_t *)puiDataIn;
-        while(ui32DataLength--)
-        {
-            //
-            // Write the next data word.
-            //
-            HWREG(ui32Base + DTHE_O_CRC_DIN) = *pui32DataIn++;
-        }
-    }
-
-    //
-    // Return the result.
-    //
-    return(CRCResultRead(ui32Base));
-}
-
-
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
diff --git a/cc3200/hal/crc.h b/cc3200/hal/crc.h
deleted file mode 100644
index c0858bb1b..000000000
--- a/cc3200/hal/crc.h
+++ /dev/null
@@ -1,98 +0,0 @@
-//*****************************************************************************
-//
-//  crc.h
-//
-//  Defines and Macros for CRC module.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __DRIVERLIB_CRC_H__
-#define __DRIVERLIB_CRC_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// The following defines are used in the ui32Config argument of the
-// ECConfig function.
-//
-//*****************************************************************************
-#define CRC_CFG_INIT_SEED       0x00000000  // Initialize with seed
-#define CRC_CFG_INIT_0          0x00004000  // Initialize to all '0s'
-#define CRC_CFG_INIT_1          0x00006000  // Initialize to all '1s'
-#define CRC_CFG_SIZE_8BIT       0x00001000  // Input Data Size
-#define CRC_CFG_SIZE_32BIT      0x00000000  // Input Data Size
-#define CRC_CFG_RESINV          0x00000200  // Result Inverse Enable
-#define CRC_CFG_OBR             0x00000100  // Output Reverse Enable
-#define CRC_CFG_IBR             0x00000080  // Bit reverse enable
-#define CRC_CFG_ENDIAN_SBHW     0x00000000  // Swap byte in half-word
-#define CRC_CFG_ENDIAN_SHW      0x00000010  // Swap half-word
-#define CRC_CFG_TYPE_P8005      0x00000000  // Polynomial 0x8005
-#define CRC_CFG_TYPE_P1021      0x00000001  // Polynomial 0x1021
-#define CRC_CFG_TYPE_P4C11DB7   0x00000002  // Polynomial 0x4C11DB7
-#define CRC_CFG_TYPE_P1EDC6F41  0x00000003  // Polynomial 0x1EDC6F41
-#define CRC_CFG_TYPE_TCPCHKSUM  0x00000008  // TCP checksum
-
-//*****************************************************************************
-//
-// Function prototypes.
-//
-//*****************************************************************************
-extern void CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig);
-extern uint32_t CRCDataProcess(uint32_t ui32Base, void *puiDataIn,
-               uint32_t ui32DataLength, uint32_t ui32Config);
-extern void CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data);
-extern uint32_t CRCResultRead(uint32_t ui32Base);
-extern void CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed);
-
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __DRIVERLIB_CRC_H__
diff --git a/cc3200/hal/debug.h b/cc3200/hal/debug.h
deleted file mode 100644
index 1f6556704..000000000
--- a/cc3200/hal/debug.h
+++ /dev/null
@@ -1,63 +0,0 @@
-//*****************************************************************************
-//
-//  debug.h
-//
-//  Macros for assisting debug of the driver library.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-#ifndef __DEBUG_H__
-#define __DEBUG_H__
-
-#include "assert.h"
-
-//*****************************************************************************
-//
-// Prototype for the function that is called when an invalid argument is passed
-// to an API.  This is only used when doing a DEBUG build.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-// The ASSERT macro, which does the actual assertion checking.  Typically, this
-// will be for procedure arguments.
-//
-//*****************************************************************************
-#if defined(DEBUG) && !defined(BOOTLOADER)
-#define ASSERT(expr)        assert(expr)
-#else
-#define ASSERT(expr)        (void)(expr)
-#endif
-
-#endif // __DEBUG_H__
diff --git a/cc3200/hal/des.c b/cc3200/hal/des.c
deleted file mode 100644
index 1620e6baf..000000000
--- a/cc3200/hal/des.c
+++ /dev/null
@@ -1,887 +0,0 @@
-//*****************************************************************************

-//

-//  des.c

-//

-//  Driver for the DES data transformation.

-//

-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/

-//

-//

-//  Redistribution and use in source and binary forms, with or without

-//  modification, are permitted provided that the following conditions

-//  are met:

-//

-//    Redistributions of source code must retain the above copyright

-//    notice, this list of conditions and the following disclaimer.

-//

-//    Redistributions in binary form must reproduce the above copyright

-//    notice, this list of conditions and the following disclaimer in the

-//    documentation and/or other materials provided with the

-//    distribution.

-//

-//    Neither the name of Texas Instruments Incorporated nor the names of

-//    its contributors may be used to endorse or promote products derived

-//    from this software without specific prior written permission.

-//

-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-//

-//*****************************************************************************

-

-//*****************************************************************************

-//

-//! \addtogroup DES_Data_Encryption_Standard_api

-//! @{

-//

-//*****************************************************************************

-

-#include <stdbool.h>

-#include <stdint.h>

-#include "inc/hw_des.h"

-#include "inc/hw_dthe.h"

-#include "inc/hw_ints.h"

-#include "inc/hw_memmap.h"

-#include "inc/hw_types.h"

-#include "debug.h"

-#include "des.h"

-#include "interrupt.h"

-

-

-//*****************************************************************************

-//

-//! Configures the DES module for operation.

-//!

-//! \param ui32Base is the base address of the DES module.

-//! \param ui32Config is the configuration of the DES module.

-//!

-//! This function configures the DES module for operation.

-//!

-//! The \e ui32Config parameter is a bit-wise OR of a number of configuration

-//! flags. The valid flags are grouped below based on their function.

-//!

-//! The direction of the operation is specified with one of the following two

-//! flags.  Only one is permitted.

-//!

-//! - \b DES_CFG_DIR_ENCRYPT - Encryption

-//! - \b DES_CFG_DIR_DECRYPT - Decryption

-//!

-//! The operational mode of the DES engine is specified with one of the

-//! following flags. Only one is permitted.

-//!

-//! - \b DES_CFG_MODE_ECB - Electronic Codebook Mode

-//! - \b DES_CFG_MODE_CBC - Cipher-Block Chaining Mode

-//! - \b DES_CFG_MODE_CFB - Cipher Feedback Mode

-//!

-//! The selection of single DES or triple DES is specified with one of the

-//! following two flags. Only one is permitted.

-//!

-//! - \b DES_CFG_SINGLE - Single DES

-//! - \b DES_CFG_TRIPLE - Triple DES

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-DESConfigSet(uint32_t ui32Base, uint32_t ui32Config)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == DES_BASE);

-

-    //

-    // Backup the save context field.

-    //

-    ui32Config |= (HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT);

-

-    //

-    // Write the control register.

-    //

-    HWREG(ui32Base + DES_O_CTRL) = ui32Config;

-}

-

-//*****************************************************************************

-//

-//! Sets the key used for DES operations.

-//!

-//! \param ui32Base is the base address of the DES module.

-//! \param pui8Key is a pointer to an array that holds the key

-//!

-//! This function sets the key used for DES operations.

-//!

-//! \e pui8Key should be 64 bits long (2 words) if single DES is being used or

-//! 192 bits (6 words) if triple DES is being used.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-DESKeySet(uint32_t ui32Base, uint8_t *pui8Key)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == DES_BASE);

-

-    //

-    // Write the first part of the key.

-    //

-    HWREG(ui32Base + DES_O_KEY1_L) =  * ((uint32_t *)(pui8Key + 0));

-    HWREG(ui32Base + DES_O_KEY1_H) = * ((uint32_t *)(pui8Key + 4));

-

-    //

-    // If we are performing triple DES, then write the key registers for

-    // the second and third rounds.

-    //

-    if(HWREG(ui32Base + DES_O_CTRL) & DES_CFG_TRIPLE)

-    {

-        HWREG(ui32Base + DES_O_KEY2_L) = * ((uint32_t *)(pui8Key + 8));

-        HWREG(ui32Base + DES_O_KEY2_H) = * ((uint32_t *)(pui8Key + 12));

-        HWREG(ui32Base + DES_O_KEY3_L) = * ((uint32_t *)(pui8Key + 16));

-        HWREG(ui32Base + DES_O_KEY3_H) = * ((uint32_t *)(pui8Key + 20));

-    }

-}

-

-//*****************************************************************************

-//

-//! Sets the initialization vector in the DES module.

-//!

-//! \param ui32Base is the base address of the DES module.

-//! \param pui8IVdata is a pointer to an array of 64 bits (2 words) of data to

-//! be written into the initialization vectors registers.

-//!

-//! This function sets the initialization vector in the DES module.  It returns

-//! true if the registers were successfully written.  If the context registers

-//! cannot be written at the time the function was called, then false is

-//! returned.

-//!

-//! \return True or false.

-//

-//*****************************************************************************

-bool

-DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == DES_BASE);

-

-    //

-    // Check to see if context registers can be overwritten.  If not, return

-    // false.

-    //

-    if((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT) == 0)

-    {

-        return(false);

-    }

-

-    //

-    // Write the initialization vector registers.

-    //

-    HWREG(ui32Base + DES_O_IV_L) =  *((uint32_t *) (pui8IVdata + 0));

-    HWREG(ui32Base + DES_O_IV_H) = *((uint32_t *) (pui8IVdata + 4));

-

-    //

-    // Return true to indicate the write was successful.

-    //

-    return(true);

-}

-

-//*****************************************************************************

-//

-//! Sets the crytographic data length in the DES module.

-//!

-//! \param ui32Base is the base address of the DES module.

-//! \param ui32Length is the length of the data in bytes.

-//!

-//! This function writes the cryptographic data length into the DES module.

-//! When this register is written, the engine is triggersed to start using

-//! this context.

-//!

-//! \note Data lengths up to (2^32 - 1) bytes are allowed.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == DES_BASE);

-

-    //

-    // Write the length register.

-    //

-    HWREG(ui32Base + DES_O_LENGTH) = ui32Length;

-}

-

-//*****************************************************************************

-//

-//! Reads plaintext/ciphertext from data registers without blocking

-//!

-//! \param ui32Base is the base address of the DES module.

-//! \param pui8Dest is a pointer to an array of 2 words.

-//! \param ui8Length the length can be from 1 to 8

-//!

-//! This function returns true if the data was ready when the function was

-//! called. If the data was not ready, false is returned.

-//!

-//! \return True or false.

-//

-//*****************************************************************************

-bool

-DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length)

-{

-	volatile uint32_t pui32Dest[2];

-	uint8_t ui8BytCnt;

-	uint8_t *pui8DestTemp;

-

-	//

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == DES_BASE);

-    if((ui8Length == 0)||(ui8Length>8))

-    {

-       	return(false);

-    }

-

-    //

-    // Check to see if the data is ready to be read.

-    //

-    if((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)

-    {

-        return(false);

-    }

-

-    //

-    // Read two words of data from the data registers.

-    //

-    pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L);

-    pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H);

-

-    //

-    //Copy the data to a block memory

-    //

-    pui8DestTemp = (uint8_t *)pui32Dest;

-    for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)

-    {

- 		*(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt);

-    }

-

-    //

-    // Return true to indicate a successful write.

-    //

-    return(true);

-}

-

-//*****************************************************************************

-//

-//! Reads plaintext/ciphertext from data registers with blocking.

-//!

-//! \param ui32Base is the base address of the DES module.

-//! \param pui8Dest is a pointer to an array of bytes.

-//! \param ui8Length the length can be from 1 to 8

-//!

-//! This function waits until the DES module is finished and encrypted or

-//! decrypted data is ready.  The output data is then stored in the pui8Dest

-//! array.

-//!

-//! \return None

-//

-//*****************************************************************************

-void

-DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length)

-{

-	volatile uint32_t pui32Dest[2];

-	uint8_t ui8BytCnt;

-	uint8_t *pui8DestTemp;

-

-	//

-	// Check the arguments.

-	//

-	ASSERT(ui32Base == DES_BASE);

-	if((ui8Length == 0)||(ui8Length>8))

-	{

-		return;

-	}

-    //

-    // Wait for data output to be ready.

-    //

-    while((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_OUTPUT_READY) == 0)

-    {

-    }

-

-    //

-    // Read two words of data from the data registers.

-    //

-    pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L);

-    pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H);

-

-    //

-    //Copy the data to a block memory

-    //

-    pui8DestTemp = (uint8_t *)pui32Dest;

-    for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)

-    {

-    	*(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt);

-    }

-}

-

-//*****************************************************************************

-//

-//! Writes plaintext/ciphertext to data registers without blocking

-//!

-//! \param ui32Base is the base address of the DES module.

-//! \param pui8Src is a pointer to an array of 2 words.

-//! \param ui8Length the length can be from 1 to 8

-//!

-//! This function returns false if the DES module is not ready to accept

-//! data.  It returns true if the data was written successfully.

-//!

-//! \return true or false.

-//

-//*****************************************************************************

-bool

-DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length)

-{

-

-    volatile uint32_t pui32Src[2]={0,0};

-    uint8_t ui8BytCnt;

-    uint8_t *pui8SrcTemp;

-

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == DES_BASE);

-

-    if((ui8Length == 0)||(ui8Length>8))

-    {

-            return(false);

-    }

-

-    //

-    // Check if the DES module is ready to encrypt or decrypt data.  If it

-    // is not, return false.

-    //

-    if(!(DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))))

-    {

-        return(false);

-    }

-

-    //

-    // Copy the data to a block memory

-    //

-    pui8SrcTemp = (uint8_t *)pui32Src;

-    for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)

-    {

-            *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt);

-    }

-

-    //

-    // Write the data.

-    //

-    HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0];

-    HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1];

-

-    //

-    // Return true to indicate a successful write.

-    //

-    return(true);

-}

-

-//*****************************************************************************

-//

-//! Writes plaintext/ciphertext to data registers without blocking

-//!

-//! \param ui32Base is the base address of the DES module.

-//! \param pui8Src is a pointer to an array of bytes.

-//! \param ui8Length the length can be from 1 to 8

-//!

-//! This function waits until the DES module is ready before writing the

-//! data contained in the pui8Src array.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length)

-{

-    volatile uint32_t pui32Src[2]={0,0};

-    uint8_t ui8BytCnt;

-    uint8_t *pui8SrcTemp;

-

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == DES_BASE);

-

-    if((ui8Length == 0)||(ui8Length>8))

-    {

-            return;

-    }

-

-    //

-    // Wait for the input ready bit to go high.

-    //

-    while(((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_INPUT_READY)) == 0)

-    {

-    }

-

-    //

-    //Copy the data to a block memory

-    //

-    pui8SrcTemp = (uint8_t *)pui32Src;

-    for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)

-    {

-            *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt);

-    }

-

-    //

-    // Write the data.

-    //

-    HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0];

-    HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1];

-}

-

-//*****************************************************************************

-//

-//! Processes blocks of data through the DES module.

-//!

-//! \param ui32Base is the base address of the DES module.

-//! \param pui8Src is a pointer to an array of words that contains the

-//! source data for processing.

-//! \param pui8Dest is a pointer to an array of words consisting of the

-//! processed data.

-//! \param ui32Length is the length of the cryptographic data in bytes.

-//! It must be a multiple of eight.

-//!

-//! This function takes the data contained in the pui8Src array and processes

-//! it using the DES engine.  The resulting data is stored in the

-//! pui8Dest array.  The function blocks until all of the data has been

-//! processed. If processing is successful, the function returns true.

-//!

-//! \note This functions assumes that the DES module has been configured,

-//! and initialization values and keys have been written.

-//!

-//! \return true or false.

-//

-//*****************************************************************************

-bool

-DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest,

-               uint32_t ui32Length)

-{

-    uint32_t ui32Count, ui32BlkCount, ui32ByteCount;

-

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == DES_BASE);

-    ASSERT((ui32Length % 8) == 0);

-

-    //

-    // Write the length register first. This triggers the engine to start

-    // using this context.

-    //

-    HWREG(ui32Base + DES_O_LENGTH) = ui32Length;

-

-

-    //

-    // Now loop until the blocks are written.

-    //

-    ui32BlkCount = ui32Length/8;

-    for(ui32Count = 0; ui32Count <ui32BlkCount; ui32Count ++)

-    {

-      //

-      // Check if the input ready is fine

-      //

-      while((DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)

-      {

-      }

-

-      //

-      // Write the data registers.

-      //

-      DESDataWriteNonBlocking(ui32Base, pui8Src + ui32Count*8 ,8);

-

-      //

-      // Wait for the output ready

-      //

-      while((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)

-      {

-      }

-

-      //

-      // Read the data registers.

-      //

-      DESDataReadNonBlocking(ui32Base, pui8Dest + ui32Count*8 ,8);

-    }

-

-    //

-    //Now handle the residue bytes

-    //

-    ui32ByteCount = ui32Length%8;

-    if(ui32ByteCount)

-    {

-      //

-      // Check if the input ready is fine

-      //

-      while((DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)

-      {

-      }

-      //

-      // Write the data registers.

-      //

-      DESDataWriteNonBlocking(ui32Base, pui8Src + (8*ui32BlkCount) ,

-                              ui32ByteCount);

-      //

-      // Wait for the output ready

-      //

-      while((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)

-      {

-      }

-

-      //

-      // Read the data registers.

-      //

-      DESDataReadNonBlocking(ui32Base, pui8Dest + (8*ui32BlkCount) ,

-                             ui32ByteCount);

-    }

-

-

-

-    //

-    // Return true to indicate the process was successful.

-    //

-    return(true);

-}

-

-//*****************************************************************************

-//

-//! Returns the current interrupt status of the DES module.

-//!

-//! \param ui32Base is the base address of the DES module.

-//! \param bMasked is \b false if the raw interrupt status is required and

-//! \b true if the masked interrupt status is required.

-//!

-//! This function gets the current interrupt status of the DES module.

-//! The value returned is a logical OR of the following values:

-//!

-//! - \b DES_INT_CONTEXT_IN - Context interrupt

-//! - \b DES_INT_DATA_IN - Data input interrupt

-//! - \b DES_INT_DATA_OUT_INT - Data output interrupt

-//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt

-//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt

-//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt

-//!

-//! \return A bit mask of the current interrupt status.

-//

-//*****************************************************************************

-uint32_t

-DESIntStatus(uint32_t ui32Base, bool bMasked)

-{

-   uint32_t ui32IntStatus;

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == DES_BASE);

-

-    //

-    // Read the status register and return the value.

-    //

-    if(bMasked)

-    {

-        ui32IntStatus = HWREG(ui32Base + DES_O_IRQSTATUS);

-        ui32IntStatus &= HWREG(ui32Base + DES_O_IRQENABLE);

-        ui32IntStatus |= ((HWREG(DTHE_BASE + DTHE_O_DES_MIS) & 0x7) << 16);

-

-        return(ui32IntStatus);

-    }

-    else

-    {

-        ui32IntStatus = HWREG(ui32Base + DES_O_IRQSTATUS);

-        ui32IntStatus |= ((HWREG(DTHE_BASE + DTHE_O_DES_MIS) & 0xD) << 16);

-        return(ui32IntStatus);

-    }

-}

-

-//*****************************************************************************

-//

-//! Enables interrupts in the DES module.

-//!

-//! \param ui32Base is the base address of the DES module.

-//! \param ui32IntFlags is a bit mask of the interrupts to be enabled.

-//!

-//! \e ui32IntFlags should be a logical OR of one or more of the following

-//! values:

-//!

-//! - \b DES_INT_CONTEXT_IN - Context interrupt

-//! - \b DES_INT_DATA_IN - Data input interrupt

-//! - \b DES_INT_DATA_OUT - Data output interrupt

-//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt

-//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt

-//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == DES_BASE);

-    ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) ||

-           (ui32IntFlags & DES_INT_DATA_IN) ||

-           (ui32IntFlags & DES_INT_DATA_OUT) ||

-           (ui32IntFlags & DES_INT_DMA_CONTEXT_IN) ||

-           (ui32IntFlags & DES_INT_DMA_DATA_IN) ||

-           (ui32IntFlags & DES_INT_DMA_DATA_OUT));

-

-    //

-    // Enable the interrupts from the flags.

-    //

-    HWREG(DTHE_BASE + DTHE_O_DES_IM)  &= ~((ui32IntFlags & 0x00070000) >> 16);

-    HWREG(ui32Base + DES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff;

-}

-

-//*****************************************************************************

-//

-//! Disables interrupts in the DES module.

-//!

-//! \param ui32Base is the base address of the DES module.

-//! \param ui32IntFlags is a bit mask of the interrupts to be disabled.

-//!

-//! This function disables interrupt sources in the DES module.

-//! \e ui32IntFlags should be a logical OR of one or more of the following

-//! values:

-//!

-//! - \b DES_INT_CONTEXT_IN - Context interrupt

-//! - \b DES_INT_DATA_IN - Data input interrupt

-//! - \b DES_INT_DATA_OUT - Data output interrupt

-//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt

-//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt

-//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == DES_BASE);

-    ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) ||

-           (ui32IntFlags & DES_INT_DATA_IN) ||

-           (ui32IntFlags & DES_INT_DATA_OUT) ||

-           (ui32IntFlags & DES_INT_DMA_CONTEXT_IN) ||

-           (ui32IntFlags & DES_INT_DMA_DATA_IN) ||

-           (ui32IntFlags & DES_INT_DMA_DATA_OUT));

-

-    //

-    // Clear the interrupts from the flags.

-    //

-    HWREG(DTHE_BASE + DTHE_O_AES_IM)  |= ((ui32IntFlags & 0x00070000) >> 16);

-    HWREG(ui32Base + DES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff);

-}

-

-//*****************************************************************************

-//

-//! Clears interrupts in the DES module.

-//!

-//! \param ui32Base is the base address of the DES module.

-//! \param ui32IntFlags is a bit mask of the interrupts to be disabled.

-//!

-//! This function disables interrupt sources in the DES module.

-//! \e ui32IntFlags should be a logical OR of one or more of the following

-//! values:

-//!

-//! - \b DES_INT_DMA_CONTEXT_IN - Context interrupt

-//! - \b DES_INT_DMA_DATA_IN - Data input interrupt

-//! - \b DES_INT_DMA_DATA_OUT - Data output interrupt

-//!

-//! \note The DMA done interrupts are the only interrupts that can be cleared.

-//! The remaining interrupts can be disabled instead using DESIntDisable().

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == DES_BASE);

-    ASSERT((ui32IntFlags & DES_INT_DMA_CONTEXT_IN) ||

-           (ui32IntFlags & DES_INT_DMA_DATA_IN) ||

-           (ui32IntFlags & DES_INT_DMA_DATA_OUT));

-

-    HWREG(DTHE_BASE + DTHE_O_DES_IC) = ((ui32IntFlags & 0x00070000) >> 16);

-}

-

-//*****************************************************************************

-//

-//! Registers an interrupt handler for the DES module.

-//!

-//! \param ui32Base is the base address of the DES module.

-//! \param pfnHandler is a pointer to the function to be called when the

-//! enabled DES interrupts occur.

-//!

-//! This function registers the interrupt handler in the interrupt vector

-//! table, and enables DES interrupts on the interrupt controller; specific DES

-//! interrupt sources must be enabled using DESIntEnable().  The interrupt

-//! handler being registered must clear the source of the interrupt using

-//! DESIntClear().

-//!

-//! If the application is using a static interrupt vector table stored in

-//! flash, then it is not necessary to register the interrupt handler this way.

-//! Instead, IntEnable() should be used to enable DES interrupts on the

-//! interrupt controller.

-//!

-//! \sa IntRegister() for important information about registering interrupt

-//! handlers.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void))

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == DES_BASE);

-

-    //

-    // Register the interrupt handler.

-    //

-    IntRegister(INT_DES, pfnHandler);

-

-    //

-    // Enable the interrupt.

-    //

-    IntEnable(INT_DES);

-}

-

-//*****************************************************************************

-//

-//! Unregisters an interrupt handler for the DES module.

-//!

-//! \param ui32Base is the base address of the DES module.

-//!

-//! This function unregisters the previously registered interrupt handler and

-//! disables the interrupt in the interrupt controller.

-//!

-//! \sa IntRegister() for important information about registering interrupt

-//! handlers.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-DESIntUnregister(uint32_t ui32Base)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == DES_BASE);

-

-    //

-    // Disable the interrupt.

-    //

-    IntDisable(INT_DES);

-

-    //

-    // Unregister the interrupt handler.

-    //

-    IntUnregister(INT_DES);

-}

-

-//*****************************************************************************

-//

-//! Enables DMA request sources in the DES module.

-//!

-//! \param ui32Base is the base address of the DES module.

-//! \param ui32Flags is a bit mask of the DMA requests to be enabled.

-//!

-//! This function enables DMA request sources in the DES module.  The

-//! \e ui32Flags parameter should be the logical OR of any of the following:

-//!

-//! - \b DES_DMA_CONTEXT_IN - Context In

-//! - \b DES_DMA_DATA_OUT - Data Out

-//! - \b DES_DMA_DATA_IN - Data In

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == DES_BASE);

-    ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) ||

-           (ui32Flags & DES_DMA_DATA_OUT) ||

-           (ui32Flags & DES_DMA_DATA_IN));

-

-    //

-    // Set the data in and data out DMA request enable bits.

-    //

-    HWREG(ui32Base + DES_O_SYSCONFIG) |= ui32Flags;

-}

-

-//*****************************************************************************

-//

-//! Disables DMA request sources in the DES module.

-//!

-//! \param ui32Base is the base address of the DES module.

-//! \param ui32Flags is a bit mask of the DMA requests to be disabled.

-//!

-//! This function disables DMA request sources in the DES module.  The

-//! \e ui32Flags parameter should be the logical OR of any of the following:

-//!

-//! - \b DES_DMA_CONTEXT_IN - Context In

-//! - \b DES_DMA_DATA_OUT - Data Out

-//! - \b DES_DMA_DATA_IN - Data In

-//!

-//! \return None.

-//

-//*****************************************************************************

-void

-DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags)

-{

-    //

-    // Check the arguments.

-    //

-    ASSERT(ui32Base == DES_BASE);

-    ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) ||

-           (ui32Flags & DES_DMA_DATA_OUT) ||

-           (ui32Flags & DES_DMA_DATA_IN));

-

-    //

-    // Disable the DMA sources.

-    //

-    HWREG(ui32Base + DES_O_SYSCONFIG) &= ~ui32Flags;

-}

-

-//*****************************************************************************

-//

-// Close the Doxygen group.

-//! @}

-//

-//*****************************************************************************

diff --git a/cc3200/hal/des.h b/cc3200/hal/des.h
deleted file mode 100644
index 3bee5e6c9..000000000
--- a/cc3200/hal/des.h
+++ /dev/null
@@ -1,143 +0,0 @@
-//*****************************************************************************
-//
-//  des.h
-//
-//  Defines and Macros for the DES module.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __DRIVERLIB_DES_H__
-#define __DRIVERLIB_DES_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// The following defines are used to specify the direction with the
-// ui32Config argument in the DESConfig() function.  Only one is permitted.
-//
-//*****************************************************************************
-#define DES_CFG_DIR_DECRYPT     0x00000000
-#define DES_CFG_DIR_ENCRYPT     0x00000004
-
-//*****************************************************************************
-//
-// The following defines are used to specify the operational with the
-// ui32Config argument in the DESConfig() function.  Only one is permitted.
-//
-//*****************************************************************************
-#define DES_CFG_MODE_ECB        0x00000000
-#define DES_CFG_MODE_CBC        0x00000010
-#define DES_CFG_MODE_CFB        0x00000020
-
-//*****************************************************************************
-//
-// The following defines are used to select between single DES and triple DES
-// with the ui32Config argument in the DESConfig() function.  Only one is
-// permitted.
-//
-//*****************************************************************************
-#define DES_CFG_SINGLE          0x00000000
-#define DES_CFG_TRIPLE          0x00000008
-
-//*****************************************************************************
-//
-// The following defines are used with the DESIntEnable(), DESIntDisable() and
-// DESIntStatus() functions.
-//
-//*****************************************************************************
-#define DES_INT_CONTEXT_IN      0x00000001
-#define DES_INT_DATA_IN         0x00000002
-#define DES_INT_DATA_OUT        0x00000004
-#define DES_INT_DMA_CONTEXT_IN  0x00010000
-#define DES_INT_DMA_DATA_IN     0x00020000
-#define DES_INT_DMA_DATA_OUT    0x00040000
-
-//*****************************************************************************
-//
-// The following defines are used with the DESEnableDMA() and DESDisableDMA()
-// functions.
-//
-//*****************************************************************************
-#define DES_DMA_CONTEXT_IN      0x00000080
-#define DES_DMA_DATA_OUT        0x00000040
-#define DES_DMA_DATA_IN         0x00000020
-
-//*****************************************************************************
-//
-// API Function prototypes
-//
-//*****************************************************************************
-extern void DESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
-extern void DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest,
-                        uint8_t ui8Length);
-extern bool DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest,
-                                   uint8_t ui8Length);
-extern bool DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src,
-                           uint8_t *pui8Dest, uint32_t ui32Length);
-extern void DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src,
-                         uint8_t ui8Length);
-extern bool DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src,
-                                    uint8_t ui8Length);
-extern void DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
-extern void DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
-extern void DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
-extern void DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
-extern void DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
-extern void DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
-extern uint32_t DESIntStatus(uint32_t ui32Base, bool bMasked);
-extern void DESIntUnregister(uint32_t ui32Base);
-extern bool DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata);
-extern void DESKeySet(uint32_t ui32Base, uint8_t *pui8Key);
-extern void DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif //  __DRIVERLIB_DES_H__
diff --git a/cc3200/hal/fault_registers.h b/cc3200/hal/fault_registers.h
deleted file mode 100644
index ade516b9e..000000000
--- a/cc3200/hal/fault_registers.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the MicroPython project, http://micropython.org/
- *
- * The MIT License (MIT)
- *
- * Copyright (c) 2015 Daniel Campora
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef FAULT_REGISTERS_H_
-#define FAULT_REGISTERS_H_
-
-
-typedef struct
-{
-    uint32_t    IERR        :1;
-    uint32_t    DERR        :1;
-    uint32_t                :1;
-    uint32_t    MUSTKE      :1;
-    uint32_t    MSTKE       :1;
-    uint32_t    MLSPERR     :1;
-    uint32_t                :1;
-    uint32_t    MMARV       :1;
-    uint32_t    IBUS        :1;
-    uint32_t    PRECISE     :1;
-    uint32_t    IMPRE       :1;
-    uint32_t    BUSTKE      :1;
-    uint32_t    BSTKE       :1;
-    uint32_t    BLSPERR     :1;
-    uint32_t                :1;
-    uint32_t    BFARV       :1;
-    uint32_t    UNDEF       :1;
-    uint32_t    INVSTAT     :1;
-    uint32_t    INVCP       :1;
-    uint32_t    NOCP        :1;
-    uint32_t                :4;
-    uint32_t    UNALIGN     :1;
-    uint32_t    DIVO0       :1;
-    uint32_t                :6;
-
-}_CFSR_t;
-
-
-typedef struct
-{
-
-    uint32_t    DBG         :1;
-    uint32_t    FORCED      :1;
-    uint32_t                :28;
-    uint32_t    VECT        :1;
-    uint32_t                :1;
-
-}_HFSR_t;
-
-
-#endif /* FAULT_REGISTERS_H_ */
diff --git a/cc3200/hal/gpio.c b/cc3200/hal/gpio.c
deleted file mode 100644
index 59aa71aa5..000000000
--- a/cc3200/hal/gpio.c
+++ /dev/null
@@ -1,706 +0,0 @@
-//*****************************************************************************
-//
-//  gpio.c
-//
-//  Driver for the GPIO module.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup GPIO_General_Purpose_InputOutput_api
-//! @{
-//
-//*****************************************************************************
-
-#include "inc/hw_types.h"
-#include "inc/hw_gpio.h"
-#include "inc/hw_ints.h"
-#include "inc/hw_memmap.h"
-#include "inc/hw_common_reg.h"
-#include "debug.h"
-#include "gpio.h"
-#include "interrupt.h"
-
-
-//*****************************************************************************
-//
-//! \internal
-//! Checks a GPIO base address.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//!
-//! This function determines if a GPIO port base address is valid.
-//!
-//! \return Returns \b true if the base address is valid and \b false
-//! otherwise.
-//
-//*****************************************************************************
-#if defined(DEBUG) && !defined(BOOTLOADER)
-static tBoolean
-GPIOBaseValid(unsigned long ulPort)
-{
-    return((ulPort == GPIOA0_BASE) ||
-           (ulPort == GPIOA1_BASE) ||
-           (ulPort == GPIOA2_BASE) ||
-           (ulPort == GPIOA3_BASE) ||             
-           (ulPort == GPIOA4_BASE));
-}
-#else
-#define GPIOBaseValid(ulPort)         (ulPort)
-#endif
-
-//*****************************************************************************
-//
-//! \internal
-//! Gets the GPIO interrupt number.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//!
-//! Given a GPIO base address, returns the corresponding interrupt number.
-//!
-//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid.
-//
-//*****************************************************************************
-static long
-GPIOGetIntNumber(unsigned long ulPort)
-{
-    unsigned int ulInt;
-
-    //
-    // Determine the GPIO interrupt number for the given module.
-    //
-    switch(ulPort)
-    {
-        case GPIOA0_BASE:
-        {
-            ulInt = INT_GPIOA0;
-            break;
-        }
-
-        case GPIOA1_BASE:
-        {
-            ulInt = INT_GPIOA1;
-            break;
-        }
-
-        case GPIOA2_BASE:
-        {
-            ulInt = INT_GPIOA2;
-            break;
-        }
-
-        case GPIOA3_BASE:
-        {
-            ulInt = INT_GPIOA3;
-            break;
-        }
-
-        default:
-        {
-            return(-1);
-        }
-    }
-
-    //
-    // Return GPIO interrupt number.
-    //
-    return(ulInt);
-}
-
-//*****************************************************************************
-//
-//! Sets the direction and mode of the specified pin(s).
-//!
-//! \param ulPort is the base address of the GPIO port
-//! \param ucPins is the bit-packed representation of the pin(s).
-//! \param ulPinIO is the pin direction and/or mode.
-//!
-//! This function will set the specified pin(s) on the selected GPIO port
-//! as either an input or output under software control, or it will set the
-//! pin to be under hardware control.
-//!
-//! The parameter \e ulPinIO is an enumerated data type that can be one of
-//! the following values:
-//!
-//! - \b GPIO_DIR_MODE_IN
-//! - \b GPIO_DIR_MODE_OUT
-//!
-//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as
-//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin
-//! will be programmed as a software controlled output.
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note GPIOPadConfigSet() must also be used to configure the corresponding
-//! pad(s) in order for them to propagate the signal to/from the GPIO.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
-               unsigned long ulPinIO)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ulPort));
-    ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT));
-
-    //
-    // Set the pin direction and mode.
-    //
-    HWREG(ulPort + GPIO_O_GPIO_DIR) = ((ulPinIO & 1) ?
-                                  (HWREG(ulPort + GPIO_O_GPIO_DIR) | ucPins) :
-                                  (HWREG(ulPort + GPIO_O_GPIO_DIR) & ~(ucPins)));
-}
-
-//*****************************************************************************
-//
-//! Gets the direction and mode of a pin.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPin is the pin number.
-//!
-//! This function gets the direction and control mode for a specified pin on
-//! the selected GPIO port.  The pin can be configured as either an input or
-//! output under software control, or it can be under hardware control.  The
-//! type of control and direction are returned as an enumerated data type.
-//!
-//! \return Returns one of the enumerated data types described for
-//! GPIODirModeSet().
-//
-//*****************************************************************************
-unsigned long
-GPIODirModeGet(unsigned long ulPort, unsigned char ucPin)
-{
-    unsigned long ulDir;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ulPort));
-
-    //
-    // Return the pin direction
-    //
-    ulDir = HWREG(ulPort + GPIO_O_GPIO_DIR);
-    return(((ulDir & ucPin) ? 1 : 0));
-}
-
-//*****************************************************************************
-//
-//! Sets the interrupt type for the specified pin(s).
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//! \param ulIntType specifies the type of interrupt trigger mechanism.
-//!
-//! This function sets up the various interrupt trigger mechanisms for the
-//! specified pin(s) on the selected GPIO port.
-//!
-//! The parameter \e ulIntType is an enumerated data type that can be one of
-//! the following values:
-//!
-//! - \b GPIO_FALLING_EDGE
-//! - \b GPIO_RISING_EDGE
-//! - \b GPIO_BOTH_EDGES
-//! - \b GPIO_LOW_LEVEL
-//! - \b GPIO_HIGH_LEVEL
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note In order to avoid any spurious interrupts, the user must
-//! ensure that the GPIO inputs remain stable for the duration of
-//! this function.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
-               unsigned long ulIntType)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ulPort));
-    ASSERT((ulIntType == GPIO_FALLING_EDGE) ||
-           (ulIntType == GPIO_RISING_EDGE) || (ulIntType == GPIO_BOTH_EDGES) ||
-           (ulIntType == GPIO_LOW_LEVEL) || (ulIntType == GPIO_HIGH_LEVEL));
-
-    //
-    // Set the pin interrupt type.
-    //
-    HWREG(ulPort + GPIO_O_GPIO_IBE) = ((ulIntType & 1) ?
-                                  (HWREG(ulPort + GPIO_O_GPIO_IBE) | ucPins) :
-                                  (HWREG(ulPort + GPIO_O_GPIO_IBE) & ~(ucPins)));
-    HWREG(ulPort + GPIO_O_GPIO_IS) = ((ulIntType & 2) ?
-                                 (HWREG(ulPort + GPIO_O_GPIO_IS) | ucPins) :
-                                 (HWREG(ulPort + GPIO_O_GPIO_IS) & ~(ucPins)));
-    HWREG(ulPort + GPIO_O_GPIO_IEV) = ((ulIntType & 4) ?
-                                  (HWREG(ulPort + GPIO_O_GPIO_IEV) | ucPins) :
-                                  (HWREG(ulPort + GPIO_O_GPIO_IEV) & ~(ucPins)));
-}
-
-//*****************************************************************************
-//
-//! Gets the interrupt type for a pin.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPin is the pin number.
-//!
-//! This function gets the interrupt type for a specified pin on the selected
-//! GPIO port.  The pin can be configured as a falling edge, rising edge, or
-//! both edge detected interrupt, or it can be configured as a low level or
-//! high level detected interrupt.  The type of interrupt detection mechanism
-//! is returned as an enumerated data type.
-//!
-//! \return Returns one of the enumerated data types described for
-//! GPIOIntTypeSet().
-//
-//*****************************************************************************
-unsigned long
-GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin)
-{
-    unsigned long ulIBE, ulIS, ulIEV;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ulPort));
-
-    //
-    // Return the pin interrupt type.
-    //
-    ulIBE = HWREG(ulPort + GPIO_O_GPIO_IBE);
-    ulIS = HWREG(ulPort + GPIO_O_GPIO_IS);
-    ulIEV = HWREG(ulPort + GPIO_O_GPIO_IEV);
-    return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) |
-           ((ulIEV & ucPin) ? 4 : 0));
-}
-
-//*****************************************************************************
-//
-//! Enables the specified GPIO interrupts.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ulIntFlags is the bit mask of the interrupt sources to enable.
-//!
-//! This function enables the indicated GPIO interrupt sources.  Only the
-//! sources that are enabled can be reflected to the processor interrupt;
-//! disabled sources have no effect on the processor.
-//!
-//! The \e ulIntFlags parameter is the logical OR of any of the following:
-//!
-//! - \b GPIO_INT_DMA   - interrupt due to GPIO triggered DMA Done
-//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0.
-//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1.
-//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2.
-//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3.
-//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4.
-//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5.
-//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6.
-//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ulPort));
-
-    //
-    // Enable the interrupts.
-    //
-    HWREG(ulPort + GPIO_O_GPIO_IM) |= ulIntFlags;
-}
-
-//*****************************************************************************
-//
-//! Disables the specified GPIO interrupts.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ulIntFlags is the bit mask of the interrupt sources to disable.
-//!
-//! This function disables the indicated GPIO interrupt sources.  Only the
-//! sources that are enabled can be reflected to the processor interrupt;
-//! disabled sources have no effect on the processor.
-//!
-//! The \e ulIntFlags parameter is the logical OR of any of the following:
-//!
-//! - \b GPIO_INT_DMA   - interrupt due to GPIO triggered DMA Done
-//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0.
-//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1.
-//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2.
-//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3.
-//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4.
-//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5.
-//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6.
-//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ulPort));
-
-    //
-    // Disable the interrupts.
-    //
-    HWREG(ulPort + GPIO_O_GPIO_IM) &= ~(ulIntFlags);
-}
-
-//*****************************************************************************
-//
-//! Gets interrupt status for the specified GPIO port.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param bMasked specifies whether masked or raw interrupt status is
-//! returned.
-//!
-//! If \e bMasked is set as \b true, then the masked interrupt status is
-//! returned; otherwise, the raw interrupt status will be returned.
-//!
-//! \return Returns the current interrupt status, enumerated as a bit field of
-//! values described in GPIOIntEnable().
-//
-//*****************************************************************************
-long
-GPIOIntStatus(unsigned long ulPort, tBoolean bMasked)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ulPort));
-
-    //
-    // Return the interrupt status.
-    //
-    if(bMasked)
-    {
-        return(HWREG(ulPort + GPIO_O_GPIO_MIS));
-    }
-    else
-    {
-        return(HWREG(ulPort + GPIO_O_GPIO_RIS));
-    }
-}
-
-//*****************************************************************************
-//
-//! Clears the interrupt for the specified pin(s).
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
-//!
-//! Clears the interrupt for the specified pin(s).
-//!
-//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
-//! parameter to GPIOIntEnable().
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ulPort));
-
-    //
-    // Clear the interrupts.
-    //
-    HWREG(ulPort + GPIO_O_GPIO_ICR) = ulIntFlags;
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for a GPIO port.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling
-//! function.
-//!
-//! This function will ensure that the interrupt handler specified by
-//! \e pfnIntHandler is called when an interrupt is detected from the selected
-//! GPIO port.  This function will also enable the corresponding GPIO interrupt
-//! in the interrupt controller; individual pin interrupts and interrupt
-//! sources must be enabled with GPIOIntEnable().
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void))
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ulPort));
-
-    //
-    // Get the interrupt number associated with the specified GPIO.
-    //
-    ulPort = GPIOGetIntNumber(ulPort);
-
-    //
-    // Register the interrupt handler.
-    //
-    IntRegister(ulPort, pfnIntHandler);
-
-    //
-    // Enable the GPIO interrupt.
-    //
-    IntEnable(ulPort);
-}
-
-//*****************************************************************************
-//
-//! Removes an interrupt handler for a GPIO port.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//!
-//! This function will unregister the interrupt handler for the specified
-//! GPIO port.  This function will also disable the corresponding
-//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts
-//! and interrupt sources must be disabled with GPIOIntDisable().
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOIntUnregister(unsigned long ulPort)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ulPort));
-
-    //
-    // Get the interrupt number associated with the specified GPIO.
-    //
-    ulPort = GPIOGetIntNumber(ulPort);
-
-    //
-    // Disable the GPIO interrupt.
-    //
-    IntDisable(ulPort);
-
-    //
-    // Unregister the interrupt handler.
-    //
-    IntUnregister(ulPort);
-}
-
-//*****************************************************************************
-//
-//! Reads the values present of the specified pin(s).
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! The values at the specified pin(s) are read, as specified by \e ucPins.
-//! Values are returned for both input and output pin(s), and the value
-//! for pin(s) that are not specified by \e ucPins are set to 0.
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return Returns a bit-packed byte providing the state of the specified
-//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents
-//! GPIO port pin 1, and so on.  Any bit that is not specified by \e ucPins
-//! is returned as a 0.  Bits 31:8 should be ignored.
-//
-//*****************************************************************************
-long
-GPIOPinRead(unsigned long ulPort, unsigned char ucPins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ulPort));
-
-    //
-    // Return the pin value(s).
-    //
-    return(HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2))));
-}
-
-//*****************************************************************************
-//
-//! Writes a value to the specified pin(s).
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//! \param ucVal is the value to write to the pin(s).
-//!
-//! Writes the corresponding bit values to the output pin(s) specified by
-//! \e ucPins.  Writing to a pin configured as an input pin has no effect.
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ulPort));
-
-    //
-    // Write the pins.
-    //
-    HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2))) = ucVal;
-}
-
-//*****************************************************************************
-//
-//! Enables a GPIO port as a trigger to start a DMA transaction.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//!
-//! This function enables a GPIO port to be used as a trigger to start a uDMA
-//! transaction. The GPIO pin will still generate interrupts if the interrupt is
-//! enabled for the selected pin.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIODMATriggerEnable(unsigned long ulPort)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ulPort));
-
-    //
-    // Set the pin as a DMA trigger.
-    //
-    if(ulPort == GPIOA0_BASE)
-    {
-      HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x1;
-    }
-    else if(ulPort == GPIOA1_BASE)
-    {
-      HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x2;
-    }
-    else if(ulPort == GPIOA2_BASE)
-    {
-      HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x4;
-    }
-    else if(ulPort == GPIOA3_BASE)
-    {
-      HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x8;
-    }
-}
-
-//*****************************************************************************
-//
-//! Disables a GPIO port as a trigger to start a DMA transaction.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//!
-//! This function disables a GPIO port to be used as a trigger to start a uDMA
-//! transaction.  This function can be used to disable this feature if it was
-//! enabled via a call to GPIODMATriggerEnable().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIODMATriggerDisable(unsigned long ulPort)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ulPort));
-
-    //
-    // Set the pin as a DMA trigger.
-    //
-    if(ulPort == GPIOA0_BASE)
-    {
-      HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x1;
-    }
-    else if(ulPort == GPIOA1_BASE)
-    {
-      HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x2;
-    }
-    else if(ulPort == GPIOA2_BASE)
-    {
-      HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x4;
-    }
-    else if(ulPort == GPIOA3_BASE)
-    {
-      HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x8;
-    }
-}
-
-
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
diff --git a/cc3200/hal/gpio.h b/cc3200/hal/gpio.h
deleted file mode 100644
index 35acf79a6..000000000
--- a/cc3200/hal/gpio.h
+++ /dev/null
@@ -1,139 +0,0 @@
-//*****************************************************************************
-//
-//  gpio.h
-//
-//  Defines and Macros for GPIO API.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __GPIO_H__
-#define __GPIO_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// The following values define the bit field for the ucPins argument to several
-// of the APIs.
-//
-//*****************************************************************************
-#define GPIO_PIN_0              0x00000001  // GPIO pin 0
-#define GPIO_PIN_1              0x00000002  // GPIO pin 1
-#define GPIO_PIN_2              0x00000004  // GPIO pin 2
-#define GPIO_PIN_3              0x00000008  // GPIO pin 3
-#define GPIO_PIN_4              0x00000010  // GPIO pin 4
-#define GPIO_PIN_5              0x00000020  // GPIO pin 5
-#define GPIO_PIN_6              0x00000040  // GPIO pin 6
-#define GPIO_PIN_7              0x00000080  // GPIO pin 7
-
-//*****************************************************************************
-//
-// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
-// returned from GPIODirModeGet.
-//
-//*****************************************************************************
-#define GPIO_DIR_MODE_IN        0x00000000  // Pin is a GPIO input
-#define GPIO_DIR_MODE_OUT       0x00000001  // Pin is a GPIO output
-
-//*****************************************************************************
-//
-// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
-// returned from GPIOIntTypeGet.
-//
-//*****************************************************************************
-#define GPIO_FALLING_EDGE       0x00000000  // Interrupt on falling edge
-#define GPIO_RISING_EDGE        0x00000004  // Interrupt on rising edge
-#define GPIO_BOTH_EDGES         0x00000001  // Interrupt on both edges
-#define GPIO_LOW_LEVEL          0x00000002  // Interrupt on low level
-#define GPIO_HIGH_LEVEL         0x00000006  // Interrupt on high level
-
-//*****************************************************************************
-//
-// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions
-// in the ulIntFlags parameter.
-//
-//*****************************************************************************
-#define GPIO_INT_DMA            0x00000100
-#define GPIO_INT_PIN_0          0x00000001
-#define GPIO_INT_PIN_1          0x00000002
-#define GPIO_INT_PIN_2          0x00000004
-#define GPIO_INT_PIN_3          0x00000008
-#define GPIO_INT_PIN_4          0x00000010
-#define GPIO_INT_PIN_5          0x00000020
-#define GPIO_INT_PIN_6          0x00000040
-#define GPIO_INT_PIN_7          0x00000080
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
-                           unsigned long ulPinIO);
-extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
-extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
-                           unsigned long ulIntType);
-extern void GPIODMATriggerEnable(unsigned long ulPort);
-extern void GPIODMATriggerDisable(unsigned long ulPort);
-extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
-extern void GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags);
-extern void GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags);
-extern long GPIOIntStatus(unsigned long ulPort, tBoolean bMasked);
-extern void GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags);
-extern void GPIOIntRegister(unsigned long ulPort,
-                                void (*pfnIntHandler)(void));
-extern void GPIOIntUnregister(unsigned long ulPort);
-extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
-extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
-                         unsigned char ucVal);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif //  __GPIO_H__
diff --git a/cc3200/hal/i2c.c b/cc3200/hal/i2c.c
deleted file mode 100644
index 487f93cc2..000000000
--- a/cc3200/hal/i2c.c
+++ /dev/null
@@ -1,2043 +0,0 @@
-//*****************************************************************************
-//
-//  i2c.c
-//
-//  Driver for Inter-IC (I2C) bus block.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup I2C_api
-//! @{
-//
-//*****************************************************************************
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "inc/hw_i2c.h"
-#include "inc/hw_ints.h"
-#include "inc/hw_memmap.h"
-#include "inc/hw_types.h"
-#include "debug.h"
-#include "i2c.h"
-#include "interrupt.h"
-
-//*****************************************************************************
-//
-// A mapping of I2C base address to interrupt number.
-//
-//*****************************************************************************
-static const uint32_t g_ppui32I2CIntMap[][2] =
-{
-    { I2CA0_BASE, INT_I2CA0},
-};
-
-static const int_fast8_t g_i8I2CIntMapRows =
-    sizeof(g_ppui32I2CIntMap) / sizeof(g_ppui32I2CIntMap[0]);
-
-//*****************************************************************************
-//
-//! \internal
-//! Checks an I2C base address.
-//!
-//! \param ui32Base is the base address of the I2C module.
-//!
-//! This function determines if a I2C module base address is valid.
-//!
-//! \return Returns \b true if the base address is valid and \b false
-//! otherwise.
-//
-//*****************************************************************************
-#ifdef DEBUG
-static bool
-_I2CBaseValid(uint32_t ui32Base)
-{
-    return((ui32Base == I2CA0_BASE));
-}
-#else
-#define _I2CBaseValid(ui32Base)         (ui32Base)
-#endif
-
-//*****************************************************************************
-//
-//! \internal
-//! Gets the I2C interrupt number.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//!
-//! Given a I2C base address, this function returns the corresponding
-//! interrupt number.
-//!
-//! \return Returns an I2C interrupt number, or 0 if \e ui32Base is invalid.
-//
-//*****************************************************************************
-static uint32_t
-_I2CIntNumberGet(uint32_t ui32Base)
-{
-    int_fast8_t i8Idx, i8Rows;
-    const uint32_t (*ppui32I2CIntMap)[2];
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    ppui32I2CIntMap = g_ppui32I2CIntMap;
-    i8Rows = g_i8I2CIntMapRows;
-
-    //
-    // Loop through the table that maps I2C base addresses to interrupt
-    // numbers.
-    //
-    for(i8Idx = 0; i8Idx < i8Rows; i8Idx++)
-    {
-        //
-        // See if this base address matches.
-        //
-        if(ppui32I2CIntMap[i8Idx][0] == ui32Base)
-        {
-            //
-            // Return the corresponding interrupt number.
-            //
-            return(ppui32I2CIntMap[i8Idx][1]);
-        }
-    }
-
-    //
-    // The base address could not be found, so return an error.
-    //
-    return(0);
-}
-
-//*****************************************************************************
-//
-//! Initializes the I2C Master block.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//! \param ui32I2CClk is the rate of the clock supplied to the I2C module.
-//! \param bFast set up for fast data transfers.
-//!
-//! This function initializes operation of the I2C Master block by configuring
-//! the bus speed for the master and enabling the I2C Master block.
-//!
-//! If the parameter \e bFast is \b true, then the master block is set up to
-//! transfer data at 400 Kbps; otherwise, it is set up to transfer data at
-//! 100 Kbps.  If Fast Mode Plus (1 Mbps) is desired, software should manually
-//! write the I2CMTPR after calling this function.  For High Speed (3.4 Mbps)
-//! mode, a specific command is used to switch to the faster clocks after the
-//! initial communication with the slave is done at either 100 Kbps or
-//! 400 Kbps.
-//!
-//! The peripheral clock is the same as the processor clock.  This value is
-//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is
-//! constant and known (to save the code/execution overhead of a call to
-//! SysCtlClockGet()).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32SCLFreq)
-{
-    uint32_t ui32TPR;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Must enable the device before doing anything else.
-    //
-    I2CMasterEnable(ui32Base);
-
-    //
-    // Compute the clock divider that achieves the fastest speed less than or
-    // equal to the desired speed.  The numerator is biased to favor a larger
-    // clock divider so that the resulting clock is always less than or equal
-    // to the desired clock, never greater.
-    //
-    ui32TPR = ((80000000 + (2 * 10 * ui32SCLFreq) - 1) /
-               (2 * 10 * ui32SCLFreq)) - 1;
-    HWREG(ui32Base + I2C_O_MTPR) = ui32TPR;
-
-    //
-    // Check to see if this I2C peripheral is High-Speed enabled.  If yes, also
-    // choose the fastest speed that is less than or equal to 3.4 Mbps.
-    //
-    if(HWREG(ui32Base + I2C_O_PP) & I2C_PP_HS)
-    {
-        ui32TPR = ((80000000 + (2 * 3 * 3400000) - 1) /
-                   (2 * 3 * 3400000)) - 1;
-        HWREG(ui32Base + I2C_O_MTPR) = I2C_MTPR_HS | ui32TPR;
-    }
-}
-
-//*****************************************************************************
-//
-//! Initializes the I2C Slave block.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//! \param ui8SlaveAddr 7-bit slave address
-//!
-//! This function initializes operation of the I2C Slave block by configuring
-//! the slave address and enabling the I2C Slave block.
-//!
-//! The parameter \e ui8SlaveAddr is the value that is compared against the
-//! slave address sent by an I2C master.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-    ASSERT(!(ui8SlaveAddr & 0x80));
-
-    //
-    // Must enable the device before doing anything else.
-    //
-    I2CSlaveEnable(ui32Base);
-
-    //
-    // Set up the slave address.
-    //
-    HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr;
-}
-
-//*****************************************************************************
-//
-//! Sets the I2C slave address.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//! \param ui8AddrNum determines which slave address is set.
-//! \param ui8SlaveAddr is the 7-bit slave address
-//!
-//! This function writes the specified slave address.  The \e ui32AddrNum field
-//! dictates which slave address is configured.  For example, a value of 0
-//! configures the primary address and a value of 1 configures the secondary.
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, uint8_t ui8SlaveAddr)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-    ASSERT(!(ui8AddrNum > 1));
-    ASSERT(!(ui8SlaveAddr & 0x80));
-
-    //
-    // Determine which slave address is being set.
-    //
-    switch(ui8AddrNum)
-    {
-        //
-        // Set up the primary slave address.
-        //
-        case 0:
-        {
-            HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr;
-            break;
-        }
-
-        //
-        // Set up and enable the secondary slave address.
-        //
-        case 1:
-        {
-            HWREG(ui32Base + I2C_O_SOAR2) = I2C_SOAR2_OAR2EN | ui8SlaveAddr;
-            break;
-        }
-    }
-}
-
-//*****************************************************************************
-//
-//! Enables the I2C Master block.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//!
-//! This function enables operation of the I2C Master block.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CMasterEnable(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Enable the master block.
-    //
-    HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_MFE;
-}
-
-//*****************************************************************************
-//
-//! Enables the I2C Slave block.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//!
-//! This fucntion enables operation of the I2C Slave block.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CSlaveEnable(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Enable the clock to the slave block.
-    //
-    HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_SFE;
-
-    //
-    // Enable the slave.
-    //
-    HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA;
-}
-
-//*****************************************************************************
-//
-//! Disables the I2C master block.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//!
-//! This function disables operation of the I2C master block.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CMasterDisable(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Disable the master block.
-    //
-    HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_MFE);
-}
-
-//*****************************************************************************
-//
-//! Disables the I2C slave block.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//!
-//! This function disables operation of the I2C slave block.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CSlaveDisable(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Disable the slave.
-    //
-    HWREG(ui32Base + I2C_O_SCSR) = 0;
-
-    //
-    // Disable the clock to the slave block.
-    //
-    HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_SFE);
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for the I2C module.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//! \param pfnHandler is a pointer to the function to be called when the
-//! I2C interrupt occurs.
-//!
-//! This function sets the handler to be called when an I2C interrupt occurs.
-//! This function enables the global interrupt in the interrupt controller;
-//! specific I2C interrupts must be enabled via I2CMasterIntEnable() and
-//! I2CSlaveIntEnable().  If necessary, it is the interrupt handler's
-//! responsibility to clear the interrupt source via I2CMasterIntClear() and
-//! I2CSlaveIntClear().
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
-{
-    uint32_t ui32Int;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Determine the interrupt number based on the I2C port.
-    //
-    ui32Int = _I2CIntNumberGet(ui32Base);
-
-    ASSERT(ui32Int != 0);
-
-    //
-    // Register the interrupt handler, returning an error if an error occurs.
-    //
-    IntRegister(ui32Int, pfnHandler);
-
-    //
-    // Enable the I2C interrupt.
-    //
-    IntEnable(ui32Int);
-}
-
-//*****************************************************************************
-//
-//! Unregisters an interrupt handler for the I2C module.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//!
-//! This function clears the handler to be called when an I2C interrupt
-//! occurs.  This function also masks off the interrupt in the interrupt r
-//! controller so that the interrupt handler no longer is called.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CIntUnregister(uint32_t ui32Base)
-{
-    uint32_t ui32Int;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Determine the interrupt number based on the I2C port.
-    //
-    ui32Int = _I2CIntNumberGet(ui32Base);
-
-    ASSERT(ui32Int != 0);
-
-    //
-    // Disable the interrupt.
-    //
-    IntDisable(ui32Int);
-
-    //
-    // Unregister the interrupt handler.
-    //
-    IntUnregister(ui32Int);
-}
-
-//*****************************************************************************
-//
-//! Enables the I2C Master interrupt.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//!
-//! This function enables the I2C Master interrupt source.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CMasterIntEnable(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Enable the master interrupt.
-    //
-    HWREG(ui32Base + I2C_O_MIMR) = 1;
-}
-
-//*****************************************************************************
-//
-//! Enables individual I2C Master interrupt sources.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
-//!
-//! This function enables the indicated I2C Master interrupt sources.  Only the
-//! sources that are enabled can be reflected to the processor interrupt;
-//! disabled sources have no effect on the processor.
-//!
-//! The \e ui32IntFlags parameter is the logical OR of any of the following:
-//!
-//! - \b I2C_MASTER_INT_RX_FIFO_FULL - RX FIFO Full interrupt
-//! - \b I2C_MASTER_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt
-//! - \b I2C_MASTER_INT_RX_FIFO_REQ - RX FIFO Request interrupt
-//! - \b I2C_MASTER_INT_TX_FIFO_REQ - TX FIFO Request interrupt
-//! - \b I2C_MASTER_INT_ARB_LOST - Arbitration Lost interrupt
-//! - \b I2C_MASTER_INT_STOP - Stop Condition interrupt
-//! - \b I2C_MASTER_INT_START - Start Condition interrupt
-//! - \b I2C_MASTER_INT_NACK - Address/Data NACK interrupt
-//! - \b I2C_MASTER_INT_TX_DMA_DONE - TX DMA Complete interrupt
-//! - \b I2C_MASTER_INT_RX_DMA_DONE - RX DMA Complete interrupt
-//! - \b I2C_MASTER_INT_TIMEOUT - Clock Timeout interrupt
-//! - \b I2C_MASTER_INT_DATA - Data interrupt
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CMasterIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Enable the master interrupt.
-    //
-    HWREG(ui32Base + I2C_O_MIMR) |= ui32IntFlags;
-}
-
-//*****************************************************************************
-//
-//! Enables the I2C Slave interrupt.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//!
-//! This function enables the I2C Slave interrupt source.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CSlaveIntEnable(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Enable the slave interrupt.
-    //
-    HWREG(ui32Base + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA;
-}
-
-//*****************************************************************************
-//
-//! Enables individual I2C Slave interrupt sources.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
-//!
-//! This function enables the indicated I2C Slave interrupt sources.  Only the
-//! sources that are enabled can be reflected to the processor interrupt;
-//! disabled sources have no effect on the processor.
-//!
-//! The \e ui32IntFlags parameter is the logical OR of any of the following:
-//!
-//! - \b I2C_SLAVE_INT_RX_FIFO_FULL - RX FIFO Full interrupt
-//! - \b I2C_SLAVE_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt
-//! - \b I2C_SLAVE_INT_RX_FIFO_REQ - RX FIFO Request interrupt
-//! - \b I2C_SLAVE_INT_TX_FIFO_REQ - TX FIFO Request interrupt
-//! - \b I2C_SLAVE_INT_TX_DMA_DONE - TX DMA Complete interrupt
-//! - \b I2C_SLAVE_INT_RX_DMA_DONE - RX DMA Complete interrupt
-//! - \b I2C_SLAVE_INT_STOP - Stop condition detected interrupt
-//! - \b I2C_SLAVE_INT_START - Start condition detected interrupt
-//! - \b I2C_SLAVE_INT_DATA - Data interrupt
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Enable the slave interrupt.
-    //
-    HWREG(ui32Base + I2C_O_SIMR) |= ui32IntFlags;
-}
-
-//*****************************************************************************
-//
-//! Disables the I2C Master interrupt.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//!
-//! This function disables the I2C Master interrupt source.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CMasterIntDisable(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Disable the master interrupt.
-    //
-    HWREG(ui32Base + I2C_O_MIMR) = 0;
-}
-
-//*****************************************************************************
-//
-//! Disables individual I2C Master interrupt sources.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//! \param ui32IntFlags is the bit mask of the interrupt sources to be
-//!        disabled.
-//!
-//! This function disables the indicated I2C Master interrupt sources.  Only
-//! the sources that are enabled can be reflected to the processor interrupt;
-//! disabled sources have no effect on the processor.
-//!
-//! The \e ui32IntFlags parameter has the same definition as the
-//! \e ui32IntFlags parameter to I2CMasterIntEnableEx().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CMasterIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Disable the master interrupt.
-    //
-    HWREG(ui32Base + I2C_O_MIMR) &= ~ui32IntFlags;
-}
-
-//*****************************************************************************
-//
-//! Disables the I2C Slave interrupt.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//!
-//! This function disables the I2C Slave interrupt source.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CSlaveIntDisable(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Disable the slave interrupt.
-    //
-    HWREG(ui32Base + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA;
-}
-
-//*****************************************************************************
-//
-//! Disables individual I2C Slave interrupt sources.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//! \param ui32IntFlags is the bit mask of the interrupt sources to be
-//!        disabled.
-//!
-//! This function disables the indicated I2C Slave interrupt sources.  Only
-//! the sources that are enabled can be reflected to the processor interrupt;
-//! disabled sources have no effect on the processor.
-//!
-//! The \e ui32IntFlags parameter has the same definition as the
-//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CSlaveIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Disable the slave interrupt.
-    //
-    HWREG(ui32Base + I2C_O_SIMR) &= ~ui32IntFlags;
-}
-
-//*****************************************************************************
-//
-//! Gets the current I2C Master interrupt status.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//! \param bMasked is false if the raw interrupt status is requested and
-//! true if the masked interrupt status is requested.
-//!
-//! This function returns the interrupt status for the I2C Master module.
-//! Either the raw interrupt status or the status of interrupts that are
-//! allowed to reflect to the processor can be returned.
-//!
-//! \return The current interrupt status, returned as \b true if active
-//! or \b false if not active.
-//
-//*****************************************************************************
-bool
-I2CMasterIntStatus(uint32_t ui32Base, bool bMasked)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Return either the interrupt status or the raw interrupt status as
-    // requested.
-    //
-    if(bMasked)
-    {
-        return((HWREG(ui32Base + I2C_O_MMIS)) ? true : false);
-    }
-    else
-    {
-        return((HWREG(ui32Base + I2C_O_MRIS)) ? true : false);
-    }
-}
-
-//*****************************************************************************
-//
-//! Gets the current I2C Master interrupt status.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//! \param bMasked is false if the raw interrupt status is requested and
-//! true if the masked interrupt status is requested.
-//!
-//! This function returns the interrupt status for the I2C Master module.
-//! Either the raw interrupt status or the status of interrupts that are
-//! allowed to reflect to the processor can be returned.
-//!
-//! \return Returns the current interrupt status, enumerated as a bit field of
-//! values described in I2CMasterIntEnableEx().
-//
-//*****************************************************************************
-uint32_t
-I2CMasterIntStatusEx(uint32_t ui32Base, bool bMasked)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Return either the interrupt status or the raw interrupt status as
-    // requested.
-    //
-    if(bMasked)
-    {
-        return(HWREG(ui32Base + I2C_O_MMIS));
-    }
-    else
-    {
-        return(HWREG(ui32Base + I2C_O_MRIS));
-    }
-}
-
-//*****************************************************************************
-//
-//! Gets the current I2C Slave interrupt status.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//! \param bMasked is false if the raw interrupt status is requested and
-//! true if the masked interrupt status is requested.
-//!
-//! This function returns the interrupt status for the I2C Slave module.
-//! Either the raw interrupt status or the status of interrupts that are
-//! allowed to reflect to the processor can be returned.
-//!
-//! \return The current interrupt status, returned as \b true if active
-//! or \b false if not active.
-//
-//*****************************************************************************
-bool
-I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Return either the interrupt status or the raw interrupt status as
-    // requested.
-    //
-    if(bMasked)
-    {
-        return((HWREG(ui32Base + I2C_O_SMIS)) ? true : false);
-    }
-    else
-    {
-        return((HWREG(ui32Base + I2C_O_SRIS)) ? true : false);
-    }
-}
-
-//*****************************************************************************
-//
-//! Gets the current I2C Slave interrupt status.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//! \param bMasked is false if the raw interrupt status is requested and
-//! true if the masked interrupt status is requested.
-//!
-//! This function returns the interrupt status for the I2C Slave module.
-//! Either the raw interrupt status or the status of interrupts that are
-//! allowed to reflect to the processor can be returned.
-//!
-//! \return Returns the current interrupt status, enumerated as a bit field of
-//! values described in I2CSlaveIntEnableEx().
-//
-//*****************************************************************************
-uint32_t
-I2CSlaveIntStatusEx(uint32_t ui32Base, bool bMasked)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Return either the interrupt status or the raw interrupt status as
-    // requested.
-    //
-    if(bMasked)
-    {
-        return(HWREG(ui32Base + I2C_O_SMIS));
-    }
-    else
-    {
-        return(HWREG(ui32Base + I2C_O_SRIS));
-    }
-}
-
-//*****************************************************************************
-//
-//! Clears I2C Master interrupt sources.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//!
-//! The I2C Master interrupt source is cleared, so that it no longer
-//! asserts.  This function must be called in the interrupt handler to keep the
-//! interrupt from being triggered again immediately upon exit.
-//!
-//! \note Because there is a write buffer in the Cortex-M processor, it may
-//! take several clock cycles before the interrupt source is actually cleared.
-//! Therefore, it is recommended that the interrupt source be cleared early in
-//! the interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (because the interrupt controller still sees
-//! the interrupt source asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CMasterIntClear(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Clear the I2C master interrupt source.
-    //
-    HWREG(ui32Base + I2C_O_MICR) = I2C_MICR_IC;
-
-    //
-    // Workaround for I2C master interrupt clear errata for some
-    // devices.  For later devices, this write is ignored and therefore
-    // harmless (other than the slight performance hit).
-    //
-    HWREG(ui32Base + I2C_O_MMIS) = I2C_MICR_IC;
-}
-
-//*****************************************************************************
-//
-//! Clears I2C Master interrupt sources.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
-//!
-//! The specified I2C Master interrupt sources are cleared, so that they no
-//! longer assert.  This function must be called in the interrupt handler to
-//! keep the interrupt from being triggered again immediately upon exit.
-//!
-//! The \e ui32IntFlags parameter has the same definition as the
-//! \e ui32IntFlags parameter to I2CMasterIntEnableEx().
-//!
-//! \note Because there is a write buffer in the Cortex-M processor, it may
-//! take several clock cycles before the interrupt source is actually cleared.
-//! Therefore, it is recommended that the interrupt source be cleared early in
-//! the interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (because the interrupt controller still sees
-//! the interrupt source asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CMasterIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Clear the I2C master interrupt source.
-    //
-    HWREG(ui32Base + I2C_O_MICR) = ui32IntFlags;
-}
-
-//*****************************************************************************
-//
-//! Clears I2C Slave interrupt sources.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//!
-//! The I2C Slave interrupt source is cleared, so that it no longer asserts.
-//! This function must be called in the interrupt handler to keep the interrupt
-//! from being triggered again immediately upon exit.
-//!
-//! \note Because there is a write buffer in the Cortex-M processor, it may
-//! take several clock cycles before the interrupt source is actually cleared.
-//! Therefore, it is recommended that the interrupt source be cleared early in
-//! the interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (because the interrupt controller still sees
-//! the interrupt source asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CSlaveIntClear(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Clear the I2C slave interrupt source.
-    //
-    HWREG(ui32Base + I2C_O_SICR) = I2C_SICR_DATAIC;
-}
-
-//*****************************************************************************
-//
-//! Clears I2C Slave interrupt sources.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
-//!
-//! The specified I2C Slave interrupt sources are cleared, so that they no
-//! longer assert.  This function must be called in the interrupt handler to
-//! keep the interrupt from being triggered again immediately upon exit.
-//!
-//! The \e ui32IntFlags parameter has the same definition as the
-//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx().
-//!
-//! \note Because there is a write buffer in the Cortex-M processor, it may
-//! take several clock cycles before the interrupt source is actually cleared.
-//! Therefore, it is recommended that the interrupt source be cleared early in
-//! the interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (because the interrupt controller still sees
-//! the interrupt source asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Clear the I2C slave interrupt source.
-    //
-    HWREG(ui32Base + I2C_O_SICR) = ui32IntFlags;
-}
-
-//*****************************************************************************
-//
-//! Sets the address that the I2C Master places on the bus.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//! \param ui8SlaveAddr 7-bit slave address
-//! \param bReceive flag indicating the type of communication with the slave
-//!
-//! This function configures the address that the I2C Master places on the
-//! bus when initiating a transaction.  When the \e bReceive parameter is set
-//! to \b true, the address indicates that the I2C Master is initiating a
-//! read from the slave; otherwise the address indicates that the I2C
-//! Master is initiating a write to the slave.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr,
-                      bool bReceive)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-    ASSERT(!(ui8SlaveAddr & 0x80));
-
-    //
-    // Set the address of the slave with which the master will communicate.
-    //
-    HWREG(ui32Base + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive;
-}
-
-//*****************************************************************************
-//
-//! Reads the state of the SDA and SCL pins.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//!
-//! This function returns the state of the I2C bus by providing the real time
-//! values of the SDA and SCL pins.
-//!
-//!
-//! \return Returns the state of the bus with SDA in bit position 1 and SCL in
-//! bit position 0.
-//
-//*****************************************************************************
-uint32_t
-I2CMasterLineStateGet(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Return the line state.
-    //
-    return(HWREG(ui32Base + I2C_O_MBMON));
-}
-
-//*****************************************************************************
-//
-//! Indicates whether or not the I2C Master is busy.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//!
-//! This function returns an indication of whether or not the I2C Master is
-//! busy transmitting or receiving data.
-//!
-//! \return Returns \b true if the I2C Master is busy; otherwise, returns
-//! \b false.
-//
-//*****************************************************************************
-bool
-I2CMasterBusy(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Return the busy status.
-    //
-    if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSY)
-    {
-        return(true);
-    }
-    else
-    {
-        return(false);
-    }
-}
-
-//*****************************************************************************
-//
-//! Indicates whether or not the I2C bus is busy.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//!
-//! This function returns an indication of whether or not the I2C bus is busy.
-//! This function can be used in a multi-master environment to determine if
-//! another master is currently using the bus.
-//!
-//! \return Returns \b true if the I2C bus is busy; otherwise, returns
-//! \b false.
-//
-//*****************************************************************************
-bool
-I2CMasterBusBusy(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Return the bus busy status.
-    //
-    if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSBSY)
-    {
-        return(true);
-    }
-    else
-    {
-        return(false);
-    }
-}
-
-//*****************************************************************************
-//
-//! Controls the state of the I2C Master module.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//! \param ui32Cmd command to be issued to the I2C Master module.
-//!
-//! This function is used to control the state of the Master module send and
-//! receive operations.  The \e ui8Cmd parameter can be one of the following
-//! values:
-//!
-//! - \b I2C_MASTER_CMD_SINGLE_SEND
-//! - \b I2C_MASTER_CMD_SINGLE_RECEIVE
-//! - \b I2C_MASTER_CMD_BURST_SEND_START
-//! - \b I2C_MASTER_CMD_BURST_SEND_CONT
-//! - \b I2C_MASTER_CMD_BURST_SEND_FINISH
-//! - \b I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
-//! - \b I2C_MASTER_CMD_BURST_RECEIVE_START
-//! - \b I2C_MASTER_CMD_BURST_RECEIVE_CONT
-//! - \b I2C_MASTER_CMD_BURST_RECEIVE_FINISH
-//! - \b I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
-//! - \b I2C_MASTER_CMD_QUICK_COMMAND
-//! - \b I2C_MASTER_CMD_HS_MASTER_CODE_SEND
-//! - \b I2C_MASTER_CMD_FIFO_SINGLE_SEND
-//! - \b I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE
-//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_START
-//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_CONT
-//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH
-//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP
-//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START
-//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT
-//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH
-//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-    ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) ||
-           (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) ||
-           (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) ||
-           (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) ||
-           (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) ||
-           (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) ||
-           (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) ||
-           (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) ||
-           (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) ||
-           (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) ||
-           (ui32Cmd == I2C_MASTER_CMD_QUICK_COMMAND) ||
-           (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_SEND) ||
-           (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE) ||
-           (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_START) ||
-           (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_CONT) ||
-           (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH) ||
-           (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP) ||
-           (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START) ||
-           (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT) ||
-           (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH) ||
-           (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP) ||
-           (ui32Cmd == I2C_MASTER_CMD_HS_MASTER_CODE_SEND));
-
-    //
-    // Send the command.
-    //
-    HWREG(ui32Base + I2C_O_MCS) = ui32Cmd;
-}
-
-//*****************************************************************************
-//
-//! Gets the error status of the I2C Master module.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//!
-//! This function is used to obtain the error status of the Master module send
-//! and receive operations.
-//!
-//! \return Returns the error status, as one of \b I2C_MASTER_ERR_NONE,
-//! \b I2C_MASTER_ERR_ADDR_ACK, \b I2C_MASTER_ERR_DATA_ACK, or
-//! \b I2C_MASTER_ERR_ARB_LOST.
-//
-//*****************************************************************************
-uint32_t
-I2CMasterErr(uint32_t ui32Base)
-{
-    uint32_t ui32Err;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Get the raw error state
-    //
-    ui32Err = HWREG(ui32Base + I2C_O_MCS);
-
-    //
-    // If the I2C master is busy, then all the other bit are invalid, and
-    // don't have an error to report.
-    //
-    if(ui32Err & I2C_MCS_BUSY)
-    {
-        return(I2C_MASTER_ERR_NONE);
-    }
-
-    //
-    // Check for errors.
-    //
-    if(ui32Err & (I2C_MCS_ERROR | I2C_MCS_ARBLST))
-    {
-        return(ui32Err & (I2C_MCS_ARBLST | I2C_MCS_ACK | I2C_MCS_ADRACK));
-    }
-    else
-    {
-        return(I2C_MASTER_ERR_NONE);
-    }
-}
-
-//*****************************************************************************
-//
-//! Transmits a byte from the I2C Master.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//! \param ui8Data data to be transmitted from the I2C Master.
-//!
-//! This function places the supplied data into I2C Master Data Register.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Write the byte.
-    //
-    HWREG(ui32Base + I2C_O_MDR) = ui8Data;
-}
-
-//*****************************************************************************
-//
-//! Receives a byte that has been sent to the I2C Master.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//!
-//! This function reads a byte of data from the I2C Master Data Register.
-//!
-//! \return Returns the byte received from by the I2C Master, cast as an
-//! uint32_t.
-//
-//*****************************************************************************
-uint32_t
-I2CMasterDataGet(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Read a byte.
-    //
-    return(HWREG(ui32Base + I2C_O_MDR));
-}
-
-//*****************************************************************************
-//
-//! Sets the Master clock timeout value.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//! \param ui32Value is the number of I2C clocks before the timeout is
-//!        asserted.
-//!
-//! This function enables and configures the clock low timeout feature in the
-//! I2C peripheral.  This feature is implemented as a 12-bit counter, with the
-//! upper 8-bits being programmable.  For example, to program a timeout of 20ms
-//! with a 100kHz SCL frequency, \e ui32Value would be 0x7d.
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Write the timeout value.
-    //
-    HWREG(ui32Base + I2C_O_MCLKOCNT) = ui32Value;
-}
-
-//*****************************************************************************
-//
-//! Configures ACK override behavior of the I2C Slave.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//! \param bEnable enables or disables ACK override.
-//!
-//! This function enables or disables ACK override, allowing the user
-//! application to drive the value on SDA during the ACK cycle.
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Enable or disable based on bEnable.
-    //
-    if(bEnable)
-    {
-        HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOEN;
-    }
-    else
-    {
-        HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOEN;
-    }
-}
-
-//*****************************************************************************
-//
-//! Writes the ACK value.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//! \param bACK chooses whether to ACK (true) or NACK (false) the transfer.
-//!
-//! This function puts the desired ACK value on SDA during the ACK cycle.  The
-//! value written is only valid when ACK override is enabled using
-//! I2CSlaveACKOverride().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // ACK or NACK based on the value of bACK.
-    //
-    if(bACK)
-    {
-        HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOVAL;
-    }
-    else
-    {
-        HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOVAL;
-    }
-}
-
-//*****************************************************************************
-//
-//! Gets the I2C Slave module status
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//!
-//! This function returns the action requested from a master, if any.
-//! Possible values are:
-//!
-//! - \b I2C_SLAVE_ACT_NONE
-//! - \b I2C_SLAVE_ACT_RREQ
-//! - \b I2C_SLAVE_ACT_TREQ
-//! - \b I2C_SLAVE_ACT_RREQ_FBR
-//! - \b I2C_SLAVE_ACT_OWN2SEL
-//! - \b I2C_SLAVE_ACT_QCMD
-//! - \b I2C_SLAVE_ACT_QCMD_DATA
-//!
-//! \note Not all devices support the second I2C slave's own address
-//! or the quick command function.  Please consult the device data sheet to
-//! determine if these features are supported.
-//!
-//! \return Returns \b I2C_SLAVE_ACT_NONE to indicate that no action has been
-//! requested of the I2C Slave module, \b I2C_SLAVE_ACT_RREQ to indicate that
-//! an I2C master has sent data to the I2C Slave module, \b I2C_SLAVE_ACT_TREQ
-//! to indicate that an I2C master has requested that the I2C Slave module send
-//! data, \b I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent
-//! data to the I2C slave and the first byte following the slave's own address
-//! has been received, \b I2C_SLAVE_ACT_OWN2SEL to indicate that the second I2C
-//! slave address was matched, \b I2C_SLAVE_ACT_QCMD to indicate that a quick
-//! command was received, and \b I2C_SLAVE_ACT_QCMD_DATA to indicate that the
-//! data bit was set when the quick command was received.
-//
-//*****************************************************************************
-uint32_t
-I2CSlaveStatus(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Return the slave status.
-    //
-    return(HWREG(ui32Base + I2C_O_SCSR));
-}
-
-//*****************************************************************************
-//
-//! Transmits a byte from the I2C Slave.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//! \param ui8Data is the data to be transmitted from the I2C Slave
-//!
-//! This function places the supplied data into I2C Slave Data Register.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Write the byte.
-    //
-    HWREG(ui32Base + I2C_O_SDR) = ui8Data;
-}
-
-//*****************************************************************************
-//
-//! Receives a byte that has been sent to the I2C Slave.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//!
-//! This function reads a byte of data from the I2C Slave Data Register.
-//!
-//! \return Returns the byte received from by the I2C Slave, cast as an
-//! uint32_t.
-//
-//*****************************************************************************
-uint32_t
-I2CSlaveDataGet(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Read a byte.
-    //
-    return(HWREG(ui32Base + I2C_O_SDR));
-}
-
-//*****************************************************************************
-//
-//! Configures the I2C transmit (TX) FIFO.
-//!
-//! \param ui32Base is the base address of the I2C Master or Slave module.
-//! \param ui32Config is the configuration of the FIFO using specified macros.
-//!
-//! This configures the I2C peripheral's transmit FIFO.  The transmit FIFO can
-//! be used by the master or slave, but not both.  The following macros are
-//! used to configure the TX FIFO behavior for master or slave, with or without
-//! DMA:
-//!
-//! \b I2C_FIFO_CFG_TX_MASTER, \b I2C_FIFO_CFG_TX_SLAVE,
-//! \b I2C_FIFO_CFG_TX_MASTER_DMA, \b I2C_FIFO_CFG_TX_SLAVE_DMA
-//!
-//! To select the trigger level, one of the following macros should be used:
-//!
-//! \b I2C_FIFO_CFG_TX_TRIG_1, \b I2C_FIFO_CFG_TX_TRIG_2,
-//! \b I2C_FIFO_CFG_TX_TRIG_3, \b I2C_FIFO_CFG_TX_TRIG_4,
-//! \b I2C_FIFO_CFG_TX_TRIG_5, \b I2C_FIFO_CFG_TX_TRIG_6,
-//! \b I2C_FIFO_CFG_TX_TRIG_7, \b I2C_FIFO_CFG_TX_TRIG_8
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Clear transmit configuration data.
-    //
-    HWREG(ui32Base + I2C_O_FIFOCTL) &= 0xffff0000;
-
-    //
-    // Store new transmit configuration data.
-    //
-    HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config;
-}
-
-//*****************************************************************************
-//
-//! Flushes the transmit (TX) FIFO.
-//!
-//! \param ui32Base is the base address of the I2C Master or Slave module.
-//!
-//! This function flushes the I2C transmit FIFO.
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CTxFIFOFlush(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Flush the TX FIFO.
-    //
-    HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_TXFLUSH;
-}
-
-//*****************************************************************************
-//
-//! Configures the I2C receive (RX) FIFO.
-//!
-//! \param ui32Base is the base address of the I2C Master or Slave module.
-//! \param ui32Config is the configuration of the FIFO using specified macros.
-//!
-//! This configures the I2C peripheral's receive FIFO.  The receive FIFO can be
-//! used by the master or slave, but not both.  The following macros are used
-//! to configure the RX FIFO behavior for master or slave, with or without DMA:
-//!
-//! \b I2C_FIFO_CFG_RX_MASTER, \b I2C_FIFO_CFG_RX_SLAVE,
-//! \b I2C_FIFO_CFG_RX_MASTER_DMA, \b I2C_FIFO_CFG_RX_SLAVE_DMA
-//!
-//! To select the trigger level, one of the following macros should be used:
-//!
-//! \b I2C_FIFO_CFG_RX_TRIG_1, \b I2C_FIFO_CFG_RX_TRIG_2,
-//! \b I2C_FIFO_CFG_RX_TRIG_3, \b I2C_FIFO_CFG_RX_TRIG_4,
-//! \b I2C_FIFO_CFG_RX_TRIG_5, \b I2C_FIFO_CFG_RX_TRIG_6,
-//! \b I2C_FIFO_CFG_RX_TRIG_7, \b I2C_FIFO_CFG_RX_TRIG_8
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Clear receive configuration data.
-    //
-    HWREG(ui32Base + I2C_O_FIFOCTL) &= 0x0000ffff;
-
-    //
-    // Store new receive configuration data.
-    //
-    HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config;
-}
-
-//*****************************************************************************
-//
-//! Flushes the receive (RX) FIFO.
-//!
-//! \param ui32Base is the base address of the I2C Master or Slave module.
-//!
-//! This function flushes the I2C receive FIFO.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CRxFIFOFlush(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Flush the TX FIFO.
-    //
-    HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_RXFLUSH;
-}
-
-//*****************************************************************************
-//
-//! Gets the current FIFO status.
-//!
-//! \param ui32Base is the base address of the I2C Master or Slave module.
-//!
-//! This function retrieves the status for both the transmit (TX) and receive
-//! (RX) FIFOs.  The trigger level for the transmit FIFO is set using
-//! I2CTxFIFOConfigSet() and for the receive FIFO using I2CTxFIFOConfigSet().
-//!
-//! \return Returns the FIFO status, enumerated as a bit field containing
-//! \b I2C_FIFO_RX_BELOW_TRIG_LEVEL, \b I2C_FIFO_RX_FULL, \b I2C_FIFO_RX_EMPTY,
-//! \b I2C_FIFO_TX_BELOW_TRIG_LEVEL, \b I2C_FIFO_TX_FULL, and
-//! \b I2C_FIFO_TX_EMPTY.
-//
-//*****************************************************************************
-uint32_t
-I2CFIFOStatus(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Return the contents of the FIFO status register.
-    //
-    return(HWREG(ui32Base + I2C_O_FIFOSTATUS));
-}
-
-//*****************************************************************************
-//
-//! Writes a data byte to the I2C transmit FIFO.
-//!
-//! \param ui32Base is the base address of the I2C Master or Slave module.
-//! \param ui8Data is the data to be placed into the transmit FIFO.
-//!
-//! This function adds a byte of data to the I2C transmit FIFO.  If there is
-//! no space available in the FIFO,  this function waits for space to become
-//! available before returning.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Wait until there is space.
-    //
-    while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF)
-    {
-    }
-
-    //
-    // Place data into the FIFO.
-    //
-    HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data;
-}
-
-//*****************************************************************************
-//
-//! Writes a data byte to the I2C transmit FIFO.
-//!
-//! \param ui32Base is the base address of the I2C Master or Slave module.
-//! \param ui8Data is the data to be placed into the transmit FIFO.
-//!
-//! This function adds a byte of data to the I2C transmit FIFO.  If there is
-//! no space available in the FIFO, this function returns a zero.
-//!
-//! \return The number of elements added to the I2C transmit FIFO.
-//
-//*****************************************************************************
-uint32_t
-I2CFIFODataPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // If FIFO is full, return zero.
-    //
-    if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF)
-    {
-        return(0);
-    }
-    else
-    {
-        HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data;
-        return(1);
-    }
-}
-
-//*****************************************************************************
-//
-//! Reads a byte from the I2C receive FIFO.
-//!
-//! \param ui32Base is the base address of the I2C Master or Slave module.
-//!
-//! This function reads a byte of data from I2C receive FIFO and places it in
-//! the location specified by the \e pui8Data parameter.  If there is no data
-//! available, this function waits until data is received before returning.
-//!
-//! \return The data byte.
-//
-//*****************************************************************************
-uint32_t
-I2CFIFODataGet(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Wait until there is data to read.
-    //
-    while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE)
-    {
-    }
-
-    //
-    // Read a byte.
-    //
-    return(HWREG(ui32Base + I2C_O_FIFODATA));
-}
-
-//*****************************************************************************
-//
-//! Reads a byte from the I2C receive FIFO.
-//!
-//! \param ui32Base is the base address of the I2C Master or Slave module.
-//! \param pui8Data is a pointer where the read data is stored.
-//!
-//! This function reads a byte of data from I2C receive FIFO and places it in
-//! the location specified by the \e pui8Data parameter.  If there is no data
-//! available, this functions returns 0.
-//!
-//! \return The number of elements read from the I2C receive FIFO.
-//
-//*****************************************************************************
-uint32_t
-I2CFIFODataGetNonBlocking(uint32_t ui32Base, uint8_t *pui8Data)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // If nothing in the FIFO, return zero.
-    //
-    if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE)
-    {
-        return(0);
-    }
-    else
-    {
-        *pui8Data = HWREG(ui32Base + I2C_O_FIFODATA);
-        return(1);
-    }
-}
-
-//*****************************************************************************
-//
-//! Set the burst length for a I2C master FIFO operation.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//! \param ui8Length is the length of the burst transfer.
-//!
-//! This function configures the burst length for a I2C Master FIFO operation.
-//! The burst field is limited to 8 bits or 256 bytes.  The burst length
-//! applies to a single I2CMCS BURST operation meaning that it specifies the
-//! burst length for only the current operation (can be TX or RX).  Each burst
-//! operation must configure the burst length prior to writing the BURST bit
-//! in the I2CMCS using I2CMasterControl().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CMasterBurstLengthSet(uint32_t ui32Base, uint8_t ui8Length)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base) && (ui8Length < 255));
-
-    //
-    // Set the burst length.
-    //
-    HWREG(ui32Base + I2C_O_MBLEN) = ui8Length;
-}
-
-//*****************************************************************************
-//
-//! Returns the current value of the burst transfer counter.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//!
-//! This function returns the current value of the burst transfer counter that
-//! is used by the FIFO mechanism.  Software can use this value to determine
-//! how many bytes remain in a transfer, or where in the transfer the burst
-//! operation was if an error has occurred.
-//!
-//! \return None.
-//
-//*****************************************************************************
-uint32_t
-I2CMasterBurstCountGet(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Get burst count.
-    //
-    return(HWREG(ui32Base + I2C_O_MBCNT));
-}
-
-//*****************************************************************************
-//
-//! Configures the I2C Master glitch filter.
-//!
-//! \param ui32Base is the base address of the I2C Master module.
-//! \param ui32Config is the glitch filter configuration.
-//!
-//! This function configures the I2C Master glitch filter.  The value passed in
-//! to \e ui32Config determines the sampling range of the glitch filter, which
-//! is configurable between 1 and 32 system clock cycles.  The default
-//! configuration of the glitch filter is 0 system clock cycles, which means
-//! that it's disabled.
-//!
-//! The \e ui32Config field should be any of the following values:
-//!
-//! - \b I2C_MASTER_GLITCH_FILTER_DISABLED
-//! - \b I2C_MASTER_GLITCH_FILTER_1
-//! - \b I2C_MASTER_GLITCH_FILTER_2
-//! - \b I2C_MASTER_GLITCH_FILTER_3
-//! - \b I2C_MASTER_GLITCH_FILTER_4
-//! - \b I2C_MASTER_GLITCH_FILTER_8
-//! - \b I2C_MASTER_GLITCH_FILTER_16
-//! - \b I2C_MASTER_GLITCH_FILTER_32
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, uint32_t ui32Config)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Configure the glitch filter field of MTPR.
-    //
-    HWREG(ui32Base + I2C_O_MTPR) |= ui32Config;
-}
-
-//*****************************************************************************
-//
-//! Enables FIFO usage for the I2C Slave module.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//! \param ui32Config is the desired FIFO configuration of the I2C Slave.
-//!
-//! This function configures the I2C Slave module to use the FIFO(s).  This
-//! function should be used in combination with I2CTxFIFOConfigSet() and/or
-//! I2CRxFIFOConfigSet(), which configure the FIFO trigger level and tell
-//! the FIFO hardware whether to interact with the I2C Master or Slave.  The
-//! application appropriate combination of \b I2C_SLAVE_TX_FIFO_ENABLE and
-//! \b I2C_SLAVE_RX_FIFO_ENABLE should be passed in to the \e ui32Config
-//! field.
-//!
-//! The Slave I2CSCSR register is write-only, so any call to I2CSlaveEnable(),
-//! I2CSlaveDisable or I2CSlaveFIFOEnable() overwrites the slave configuration.
-//! Therefore, application software should call I2CSlaveEnable() followed by
-//! I2CSlaveFIFOEnable() with the desired FIFO configuration.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Enable the FIFOs for the slave.
-    //
-    HWREG(ui32Base + I2C_O_SCSR) = ui32Config | I2C_SCSR_DA;
-}
-
-//*****************************************************************************
-//
-//! Disable FIFO usage for the I2C Slave module.
-//!
-//! \param ui32Base is the base address of the I2C Slave module.
-//!
-//! This function disables the FIFOs for the I2C Slave.  After calling this
-//! this function, the FIFOs are disabled, but the Slave remains active.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-I2CSlaveFIFODisable(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_I2CBaseValid(ui32Base));
-
-    //
-    // Disable slave FIFOs.
-    //
-    HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA;
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
diff --git a/cc3200/hal/i2c.h b/cc3200/hal/i2c.h
deleted file mode 100644
index d966dbf56..000000000
--- a/cc3200/hal/i2c.h
+++ /dev/null
@@ -1,360 +0,0 @@
-//*****************************************************************************
-//
-//  i2c.h
-//
-//  Prototypes for the I2C Driver.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __DRIVERLIB_I2C_H__
-#define __DRIVERLIB_I2C_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Defines for the API.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-// Interrupt defines.
-//
-//*****************************************************************************
-#define I2C_INT_MASTER          0x00000001
-#define I2C_INT_SLAVE           0x00000002
-
-//*****************************************************************************
-//
-// I2C Master commands.
-//
-//*****************************************************************************
-#define I2C_MASTER_CMD_SINGLE_SEND                                            \
-                                0x00000007
-#define I2C_MASTER_CMD_SINGLE_RECEIVE                                         \
-                                0x00000007
-#define I2C_MASTER_CMD_BURST_SEND_START                                       \
-                                0x00000003
-#define I2C_MASTER_CMD_BURST_SEND_CONT                                        \
-                                0x00000001
-#define I2C_MASTER_CMD_BURST_SEND_FINISH                                      \
-                                0x00000005
-#define I2C_MASTER_CMD_BURST_SEND_STOP                                        \
-                                0x00000004
-#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP                                  \
-                                0x00000004
-#define I2C_MASTER_CMD_BURST_RECEIVE_START                                    \
-                                0x0000000b
-#define I2C_MASTER_CMD_BURST_RECEIVE_CONT                                     \
-                                0x00000009
-#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH                                   \
-                                0x00000005
-#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP                               \
-                                0x00000004
-#define I2C_MASTER_CMD_QUICK_COMMAND                                          \
-                                0x00000027
-#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND                                    \
-                                0x00000013
-#define I2C_MASTER_CMD_FIFO_SINGLE_SEND                                       \
-                                0x00000046
-#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE                                    \
-                                0x00000046
-#define I2C_MASTER_CMD_FIFO_BURST_SEND_START                                  \
-                                0x00000042
-#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT                                   \
-                                0x00000040
-#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH                                 \
-                                0x00000044
-#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP                             \
-                                0x00000004
-#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START                               \
-                                0x0000004a
-#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT                                \
-                                0x00000048
-#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH                              \
-                                0x00000044
-#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP                          \
-                                0x00000004
-
-//*****************************************************************************
-//
-// I2C Master glitch filter configuration.
-//
-//*****************************************************************************
-#define I2C_MASTER_GLITCH_FILTER_DISABLED                                     \
-                                0
-#define I2C_MASTER_GLITCH_FILTER_1                                            \
-                                0x00010000
-#define I2C_MASTER_GLITCH_FILTER_2                                            \
-                                0x00020000
-#define I2C_MASTER_GLITCH_FILTER_3                                            \
-                                0x00030000
-#define I2C_MASTER_GLITCH_FILTER_4                                            \
-                                0x00040000
-#define I2C_MASTER_GLITCH_FILTER_8                                            \
-                                0x00050000
-#define I2C_MASTER_GLITCH_FILTER_16                                           \
-                                0x00060000
-#define I2C_MASTER_GLITCH_FILTER_32                                           \
-                                0x00070000
-
-//*****************************************************************************
-//
-// I2C Master error status.
-//
-//*****************************************************************************
-#define I2C_MASTER_ERR_NONE     0
-#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
-#define I2C_MASTER_ERR_DATA_ACK 0x00000008
-#define I2C_MASTER_ERR_ARB_LOST 0x00000010
-#define I2C_MASTER_ERR_CLK_TOUT 0x00000080
-
-//*****************************************************************************
-//
-// I2C Slave action requests
-//
-//*****************************************************************************
-#define I2C_SLAVE_ACT_NONE      0
-#define I2C_SLAVE_ACT_RREQ      0x00000001  // Master has sent data
-#define I2C_SLAVE_ACT_TREQ      0x00000002  // Master has requested data
-#define I2C_SLAVE_ACT_RREQ_FBR  0x00000005  // Master has sent first byte
-#define I2C_SLAVE_ACT_OWN2SEL   0x00000008  // Master requested secondary slave
-#define I2C_SLAVE_ACT_QCMD      0x00000010  // Master has sent a Quick Command
-#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020  // Master Quick Command value
-
-//*****************************************************************************
-//
-// Miscellaneous I2C driver definitions.
-//
-//*****************************************************************************
-#define I2C_MASTER_MAX_RETRIES  1000        // Number of retries
-
-//*****************************************************************************
-//
-// I2C Master interrupts.
-//
-//*****************************************************************************
-#define I2C_MASTER_INT_RX_FIFO_FULL                                           \
-                                0x00000800  // RX FIFO Full Interrupt
-#define I2C_MASTER_INT_TX_FIFO_EMPTY                                          \
-                                0x00000400  // TX FIFO Empty Interrupt
-#define I2C_MASTER_INT_RX_FIFO_REQ                                            \
-                                0x00000200  // RX FIFO Request Interrupt
-#define I2C_MASTER_INT_TX_FIFO_REQ                                            \
-                                0x00000100  // TX FIFO Request Interrupt
-#define I2C_MASTER_INT_ARB_LOST                                               \
-                                0x00000080  // Arb Lost Interrupt
-#define I2C_MASTER_INT_STOP     0x00000040  // Stop Condition Interrupt
-#define I2C_MASTER_INT_START    0x00000020  // Start Condition Interrupt
-#define I2C_MASTER_INT_NACK     0x00000010  // Addr/Data NACK Interrupt
-#define I2C_MASTER_INT_TX_DMA_DONE                                            \
-                                0x00000008  // TX DMA Complete Interrupt
-#define I2C_MASTER_INT_RX_DMA_DONE                                            \
-                                0x00000004  // RX DMA Complete Interrupt
-#define I2C_MASTER_INT_TIMEOUT  0x00000002  // Clock Timeout Interrupt
-#define I2C_MASTER_INT_DATA     0x00000001  // Data Interrupt
-
-//*****************************************************************************
-//
-// I2C Slave interrupts.
-//
-//*****************************************************************************
-#define I2C_SLAVE_INT_RX_FIFO_FULL                                            \
-                                0x00000100  // RX FIFO Full Interrupt
-#define I2C_SLAVE_INT_TX_FIFO_EMPTY                                           \
-                                0x00000080  // TX FIFO Empty Interrupt
-#define I2C_SLAVE_INT_RX_FIFO_REQ                                             \
-                                0x00000040  // RX FIFO Request Interrupt
-#define I2C_SLAVE_INT_TX_FIFO_REQ                                             \
-                                0x00000020  // TX FIFO Request Interrupt
-#define I2C_SLAVE_INT_TX_DMA_DONE                                             \
-                                0x00000010  // TX DMA Complete Interrupt
-#define I2C_SLAVE_INT_RX_DMA_DONE                                             \
-                                0x00000008  // RX DMA Complete Interrupt
-#define I2C_SLAVE_INT_STOP      0x00000004  // Stop Condition Interrupt
-#define I2C_SLAVE_INT_START     0x00000002  // Start Condition Interrupt
-#define I2C_SLAVE_INT_DATA      0x00000001  // Data Interrupt
-
-//*****************************************************************************
-//
-// I2C Slave FIFO configuration macros.
-//
-//*****************************************************************************
-#define I2C_SLAVE_TX_FIFO_ENABLE                                              \
-                                0x00000002
-#define I2C_SLAVE_RX_FIFO_ENABLE                                              \
-                                0x00000004
-
-//*****************************************************************************
-//
-// I2C FIFO configuration macros.
-//
-//*****************************************************************************
-#define I2C_FIFO_CFG_TX_MASTER  0x00000000
-#define I2C_FIFO_CFG_TX_SLAVE   0x00008000
-#define I2C_FIFO_CFG_RX_MASTER  0x00000000
-#define I2C_FIFO_CFG_RX_SLAVE   0x80000000
-#define I2C_FIFO_CFG_TX_MASTER_DMA                                            \
-                                0x00002000
-#define I2C_FIFO_CFG_TX_SLAVE_DMA                                             \
-                                0x0000a000
-#define I2C_FIFO_CFG_RX_MASTER_DMA                                            \
-                                0x20000000
-#define I2C_FIFO_CFG_RX_SLAVE_DMA                                             \
-                                0xa0000000
-#define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000
-#define I2C_FIFO_CFG_TX_TRIG_1  0x00000001
-#define I2C_FIFO_CFG_TX_TRIG_2  0x00000002
-#define I2C_FIFO_CFG_TX_TRIG_3  0x00000003
-#define I2C_FIFO_CFG_TX_TRIG_4  0x00000004
-#define I2C_FIFO_CFG_TX_TRIG_5  0x00000005
-#define I2C_FIFO_CFG_TX_TRIG_6  0x00000006
-#define I2C_FIFO_CFG_TX_TRIG_7  0x00000007
-#define I2C_FIFO_CFG_TX_TRIG_8  0x00000008
-#define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000
-#define I2C_FIFO_CFG_RX_TRIG_1  0x00010000
-#define I2C_FIFO_CFG_RX_TRIG_2  0x00020000
-#define I2C_FIFO_CFG_RX_TRIG_3  0x00030000
-#define I2C_FIFO_CFG_RX_TRIG_4  0x00040000
-#define I2C_FIFO_CFG_RX_TRIG_5  0x00050000
-#define I2C_FIFO_CFG_RX_TRIG_6  0x00060000
-#define I2C_FIFO_CFG_RX_TRIG_7  0x00070000
-#define I2C_FIFO_CFG_RX_TRIG_8  0x00080000
-
-//*****************************************************************************
-//
-// I2C FIFO status.
-//
-//*****************************************************************************
-#define I2C_FIFO_RX_BELOW_TRIG_LEVEL                                          \
-                                0x00040000
-#define I2C_FIFO_RX_FULL        0x00020000
-#define I2C_FIFO_RX_EMPTY       0x00010000
-#define I2C_FIFO_TX_BELOW_TRIG_LEVEL                                          \
-                                0x00000004
-#define I2C_FIFO_TX_FULL        0x00000002
-#define I2C_FIFO_TX_EMPTY       0x00000001
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-extern void I2CIntRegister(uint32_t ui32Base, void(pfnHandler)(void));
-extern void I2CIntUnregister(uint32_t ui32Base);
-extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
-extern void I2CTxFIFOFlush(uint32_t ui32Base);
-extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
-extern void I2CRxFIFOFlush(uint32_t ui32Base);
-extern uint32_t I2CFIFOStatus(uint32_t ui32Base);
-extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data);
-extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base,
-                                          uint8_t ui8Data);
-extern uint32_t I2CFIFODataGet(uint32_t ui32Base);
-extern uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base,
-                                          uint8_t *pui8Data);
-extern void I2CMasterBurstLengthSet(uint32_t ui32Base,
-                                    uint8_t ui8Length);
-extern uint32_t I2CMasterBurstCountGet(uint32_t ui32Base);
-extern void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base,
-                                           uint32_t ui32Config);
-extern void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config);
-extern void I2CSlaveFIFODisable(uint32_t ui32Base);
-extern bool I2CMasterBusBusy(uint32_t ui32Base);
-extern bool I2CMasterBusy(uint32_t ui32Base);
-extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd);
-extern uint32_t I2CMasterDataGet(uint32_t ui32Base);
-extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data);
-extern void I2CMasterDisable(uint32_t ui32Base);
-extern void I2CMasterEnable(uint32_t ui32Base);
-extern uint32_t I2CMasterErr(uint32_t ui32Base);
-extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32SCLFreq);
-extern void I2CMasterIntClear(uint32_t ui32Base);
-extern void I2CMasterIntDisable(uint32_t ui32Base);
-extern void I2CMasterIntEnable(uint32_t ui32Base);
-extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked);
-extern void I2CMasterIntEnableEx(uint32_t ui32Base,
-                                 uint32_t ui32IntFlags);
-extern void I2CMasterIntDisableEx(uint32_t ui32Base,
-                                  uint32_t ui32IntFlags);
-extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base,
-                                       bool bMasked);
-extern void I2CMasterIntClearEx(uint32_t ui32Base,
-                                uint32_t ui32IntFlags);
-extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value);
-extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable);
-extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK);
-extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base);
-extern void I2CMasterSlaveAddrSet(uint32_t ui32Base,
-                                  uint8_t ui8SlaveAddr,
-                                  bool bReceive);
-extern uint32_t I2CSlaveDataGet(uint32_t ui32Base);
-extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data);
-extern void I2CSlaveDisable(uint32_t ui32Base);
-extern void I2CSlaveEnable(uint32_t ui32Base);
-extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr);
-extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum,
-                                 uint8_t ui8SlaveAddr);
-extern void I2CSlaveIntClear(uint32_t ui32Base);
-extern void I2CSlaveIntDisable(uint32_t ui32Base);
-extern void I2CSlaveIntEnable(uint32_t ui32Base);
-extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags);
-extern void I2CSlaveIntDisableEx(uint32_t ui32Base,
-                                 uint32_t ui32IntFlags);
-extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags);
-extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked);
-extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base,
-                                      bool bMasked);
-extern uint32_t I2CSlaveStatus(uint32_t ui32Base);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __DRIVERLIB_I2C_H__
diff --git a/cc3200/hal/i2s.c b/cc3200/hal/i2s.c
deleted file mode 100644
index dbbb936d7..000000000
--- a/cc3200/hal/i2s.c
+++ /dev/null
@@ -1,1012 +0,0 @@
-//*****************************************************************************

-//

-//  i2s.c

-//

-//  Driver for the I2S interface.

-//

-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/

-//

-//

-//  Redistribution and use in source and binary forms, with or without

-//  modification, are permitted provided that the following conditions

-//  are met:

-//

-//    Redistributions of source code must retain the above copyright

-//    notice, this list of conditions and the following disclaimer.

-//

-//    Redistributions in binary form must reproduce the above copyright

-//    notice, this list of conditions and the following disclaimer in the

-//    documentation and/or other materials provided with the

-//    distribution.

-//

-//    Neither the name of Texas Instruments Incorporated nor the names of

-//    its contributors may be used to endorse or promote products derived

-//    from this software without specific prior written permission.

-//

-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-//

-//*****************************************************************************

-

-//*****************************************************************************

-//

-//! \addtogroup I2S_api

-//! @{

-//

-//*****************************************************************************

-#include "inc/hw_types.h"

-#include "inc/hw_ints.h"

-#include "inc/hw_memmap.h"

-#include "inc/hw_mcasp.h"

-#include "inc/hw_apps_config.h"

-#include "interrupt.h"

-#include "i2s.h"

-

-//*****************************************************************************

-// Macros

-//*****************************************************************************

-#define MCASP_GBL_RCLK		0x00000001

-#define MCASP_GBL_RHCLK		0x00000002

-#define MCASP_GBL_RSER		0x00000004

-#define MCASP_GBL_RSM		0x00000008

-#define MCASP_GBL_RFSYNC	0x00000010

-#define MCASP_GBL_XCLK		0x00000100

-#define MCASP_GBL_XHCLK		0x00000200

-#define MCASP_GBL_XSER		0x00000400

-#define MCASP_GBL_XSM		0x00000800

-#define MCASP_GBL_XFSYNC	0x00001000

-

-

-//*****************************************************************************

-//

-//! \internal

-//! Releases the specifed submodule out of reset.

-//!

-//! \param ulBase is the base address of the I2S module.

-//! \param ulFlag is one of the valid sub module.

-//!

-//! This function Releases the specifed submodule out of reset.

-//!

-//! \return None.

-//

-//*****************************************************************************

-static void I2SGBLEnable(unsigned long ulBase, unsigned long ulFlag)

-{

-  unsigned long ulReg;

-

-  //

-  // Read global control register

-  //

-  ulReg = HWREG(ulBase + MCASP_O_GBLCTL);

-

-  //

-  // Remove the sub modules reset as specified by ulFlag parameter

-  //

-  ulReg |= ulFlag;

-

-  //

-  // Write the configuration

-  //

-  HWREG(ulBase + MCASP_O_GBLCTL) = ulReg;

-

-  //

-  // Wait for write completeion

-  //

-  while(HWREG(ulBase + MCASP_O_GBLCTL) != ulReg)

-  {

-

-  }

-

-}

-

-//*****************************************************************************

-//

-//! Enables transmit and/or receive.

-//!

-//! \param ulBase is the base address of the I2S module.

-//! \param ulMode is one of the valid modes.

-//!

-//! This function enables the I2S module in specified mode. The parameter

-//! \e ulMode should be one of the following

-//!

-//! -\b I2S_MODE_TX_ONLY

-//! -\b I2S_MODE_TX_RX_SYNC

-//!

-//! \return None.

-//

-//*****************************************************************************

-void I2SEnable(unsigned long ulBase, unsigned long ulMode)

-{

-  //

-  // FSYNC and Bit clock are output only in master mode

-  //

-  if( HWREG(ulBase + MCASP_O_ACLKXCTL) & 0x20)

-  {

-    //

-    // Set FSYNC anc BitClk as output

-    //

-    HWREG(ulBase + MCASP_O_PDIR) |= 0x14000000;

-  }

-

-

-  if(ulMode & 0x2)

-  {

-    //

-    // Remove Rx HCLK reset

-    //

-    I2SGBLEnable(ulBase, MCASP_GBL_RHCLK);

-

-    //

-    // Remove Rx XCLK reset

-    //

-    I2SGBLEnable(ulBase, MCASP_GBL_RCLK);

-

-    //

-    // Enable Rx SERDES(s)

-    //

-    I2SGBLEnable(ulBase, MCASP_GBL_RSER);

-

-    //

-    // Enable Rx state machine

-    //

-    I2SGBLEnable(ulBase, MCASP_GBL_RSM);

-

-    //

-    // Enable FSync generator

-    //

-    I2SGBLEnable(ulBase, MCASP_GBL_RFSYNC);

-  }

-

-

-  //

-  // Remove Tx  HCLK reset

-  //

-  I2SGBLEnable(ulBase, MCASP_GBL_XHCLK);

-

-  //

-  // Remove Tx XCLK reset

-  //

-  I2SGBLEnable(ulBase, MCASP_GBL_XCLK);

-

-

-  if(ulMode & 0x1)

-  {

-    //

-    // Enable Tx SERDES(s)

-    //

-    I2SGBLEnable(ulBase, MCASP_GBL_XSER);

-

-    //

-    // Enable Tx state machine

-    //

-    I2SGBLEnable(ulBase, MCASP_GBL_XSM);

-  }

-

-   //

-   // Enable FSync generator

-   //

-   I2SGBLEnable(ulBase, MCASP_GBL_XFSYNC);

-}

-

-//*****************************************************************************

-//

-//! Disables transmit and/or receive.

-//!

-//! \param ulBase is the base address of the I2S module.

-//!

-//! This function disables transmit and/or receive from I2S module.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void I2SDisable(unsigned long ulBase)

-{

-  //

-  // Reset all sub modules

-  //

-  HWREG(ulBase + MCASP_O_GBLCTL) = 0;

-

-  //

-  // Wait for write to complete

-  //

-  while( HWREG(ulBase + MCASP_O_GBLCTL) != 0)

-  {

-

-  }

-}

-

-//*****************************************************************************

-//

-//! Waits to send data over the specified data line

-//!

-//! \param ulBase is the base address of the I2S module.

-//! \param ulDataLine is one of the valid data lines.

-//! \param ulData is the data to be transmitted.

-//!

-//! This function sends the \e ucData to the transmit register for the

-//! specified data line. If there is no space available, this

-//! function waits until there is space available before returning.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void I2SDataPut(unsigned long ulBase, unsigned long ulDataLine,

-                unsigned long ulData)

-{

-  //

-  // Compute register the offeset

-  //

-  ulDataLine = (ulDataLine-1) << 2;

-

-  //

-  // Wait for free space in fifo

-  //

-  while(!( HWREG(ulBase + MCASP_O_TXSTAT) & MCASP_TXSTAT_XDATA))

-  {

-

-  }

-

-  //

-  // Write Data into the FIFO

-  //

-  HWREG(ulBase + MCASP_O_TXBUF0 + ulDataLine) = ulData;

-}

-

-//*****************************************************************************

-//

-//! Sends data over the specified data line

-//!

-//! \param ulBase is the base address of the I2S module.

-//! \param ulDataLine is one of the valid data lines.

-//! \param ulData is the data to be transmitted.

-//!

-//! This function writes the \e ucData to the transmit register for

-//! the specified data line. This function does not block, so if there is no

-//! space available, then \b -1 is returned, and the application must retry the

-//! function later.

-//!

-//! \return Returns 0 on success, -1 otherwise.

-//

-//*****************************************************************************

-long I2SDataPutNonBlocking(unsigned long ulBase,  unsigned long ulDataLine,

-                           unsigned long ulData)

-{

-

-  //

-  // Compute register the offeset

-  //

-  ulDataLine = (ulDataLine-1) << 2;

-

-  //

-  // Send Data if fifo has free space

-  //

-  if( HWREG(ulBase + MCASP_O_TXSTAT) & MCASP_TXSTAT_XDATA)

-  {

-    //

-    // Write data into the FIFO

-    //

-    HWREG(ulBase + MCASP_O_TXBUF0 + ulDataLine) = ulData;

-    return 0;

-  }

-

-  //

-  // FIFO is full

-  //

-  return(-1);

-}

-

-//*****************************************************************************

-//

-//! Waits for data from the specified data line.

-//!

-//! \param ulBase is the base address of the I2S module.

-//! \param ulDataLine is one of the valid data lines.

-//! \param pulData is pointer to receive data variable.

-//!

-//! This function gets data from the receive register for the specified

-//! data line. If there are no data available, this function waits until a

-//! receive before returning.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void I2SDataGet(unsigned long ulBase, unsigned long ulDataLine,

-                unsigned long *pulData)

-{

-

-  //

-  // Compute register the offeset

-  //

-  ulDataLine = (ulDataLine-1) << 2;

-

-  //

-  // Wait for atleat on word in FIFO

-  //

-  while(!(HWREG(ulBase + MCASP_O_RXSTAT) & MCASP_RXSTAT_RDATA))

-  {

-

-  }

-

-  //

-  // Read the Data

-  //

-  *pulData = HWREG(ulBase + MCASP_O_RXBUF0 + ulDataLine);

-}

-

-

-//*****************************************************************************

-//

-//! Receives data from the specified data line.

-//!

-//! \param ulBase is the base address of the I2S module.

-//! \param ulDataLine is one of the valid data lines.

-//! \param pulData is pointer to receive data variable.

-//!

-//! This function gets data from the receive register for the specified

-//! data line.

-//!

-//!

-//! \return Returns 0 on success, -1 otherwise.

-//

-//*****************************************************************************

-long I2SDataGetNonBlocking(unsigned long ulBase, unsigned long ulDataLine,

-                unsigned long *pulData)

-{

-

-  //

-  // Compute register the offeset

-  //

-  ulDataLine = (ulDataLine-1) << 2;

-

-  //

-  // Check if data is available in FIFO

-  //

-  if(HWREG(ulBase + MCASP_O_RXSTAT) & MCASP_RXSTAT_RDATA)

-  {

-    //

-    // Read the Data

-    //

-    *pulData = HWREG(ulBase + MCASP_O_RXBUF0 + ulDataLine);

-    return 0;

-  }

-

-  //

-  // FIFO is empty

-  //

-  return -1;

-}

-

-

-//*****************************************************************************

-//

-//! Sets the configuration of the I2S module.

-//!

-//! \param ulBase is the base address of the I2S module.

-//! \param ulI2SClk is the rate of the clock supplied to the I2S module.

-//! \param ulBitClk is the desired bit rate.

-//! \param ulConfig is the data format.

-//!

-//! This function configures the I2S for operation in the specified data

-//! format.  The bit rate is provided in the \e ulBitClk parameter and the data

-//! format in the \e ulConfig parameter.

-//!

-//! The \e ulConfig parameter is the logical OR of three values: the slot size

-//! the data read/write port select, Master or Slave mode

-//!

-//! Follwoing selects the Master-Slave mode

-//! -\b I2S_MODE_MASTER

-//! -\b I2S_MODE_SLAVE

-//!

-//! Following selects the slot size:

-//! -\b I2S_SLOT_SIZE_24

-//! -\b I2S_SLOT_SIZE_16

-//!

-//! Following selects the data read/write port:

-//! -\b I2S_PORT_DMA

-//! -\b I2S_PORT_CPU

-//!

-//! \return None.

-//

-//*****************************************************************************

-void I2SConfigSetExpClk(unsigned long ulBase, unsigned long ulI2SClk,

-                               unsigned long ulBitClk, unsigned long ulConfig)

-{

-  unsigned long ulHClkDiv;

-  unsigned long ulClkDiv;

-  unsigned long ulSlotSize;

-  unsigned long ulBitMask;

-

-  //

-  // Calculate clock dividers

-  //

-  ulHClkDiv = ((ulI2SClk/ulBitClk)-1);

-  ulClkDiv  = 0;

-

-  //

-  // Check if HCLK divider is overflowing

-  //

-  if(ulHClkDiv > 0xFFF)

-  {

-    ulHClkDiv = 0xFFF;

-

-    //

-    // Calculate clock divider

-    //

-    ulClkDiv = ((ulI2SClk/(ulBitClk * (ulHClkDiv + 1))) & 0x1F);

-  }

-

-  //

-  //

-  //

-  ulClkDiv = ((ulConfig & I2S_MODE_SLAVE )?0x80:0xA0|ulClkDiv);

-

-  HWREG(ulBase + MCASP_O_ACLKXCTL) = ulClkDiv;

-

-  HWREG(ulBase + MCASP_O_AHCLKXCTL) = (0x8000|ulHClkDiv);

-

-  //

-  // Write the Tx format register

-  //

-  HWREG(ulBase + MCASP_O_TXFMT) = (0x18000 | (ulConfig & 0x7FFF));

-

-  //

-  // Write the Rx format register

-  //

-  HWREG(ulBase + MCASP_O_RXFMT) = (0x18000 | ((ulConfig >> 16) &0x7FFF));

-

-  //

-  // Check if in master mode

-  //

-  if( ulConfig & I2S_MODE_SLAVE)

-  {

-    //

-    // Configure Tx FSync generator in I2S mode

-    //

-    HWREG(ulBase + MCASP_O_TXFMCTL) = 0x111;

-

-    //

-    // Configure Rx FSync generator in I2S mode

-    //

-    HWREG(ulBase + MCASP_O_RXFMCTL) = 0x111;

-  }

-  else

-  {

-    //

-    // Configure Tx FSync generator in I2S mode

-    //

-    HWREG(ulBase + MCASP_O_TXFMCTL) = 0x113;

-

-    //

-    // Configure Rx FSync generator in I2S mode

-    //

-    HWREG(ulBase + MCASP_O_RXFMCTL) = 0x113;

-  }

-

-  //

-  // Compute Slot Size

-  //

-  ulSlotSize = ((((ulConfig & 0xFF) >> 4) + 1) * 2);

-

-  //

-  // Creat the bit mask

-  //

-  ulBitMask = (0xFFFFFFFF >> (32 - ulSlotSize));

-

-  //

-  // Set Tx bit valid mask

-  //

-  HWREG(ulBase + MCASP_O_TXMASK) = ulBitMask;

-

-  //

-  // Set Rx bit valid mask

-  //

-  HWREG(ulBase + MCASP_O_RXMASK) = ulBitMask;

-

-  //

-  // Set Tx slot valid mask

-  //

-  HWREG(ulBase + MCASP_O_TXTDM) = 0x3;

-

-  //

-  // Set Rx slot valid mask

-  //

-  HWREG(ulBase + MCASP_O_RXTDM) = 0x3;

-}

-

-//*****************************************************************************

-//

-//! Configure and enable transmit FIFO.

-//!

-//! \param ulBase is the base address of the I2S module.

-//! \param ulTxLevel is the transmit FIFO DMA request level.

-//! \param ulWordsPerTransfer is the nuber of words transferred from the FIFO.

-//!

-//! This function configures and enable I2S transmit FIFO.

-//!

-//! The parameter \e ulTxLevel sets the level at which transmit DMA requests

-//! are generated. This should be non-zero integer multiple of number of

-//! serializers enabled as transmitters

-//!

-//! The parameter \e ulWordsPerTransfer sets the number of words that are

-//! transferred from the transmit FIFO to the data line(s). This value must

-//! equal the number of serializers used as transmitters.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void I2STxFIFOEnable(unsigned long ulBase, unsigned long ulTxLevel,

-                     unsigned long ulWordsPerTransfer)

-{

-  //

-  // Set transmit FIFO configuration and

-  // enable it

-  //

-  HWREG(ulBase + MCASP_0_WFIFOCTL) = ((1 <<16) | ((ulTxLevel & 0xFF) << 8)

-					| (ulWordsPerTransfer & 0x1F));

-

-}

-

-//*****************************************************************************

-//

-//! Disables transmit FIFO.

-//!

-//! \param ulBase is the base address of the I2S module.

-//!

-//! This function disables the I2S transmit FIFO.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void I2STxFIFODisable(unsigned long ulBase)

-{

-  //

-  // Disable transmit FIFO.

-  //

-  HWREG(ulBase + MCASP_0_WFIFOCTL) = 0;

-}

-

-//*****************************************************************************

-//

-//! Configure and enable receive FIFO.

-//!

-//! \param ulBase is the base address of the I2S module.

-//! \param ulRxLevel is the receive FIFO DMA request level.

-//! \param ulWordsPerTransfer is the nuber of words transferred from the FIFO.

-//!

-//! This function configures and enable I2S receive FIFO.

-//!

-//! The parameter \e ulRxLevel sets the level at which receive DMA requests

-//! are generated. This should be non-zero integer multiple of number of

-//! serializers enabled as receivers.

-//!

-//! The parameter \e ulWordsPerTransfer sets the number of words that are

-//! transferred to the receive FIFO from the data line(s). This value must

-//! equal the number of serializers used as receivers.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void I2SRxFIFOEnable(unsigned long ulBase, unsigned long ulRxLevel,

-                     unsigned long ulWordsPerTransfer)

-{

-  //

-  // Set FIFO configuration

-  //

-  HWREG(ulBase + MCASP_0_RFIFOCTL) = ( (1 <<16) | ((ulRxLevel & 0xFF) << 8)

-					| (ulWordsPerTransfer & 0x1F));

-

-}

-

-//*****************************************************************************

-//

-//! Disables receive FIFO.

-//!

-//! \param ulBase is the base address of the I2S module.

-//!

-//! This function disables the I2S receive FIFO.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void I2SRxFIFODisable(unsigned long ulBase)

-{

-  //

-  // Disable receive FIFO.

-  //

-  HWREG(ulBase + MCASP_0_RFIFOCTL) = 0;

-}

-

-//*****************************************************************************

-//

-//! Get the transmit FIFO status.

-//!

-//! \param ulBase is the base address of the I2S module.

-//!

-//! This function gets the number of 32-bit words currently in the transmit

-//! FIFO.

-//!

-//! \return Returns transmit FIFO status.

-//

-//*****************************************************************************

-unsigned long I2STxFIFOStatusGet(unsigned long ulBase)

-{

-  //

-  // Return transmit FIFO level

-  //

-  return HWREG(ulBase + MCASP_0_WFIFOSTS);

-}

-

-//*****************************************************************************

-//

-//! Get the receive FIFO status.

-//!

-//! \param ulBase is the base address of the I2S module.

-//!

-//! This function gets the number of 32-bit words currently in the receive

-//! FIFO.

-//!

-//! \return Returns receive FIFO status.

-//

-//*****************************************************************************

-unsigned long I2SRxFIFOStatusGet(unsigned long ulBase)

-{

-  //

-  // Return receive FIFO level

-  //

-  return HWREG(ulBase + MCASP_0_RFIFOSTS);

-}

-

-//*****************************************************************************

-//

-//! Configure the serializer in specified mode.

-//!

-//! \param ulBase is the base address of the I2S module.

-//! \param ulDataLine is the data line (serilizer) to be configured.

-//! \param ulSerMode is the required serializer mode.

-//! \param ulInActState sets the inactive state of the data line.

-//!

-//! This function configure and enable the serializer associated with the given

-//! data line in specified mode.

-//!

-//! The paramenter \e ulDataLine selects to data line to be configured and

-//! can be one of the following:

-//! -\b I2S_DATA_LINE_0

-//! -\b I2S_DATA_LINE_1

-//!

-//! The parameter \e ulSerMode can be one of the following:

-//! -\b I2S_SER_MODE_TX

-//! -\b I2S_SER_MODE_RX

-//! -\b I2S_SER_MODE_DISABLE

-//!

-//! The parameter \e ulInActState can be one of the following

-//! -\b I2S_INACT_TRI_STATE

-//! -\b I2S_INACT_LOW_LEVEL

-//! -\b I2S_INACT_LOW_HIGH

-//!

-//! \return Returns receive FIFO status.

-//

-//*****************************************************************************

-void I2SSerializerConfig(unsigned long ulBase, unsigned long ulDataLine,

-                         unsigned long ulSerMode, unsigned long ulInActState)

-{

-  if( ulSerMode == I2S_SER_MODE_TX)

-  {

-    //

-    // Set the data line in output mode

-    //

-    HWREG(ulBase + MCASP_O_PDIR) |= ulDataLine;

-  }

-  else

-  {

-    //

-    // Set the data line in input mode

-    //

-    HWREG(ulBase + MCASP_O_PDIR) &= ~ulDataLine;

-  }

-

-  //

-  // Set the serializer configuration.

-  //

-  HWREG(ulBase + MCASP_O_XRSRCTL0 + ((ulDataLine-1) << 2))

-                                            = (ulSerMode | ulInActState);

-}

-

-//*****************************************************************************

-//

-//! Enables individual I2S interrupt sources.

-//!

-//! \param ulBase is the base address of the I2S module.

-//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.

-//!

-//! This function enables the indicated I2S interrupt sources.  Only the

-//! sources that are enabled can be reflected to the processor interrupt;

-//! disabled sources have no effect on the processor.

-//!

-//! The \e ulIntFlags parameter is the logical OR of any of the following:

-//!

-//! -\b I2S_INT_XUNDRN

-//! -\b I2S_INT_XSYNCERR

-//! -\b I2S_INT_XLAST

-//! -\b I2S_INT_XDATA

-//! -\b I2S_INT_XSTAFRM

-//! -\b I2S_INT_XDMA

-//! -\b I2S_INT_ROVRN

-//! -\b I2S_INT_RSYNCERR

-//! -\b I2S_INT_RLAST

-//! -\b I2S_INT_RDATA

-//! -\b I2S_INT_RSTAFRM

-//! -\b I2S_INT_RDMA

-//!

-//! \return None.

-//

-//*****************************************************************************

-void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags)

-{

-

-  //

-  // Enable DMA done interrupts

-  //

-  HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR )

-     |= ((ulIntFlags &0xC0000000) >> 20);

-

-  //

-  // Enable specific Tx Interrupts

-  //

-  HWREG(ulBase + MCASP_O_EVTCTLX) |= (ulIntFlags & 0xFF);

-

-  //

-  // Enable specific Rx Interrupts

-  //

-  HWREG(ulBase + MCASP_O_EVTCTLR) |= ((ulIntFlags >> 16) & 0xFF);

-}

-

-//*****************************************************************************

-//

-//! Disables individual I2S interrupt sources.

-//!

-//! \param ulBase is the base address of the I2S module.

-//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.

-//!

-//! This function disables the indicated I2S interrupt sources.  Only the

-//! sources that are enabled can be reflected to the processor interrupt;

-//! disabled sources have no effect on the processor.

-//!

-//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags

-//! parameter to I2SIntEnable().

-//!

-//! \return None.

-//

-//*****************************************************************************

-void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags)

-{

-  //

-  // Disable DMA done interrupts

-  //

-  HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET)

-     |= ((ulIntFlags &0xC0000000) >> 20);

-

-  //

-  // Disable specific Tx Interrupts

-  //

-  HWREG(ulBase + MCASP_O_EVTCTLX) &= ~(ulIntFlags & 0xFF);

-

-  //

-  // Disable specific Rx Interrupts

-  //

-  HWREG(ulBase + MCASP_O_EVTCTLR) &= ~((ulIntFlags >> 16) & 0xFF);

-}

-

-

-//*****************************************************************************

-//

-//! Gets the current interrupt status.

-//!

-//! \param ulBase is the base address of the I2S module.

-//!

-//! This function returns the raw interrupt status for I2S enumerated

-//! as a bit field of values:

-//! -\b I2S_STS_XERR

-//! -\b I2S_STS_XDMAERR

-//! -\b I2S_STS_XSTAFRM

-//! -\b I2S_STS_XDATA

-//! -\b I2S_STS_XLAST

-//! -\b I2S_STS_XSYNCERR

-//! -\b I2S_STS_XUNDRN

-//! -\b I2S_STS_XDMA

-//! -\b I2S_STS_RERR

-//! -\b I2S_STS_RDMAERR

-//! -\b I2S_STS_RSTAFRM

-//! -\b I2S_STS_RDATA

-//! -\b I2S_STS_RLAST

-//! -\b I2S_STS_RSYNCERR

-//! -\b I2S_STS_ROVERN

-//! -\b I2S_STS_RDMA

-//!

-//! \return Returns the current interrupt status, enumerated as a bit field of

-//! values described above.

-//

-//*****************************************************************************

-unsigned long I2SIntStatus(unsigned long ulBase)

-{

-  unsigned long ulStatus;

-

-  //

-  // Get DMA interrupt status

-  //

-  ulStatus =

-    HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW) << 20;

-

-  ulStatus &= 0xC0000000;

-

-  //

-  // Read Tx Interrupt status

-  //

-  ulStatus |= HWREG(ulBase + MCASP_O_TXSTAT);

-

-  //

-  // Read Rx Interrupt status

-  //

-  ulStatus |= HWREG(ulBase + MCASP_O_RXSTAT) << 16;

-

-  //

-  // Return the status

-  //

-  return ulStatus;

-}

-

-//*****************************************************************************

-//

-//! Clears I2S interrupt sources.

-//!

-//! \param ulBase is the base address of the I2S module.

-//! \param ulStatFlags is a bit mask of the interrupt sources to be cleared.

-//!

-//! The specified I2S interrupt sources are cleared, so that they no longer

-//! assert.  This function must be called in the interrupt handler to keep the

-//! interrupt from being recognized again immediately upon exit.

-//!

-//! The \e ulIntFlags parameter is the logical OR of any of the value

-//! describe in I2SIntStatus().

-//!

-//! \return None.

-//

-//*****************************************************************************

-void I2SIntClear(unsigned long ulBase, unsigned long ulStatFlags)

-{

-  //

-  // Clear DMA done interrupts

-  //

-  HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK)

-     |= ((ulStatFlags &0xC0000000) >> 20);

-

-  //

-  // Clear Tx Interrupt

-  //

-  HWREG(ulBase + MCASP_O_TXSTAT) = ulStatFlags & 0x1FF ;

-

-  //

-  // Clear Rx Interrupt

-  //

-  HWREG(ulBase + MCASP_O_RXSTAT) = (ulStatFlags >> 16) & 0x1FF;

-}

-

-//*****************************************************************************

-//

-//! Registers an interrupt handler for a I2S interrupt.

-//!

-//! \param ulBase is the base address of the I2S module.

-//! \param pfnHandler is a pointer to the function to be called when the

-//! I2S interrupt occurs.

-//!

-//! This function does the actual registering of the interrupt handler.  This

-//! function enables the global interrupt in the interrupt controller; specific

-//! I2S interrupts must be enabled via I2SIntEnable().  It is the interrupt

-//! handler's responsibility to clear the interrupt source.

-//!

-//! \sa IntRegister() for important information about registering interrupt

-//! handlers.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void))

-{

-  //

-  // Register the interrupt handler

-  //

-  IntRegister(INT_I2S,pfnHandler);

-

-  //

-  // Enable the interrupt

-  //

-  IntEnable(INT_I2S);

-}

-

-//*****************************************************************************

-//

-//! Unregisters an interrupt handler for a I2S interrupt.

-//!

-//! \param ulBase is the base address of the I2S module.

-//!

-//! This function does the actual unregistering of the interrupt handler.  It

-//! clears the handler to be called when a I2S interrupt occurs.  This

-//! function also masks off the interrupt in the interrupt controller so that

-//! the interrupt handler no longer is called.

-//!

-//! \sa IntRegister() for important information about registering interrupt

-//! handlers.

-//!

-//! \return None.

-//

-//*****************************************************************************

-void I2SIntUnregister(unsigned long ulBase)

-{

-  //

-  // Disable interrupt

-  //

-  IntDisable(INT_I2S);

-

-  //

-  // Unregister the handler

-  //

-  IntUnregister(INT_I2S);

-

-}

-

-//*****************************************************************************

-//

-//! Set the active slots for Trasmitter

-//!

-//! \param ulBase is the base address of the I2S module.

-//! \param ulActSlot is the bit-mask of activ slots

-//!

-//! This function sets the active slots for the transmitter. By default both

-//! the slots are active. The parameter \e ulActSlot is logical OR follwoing

-//! values:

-//! -\b I2S_ACT_SLOT_EVEN

-//! -\b I2S_ACT_SLOT_ODD

-//!

-//! \return None.

-//

-//*****************************************************************************

-void I2STxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot)

-{

-   HWREG(ulBase + MCASP_O_TXTDM) = ulActSlot;

-}

-

-//*****************************************************************************

-//

-//! Set the active slots for Receiver

-//!

-//! \param ulBase is the base address of the I2S module.

-//! \param ulActSlot is the bit-mask of activ slots

-//!

-//! This function sets the active slots for the receiver. By default both

-//! the slots are active. The parameter \e ulActSlot is logical OR follwoing

-//! values:

-//! -\b I2S_ACT_SLOT_EVEN

-//! -\b I2S_ACT_SLOT_ODD

-//!

-//! \return None.

-//

-//*****************************************************************************

-void I2SRxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot)

-{

-   HWREG(ulBase + MCASP_O_RXTDM) = ulActSlot;

-}

-

-//*****************************************************************************

-//

-// Close the Doxygen group.

-//! @}

-//

-//*****************************************************************************

diff --git a/cc3200/hal/i2s.h b/cc3200/hal/i2s.h
deleted file mode 100644
index 38620aef5..000000000
--- a/cc3200/hal/i2s.h
+++ /dev/null
@@ -1,218 +0,0 @@
-//*****************************************************************************

-//

-//  i2s.h

-//

-//  Defines and Macros for the I2S.

-//

-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/

-//

-//

-//  Redistribution and use in source and binary forms, with or without

-//  modification, are permitted provided that the following conditions

-//  are met:

-//

-//    Redistributions of source code must retain the above copyright

-//    notice, this list of conditions and the following disclaimer.

-//

-//    Redistributions in binary form must reproduce the above copyright

-//    notice, this list of conditions and the following disclaimer in the

-//    documentation and/or other materials provided with the

-//    distribution.

-//

-//    Neither the name of Texas Instruments Incorporated nor the names of

-//    its contributors may be used to endorse or promote products derived

-//    from this software without specific prior written permission.

-//

-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-//

-//*****************************************************************************

-

-#ifndef __I2S_H__

-#define __I2S_H__

-

-//*****************************************************************************

-//

-// If building with a C++ compiler, make all of the definitions in this header

-// have a C binding.

-//

-//*****************************************************************************

-#ifdef __cplusplus

-extern "C"

-{

-#endif

-

-//*****************************************************************************

-//

-// I2S DMA ports.

-//

-//*****************************************************************************

-#define I2S_TX_DMA_PORT      0x4401E200

-#define I2S_RX_DMA_PORT      0x4401E280

-

-//*****************************************************************************

-//

-// Values that can be passed to I2SConfigSetExpClk() as the ulConfig parameter.

-//

-//*****************************************************************************

-#define I2S_SLOT_SIZE_8       0x00300032

-#define I2S_SLOT_SIZE_16      0x00700074

-#define I2S_SLOT_SIZE_24      0x00B000B6

-

-

-#define I2S_PORT_CPU          0x00080008

-#define I2S_PORT_DMA          0x00000000

-

-#define I2S_MODE_MASTER       0x00000000

-#define I2S_MODE_SLAVE        0x00008000

-

-//*****************************************************************************

-//

-// Values that can be passed as ulDataLine parameter.

-//

-//*****************************************************************************

-#define I2S_DATA_LINE_0       0x00000001

-#define I2S_DATA_LINE_1       0x00000002

-

-//*****************************************************************************

-//

-// Values that can be passed to I2SSerializerConfig() as the ulSerMode

-// parameter.

-//

-//*****************************************************************************

-#define I2S_SER_MODE_TX       0x00000001

-#define I2S_SER_MODE_RX       0x00000002

-#define I2S_SER_MODE_DISABLE  0x00000000

-

-//*****************************************************************************

-//

-// Values that can be passed to I2SSerializerConfig() as the ulInActState

-// parameter.

-//

-//*****************************************************************************

-#define I2S_INACT_TRI_STATE   0x00000000

-#define I2S_INACT_LOW_LEVEL   0x00000008

-#define I2S_INACT_HIGH_LEVEL  0x0000000C

-

-//*****************************************************************************

-//

-// Values that can be passed to I2SIntEnable() and I2SIntDisable() as the

-// ulIntFlags parameter.

-//

-//*****************************************************************************

-#define I2S_INT_XUNDRN	      0x00000001

-#define I2S_INT_XSYNCERR      0x00000002

-#define I2S_INT_XLAST         0x00000010

-#define I2S_INT_XDATA         0x00000020

-#define I2S_INT_XSTAFRM       0x00000080

-#define I2S_INT_XDMA	      0x80000000

-#define I2S_INT_ROVRN         0x00010000

-#define I2S_INT_RSYNCERR      0x00020000

-#define I2S_INT_RLAST         0x00100000

-#define I2S_INT_RDATA         0x00200000

-#define I2S_INT_RSTAFRM       0x00800000

-#define I2S_INT_RDMA          0x40000000

-

-

-//*****************************************************************************

-//

-// Values that can be passed to I2SRxActiveSlotSet() and I2STxActiveSlotSet

-//

-//*****************************************************************************

-#define I2S_ACT_SLOT_EVEN     0x00000001

-#define I2S_ACT_SLOT_ODD      0x00000002

-

-//*****************************************************************************

-//

-// Values that can be passed to I2SIntClear() as the

-// ulIntFlags parameter and returned from I2SIntStatus().

-//

-//*****************************************************************************

-#define I2S_STS_XERR          0x00000100

-#define I2S_STS_XDMAERR	      0x00000080

-#define I2S_STS_XSTAFRM	      0x00000040

-#define I2S_STS_XDATA	      0x00000020

-#define I2S_STS_XLAST	      0x00000010

-#define I2S_STS_XSYNCERR      0x00000002

-#define I2S_STS_XUNDRN	      0x00000001

-#define I2S_STS_XDMA	      0x80000000

-#define I2S_STS_RERR          0x01000000

-#define I2S_STS_RDMAERR       0x00800000

-#define I2S_STS_RSTAFRM       0x00400000

-#define I2S_STS_RDATA         0x00200000

-#define I2S_STS_RLAST         0x00100000

-#define I2S_STS_RSYNCERR      0x00020000

-#define I2S_STS_ROVERN	      0x00010000

-#define I2S_STS_RDMA          0x40000000

-

-//*****************************************************************************

-//

-// Values that can be passed to I2SEnable() as the ulMode parameter.

-//

-//*****************************************************************************

-#define I2S_MODE_TX_ONLY      0x00000001

-#define I2S_MODE_TX_RX_SYNC   0x00000003

-

-

-//*****************************************************************************

-//

-// API Function prototypes

-//

-//*****************************************************************************

-extern void I2SEnable(unsigned long ulBase, unsigned long ulMode);

-extern void I2SDisable(unsigned long ulBase);

-

-extern void I2SDataPut(unsigned long ulBase, unsigned long ulDataLine,

-                unsigned long ulData);

-extern long I2SDataPutNonBlocking(unsigned long ulBase,

-                               unsigned long ulDataLine, unsigned long ulData);

-

-extern void I2SDataGet(unsigned long ulBase, unsigned long ulDataLine,

-                unsigned long *pulData);

-extern long I2SDataGetNonBlocking(unsigned long ulBase,

-                unsigned long ulDataLine, unsigned long *pulData);

-

-extern void I2SConfigSetExpClk(unsigned long ulBase, unsigned long ulI2SClk,

-                               unsigned long ulBitClk, unsigned long ulConfig);

-

-extern void I2STxFIFOEnable(unsigned long ulBase, unsigned long ulTxLevel,

-                     unsigned long ulWordsPerTransfer);

-extern void I2STxFIFODisable(unsigned long ulBase);

-extern void I2SRxFIFOEnable(unsigned long ulBase, unsigned long ulRxLevel,

-                     unsigned long ulWordsPerTransfer);

-extern void I2SRxFIFODisable(unsigned long ulBase);

-extern unsigned long I2STxFIFOStatusGet(unsigned long ulBase);

-extern unsigned long I2SRxFIFOStatusGet(unsigned long ulBase);

-

-extern void I2SSerializerConfig(unsigned long ulBase, unsigned long ulDataLine,

-                         unsigned long ulSerMode, unsigned long ulInActState);

-

-extern void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags);

-extern void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags);

-extern unsigned long I2SIntStatus(unsigned long ulBase);

-extern void I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags);

-extern void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void));

-extern void I2SIntUnregister(unsigned long ulBase);

-extern void I2STxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot);

-extern void I2SRxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot);

-

-//*****************************************************************************

-//

-// Mark the end of the C bindings section for C++ compilers.

-//

-//*****************************************************************************

-#ifdef __cplusplus

-}

-#endif

-

-#endif //__I2S_H__

-

diff --git a/cc3200/hal/inc/asmdefs.h b/cc3200/hal/inc/asmdefs.h
deleted file mode 100644
index c2a6f9734..000000000
--- a/cc3200/hal/inc/asmdefs.h
+++ /dev/null
@@ -1,229 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-// asmdefs.h - Macros to allow assembly code be portable among toolchains.
-//
-//*****************************************************************************
-
-#ifndef __ASMDEFS_H__
-#define __ASMDEFS_H__
-
-//*****************************************************************************
-//
-// The defines required for code_red.
-//
-//*****************************************************************************
-#ifdef codered
-
-//
-// The assembly code preamble required to put the assembler into the correct
-// configuration.
-//
-    .syntax unified
-    .thumb
-
-//
-// Section headers.
-//
-#define __LIBRARY__             @
-#define __TEXT__                .text
-#define __DATA__                .data
-#define __BSS__                 .bss
-#define __TEXT_NOROOT__         .text
-
-//
-// Assembler nmenonics.
-//
-#define __ALIGN__               .balign 4
-#define __END__                 .end
-#define __EXPORT__              .globl
-#define __IMPORT__              .extern
-#define __LABEL__               :
-#define __STR__                 .ascii
-#define __THUMB_LABEL__         .thumb_func
-#define __WORD__                .word
-#define __INLINE_DATA__
-
-#endif // codered
-
-//*****************************************************************************
-//
-// The defines required for EW-ARM.
-//
-//*****************************************************************************
-#ifdef ewarm
-
-//
-// Section headers.
-//
-#define __LIBRARY__             module
-#define __TEXT__                rseg CODE:CODE(2)
-#define __DATA__                rseg DATA:DATA(2)
-#define __BSS__                 rseg DATA:DATA(2)
-#define __TEXT_NOROOT__         rseg CODE:CODE:NOROOT(2)
-
-//
-// Assembler nmenonics.
-//
-#define __ALIGN__               alignrom 2
-#define __END__                 end
-#define __EXPORT__              export
-#define __IMPORT__              import
-#define __LABEL__
-#define __STR__                 dcb
-#define __THUMB_LABEL__         thumb
-#define __WORD__                dcd
-#define __INLINE_DATA__         data
-
-#endif // ewarm
-
-//*****************************************************************************
-//
-// The defines required for GCC.
-//
-//*****************************************************************************
-#if defined(gcc)
-
-//
-// The assembly code preamble required to put the assembler into the correct
-// configuration.
-//
-    .syntax unified
-    .thumb
-
-//
-// Section headers.
-//
-#define __LIBRARY__             @
-#define __TEXT__                .text
-#define __DATA__                .data
-#define __BSS__                 .bss
-#define __TEXT_NOROOT__         .text
-
-//
-// Assembler nmenonics.
-//
-#define __ALIGN__               .balign 4
-#define __END__                 .end
-#define __EXPORT__              .globl
-#define __IMPORT__              .extern
-#define __LABEL__               :
-#define __STR__                 .ascii
-#define __THUMB_LABEL__         .thumb_func
-#define __WORD__                .word
-#define __INLINE_DATA__
-
-#endif // gcc
-
-//*****************************************************************************
-//
-// The defines required for RV-MDK.
-//
-//*****************************************************************************
-#ifdef rvmdk
-
-//
-// The assembly code preamble required to put the assembler into the correct
-// configuration.
-//
-    thumb
-    require8
-    preserve8
-
-//
-// Section headers.
-//
-#define __LIBRARY__             ;
-#define __TEXT__                area ||.text||, code, readonly, align=2
-#define __DATA__                area ||.data||, data, align=2
-#define __BSS__                 area ||.bss||, noinit, align=2
-#define __TEXT_NOROOT__         area ||.text||, code, readonly, align=2
-
-//
-// Assembler nmenonics.
-//
-#define __ALIGN__               align 4
-#define __END__                 end
-#define __EXPORT__              export
-#define __IMPORT__              import
-#define __LABEL__
-#define __STR__                 dcb
-#define __THUMB_LABEL__
-#define __WORD__                dcd
-#define __INLINE_DATA__
-
-#endif // rvmdk
-
-//*****************************************************************************
-//
-// The defines required for Sourcery G++.
-//
-//*****************************************************************************
-#if defined(sourcerygxx)
-
-//
-// The assembly code preamble required to put the assembler into the correct
-// configuration.
-//
-    .syntax unified
-    .thumb
-
-//
-// Section headers.
-//
-#define __LIBRARY__             @
-#define __TEXT__                .text
-#define __DATA__                .data
-#define __BSS__                 .bss
-#define __TEXT_NOROOT__         .text
-
-//
-// Assembler nmenonics.
-//
-#define __ALIGN__               .balign 4
-#define __END__                 .end
-#define __EXPORT__              .globl
-#define __IMPORT__              .extern
-#define __LABEL__               :
-#define __STR__                 .ascii
-#define __THUMB_LABEL__         .thumb_func
-#define __WORD__                .word
-#define __INLINE_DATA__
-
-#endif // sourcerygxx
-
-#endif // __ASMDEF_H__
diff --git a/cc3200/hal/inc/hw_adc.h b/cc3200/hal/inc/hw_adc.h
deleted file mode 100644
index 525ce905c..000000000
--- a/cc3200/hal/inc/hw_adc.h
+++ /dev/null
@@ -1,888 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_ADC_H__
-#define __HW_ADC_H__
-
-//*****************************************************************************
-//
-// The following are defines for the ADC register offsets.
-//
-//*****************************************************************************
-#define ADC_O_ADC_CTRL          0x00000000  // ADC control register.
-#define ADC_O_adc_ch0_gain      0x00000004  // Channel 0 gain setting
-#define ADC_O_adc_ch1_gain      0x00000008  // Channel 1 gain setting
-#define ADC_O_adc_ch2_gain      0x0000000C  // Channel 2 gain setting
-#define ADC_O_adc_ch3_gain      0x00000010  // Channel 3 gain setting
-#define ADC_O_adc_ch4_gain      0x00000014  // Channel 4 gain setting
-#define ADC_O_adc_ch5_gain      0x00000018  // Channel 5 gain setting
-#define ADC_O_adc_ch6_gain      0x0000001C  // Channel 6 gain setting
-#define ADC_O_adc_ch7_gain      0x00000020  // Channel 7 gain setting
-#define ADC_O_adc_ch0_irq_en    0x00000024  // Channel 0 interrupt enable
-                                            // register
-#define ADC_O_adc_ch1_irq_en    0x00000028  // Channel 1 interrupt enable
-                                            // register
-#define ADC_O_adc_ch2_irq_en    0x0000002C  // Channel 2 interrupt enable
-                                            // register
-#define ADC_O_adc_ch3_irq_en    0x00000030  // Channel 3 interrupt enable
-                                            // register
-#define ADC_O_adc_ch4_irq_en    0x00000034  // Channel 4 interrupt enable
-                                            // register
-#define ADC_O_adc_ch5_irq_en    0x00000038  // Channel 5 interrupt enable
-                                            // register
-#define ADC_O_adc_ch6_irq_en    0x0000003C  // Channel 6 interrupt enable
-                                            // register
-#define ADC_O_adc_ch7_irq_en    0x00000040  // Channel 7 interrupt enable
-                                            // register
-#define ADC_O_adc_ch0_irq_status \
-                                0x00000044  // Channel 0 interrupt status
-                                            // register
-
-#define ADC_O_adc_ch1_irq_status \
-                                0x00000048  // Channel 1 interrupt status
-                                            // register
-
-#define ADC_O_adc_ch2_irq_status \
-                                0x0000004C
-
-#define ADC_O_adc_ch3_irq_status \
-                                0x00000050  // Channel 3 interrupt status
-                                            // register
-
-#define ADC_O_adc_ch4_irq_status \
-                                0x00000054  // Channel 4 interrupt status
-                                            // register
-
-#define ADC_O_adc_ch5_irq_status \
-                                0x00000058
-
-#define ADC_O_adc_ch6_irq_status \
-                                0x0000005C  // Channel 6 interrupt status
-                                            // register
-
-#define ADC_O_adc_ch7_irq_status \
-                                0x00000060  // Channel 7 interrupt status
-                                            // register
-
-#define ADC_O_adc_dma_mode_en   0x00000064  // DMA mode enable register
-#define ADC_O_adc_timer_configuration \
-                                0x00000068  // ADC timer configuration register
-
-#define ADC_O_adc_timer_current_count \
-                                0x00000070  // ADC timer current count register
-
-#define ADC_O_channel0FIFODATA  0x00000074  // CH0 FIFO DATA register
-#define ADC_O_channel1FIFODATA  0x00000078  // CH1 FIFO DATA register
-#define ADC_O_channel2FIFODATA  0x0000007C  // CH2 FIFO DATA register
-#define ADC_O_channel3FIFODATA  0x00000080  // CH3 FIFO DATA register
-#define ADC_O_channel4FIFODATA  0x00000084  // CH4 FIFO DATA register
-#define ADC_O_channel5FIFODATA  0x00000088  // CH5 FIFO DATA register
-#define ADC_O_channel6FIFODATA  0x0000008C  // CH6 FIFO DATA register
-#define ADC_O_channel7FIFODATA  0x00000090  // CH7 FIFO DATA register
-#define ADC_O_adc_ch0_fifo_lvl  0x00000094  // channel 0 FIFO Level register
-#define ADC_O_adc_ch1_fifo_lvl  0x00000098  // Channel 1 interrupt status
-                                            // register
-#define ADC_O_adc_ch2_fifo_lvl  0x0000009C
-#define ADC_O_adc_ch3_fifo_lvl  0x000000A0  // Channel 3 interrupt status
-                                            // register
-#define ADC_O_adc_ch4_fifo_lvl  0x000000A4  // Channel 4 interrupt status
-                                            // register
-#define ADC_O_adc_ch5_fifo_lvl  0x000000A8
-#define ADC_O_adc_ch6_fifo_lvl  0x000000AC  // Channel 6 interrupt status
-                                            // register
-#define ADC_O_adc_ch7_fifo_lvl  0x000000B0  // Channel 7 interrupt status
-                                            // register
-
-#define ADC_O_ADC_CH_ENABLE     0x000000B8
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_ADC_CTRL register.
-//
-//******************************************************************************
-#define ADC_ADC_CTRL_adc_cap_scale \
-                                0x00000020  // ADC CAP SCALE.
-
-#define ADC_ADC_CTRL_adc_buf_bypass \
-                                0x00000010  // ADC ANA CIO buffer bypass.
-                                            // Signal is modelled in ANA TOP.
-                                            // When '1': ADC buffer is bypassed.
-
-#define ADC_ADC_CTRL_adc_buf_en 0x00000008  // ADC ANA buffer enable. When 1:
-                                            // ADC buffer is enabled.
-#define ADC_ADC_CTRL_adc_core_en \
-                                0x00000004  // ANA ADC core en. This signal act
-                                            // as glbal enable to ADC CIO. When
-                                            // 1: ADC core is enabled.
-
-#define ADC_ADC_CTRL_adc_soft_reset \
-                                0x00000002  // ADC soft reset. When '1' : reset
-                                            // ADC internal logic.
-
-#define ADC_ADC_CTRL_adc_en     0x00000001  // ADC global enable. When set ADC
-                                            // module is enabled
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch0_gain register.
-//
-//******************************************************************************
-#define ADC_adc_ch0_gain_adc_channel0_gain_M \
-                                0x00000003  // gain setting for ADC channel 0.
-                                            // when "00": 1x when "01: 2x when
-                                            // "10":3x when "11" 4x
-
-#define ADC_adc_ch0_gain_adc_channel0_gain_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch1_gain register.
-//
-//******************************************************************************
-#define ADC_adc_ch1_gain_adc_channel1_gain_M \
-                                0x00000003  // gain setting for ADC channel 1.
-                                            // when "00": 1x when "01: 2x when
-                                            // "10":3x when "11" 4x
-
-#define ADC_adc_ch1_gain_adc_channel1_gain_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch2_gain register.
-//
-//******************************************************************************
-#define ADC_adc_ch2_gain_adc_channel2_gain_M \
-                                0x00000003  // gain setting for ADC channel 2.
-                                            // when "00": 1x when "01: 2x when
-                                            // "10":3x when "11" 4x
-
-#define ADC_adc_ch2_gain_adc_channel2_gain_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch3_gain register.
-//
-//******************************************************************************
-#define ADC_adc_ch3_gain_adc_channel3_gain_M \
-                                0x00000003  // gain setting for ADC channel 3.
-                                            // when "00": 1x when "01: 2x when
-                                            // "10":3x when "11" 4x
-
-#define ADC_adc_ch3_gain_adc_channel3_gain_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch4_gain register.
-//
-//******************************************************************************
-#define ADC_adc_ch4_gain_adc_channel4_gain_M \
-                                0x00000003  // gain setting for ADC channel 4
-                                            // when "00": 1x when "01: 2x when
-                                            // "10":3x when "11" 4x
-
-#define ADC_adc_ch4_gain_adc_channel4_gain_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch5_gain register.
-//
-//******************************************************************************
-#define ADC_adc_ch5_gain_adc_channel5_gain_M \
-                                0x00000003  // gain setting for ADC channel 5.
-                                            // when "00": 1x when "01: 2x when
-                                            // "10":3x when "11" 4x
-
-#define ADC_adc_ch5_gain_adc_channel5_gain_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch6_gain register.
-//
-//******************************************************************************
-#define ADC_adc_ch6_gain_adc_channel6_gain_M \
-                                0x00000003  // gain setting for ADC channel 6
-                                            // when "00": 1x when "01: 2x when
-                                            // "10":3x when "11" 4x
-
-#define ADC_adc_ch6_gain_adc_channel6_gain_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch7_gain register.
-//
-//******************************************************************************
-#define ADC_adc_ch7_gain_adc_channel7_gain_M \
-                                0x00000003  // gain setting for ADC channel 7.
-                                            // when "00": 1x when "01: 2x when
-                                            // "10":3x when "11" 4x
-
-#define ADC_adc_ch7_gain_adc_channel7_gain_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch0_irq_en register.
-//
-//******************************************************************************
-#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_M \
-                                0x0000000F  // interrupt enable register for
-                                            // per ADC channel bit 3: when '1'
-                                            // -> enable FIFO overflow interrupt
-                                            // bit 2: when '1' -> enable FIFO
-                                            // underflow interrupt bit 1: when
-                                            // "1' -> enable FIFO empty
-                                            // interrupt bit 0: when "1" ->
-                                            // enable FIFO full interrupt
-
-#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch1_irq_en register.
-//
-//******************************************************************************
-#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_M \
-                                0x0000000F  // interrupt enable register for
-                                            // per ADC channel bit 3: when '1'
-                                            // -> enable FIFO overflow interrupt
-                                            // bit 2: when '1' -> enable FIFO
-                                            // underflow interrupt bit 1: when
-                                            // "1' -> enable FIFO empty
-                                            // interrupt bit 0: when "1" ->
-                                            // enable FIFO full interrupt
-
-#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch2_irq_en register.
-//
-//******************************************************************************
-#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_M \
-                                0x0000000F  // interrupt enable register for
-                                            // per ADC channel bit 3: when '1'
-                                            // -> enable FIFO overflow interrupt
-                                            // bit 2: when '1' -> enable FIFO
-                                            // underflow interrupt bit 1: when
-                                            // "1' -> enable FIFO empty
-                                            // interrupt bit 0: when "1" ->
-                                            // enable FIFO full interrupt
-
-#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch3_irq_en register.
-//
-//******************************************************************************
-#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_M \
-                                0x0000000F  // interrupt enable register for
-                                            // per ADC channel bit 3: when '1'
-                                            // -> enable FIFO overflow interrupt
-                                            // bit 2: when '1' -> enable FIFO
-                                            // underflow interrupt bit 1: when
-                                            // "1' -> enable FIFO empty
-                                            // interrupt bit 0: when "1" ->
-                                            // enable FIFO full interrupt
-
-#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch4_irq_en register.
-//
-//******************************************************************************
-#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_M \
-                                0x0000000F  // interrupt enable register for
-                                            // per ADC channel bit 3: when '1'
-                                            // -> enable FIFO overflow interrupt
-                                            // bit 2: when '1' -> enable FIFO
-                                            // underflow interrupt bit 1: when
-                                            // "1' -> enable FIFO empty
-                                            // interrupt bit 0: when "1" ->
-                                            // enable FIFO full interrupt
-
-#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch5_irq_en register.
-//
-//******************************************************************************
-#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_M \
-                                0x0000000F  // interrupt enable register for
-                                            // per ADC channel bit 3: when '1'
-                                            // -> enable FIFO overflow interrupt
-                                            // bit 2: when '1' -> enable FIFO
-                                            // underflow interrupt bit 1: when
-                                            // "1' -> enable FIFO empty
-                                            // interrupt bit 0: when "1" ->
-                                            // enable FIFO full interrupt
-
-#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch6_irq_en register.
-//
-//******************************************************************************
-#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_M \
-                                0x0000000F  // interrupt enable register for
-                                            // per ADC channel bit 3: when '1'
-                                            // -> enable FIFO overflow interrupt
-                                            // bit 2: when '1' -> enable FIFO
-                                            // underflow interrupt bit 1: when
-                                            // "1' -> enable FIFO empty
-                                            // interrupt bit 0: when "1" ->
-                                            // enable FIFO full interrupt
-
-#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch7_irq_en register.
-//
-//******************************************************************************
-#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_M \
-                                0x0000000F  // interrupt enable register for
-                                            // per ADC channel bit 3: when '1'
-                                            // -> enable FIFO overflow interrupt
-                                            // bit 2: when '1' -> enable FIFO
-                                            // underflow interrupt bit 1: when
-                                            // "1' -> enable FIFO empty
-                                            // interrupt bit 0: when "1" ->
-                                            // enable FIFO full interrupt
-
-#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch0_irq_status register.
-//
-//******************************************************************************
-#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_M \
-                                0x0000000F  // interrupt status register for
-                                            // per ADC channel. Interrupt status
-                                            // can be cleared on write. bit 3:
-                                            // when value '1' is written ->
-                                            // would clear FIFO overflow
-                                            // interrupt status in the next
-                                            // cycle. if same interrupt is set
-                                            // in the same cycle then interurpt
-                                            // would be set and clear command
-                                            // will be ignored. bit 2: when
-                                            // value '1' is written -> would
-                                            // clear FIFO underflow interrupt
-                                            // status in the next cycle. bit 1:
-                                            // when value '1' is written ->
-                                            // would clear FIFO empty interrupt
-                                            // status in the next cycle. bit 0:
-                                            // when value '1' is written ->
-                                            // would clear FIFO full interrupt
-                                            // status in the next cycle.
-
-#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch1_irq_status register.
-//
-//******************************************************************************
-#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_M \
-                                0x0000000F  // interrupt status register for
-                                            // per ADC channel. Interrupt status
-                                            // can be cleared on write. bit 3:
-                                            // when value '1' is written ->
-                                            // would clear FIFO overflow
-                                            // interrupt status in the next
-                                            // cycle. if same interrupt is set
-                                            // in the same cycle then interurpt
-                                            // would be set and clear command
-                                            // will be ignored. bit 2: when
-                                            // value '1' is written -> would
-                                            // clear FIFO underflow interrupt
-                                            // status in the next cycle. bit 1:
-                                            // when value '1' is written ->
-                                            // would clear FIFO empty interrupt
-                                            // status in the next cycle. bit 0:
-                                            // when value '1' is written ->
-                                            // would clear FIFO full interrupt
-                                            // status in the next cycle.
-
-#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch2_irq_status register.
-//
-//******************************************************************************
-#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_M \
-                                0x0000000F  // interrupt status register for
-                                            // per ADC channel. Interrupt status
-                                            // can be cleared on write. bit 3:
-                                            // when value '1' is written ->
-                                            // would clear FIFO overflow
-                                            // interrupt status in the next
-                                            // cycle. if same interrupt is set
-                                            // in the same cycle then interurpt
-                                            // would be set and clear command
-                                            // will be ignored. bit 2: when
-                                            // value '1' is written -> would
-                                            // clear FIFO underflow interrupt
-                                            // status in the next cycle. bit 1:
-                                            // when value '1' is written ->
-                                            // would clear FIFO empty interrupt
-                                            // status in the next cycle. bit 0:
-                                            // when value '1' is written ->
-                                            // would clear FIFO full interrupt
-                                            // status in the next cycle.
-
-#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch3_irq_status register.
-//
-//******************************************************************************
-#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_M \
-                                0x0000000F  // interrupt status register for
-                                            // per ADC channel. Interrupt status
-                                            // can be cleared on write. bit 3:
-                                            // when value '1' is written ->
-                                            // would clear FIFO overflow
-                                            // interrupt status in the next
-                                            // cycle. if same interrupt is set
-                                            // in the same cycle then interurpt
-                                            // would be set and clear command
-                                            // will be ignored. bit 2: when
-                                            // value '1' is written -> would
-                                            // clear FIFO underflow interrupt
-                                            // status in the next cycle. bit 1:
-                                            // when value '1' is written ->
-                                            // would clear FIFO empty interrupt
-                                            // status in the next cycle. bit 0:
-                                            // when value '1' is written ->
-                                            // would clear FIFO full interrupt
-                                            // status in the next cycle.
-
-#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch4_irq_status register.
-//
-//******************************************************************************
-#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_M \
-                                0x0000000F  // interrupt status register for
-                                            // per ADC channel. Interrupt status
-                                            // can be cleared on write. bit 3:
-                                            // when value '1' is written ->
-                                            // would clear FIFO overflow
-                                            // interrupt status in the next
-                                            // cycle. if same interrupt is set
-                                            // in the same cycle then interurpt
-                                            // would be set and clear command
-                                            // will be ignored. bit 2: when
-                                            // value '1' is written -> would
-                                            // clear FIFO underflow interrupt
-                                            // status in the next cycle. bit 1:
-                                            // when value '1' is written ->
-                                            // would clear FIFO empty interrupt
-                                            // status in the next cycle. bit 0:
-                                            // when value '1' is written ->
-                                            // would clear FIFO full interrupt
-                                            // status in the next cycle.
-
-#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch5_irq_status register.
-//
-//******************************************************************************
-#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_M \
-                                0x0000000F  // interrupt status register for
-                                            // per ADC channel. Interrupt status
-                                            // can be cleared on write. bit 3:
-                                            // when value '1' is written ->
-                                            // would clear FIFO overflow
-                                            // interrupt status in the next
-                                            // cycle. if same interrupt is set
-                                            // in the same cycle then interurpt
-                                            // would be set and clear command
-                                            // will be ignored. bit 2: when
-                                            // value '1' is written -> would
-                                            // clear FIFO underflow interrupt
-                                            // status in the next cycle. bit 1:
-                                            // when value '1' is written ->
-                                            // would clear FIFO empty interrupt
-                                            // status in the next cycle. bit 0:
-                                            // when value '1' is written ->
-                                            // would clear FIFO full interrupt
-                                            // status in the next cycle.
-
-#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch6_irq_status register.
-//
-//******************************************************************************
-#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_M \
-                                0x0000000F  // interrupt status register for
-                                            // per ADC channel. Interrupt status
-                                            // can be cleared on write. bit 3:
-                                            // when value '1' is written ->
-                                            // would clear FIFO overflow
-                                            // interrupt status in the next
-                                            // cycle. if same interrupt is set
-                                            // in the same cycle then interurpt
-                                            // would be set and clear command
-                                            // will be ignored. bit 2: when
-                                            // value '1' is written -> would
-                                            // clear FIFO underflow interrupt
-                                            // status in the next cycle. bit 1:
-                                            // when value '1' is written ->
-                                            // would clear FIFO empty interrupt
-                                            // status in the next cycle. bit 0:
-                                            // when value '1' is written ->
-                                            // would clear FIFO full interrupt
-                                            // status in the next cycle.
-
-#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch7_irq_status register.
-//
-//******************************************************************************
-#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_M \
-                                0x0000000F  // interrupt status register for
-                                            // per ADC channel. Interrupt status
-                                            // can be cleared on write. bit 3:
-                                            // when value '1' is written ->
-                                            // would clear FIFO overflow
-                                            // interrupt status in the next
-                                            // cycle. if same interrupt is set
-                                            // in the same cycle then interurpt
-                                            // would be set and clear command
-                                            // will be ignored. bit 2: when
-                                            // value '1' is written -> would
-                                            // clear FIFO underflow interrupt
-                                            // status in the next cycle. bit 1:
-                                            // when value '1' is written ->
-                                            // would clear FIFO empty interrupt
-                                            // status in the next cycle. bit 0:
-                                            // when value '1' is written ->
-                                            // would clear FIFO full interrupt
-                                            // status in the next cycle.
-
-#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_dma_mode_en register.
-//
-//******************************************************************************
-#define ADC_adc_dma_mode_en_DMA_MODEenable_M \
-                                0x000000FF  // this register enable DMA mode.
-                                            // when '1' respective ADC channel
-                                            // is enabled for DMA. When '0' only
-                                            // interrupt mode is enabled. Bit 0:
-                                            // channel 0 DMA mode enable. Bit 1:
-                                            // channel 1 DMA mode enable. Bit 2:
-                                            // channel 2 DMA mode enable. Bit 3:
-                                            // channel 3 DMA mode enable. bit 4:
-                                            // channel 4 DMA mode enable. bit 5:
-                                            // channel 5 DMA mode enable. bit 6:
-                                            // channel 6 DMA mode enable. bit 7:
-                                            // channel 7 DMA mode enable.
-
-#define ADC_adc_dma_mode_en_DMA_MODEenable_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_timer_configuration register.
-//
-//******************************************************************************
-#define ADC_adc_timer_configuration_timeren \
-                                0x02000000  // when '1' timer is enabled.
-
-#define ADC_adc_timer_configuration_timerreset \
-                                0x01000000  // when '1' reset timer.
-
-#define ADC_adc_timer_configuration_timercount_M \
-                                0x00FFFFFF  // Timer count configuration. 17
-                                            // bit counter is supported. Other
-                                            // MSB's are redundent.
-
-#define ADC_adc_timer_configuration_timercount_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_timer_current_count register.
-//
-//******************************************************************************
-#define ADC_adc_timer_current_count_timercurrentcount_M \
-                                0x0001FFFF  // Timer count configuration
-
-#define ADC_adc_timer_current_count_timercurrentcount_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_channel0FIFODATA register.
-//
-//******************************************************************************
-#define ADC_channel0FIFODATA_FIFO_RD_DATA_M \
-                                0xFFFFFFFF  // read to this register would
-                                            // return ADC data along with time
-                                            // stamp information in following
-                                            // format: bits [13:0] : ADC sample
-                                            // bits [31:14]: : time stamp per
-                                            // ADC sample
-
-#define ADC_channel0FIFODATA_FIFO_RD_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_channel1FIFODATA register.
-//
-//******************************************************************************
-#define ADC_channel1FIFODATA_FIFO_RD_DATA_M \
-                                0xFFFFFFFF  // read to this register would
-                                            // return ADC data along with time
-                                            // stamp information in following
-                                            // format: bits [13:0] : ADC sample
-                                            // bits [31:14]: : time stamp per
-                                            // ADC sample
-
-#define ADC_channel1FIFODATA_FIFO_RD_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_channel2FIFODATA register.
-//
-//******************************************************************************
-#define ADC_channel2FIFODATA_FIFO_RD_DATA_M \
-                                0xFFFFFFFF  // read to this register would
-                                            // return ADC data along with time
-                                            // stamp information in following
-                                            // format: bits [13:0] : ADC sample
-                                            // bits [31:14]: : time stamp per
-                                            // ADC sample
-
-#define ADC_channel2FIFODATA_FIFO_RD_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_channel3FIFODATA register.
-//
-//******************************************************************************
-#define ADC_channel3FIFODATA_FIFO_RD_DATA_M \
-                                0xFFFFFFFF  // read to this register would
-                                            // return ADC data along with time
-                                            // stamp information in following
-                                            // format: bits [13:0] : ADC sample
-                                            // bits [31:14]: : time stamp per
-                                            // ADC sample
-
-#define ADC_channel3FIFODATA_FIFO_RD_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_channel4FIFODATA register.
-//
-//******************************************************************************
-#define ADC_channel4FIFODATA_FIFO_RD_DATA_M \
-                                0xFFFFFFFF  // read to this register would
-                                            // return ADC data along with time
-                                            // stamp information in following
-                                            // format: bits [13:0] : ADC sample
-                                            // bits [31:14]: : time stamp per
-                                            // ADC sample
-
-#define ADC_channel4FIFODATA_FIFO_RD_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_channel5FIFODATA register.
-//
-//******************************************************************************
-#define ADC_channel5FIFODATA_FIFO_RD_DATA_M \
-                                0xFFFFFFFF  // read to this register would
-                                            // return ADC data along with time
-                                            // stamp information in following
-                                            // format: bits [13:0] : ADC sample
-                                            // bits [31:14]: : time stamp per
-                                            // ADC sample
-
-#define ADC_channel5FIFODATA_FIFO_RD_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_channel6FIFODATA register.
-//
-//******************************************************************************
-#define ADC_channel6FIFODATA_FIFO_RD_DATA_M \
-                                0xFFFFFFFF  // read to this register would
-                                            // return ADC data along with time
-                                            // stamp information in following
-                                            // format: bits [13:0] : ADC sample
-                                            // bits [31:14]: : time stamp per
-                                            // ADC sample
-
-#define ADC_channel6FIFODATA_FIFO_RD_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_channel7FIFODATA register.
-//
-//******************************************************************************
-#define ADC_channel7FIFODATA_FIFO_RD_DATA_M \
-                                0xFFFFFFFF  // read to this register would
-                                            // return ADC data along with time
-                                            // stamp information in following
-                                            // format: bits [13:0] : ADC sample
-                                            // bits [31:14]: : time stamp per
-                                            // ADC sample
-
-#define ADC_channel7FIFODATA_FIFO_RD_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch0_fifo_lvl register.
-//
-//******************************************************************************
-#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_M \
-                                0x00000007  // This register shows current FIFO
-                                            // level. FIFO is 4 word wide.
-                                            // Possible supported levels are :
-                                            // 0x0 to 0x3
-
-#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch1_fifo_lvl register.
-//
-//******************************************************************************
-#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_M \
-                                0x00000007  // This register shows current FIFO
-                                            // level. FIFO is 4 word wide.
-                                            // Possible supported levels are :
-                                            // 0x0 to 0x3
-
-#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch2_fifo_lvl register.
-//
-//******************************************************************************
-#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_M \
-                                0x00000007  // This register shows current FIFO
-                                            // level. FIFO is 4 word wide.
-                                            // Possible supported levels are :
-                                            // 0x0 to 0x3
-
-#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch3_fifo_lvl register.
-//
-//******************************************************************************
-#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_M \
-                                0x00000007  // This register shows current FIFO
-                                            // level. FIFO is 4 word wide.
-                                            // Possible supported levels are :
-                                            // 0x0 to 0x3
-
-#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch4_fifo_lvl register.
-//
-//******************************************************************************
-#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_M \
-                                0x00000007  // This register shows current FIFO
-                                            // level. FIFO is 4 word wide.
-                                            // Possible supported levels are :
-                                            // 0x0 to 0x3
-
-#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch5_fifo_lvl register.
-//
-//******************************************************************************
-#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_M \
-                                0x00000007  // This register shows current FIFO
-                                            // level. FIFO is 4 word wide.
-                                            // Possible supported levels are :
-                                            // 0x0 to 0x3
-
-#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch6_fifo_lvl register.
-//
-//******************************************************************************
-#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_M \
-                                0x00000007  // This register shows current FIFO
-                                            // level. FIFO is 4 word wide.
-                                            // Possible supported levels are :
-                                            // 0x0 to 0x3
-
-#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// ADC_O_adc_ch7_fifo_lvl register.
-//
-//******************************************************************************
-#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_M \
-                                0x00000007  // This register shows current FIFO
-                                            // level. FIFO is 4 word wide.
-                                            // Possible supported levels are :
-                                            // 0x0 to 0x3
-
-#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_S 0
-
-
-
-#endif // __HW_ADC_H__
diff --git a/cc3200/hal/inc/hw_aes.h b/cc3200/hal/inc/hw_aes.h
deleted file mode 100644
index 3ab0398b3..000000000
--- a/cc3200/hal/inc/hw_aes.h
+++ /dev/null
@@ -1,802 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_AES_H__
-#define __HW_AES_H__
-
-//*****************************************************************************
-//
-// The following are defines for the AES_P register offsets.
-//
-//*****************************************************************************
-#define AES_O_KEY2_6          0x00000000  // XTS second key / CBC-MAC third
-                                            // key
-#define AES_O_KEY2_7          0x00000004  // XTS second key (MSW for 256-bit
-                                            // key) / CBC-MAC third key (MSW)
-#define AES_O_KEY2_4          0x00000008  // XTS / CCM second key / CBC-MAC
-                                            // third key (LSW)
-#define AES_O_KEY2_5          0x0000000C  // XTS second key (MSW for 192-bit
-                                            // key) / CBC-MAC third key
-#define AES_O_KEY2_2          0x00000010  // XTS / CCM / CBC-MAC second key /
-                                            // Hash Key input
-#define AES_O_KEY2_3          0x00000014  // XTS second key (MSW for 128-bit
-                                            // key) + CCM/CBC-MAC second key
-                                            // (MSW) / Hash Key input (MSW)
-#define AES_O_KEY2_0          0x00000018  // XTS / CCM / CBC-MAC second key
-                                            // (LSW) / Hash Key input (LSW)
-#define AES_O_KEY2_1          0x0000001C  // XTS / CCM / CBC-MAC second key /
-                                            // Hash Key input
-#define AES_O_KEY1_6          0x00000020  // Key (LSW for 256-bit key)
-#define AES_O_KEY1_7          0x00000024  // Key (MSW for 256-bit key)
-#define AES_O_KEY1_4          0x00000028  // Key (LSW for 192-bit key)
-#define AES_O_KEY1_5          0x0000002C  // Key (MSW for 192-bit key)
-#define AES_O_KEY1_2          0x00000030  // Key
-#define AES_O_KEY1_3          0x00000034  // Key (MSW for 128-bit key)
-#define AES_O_KEY1_0          0x00000038  // Key (LSW for 128-bit key)
-#define AES_O_KEY1_1          0x0000003C  // Key
-#define AES_O_IV_IN_0         0x00000040  // Initialization Vector input
-                                            // (LSW)
-#define AES_O_IV_IN_1         0x00000044  // Initialization vector input
-#define AES_O_IV_IN_2         0x00000048  // Initialization vector input
-#define AES_O_IV_IN_3         0x0000004C  // Initialization Vector input
-                                            // (MSW)
-#define AES_O_CTRL            0x00000050  // register determines the mode of
-                                            // operation of the AES Engine
-#define AES_O_C_LENGTH_0      0x00000054  // Crypto data length registers
-                                            // (LSW and MSW) store the
-                                            // cryptographic data length in
-                                            // bytes for all modes. Once
-                                            // processing with this context is
-                                            // started@@ this length decrements
-                                            // to zero. Data lengths up to (2^61
-                                            // – 1) bytes are allowed. For GCM@@
-                                            // any value up to 2^36 - 32 bytes
-                                            // can be used. This is because a
-                                            // 32-bit counter mode is used; the
-                                            // maximum number of 128-bit blocks
-                                            // is 2^32 – 2@@ resulting in a
-                                            // maximum number of bytes of 2^36 -
-                                            // 32. A write to this register
-                                            // triggers the engine to start
-                                            // using this context. This is valid
-                                            // for all modes except GCM and CCM.
-                                            // Note that for the combined
-                                            // modes@@ this length does not
-                                            // include the authentication only
-                                            // data; the authentication length
-                                            // is specified in the
-                                            // AES_AUTH_LENGTH register below.
-                                            // All modes must have a length > 0.
-                                            // For the combined modes@@ it is
-                                            // allowed to have one of the
-                                            // lengths equal to zero. For the
-                                            // basic encryption modes
-                                            // (ECB/CBC/CTR/ICM/CFB128) it is
-                                            // allowed to program zero to the
-                                            // length field; in that case the
-                                            // length is assumed infinite. All
-                                            // data must be byte (8-bit)
-                                            // aligned; bit aligned data streams
-                                            // are not supported by the AES
-                                            // Engine. For a Host read
-                                            // operation@@ these registers
-                                            // return all-zeroes.
-#define AES_O_C_LENGTH_1      0x00000058  // Crypto data length registers
-                                            // (LSW and MSW) store the
-                                            // cryptographic data length in
-                                            // bytes for all modes. Once
-                                            // processing with this context is
-                                            // started@@ this length decrements
-                                            // to zero. Data lengths up to (2^61
-                                            // – 1) bytes are allowed. For GCM@@
-                                            // any value up to 2^36 - 32 bytes
-                                            // can be used. This is because a
-                                            // 32-bit counter mode is used; the
-                                            // maximum number of 128-bit blocks
-                                            // is 2^32 – 2@@ resulting in a
-                                            // maximum number of bytes of 2^36 -
-                                            // 32. A write to this register
-                                            // triggers the engine to start
-                                            // using this context. This is valid
-                                            // for all modes except GCM and CCM.
-                                            // Note that for the combined
-                                            // modes@@ this length does not
-                                            // include the authentication only
-                                            // data; the authentication length
-                                            // is specified in the
-                                            // AES_AUTH_LENGTH register below.
-                                            // All modes must have a length > 0.
-                                            // For the combined modes@@ it is
-                                            // allowed to have one of the
-                                            // lengths equal to zero. For the
-                                            // basic encryption modes
-                                            // (ECB/CBC/CTR/ICM/CFB128) it is
-                                            // allowed to program zero to the
-                                            // length field; in that case the
-                                            // length is assumed infinite. All
-                                            // data must be byte (8-bit)
-                                            // aligned; bit aligned data streams
-                                            // are not supported by the AES
-                                            // Engine. For a Host read
-                                            // operation@@ these registers
-                                            // return all-zeroes.
-#define AES_O_AUTH_LENGTH     0x0000005C  // AAD data length. The
-                                            // authentication length register
-                                            // store the authentication data
-                                            // length in bytes for combined
-                                            // modes only (GCM or CCM) Supported
-                                            // AAD-lengths for CCM are from 0 to
-                                            // (2^16 - 2^8) bytes. For GCM any
-                                            // value up to (2^32 - 1) bytes can
-                                            // be used. Once processing with
-                                            // this context is started@@ this
-                                            // length decrements to zero. A
-                                            // write to this register triggers
-                                            // the engine to start using this
-                                            // context for GCM and CCM. For XTS
-                                            // this register is optionally used
-                                            // to load ‘j’. Loading of ‘j’ is
-                                            // only required if ‘j’ != 0. ‘j’ is
-                                            // a 28-bit value and must be
-                                            // written to bits [31-4] of this
-                                            // register. ‘j’ represents the
-                                            // sequential number of the 128-bit
-                                            // block inside the data unit. For
-                                            // the first block in a unit@@ this
-                                            // value is zero. It is not required
-                                            // to provide a ‘j’ for each new
-                                            // data block within a unit. Note
-                                            // that it is possible to start with
-                                            // a ‘j’ unequal to zero; refer to
-                                            // Table 4 for more details. For a
-                                            // Host read operation@@ these
-                                            // registers return all-zeroes.
-#define AES_O_DATA_IN_0       0x00000060  // Data register to read and write
-                                            // plaintext/ciphertext (MSW)
-#define AES_O_DATA_IN_1       0x00000064  // Data register to read and write
-                                            // plaintext/ciphertext
-#define AES_O_DATA_IN_2       0x00000068  // Data register to read and write
-                                            // plaintext/ciphertext
-#define AES_O_DATA_IN_3       0x0000006C  // Data register to read and write
-                                            // plaintext/ciphertext (LSW)
-#define AES_O_TAG_OUT_0       0x00000070
-#define AES_O_TAG_OUT_1       0x00000074
-#define AES_O_TAG_OUT_2       0x00000078
-#define AES_O_TAG_OUT_3       0x0000007C
-#define AES_O_REVISION        0x00000080  // Register AES_REVISION
-#define AES_O_SYSCONFIG       0x00000084  // Register AES_SYSCONFIG.This
-                                            // register configures the DMA
-                                            // signals and controls the IDLE and
-                                            // reset logic
-#define AES_O_SYSSTATUS       0x00000088
-#define AES_O_IRQSTATUS       0x0000008C  // This register indicates the
-                                            // interrupt status. If one of the
-                                            // interrupt bits is set the
-                                            // interrupt output will be asserted
-#define AES_O_IRQENABLE       0x00000090  // This register contains an enable
-                                            // bit for each unique interrupt
-                                            // generated by the module. It
-                                            // matches the layout of
-                                            // AES_IRQSTATUS register. An
-                                            // interrupt is enabled when the bit
-                                            // in this register is set to ‘1’.
-                                            // An interrupt that is enabled is
-                                            // propagated to the SINTREQUEST_x
-                                            // output. All interrupts need to be
-                                            // enabled explicitly by writing
-                                            // this register.
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_KEY2_6 register.
-//
-//******************************************************************************
-#define AES_KEY2_6_KEY_M      0xFFFFFFFF  // key data
-#define AES_KEY2_6_KEY_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_KEY2_7 register.
-//
-//******************************************************************************
-#define AES_KEY2_7_KEY_M      0xFFFFFFFF  // key data
-#define AES_KEY2_7_KEY_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_KEY2_4 register.
-//
-//******************************************************************************
-#define AES_KEY2_4_KEY_M      0xFFFFFFFF  // key data
-#define AES_KEY2_4_KEY_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_KEY2_5 register.
-//
-//******************************************************************************
-#define AES_KEY2_5_KEY_M      0xFFFFFFFF  // key data
-#define AES_KEY2_5_KEY_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_KEY2_2 register.
-//
-//******************************************************************************
-#define AES_KEY2_2_KEY_M      0xFFFFFFFF  // key data
-#define AES_KEY2_2_KEY_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_KEY2_3 register.
-//
-//******************************************************************************
-#define AES_KEY2_3_KEY_M      0xFFFFFFFF  // key data
-#define AES_KEY2_3_KEY_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_KEY2_0 register.
-//
-//******************************************************************************
-#define AES_KEY2_0_KEY_M      0xFFFFFFFF  // key data
-#define AES_KEY2_0_KEY_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_KEY2_1 register.
-//
-//******************************************************************************
-#define AES_KEY2_1_KEY_M      0xFFFFFFFF  // key data
-#define AES_KEY2_1_KEY_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_KEY1_6 register.
-//
-//******************************************************************************
-#define AES_KEY1_6_KEY_M      0xFFFFFFFF  // key data
-#define AES_KEY1_6_KEY_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_KEY1_7 register.
-//
-//******************************************************************************
-#define AES_KEY1_7_KEY_M      0xFFFFFFFF  // key data
-#define AES_KEY1_7_KEY_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_KEY1_4 register.
-//
-//******************************************************************************
-#define AES_KEY1_4_KEY_M      0xFFFFFFFF  // key data
-#define AES_KEY1_4_KEY_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_KEY1_5 register.
-//
-//******************************************************************************
-#define AES_KEY1_5_KEY_M      0xFFFFFFFF  // key data
-#define AES_KEY1_5_KEY_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_KEY1_2 register.
-//
-//******************************************************************************
-#define AES_KEY1_2_KEY_M      0xFFFFFFFF  // key data
-#define AES_KEY1_2_KEY_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_KEY1_3 register.
-//
-//******************************************************************************
-#define AES_KEY1_3_KEY_M      0xFFFFFFFF  // key data
-#define AES_KEY1_3_KEY_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_KEY1_0 register.
-//
-//******************************************************************************
-#define AES_KEY1_0_KEY_M      0xFFFFFFFF  // key data
-#define AES_KEY1_0_KEY_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_KEY1_1 register.
-//
-//******************************************************************************
-#define AES_KEY1_1_KEY_M      0xFFFFFFFF  // key data
-#define AES_KEY1_1_KEY_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_IV_IN_0 register.
-//
-//******************************************************************************
-#define AES_IV_IN_0_DATA_M    0xFFFFFFFF  // IV data
-#define AES_IV_IN_0_DATA_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_IV_IN_1 register.
-//
-//******************************************************************************
-#define AES_IV_IN_1_DATA_M    0xFFFFFFFF  // IV data
-#define AES_IV_IN_1_DATA_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_IV_IN_2 register.
-//
-//******************************************************************************
-#define AES_IV_IN_2_DATA_M    0xFFFFFFFF  // IV data
-#define AES_IV_IN_2_DATA_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_IV_IN_3 register.
-//
-//******************************************************************************
-#define AES_IV_IN_3_DATA_M    0xFFFFFFFF  // IV data
-#define AES_IV_IN_3_DATA_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_CTRL register.
-//
-//******************************************************************************
-#define AES_CTRL_CONTEXT_READY \
-                                0x80000000  // If ‘1’@@ this read-only status
-                                            // bit indicates that the context
-                                            // data registers can be overwritten
-                                            // and the host is permitted to
-                                            // write the next context.
-
-#define AES_CTRL_SVCTXTRDY \
-                                0x40000000  // If ‘1’@@ this read-only status
-                                            // bit indicates that an AES
-                                            // authentication TAG and/or IV
-                                            // block(s) is/are available for the
-                                            // host to retrieve. This bit is
-                                            // only asserted if the
-                                            // ‘save_context’ bit is set to ‘1’.
-                                            // The bit is mutual exclusive with
-                                            // the ‘context_ready’ bit.
-
-#define AES_CTRL_SAVE_CONTEXT 0x20000000  // This bit is used to indicate
-                                            // that an authentication TAG or
-                                            // result IV needs to be stored as a
-                                            // result context. If this bit is
-                                            // set@@ context output DMA and/or
-                                            // interrupt will be asserted if the
-                                            // operation is finished and related
-                                            // signals are enabled.
-#define AES_CTRL_CCM_M      0x01C00000  // Defines “M” that indicated the
-                                            // length of the authentication
-                                            // field for CCM operations; the
-                                            // authentication field length
-                                            // equals two times (the value of
-                                            // CCM-M plus one). Note that the
-                                            // AES Engine always returns a
-                                            // 128-bit authentication field@@ of
-                                            // which the M least significant
-                                            // bytes are valid. All values are
-                                            // supported.
-#define AES_CTRL_CCM_S      22
-#define AES_CTRL_CCM_L_M      0x00380000  // Defines “L” that indicated the
-                                            // width of the length field for CCM
-                                            // operations; the length field in
-                                            // bytes equals the value of CMM-L
-                                            // plus one. Supported values for L
-                                            // are (programmed value): 2 (1)@@ 4
-                                            // (3) and 8 (7).
-#define AES_CTRL_CCM_L_S      19
-#define AES_CTRL_CCM          0x00040000  // AES-CCM is selected@@ this is a
-                                            // combined mode@@ using AES for
-                                            // both authentication and
-                                            // encryption. No additional mode
-                                            // selection is required. 0 Other
-                                            // mode selected 1 ccm mode selected
-#define AES_CTRL_GCM_M        0x00030000  // AES-GCM mode is selected.this is
-                                            // a combined mode@@ using the
-                                            // Galois field multiplier GF(2^128)
-                                            // for authentication and AES-CTR
-                                            // mode for encryption@@ the bits
-                                            // specify the GCM mode. 0x0 No
-                                            // operation 0x1 GHASH with H loaded
-                                            // and Y0-encrypted forced to zero
-                                            // 0x2 GHASH with H loaded and
-                                            // Y0-encrypted calculated
-                                            // internally 0x3 Autonomous GHASH
-                                            // (both H and Y0-encrypted
-                                            // calculated internally)
-#define AES_CTRL_GCM_S        16
-#define AES_CTRL_CBCMAC       0x00008000  // AES-CBC MAC is selected@@ the
-                                            // Direction bit must be set to ‘1’
-                                            // for this mode. 0 Other mode
-                                            // selected 1 cbcmac mode selected
-#define AES_CTRL_F9           0x00004000  // AES f9 mode is selected@@ the
-                                            // AES key size must be set to
-                                            // 128-bit for this mode. 0 Other
-                                            // mode selected 1 f9 selected
-#define AES_CTRL_F8           0x00002000  // AES f8 mode is selected@@ the
-                                            // AES key size must be set to
-                                            // 128-bit for this mode. 0 Other
-                                            // mode selected 1 f8 selected
-#define AES_CTRL_XTS_M        0x00001800  // AES-XTS operation is selected;
-                                            // the bits specify the XTS mode.01
-                                            // = Previous/intermediate tweak
-                                            // value and ‘j’ loaded (value is
-                                            // loaded via IV@@ j is loaded via
-                                            // the AAD length register) 0x0 No
-                                            // operation 0x1
-                                            // Previous/intermediate tweak value
-                                            // and ‘j’ loaded (value is loaded
-                                            // via IV@@ j is loaded via the AAD
-                                            // length register) 0x2 Key2@@ i and
-                                            // j loaded (i is loaded via IV@@ j
-                                            // is loaded via the AAD length
-                                            // register) 0x3 Key2 and i loaded@@
-                                            // j=0 (i is loaded via IV)
-#define AES_CTRL_XTS_S        11
-#define AES_CTRL_CFB          0x00000400  // full block AES cipher feedback
-                                            // mode (CFB128) is selected. 0
-                                            // other mode selected 1 cfb
-                                            // selected
-#define AES_CTRL_ICM          0x00000200  // AES integer counter mode (ICM)
-                                            // is selected@@ this is a counter
-                                            // mode with a 16-bit wide counter.
-                                            // 0 Other mode selected. 1 ICM mode
-                                            // selected
-#define AES_CTRL_CTR_WIDTH_M  0x00000180  // Specifies the counter width for
-                                            // AES-CTR mode 0x0 Counter is 32
-                                            // bits 0x1 Counter is 64 bits 0x2
-                                            // Counter is 128 bits 0x3 Counter
-                                            // is 192 bits
-#define AES_CTRL_CTR_WIDTH_S  7
-#define AES_CTRL_CTR          0x00000040  // Tthis bit must also be set for
-                                            // GCM and CCM@@ when
-                                            // encryption/decryption is
-                                            // required. 0 Other mode selected 1
-                                            // Counter mode
-#define AES_CTRL_MODE         0x00000020  // ecb/cbc mode 0 ecb mode 1 cbc
-                                            // mode
-#define AES_CTRL_KEY_SIZE_M   0x00000018  // key size 0x0 reserved 0x1 Key is
-                                            // 128 bits. 0x2 Key is 192 bits 0x3
-                                            // Key is 256
-#define AES_CTRL_KEY_SIZE_S   3
-#define AES_CTRL_DIRECTION    0x00000004  // If set to ‘1’ an encrypt
-                                            // operation is performed. If set to
-                                            // ‘0’ a decrypt operation is
-                                            // performed. Read 0 decryption is
-                                            // selected Read 1 Encryption is
-                                            // selected
-#define AES_CTRL_INPUT_READY  0x00000002  // If ‘1’@@ this read-only status
-                                            // bit indicates that the 16-byte
-                                            // input buffer is empty@@ and the
-                                            // host is permitted to write the
-                                            // next block of data.
-#define AES_CTRL_OUTPUT_READY 0x00000001  // If ‘1’@@ this read-only status
-                                            // bit indicates that an AES output
-                                            // block is available for the host
-                                            // to retrieve.
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// AES_O_C_LENGTH_0 register.
-//
-//******************************************************************************
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// AES_O_C_LENGTH_1 register.
-//
-//******************************************************************************
-#define AES_C_LENGTH_1_LENGTH_M \
-                                0x1FFFFFFF  // Data length (MSW) length
-                                            // registers (LSW and MSW) store the
-                                            // cryptographic data length in
-                                            // bytes for all modes. Once
-                                            // processing with this context is
-                                            // started@@ this length decrements
-                                            // to zero. Data lengths up to (2^61
-                                            // – 1) bytes are allowed. For GCM@@
-                                            // any value up to 2^36 - 32 bytes
-                                            // can be used. This is because a
-                                            // 32-bit counter mode is used; the
-                                            // maximum number of 128-bit blocks
-                                            // is 2^32 – 2@@ resulting in a
-                                            // maximum number of bytes of 2^36 -
-                                            // 32. A write to this register
-                                            // triggers the engine to start
-                                            // using this context. This is valid
-                                            // for all modes except GCM and CCM.
-                                            // Note that for the combined
-                                            // modes@@ this length does not
-                                            // include the authentication only
-                                            // data; the authentication length
-                                            // is specified in the
-                                            // AES_AUTH_LENGTH register below.
-                                            // All modes must have a length > 0.
-                                            // For the combined modes@@ it is
-                                            // allowed to have one of the
-                                            // lengths equal to zero. For the
-                                            // basic encryption modes
-                                            // (ECB/CBC/CTR/ICM/CFB128) it is
-                                            // allowed to program zero to the
-                                            // length field; in that case the
-                                            // length is assumed infinite. All
-                                            // data must be byte (8-bit)
-                                            // aligned; bit aligned data streams
-                                            // are not supported by the AES
-                                            // Engine. For a Host read
-                                            // operation@@ these registers
-                                            // return all-zeroes.
-
-#define AES_C_LENGTH_1_LENGTH_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// AES_O_AUTH_LENGTH register.
-//
-//******************************************************************************
-#define AES_AUTH_LENGTH_AUTH_M \
-                                0xFFFFFFFF  // data
-
-#define AES_AUTH_LENGTH_AUTH_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_DATA_IN_0 register.
-//
-//******************************************************************************
-#define AES_DATA_IN_0_DATA_M  0xFFFFFFFF  // Data to encrypt/decrypt
-#define AES_DATA_IN_0_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_DATA_IN_1 register.
-//
-//******************************************************************************
-#define AES_DATA_IN_1_DATA_M  0xFFFFFFFF  // Data to encrypt/decrypt
-#define AES_DATA_IN_1_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_DATA_IN_2 register.
-//
-//******************************************************************************
-#define AES_DATA_IN_2_DATA_M  0xFFFFFFFF  // Data to encrypt/decrypt
-#define AES_DATA_IN_2_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_DATA_IN_3 register.
-//
-//******************************************************************************
-#define AES_DATA_IN_3_DATA_M  0xFFFFFFFF  // Data to encrypt/decrypt
-#define AES_DATA_IN_3_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_TAG_OUT_0 register.
-//
-//******************************************************************************
-#define AES_TAG_OUT_0_HASH_M  0xFFFFFFFF  // Hash result (MSW)
-#define AES_TAG_OUT_0_HASH_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_TAG_OUT_1 register.
-//
-//******************************************************************************
-#define AES_TAG_OUT_1_HASH_M  0xFFFFFFFF  // Hash result (MSW)
-#define AES_TAG_OUT_1_HASH_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_TAG_OUT_2 register.
-//
-//******************************************************************************
-#define AES_TAG_OUT_2_HASH_M  0xFFFFFFFF  // Hash result (MSW)
-#define AES_TAG_OUT_2_HASH_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_TAG_OUT_3 register.
-//
-//******************************************************************************
-#define AES_TAG_OUT_3_HASH_M  0xFFFFFFFF  // Hash result (LSW)
-#define AES_TAG_OUT_3_HASH_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_REVISION register.
-//
-//******************************************************************************
-#define AES_REVISION_SCHEME_M 0xC0000000
-#define AES_REVISION_SCHEME_S 30
-#define AES_REVISION_FUNC_M   0x0FFF0000  // Function indicates a software
-                                            // compatible module family. If
-                                            // there is no level of software
-                                            // compatibility a new Func number
-                                            // (and hence REVISION) should be
-                                            // assigned.
-#define AES_REVISION_FUNC_S   16
-#define AES_REVISION_R_RTL_M  0x0000F800  // RTL Version (R)@@ maintained by
-                                            // IP design owner. RTL follows a
-                                            // numbering such as X.Y.R.Z which
-                                            // are explained in this table. R
-                                            // changes ONLY when: (1) PDS
-                                            // uploads occur which may have been
-                                            // due to spec changes (2) Bug fixes
-                                            // occur (3) Resets to '0' when X or
-                                            // Y changes. Design team has an
-                                            // internal 'Z' (customer invisible)
-                                            // number which increments on every
-                                            // drop that happens due to DV and
-                                            // RTL updates. Z resets to 0 when R
-                                            // increments.
-#define AES_REVISION_R_RTL_S  11
-#define AES_REVISION_X_MAJOR_M \
-                                0x00000700  // Major Revision (X)@@ maintained
-                                            // by IP specification owner. X
-                                            // changes ONLY when: (1) There is a
-                                            // major feature addition. An
-                                            // example would be adding Master
-                                            // Mode to Utopia Level2. The Func
-                                            // field (or Class/Type in old PID
-                                            // format) will remain the same. X
-                                            // does NOT change due to: (1) Bug
-                                            // fixes (2) Change in feature
-                                            // parameters.
-
-#define AES_REVISION_X_MAJOR_S 8
-#define AES_REVISION_CUSTOM_M 0x000000C0
-#define AES_REVISION_CUSTOM_S 6
-#define AES_REVISION_Y_MINOR_M \
-                                0x0000003F  // Minor Revision (Y)@@ maintained
-                                            // by IP specification owner. Y
-                                            // changes ONLY when: (1) Features
-                                            // are scaled (up or down).
-                                            // Flexibility exists in that this
-                                            // feature scalability may either be
-                                            // represented in the Y change or a
-                                            // specific register in the IP that
-                                            // indicates which features are
-                                            // exactly available. (2) When
-                                            // feature creeps from Is-Not list
-                                            // to Is list. But this may not be
-                                            // the case once it sees silicon; in
-                                            // which case X will change. Y does
-                                            // NOT change due to: (1) Bug fixes
-                                            // (2) Typos or clarifications (3)
-                                            // major functional/feature
-                                            // change/addition/deletion. Instead
-                                            // these changes may be reflected
-                                            // via R@@ S@@ X as applicable. Spec
-                                            // owner maintains a
-                                            // customer-invisible number 'S'
-                                            // which changes due to: (1)
-                                            // Typos/clarifications (2) Bug
-                                            // documentation. Note that this bug
-                                            // is not due to a spec change but
-                                            // due to implementation.
-                                            // Nevertheless@@ the spec tracks
-                                            // the IP bugs. An RTL release (say
-                                            // for silicon PG1.1) that occurs
-                                            // due to bug fix should document
-                                            // the corresponding spec number
-                                            // (X.Y.S) in its release notes.
-
-#define AES_REVISION_Y_MINOR_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_SYSCONFIG register.
-//
-//******************************************************************************
-#define AES_SYSCONFIG_MACONTEXT_OUT_ON_DATA_OUT \
-                                0x00000200  // If set to '1' the two context
-                                            // out requests
-                                            // (dma_req_context_out_en@@ Bit [8]
-                                            // above@@ and context_out interrupt
-                                            // enable@@ Bit [3] of AES_IRQENABLE
-                                            // register) are mapped on the
-                                            // corresponding data output request
-                                            // bit. In this case@@ the original
-                                            // ‘context out’ bit values are
-                                            // ignored.
-
-#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \
-                                0x00000100  // If set to ‘1’@@ the DMA context
-                                            // output request is enabled (for
-                                            // context data out@@ e.g. TAG for
-                                            // authentication modes). 0 Dma
-                                            // disabled 1 Dma enabled
-
-#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
-                                0x00000080  // If set to ‘1’@@ the DMA context
-                                            // request is enabled. 0 Dma
-                                            // disabled 1 Dma enabled
-
-#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
-                                0x00000040  // If set to ‘1’@@ the DMA output
-                                            // request is enabled. 0 Dma
-                                            // disabled 1 Dma enabled
-
-#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
-                                0x00000020  // If set to ‘1’@@ the DMA input
-                                            // request is enabled. 0 Dma
-                                            // disabled 1 Dma enabled
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_SYSSTATUS register.
-//
-//******************************************************************************
-#define AES_SYSSTATUS_RESETDONE \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_IRQSTATUS register.
-//
-//******************************************************************************
-#define AES_IRQSTATUS_CONTEXT_OUT \
-                                0x00000008  // This bit indicates
-                                            // authentication tag (and IV)
-                                            // interrupt(s) is/are active and
-                                            // triggers the interrupt output.
-
-#define AES_IRQSTATUS_DATA_OUT \
-                                0x00000004  // This bit indicates data output
-                                            // interrupt is active and triggers
-                                            // the interrupt output.
-
-#define AES_IRQSTATUS_DATA_IN 0x00000002  // This bit indicates data input
-                                            // interrupt is active and triggers
-                                            // the interrupt output.
-#define AES_IRQSTATUS_CONTEX_IN \
-                                0x00000001  // This bit indicates context
-                                            // interrupt is active and triggers
-                                            // the interrupt output.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the AES_O_IRQENABLE register.
-//
-//******************************************************************************
-#define AES_IRQENABLE_CONTEXT_OUT \
-                                0x00000008  // This bit indicates
-                                            // authentication tag (and IV)
-                                            // interrupt(s) is/are active and
-                                            // triggers the interrupt output.
-
-#define AES_IRQENABLE_DATA_OUT \
-                                0x00000004  // This bit indicates data output
-                                            // interrupt is active and triggers
-                                            // the interrupt output.
-
-#define AES_IRQENABLE_DATA_IN 0x00000002  // This bit indicates data input
-                                            // interrupt is active and triggers
-                                            // the interrupt output.
-#define AES_IRQENABLE_CONTEX_IN \
-                                0x00000001  // This bit indicates context
-                                            // interrupt is active and triggers
-                                            // the interrupt output.
-
-
-
-
-#endif // __HW_AES_H__
diff --git a/cc3200/hal/inc/hw_apps_config.h b/cc3200/hal/inc/hw_apps_config.h
deleted file mode 100644
index b8789b980..000000000
--- a/cc3200/hal/inc/hw_apps_config.h
+++ /dev/null
@@ -1,747 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-
-#ifndef __HW_APPS_CONFIG_H__
-#define __HW_APPS_CONFIG_H__
-
-//*****************************************************************************
-//
-// The following are defines for the APPS_CONFIG register offsets.
-//
-//*****************************************************************************
-#define APPS_CONFIG_O_PATCH_TRAP_ADDR_REG \
-                                0x00000000  // Patch trap address Register
-                                            // array
-
-#define APPS_CONFIG_O_PATCH_TRAP_EN_REG \
-                                0x00000078
-
-#define APPS_CONFIG_O_FAULT_STATUS_REG \
-                                0x0000007C
-
-#define APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG \
-                                0x00000080
-
-#define APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG \
-                                0x00000084
-
-#define APPS_CONFIG_O_DMA_DONE_INT_MASK \
-                                0x0000008C
-
-#define APPS_CONFIG_O_DMA_DONE_INT_MASK_SET \
-                                0x00000090
-
-#define APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR \
-                                0x00000094
-
-#define APPS_CONFIG_O_DMA_DONE_INT_STS_CLR \
-                                0x00000098
-
-#define APPS_CONFIG_O_DMA_DONE_INT_ACK \
-                                0x0000009C
-
-#define APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED \
-                                0x000000A0
-
-#define APPS_CONFIG_O_DMA_DONE_INT_STS_RAW \
-                                0x000000A4
-
-#define APPS_CONFIG_O_FAULT_STATUS_CLR_REG \
-                                0x000000A8
-
-#define APPS_CONFIG_O_RESERVD_REG_0 \
-                                0x000000AC
-
-#define APPS_CONFIG_O_GPT_TRIG_SEL \
-                                0x000000B0
-
-#define APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG \
-                                0x000000B4
-
-#define APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG \
-                                0x000000B8
-
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_CONFIG_O_PATCH_TRAP_ADDR_REG register.
-//
-//******************************************************************************
-#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_M \
-                                0xFFFFFFFF  // When PATCH_TRAP_EN[n] is set bus
-                                            // fault is generated for the
-                                            // address
-                                            // PATCH_TRAP_ADDR_REG[n][31:0] from
-                                            // Idcode bus. The exception routine
-                                            // should take care to jump to the
-                                            // location where the patch
-                                            // correspond to this address is
-                                            // kept.
-
-#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_CONFIG_O_PATCH_TRAP_EN_REG register.
-//
-//******************************************************************************
-#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_M \
-                                0x3FFFFFFF  // When PATCH_TRAP_EN[n] is set bus
-                                            // fault is generated for the
-                                            // address PATCH_TRAP_ADD[n][31:0]
-                                            // from Idcode bus. The exception
-                                            // routine should take care to jump
-                                            // to the location where the patch
-                                            // correspond to this address is
-                                            // kept.
-
-#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_CONFIG_O_FAULT_STATUS_REG register.
-//
-//******************************************************************************
-#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_M \
-                                0x0000003E  // This field shows because of
-                                            // which patch trap address the
-                                            // bus_fault is generated. If the
-                                            // PATCH_ERR bit is set, then it
-                                            // means the bus fault is generated
-                                            // because of
-                                            // PATCH_TRAP_ADDR_REG[2^PATCH_ERR_INDEX]
-
-#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_S 1
-#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR \
-                                0x00000001  // This bit is set when there is a
-                                            // bus fault because of patched
-                                            // address access to the Apps boot
-                                            // rom. Write 0 to clear this
-                                            // register.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG register.
-//
-//******************************************************************************
-#define APPS_CONFIG_MEMSS_WR_ERR_CLR_REG_MEMSS_WR_ERR_CLR \
-                                0x00000001  // This bit is set when there is a
-                                            // an error in memss write access.
-                                            // And the address causing this
-                                            // error is captured in
-                                            // MEMSS_ERR_ADDR_REG. To capture
-                                            // the next error address one have
-                                            // to clear this bit.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG register.
-//
-//******************************************************************************
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_CONFIG_O_DMA_DONE_INT_MASK register.
-//
-//******************************************************************************
-#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_M \
-                                0x0000F000  // 1= disable corresponding
-                                            // interrupt;0 = interrupt enabled
-                                            // bit 14: ADC channel 7 interrupt
-                                            // enable/disable bit 13: ADC
-                                            // channel 5 interrupt
-                                            // enable/disable bit 12: ADC
-                                            // channel 3 interrupt
-                                            // enable/disable bit 11: ADC
-                                            // channel 1 interrupt
-                                            // enable/disable
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_S 12
-#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_WR_DMA_DONE_INT_MASK \
-                                0x00000800  // 1= disable corresponding
-                                            // interrupt;0 = interrupt enabled
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_RD_DMA_DONE_INT_MASK \
-                                0x00000400  // 1= disable corresponding
-                                            // interrupt;0 = interrupt enabled
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK \
-                                0x00000200  // 1= disable corresponding
-                                            // interrupt;0 = interrupt enabled
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_THRESHHOLD_DMA_DONE_INT_MASK \
-                                0x00000100  // 1= disable corresponding
-                                            // interrupt;0 = interrupt enabled
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK \
-                                0x00000080  // 1= disable corresponding
-                                            // interrupt;0 = interrupt enabled
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_RD_DMA_DONE_INT_MASK \
-                                0x00000040  // 1= disable corresponding
-                                            // interrupt;0 = interrupt enabled
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK \
-                                0x00000020  // 1= disable corresponding
-                                            // interrupt;0 = interrupt enabled
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_RD_DMA_DONE_INT_MASK \
-                                0x00000010  // 1= disable corresponding
-                                            // interrupt;0 = interrupt enabled
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK \
-                                0x00000008  // 1= disable corresponding
-                                            // interrupt;0 = interrupt enabled
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_RD_DMA_DONE_INT_MASK \
-                                0x00000004  // 1= disable corresponding
-                                            // interrupt;0 = interrupt enabled
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_WR_DMA_DONE_INT_MASK \
-                                0x00000002  // 1= disable corresponding
-                                            // interrupt;0 = interrupt enabled
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_RD_DMA_DONE_INT_MASK \
-                                0x00000001  // 1= disable corresponding
-                                            // interrupt;0 = interrupt enabled
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_CONFIG_O_DMA_DONE_INT_MASK_SET register.
-//
-//******************************************************************************
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_M \
-                                0x0000F000  // write 1 to set mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect bit 14: ADC channel 7 DMA
-                                            // Done IRQ bit 13: ADC channel 5
-                                            // DMA Done IRQ bit 12: ADC channel
-                                            // 3 DMA Done IRQ bit 11: ADC
-                                            // channel 1 DMA Done IRQ
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_S 12
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_WR_DMA_DONE_INT_MASK_SET \
-                                0x00000800  // write 1 to set mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_RD_DMA_DONE_INT_MASK_SET \
-                                0x00000400  // write 1 to set mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_SET \
-                                0x00000200  // write 1 to set mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_THRESHHOLD_DMA_DONE_INT_MASK_SET \
-                                0x00000100  // write 1 to set mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_WR_DMA_DONE_INT_MASK_SET \
-                                0x00000080  // write 1 to set mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_RD_DMA_DONE_INT_MASK_SET \
-                                0x00000040  // write 1 to set mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_WR_DMA_DONE_INT_MASK_SET \
-                                0x00000020  // write 1 to set mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_RD_DMA_DONE_INT_MASK_SET \
-                                0x00000010  // write 1 to set mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_WR_DMA_DONE_INT_MASK_SET \
-                                0x00000008  // write 1 to set mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_RD_DMA_DONE_INT_MASK_SET \
-                                0x00000004  // write 1 to set mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_WR_DMA_DONE_INT_MASK_SET \
-                                0x00000002  // write 1 to set mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_RD_DMA_DONE_INT_MASK_SET \
-                                0x00000001  // write 1 to set mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR register.
-//
-//******************************************************************************
-#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_M \
-                                0x0000F000  // write 1 to clear mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect bit 14: ADC channel 7 DMA
-                                            // Done IRQ mask bit 13: ADC channel
-                                            // 5 DMA Done IRQ mask bit 12: ADC
-                                            // channel 3 DMA Done IRQ mask bit
-                                            // 11: ADC channel 1 DMA Done IRQ
-                                            // mask
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_S 12
-#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MACASP_WR_DMA_DONE_INT_MASK_CLR \
-                                0x00000800  // write 1 to clear mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MCASP_RD_DMA_DONE_INT_MASK_CLR \
-                                0x00000400  // write 1 to clear mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_CLR \
-                                0x00000200  // write 1 to clear mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_THRESHHOLD_DMA_DONE_INT_MASK_CLR \
-                                0x00000100  // write 1 to clear mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_WR_DMA_DONE_INT_MASK_CLR \
-                                0x00000080  // write 1 to clear mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_RD_DMA_DONE_INT_MASK_CLR \
-                                0x00000040  // write 1 to clear mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_WR_DMA_DONE_INT_MASK_CLR \
-                                0x00000020  // write 1 to clear mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_RD_DMA_DONE_INT_MASK_CLR \
-                                0x00000010  // write 1 to clear mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_WR_DMA_DONE_INT_MASK_CLR \
-                                0x00000008  // write 1 to clear mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_RD_DMA_DONE_INT_MASK_CLR \
-                                0x00000004  // write 1 to clear mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_WR_DMA_DONE_INT_MASK_CLR \
-                                0x00000002  // write 1 to clear mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_RD_DMA_DONE_INT_MASK_CLR \
-                                0x00000001  // write 1 to clear mask of the
-                                            // corresponding DMA DONE IRQ;0 = no
-                                            // effect
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_CONFIG_O_DMA_DONE_INT_STS_CLR register.
-//
-//******************************************************************************
-#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_M \
-                                0xFFFFFFFF  // write 1 or 0 to clear all
-                                            // DMA_DONE interrupt;
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_CONFIG_O_DMA_DONE_INT_ACK register.
-//
-//******************************************************************************
-#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_M \
-                                0x0000F000  // write 1 to clear corresponding
-                                            // interrupt; 0 = no effect; bit 14:
-                                            // ADC channel 7 DMA Done IRQ bit
-                                            // 13: ADC channel 5 DMA Done IRQ
-                                            // bit 12: ADC channel 3 DMA Done
-                                            // IRQ bit 11: ADC channel 1 DMA
-                                            // Done IRQ
-
-#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_S 12
-#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_WR_DMA_DONE_INT_ACK \
-                                0x00000800  // write 1 to clear corresponding
-                                            // interrupt; 0 = no effect;
-
-#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_RD_DMA_DONE_INT_ACK \
-                                0x00000400  // write 1 to clear corresponding
-                                            // interrupt; 0 = no effect;
-
-#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_FIFO_EMPTY_DMA_DONE_INT_ACK \
-                                0x00000200  // write 1 to clear corresponding
-                                            // interrupt; 0 = no effect;
-
-#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_THRESHHOLD_DMA_DONE_INT_ACK \
-                                0x00000100  // write 1 to clear corresponding
-                                            // interrupt; 0 = no effect;
-
-#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_WR_DMA_DONE_INT_ACK \
-                                0x00000080  // write 1 to clear corresponding
-                                            // interrupt; 0 = no effect;
-
-#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_RD_DMA_DONE_INT_ACK \
-                                0x00000040  // write 1 to clear corresponding
-                                            // interrupt; 0 = no effect;
-
-#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_WR_DMA_DONE_INT_ACK \
-                                0x00000020  // write 1 to clear corresponding
-                                            // interrupt; 0 = no effect;
-
-#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_RD_DMA_DONE_INT_ACK \
-                                0x00000010  // write 1 to clear corresponding
-                                            // interrupt; 0 = no effect;
-
-#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_WR_DMA_DONE_INT_ACK \
-                                0x00000008  // write 1 to clear corresponding
-                                            // interrupt; 0 = no effect;
-
-#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_RD_DMA_DONE_INT_ACK \
-                                0x00000004  // write 1 to clear corresponding
-                                            // interrupt; 0 = no effect;
-
-#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_WR_DMA_DONE_INT_ACK \
-                                0x00000002  // write 1 to clear corresponding
-                                            // interrupt; 0 = no effect;
-
-#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_RD_DMA_DONE_INT_ACK \
-                                0x00000001  // write 1 to clear corresponding
-                                            // interrupt; 0 = no effect;
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED register.
-//
-//******************************************************************************
-#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_M \
-                                0x0000F000  // 1= corresponding interrupt is
-                                            // active and not masked. read is
-                                            // non-destructive;0 = corresponding
-                                            // interrupt is inactive or masked
-                                            // by DMA_DONE_INT mask bit 14: ADC
-                                            // channel 7 DMA Done IRQ bit 13:
-                                            // ADC channel 5 DMA Done IRQ bit
-                                            // 12: ADC channel 3 DMA Done IRQ
-                                            // bit 11: ADC channel 1 DMA Done
-                                            // IRQ
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_S 12
-#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_WR_DMA_DONE_INT_STS_MASKED \
-                                0x00000800  // 1= corresponding interrupt is
-                                            // active and not masked. read is
-                                            // non-destructive;0 = corresponding
-                                            // interrupt is inactive or masked
-                                            // by DMA_DONE_INT mask
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_RD_DMA_DONE_INT_STS_MASKED \
-                                0x00000400  // 1= corresponding interrupt is
-                                            // active and not masked. read is
-                                            // non-destructive;0 = corresponding
-                                            // interrupt is inactive or masked
-                                            // by DMA_DONE_INT mask
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_FIFO_EMPTY_DMA_DONE_INT_STS_MASKED \
-                                0x00000200  // 1= corresponding interrupt is
-                                            // active and not masked. read is
-                                            // non-destructive;0 = corresponding
-                                            // interrupt is inactive or masked
-                                            // by DMA_DONE_INT mask
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_THRESHHOLD_DMA_DONE_INT_STS_MASKED \
-                                0x00000100  // 1= corresponding interrupt is
-                                            // active and not masked. read is
-                                            // non-destructive;0 = corresponding
-                                            // interrupt is inactive or masked
-                                            // by DMA_DONE_INT mask
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_WR_DMA_DONE_INT_STS_MASKED \
-                                0x00000080  // 1= corresponding interrupt is
-                                            // active and not masked. read is
-                                            // non-destructive;0 = corresponding
-                                            // interrupt is inactive or masked
-                                            // by DMA_DONE_INT mask
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_RD_DMA_DONE_INT_STS_MASKED \
-                                0x00000040  // 1= corresponding interrupt is
-                                            // active and not masked. read is
-                                            // non-destructive;0 = corresponding
-                                            // interrupt is inactive or masked
-                                            // by DMA_DONE_INT mask
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_WR_DMA_DONE_INT_STS_MASKED \
-                                0x00000020  // 1= corresponding interrupt is
-                                            // active and not masked. read is
-                                            // non-destructive;0 = corresponding
-                                            // interrupt is inactive or masked
-                                            // by DMA_DONE_INT mask
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_RD_DMA_DONE_INT_STS_MASKED \
-                                0x00000010  // 1= corresponding interrupt is
-                                            // active and not masked. read is
-                                            // non-destructive;0 = corresponding
-                                            // interrupt is inactive or masked
-                                            // by DMA_DONE_INT mask
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_WR_DMA_DONE_INT_STS_MASKED \
-                                0x00000008  // 1= corresponding interrupt is
-                                            // active and not masked. read is
-                                            // non-destructive;0 = corresponding
-                                            // interrupt is inactive or masked
-                                            // by DMA_DONE_INT mask
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_RD_DMA_DONE_INT_STS_MASKED \
-                                0x00000004  // 1= corresponding interrupt is
-                                            // active and not masked. read is
-                                            // non-destructive;0 = corresponding
-                                            // interrupt is inactive or masked
-                                            // by DMA_DONE_INT mask
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_WR_DMA_DONE_INT_STS_MASKED \
-                                0x00000002  // 1= corresponding interrupt is
-                                            // active and not masked. read is
-                                            // non-destructive;0 = corresponding
-                                            // interrupt is inactive or masked
-                                            // by DMA_DONE_INT mask
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_RD_DMA_DONE_INT_STS_MASKED \
-                                0x00000001  // 1= corresponding interrupt is
-                                            // active and not masked. read is
-                                            // non-destructive;0 = corresponding
-                                            // interrupt is inactive or masked
-                                            // by DMA_DONE_INT mask
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_CONFIG_O_DMA_DONE_INT_STS_RAW register.
-//
-//******************************************************************************
-#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_M \
-                                0x0000F000  // 1= corresponding interrupt is
-                                            // active. read is non-destructive;0
-                                            // = corresponding interrupt is
-                                            // inactive bit 14: ADC channel 7
-                                            // DMA Done IRQ bit 13: ADC channel
-                                            // 5 DMA Done IRQ bit 12: ADC
-                                            // channel 3 DMA Done IRQ bit 11:
-                                            // ADC channel 1 DMA Done IRQ
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_S 12
-#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_WR_DMA_DONE_INT_STS_RAW \
-                                0x00000800  // 1= corresponding interrupt is
-                                            // active. read is non-destructive;0
-                                            // = corresponding interrupt is
-                                            // inactive
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_RD_DMA_DONE_INT_STS_RAW \
-                                0x00000400  // 1= corresponding interrupt is
-                                            // active. read is non-destructive;0
-                                            // = corresponding interrupt is
-                                            // inactive
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_EPMTY_FIFO_DMA_DONE_INT_STS_RAW \
-                                0x00000200  // 1= corresponding interrupt is
-                                            // active. read is non-destructive;0
-                                            // = corresponding interrupt is
-                                            // inactive
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_THRESHHOLD_DMA_DONE_INT_STS_RAW \
-                                0x00000100  // 1= corresponding interrupt is
-                                            // active. read is non-destructive;0
-                                            // = corresponding interrupt is
-                                            // inactive
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_WR_DMA_DONE_INT_STS_RAW \
-                                0x00000080  // 1= corresponding interrupt is
-                                            // active. read is non-destructive;0
-                                            // = corresponding interrupt is
-                                            // inactive
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_RD_DMA_DONE_INT_STS_RAW \
-                                0x00000040  // 1= corresponding interrupt is
-                                            // active. read is non-destructive;0
-                                            // = corresponding interrupt is
-                                            // inactive
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_WR_DMA_DONE_INT_STS_RAW \
-                                0x00000020  // 1= corresponding interrupt is
-                                            // active. read is non-destructive;0
-                                            // = corresponding interrupt is
-                                            // inactive
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_RD_DMA_DONE_INT_STS_RAW \
-                                0x00000010  // 1= corresponding interrupt is
-                                            // active. read is non-destructive;0
-                                            // = corresponding interrupt is
-                                            // inactive
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_WR_DMA_DONE_INT_STS_RAW \
-                                0x00000008  // 1= corresponding interrupt is
-                                            // active. read is non-destructive;0
-                                            // = corresponding interrupt is
-                                            // inactive
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_RD_DMA_DONE_INT_STS_RAW \
-                                0x00000004  // 1= corresponding interrupt is
-                                            // active. read is non-destructive;0
-                                            // = corresponding interrupt is
-                                            // inactive
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_WR_DMA_DONE_INT_STS_RAW \
-                                0x00000002  // 1= corresponding interrupt is
-                                            // active. read is non-destructive;0
-                                            // = corresponding interrupt is
-                                            // inactive
-
-#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_RD_DMA_DONE_INT_STS_RAW \
-                                0x00000001  // 1= corresponding interrupt is
-                                            // active. read is non-destructive;0
-                                            // = corresponding interrupt is
-                                            // inactive
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_CONFIG_O_FAULT_STATUS_CLR_REG register.
-//
-//******************************************************************************
-#define APPS_CONFIG_FAULT_STATUS_CLR_REG_PATCH_ERR_CLR \
-                                0x00000001  // Write 1 to clear the LSB of
-                                            // FAULT_STATUS_REG
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_CONFIG_O_RESERVD_REG_0 register.
-//
-//******************************************************************************
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_CONFIG_O_GPT_TRIG_SEL register.
-//
-//******************************************************************************
-#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_M \
-                                0x000000FF  // This bit is implemented for GPT
-                                            // trigger mode select. GPT IP
-                                            // support 2 modes: RTC mode and
-                                            // external trigger. When this bit
-                                            // is set to logic '1': enable
-                                            // external trigger mode for APPS
-                                            // GPT CP0 and CP1 pin. bit 0: when
-                                            // set '1' enable external GPT
-                                            // trigger 0 on GPIO0 CP0 pin else
-                                            // RTC mode is selected. bit 1: when
-                                            // set '1' enable external GPT
-                                            // trigger 1 on GPIO0 CP1 pin else
-                                            // RTC mode is selected. bit 2: when
-                                            // set '1' enable external GPT
-                                            // trigger 2 on GPIO1 CP0 pin else
-                                            // RTC mode is selected. bit 3: when
-                                            // set '1' enable external GPT
-                                            // trigger 3 on GPIO1 CP1 pin else
-                                            // RTC mode is selected. bit 4: when
-                                            // set '1' enable external GPT
-                                            // trigger 4 on GPIO2 CP0 pin else
-                                            // RTC mode is selected. bit 5: when
-                                            // set '1' enable external GPT
-                                            // trigger 5 on GPIO2 CP1 pin else
-                                            // RTC mode is selected. bit 6: when
-                                            // set '1' enable external GPT
-                                            // trigger 6 on GPIO3 CP0 pin else
-                                            // RTC mode is selected. bit 7: when
-                                            // set '1' enable external GPT
-                                            // trigger 7 on GPIO3 CP1 pin else
-                                            // RTC mode is selected.
-
-#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG register.
-//
-//******************************************************************************
-#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_M \
-                                0x00000007  // Capture data from d2d_spare pads
-
-#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG register.
-//
-//******************************************************************************
-#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_M \
-                                0x00000007  // Send data to d2d_spare pads -
-                                            // eventually this will get
-                                            // registered in top die
-
-#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_S 0
-
-
-
-#endif // __HW_APPS_CONFIG_H__
diff --git a/cc3200/hal/inc/hw_apps_rcm.h b/cc3200/hal/inc/hw_apps_rcm.h
deleted file mode 100644
index edb52d26b..000000000
--- a/cc3200/hal/inc/hw_apps_rcm.h
+++ /dev/null
@@ -1,1506 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_APPS_RCM_H__
-#define __HW_APPS_RCM_H__
-
-//*****************************************************************************
-//
-// The following are defines for the APPS_RCM register offsets.
-//
-//*****************************************************************************
-#define APPS_RCM_O_CAMERA_CLK_GEN \
-                                0x00000000
-
-#define APPS_RCM_O_CAMERA_CLK_GATING \
-                                0x00000004
-
-#define APPS_RCM_O_CAMERA_SOFT_RESET \
-                                0x00000008
-
-#define APPS_RCM_O_MCASP_CLK_GATING \
-                                0x00000014
-
-#define APPS_RCM_O_MCASP_SOFT_RESET \
-                                0x00000018
-
-#define APPS_RCM_O_MMCHS_CLK_GEN \
-                                0x00000020
-
-#define APPS_RCM_O_MMCHS_CLK_GATING \
-                                0x00000024
-
-#define APPS_RCM_O_MMCHS_SOFT_RESET \
-                                0x00000028
-
-#define APPS_RCM_O_MCSPI_A1_CLK_GEN \
-                                0x0000002C
-
-#define APPS_RCM_O_MCSPI_A1_CLK_GATING \
-                                0x00000030
-
-#define APPS_RCM_O_MCSPI_A1_SOFT_RESET \
-                                0x00000034
-
-#define APPS_RCM_O_MCSPI_A2_CLK_GEN \
-                                0x00000038
-
-#define APPS_RCM_O_MCSPI_A2_CLK_GATING \
-                                0x00000040
-
-#define APPS_RCM_O_MCSPI_A2_SOFT_RESET \
-                                0x00000044
-
-#define APPS_RCM_O_UDMA_A_CLK_GATING \
-                                0x00000048
-
-#define APPS_RCM_O_UDMA_A_SOFT_RESET \
-                                0x0000004C
-
-#define APPS_RCM_O_GPIO_A_CLK_GATING \
-                                0x00000050
-
-#define APPS_RCM_O_GPIO_A_SOFT_RESET \
-                                0x00000054
-
-#define APPS_RCM_O_GPIO_B_CLK_GATING \
-                                0x00000058
-
-#define APPS_RCM_O_GPIO_B_SOFT_RESET \
-                                0x0000005C
-
-#define APPS_RCM_O_GPIO_C_CLK_GATING \
-                                0x00000060
-
-#define APPS_RCM_O_GPIO_C_SOFT_RESET \
-                                0x00000064
-
-#define APPS_RCM_O_GPIO_D_CLK_GATING \
-                                0x00000068
-
-#define APPS_RCM_O_GPIO_D_SOFT_RESET \
-                                0x0000006C
-
-#define APPS_RCM_O_GPIO_E_CLK_GATING \
-                                0x00000070
-
-#define APPS_RCM_O_GPIO_E_SOFT_RESET \
-                                0x00000074
-
-#define APPS_RCM_O_WDOG_A_CLK_GATING \
-                                0x00000078
-
-#define APPS_RCM_O_WDOG_A_SOFT_RESET \
-                                0x0000007C
-
-#define APPS_RCM_O_UART_A0_CLK_GATING \
-                                0x00000080
-
-#define APPS_RCM_O_UART_A0_SOFT_RESET \
-                                0x00000084
-
-#define APPS_RCM_O_UART_A1_CLK_GATING \
-                                0x00000088
-
-#define APPS_RCM_O_UART_A1_SOFT_RESET \
-                                0x0000008C
-
-#define APPS_RCM_O_GPT_A0_CLK_GATING \
-                                0x00000090
-
-#define APPS_RCM_O_GPT_A0_SOFT_RESET \
-                                0x00000094
-
-#define APPS_RCM_O_GPT_A1_CLK_GATING \
-                                0x00000098
-
-#define APPS_RCM_O_GPT_A1_SOFT_RESET \
-                                0x0000009C
-
-#define APPS_RCM_O_GPT_A2_CLK_GATING \
-                                0x000000A0
-
-#define APPS_RCM_O_GPT_A2_SOFT_RESET \
-                                0x000000A4
-
-#define APPS_RCM_O_GPT_A3_CLK_GATING \
-                                0x000000A8
-
-#define APPS_RCM_O_GPT_A3_SOFT_RESET \
-                                0x000000AC
-
-#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 \
-                                0x000000B0
-
-#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 \
-                                0x000000B4
-
-#define APPS_RCM_O_CRYPTO_CLK_GATING \
-                                0x000000B8
-
-#define APPS_RCM_O_CRYPTO_SOFT_RESET \
-                                0x000000BC
-
-#define APPS_RCM_O_MCSPI_S0_CLK_GATING \
-                                0x000000C8
-
-#define APPS_RCM_O_MCSPI_S0_SOFT_RESET \
-                                0x000000CC
-
-#define APPS_RCM_O_MCSPI_S0_CLKDIV_CFG \
-                                0x000000D0
-
-#define APPS_RCM_O_I2C_CLK_GATING \
-                                0x000000D8
-
-#define APPS_RCM_O_I2C_SOFT_RESET \
-                                0x000000DC
-
-#define APPS_RCM_O_APPS_LPDS_REQ \
-                                0x000000E4
-
-#define APPS_RCM_O_APPS_TURBO_REQ \
-                                0x000000EC
-
-#define APPS_RCM_O_APPS_DSLP_WAKE_CONFIG \
-                                0x00000108
-
-#define APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG \
-                                0x0000010C
-
-#define APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE \
-                                0x00000110
-
-#define APPS_RCM_O_APPS_SLP_WAKETIMER_CFG \
-                                0x00000114
-
-#define APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST \
-                                0x00000118
-
-#define APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS \
-                                0x00000120
-
-#define APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE \
-                                0x00000124
-
-
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_CAMERA_CLK_GEN register.
-//
-//******************************************************************************
-#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_M \
-                                0x00000700  // Configuration of OFF-TIME for
-                                            // dividing PLL clk (240 MHz) in
-                                            // generation of Camera func-clk :
-                                            // "000" - 1 "001" - 2 "010" - 3
-                                            // "011" - 4 "100" - 5 "101" - 6
-                                            // "110" - 7 "111" - 8
-
-#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_S 8
-#define APPS_RCM_CAMERA_CLK_GEN_NU1_M \
-                                0x000000F8
-
-#define APPS_RCM_CAMERA_CLK_GEN_NU1_S 3
-#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_M \
-                                0x00000007  // Configuration of ON-TIME for
-                                            // dividing PLL clk (240 MHz) in
-                                            // generation of Camera func-clk :
-                                            // "000" - 1 "001" - 2 "010" - 3
-                                            // "011" - 4 "100" - 5 "101" - 6
-                                            // "110" - 7 "111" - 8
-
-#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_CAMERA_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_CAMERA_CLK_GATING_NU1_M \
-                                0x00FE0000
-
-#define APPS_RCM_CAMERA_CLK_GATING_NU1_S 17
-#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_DSLP_CLK_ENABLE \
-                                0x00010000  // 0 - Disable camera clk during
-                                            // deep-sleep mode
-
-#define APPS_RCM_CAMERA_CLK_GATING_NU2_M \
-                                0x0000FE00
-
-#define APPS_RCM_CAMERA_CLK_GATING_NU2_S 9
-#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_SLP_CLK_ENABLE \
-                                0x00000100  // 1- Enable camera clk during
-                                            // sleep mode ; 0- Disable camera
-                                            // clk during sleep mode
-
-#define APPS_RCM_CAMERA_CLK_GATING_NU3_M \
-                                0x000000FE
-
-#define APPS_RCM_CAMERA_CLK_GATING_NU3_S 1
-#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_RUN_CLK_ENABLE \
-                                0x00000001  // 1- Enable camera clk during run
-                                            // mode ; 0- Disable camera clk
-                                            // during run mode
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_CAMERA_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_ENABLED_STATUS \
-                                0x00000002  // 1 - Camera clocks/resets are
-                                            // enabled ; 0 - Camera
-                                            // clocks/resets are disabled
-
-#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_SOFT_RESET \
-                                0x00000001  // 1 - Assert reset for Camera-core
-                                            // ; 0 - De-assert reset for
-                                            // Camera-core
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_MCASP_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_MCASP_CLK_GATING_NU1_M \
-                                0x00FE0000
-
-#define APPS_RCM_MCASP_CLK_GATING_NU1_S 17
-#define APPS_RCM_MCASP_CLK_GATING_MCASP_DSLP_CLK_ENABLE \
-                                0x00010000  // 0 - Disable MCASP clk during
-                                            // deep-sleep mode
-
-#define APPS_RCM_MCASP_CLK_GATING_NU2_M \
-                                0x0000FE00
-
-#define APPS_RCM_MCASP_CLK_GATING_NU2_S 9
-#define APPS_RCM_MCASP_CLK_GATING_MCASP_SLP_CLK_ENABLE \
-                                0x00000100  // 1- Enable MCASP clk during sleep
-                                            // mode ; 0- Disable MCASP clk
-                                            // during sleep mode
-
-#define APPS_RCM_MCASP_CLK_GATING_NU3_M \
-                                0x000000FE
-
-#define APPS_RCM_MCASP_CLK_GATING_NU3_S 1
-#define APPS_RCM_MCASP_CLK_GATING_MCASP_RUN_CLK_ENABLE \
-                                0x00000001  // 1- Enable MCASP clk during run
-                                            // mode ; 0- Disable MCASP clk
-                                            // during run mode
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_MCASP_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_MCASP_SOFT_RESET_MCASP_ENABLED_STATUS \
-                                0x00000002  // 1 - MCASP Clocks/resets are
-                                            // enabled ; 0 - MCASP Clocks/resets
-                                            // are disabled
-
-#define APPS_RCM_MCASP_SOFT_RESET_MCASP_SOFT_RESET \
-                                0x00000001  // 1 - Assert reset for MCASP-core
-                                            // ; 0 - De-assert reset for
-                                            // MCASP-core
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_MMCHS_CLK_GEN register.
-//
-//******************************************************************************
-#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_M \
-                                0x00000700  // Configuration of OFF-TIME for
-                                            // dividing PLL clk (240 MHz) in
-                                            // generation of MMCHS func-clk :
-                                            // "000" - 1 "001" - 2 "010" - 3
-                                            // "011" - 4 "100" - 5 "101" - 6
-                                            // "110" - 7 "111" - 8
-
-#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_S 8
-#define APPS_RCM_MMCHS_CLK_GEN_NU1_M \
-                                0x000000F8
-
-#define APPS_RCM_MMCHS_CLK_GEN_NU1_S 3
-#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_M \
-                                0x00000007  // Configuration of ON-TIME for
-                                            // dividing PLL clk (240 MHz) in
-                                            // generation of MMCHS func-clk :
-                                            // "000" - 1 "001" - 2 "010" - 3
-                                            // "011" - 4 "100" - 5 "101" - 6
-                                            // "110" - 7 "111" - 8
-
-#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_MMCHS_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_MMCHS_CLK_GATING_NU1_M \
-                                0x00FE0000
-
-#define APPS_RCM_MMCHS_CLK_GATING_NU1_S 17
-#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_DSLP_CLK_ENABLE \
-                                0x00010000  // 0 - Disable MMCHS clk during
-                                            // deep-sleep mode
-
-#define APPS_RCM_MMCHS_CLK_GATING_NU2_M \
-                                0x0000FE00
-
-#define APPS_RCM_MMCHS_CLK_GATING_NU2_S 9
-#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_SLP_CLK_ENABLE \
-                                0x00000100  // 1- Enable MMCHS clk during sleep
-                                            // mode ; 0- Disable MMCHS clk
-                                            // during sleep mode
-
-#define APPS_RCM_MMCHS_CLK_GATING_NU3_M \
-                                0x000000FE
-
-#define APPS_RCM_MMCHS_CLK_GATING_NU3_S 1
-#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_RUN_CLK_ENABLE \
-                                0x00000001  // 1- Enable MMCHS clk during run
-                                            // mode ; 0- Disable MMCHS clk
-                                            // during run mode
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_MMCHS_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_ENABLED_STATUS \
-                                0x00000002  // 1 - MMCHS Clocks/resets are
-                                            // enabled ; 0 - MMCHS Clocks/resets
-                                            // are disabled
-
-#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_SOFT_RESET \
-                                0x00000001  // 1 - Assert reset for MMCHS-core
-                                            // ; 0 - De-assert reset for
-                                            // MMCHS-core
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_MCSPI_A1_CLK_GEN register.
-//
-//******************************************************************************
-#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_BAUD_CLK_SEL \
-                                0x00010000  // 0 - XTAL clk is used as baud clk
-                                            // for MCSPI_A1 ; 1 - PLL divclk is
-                                            // used as baud clk for MCSPI_A1.
-
-#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_M \
-                                0x0000F800
-
-#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_S 11
-#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_M \
-                                0x00000700  // Configuration of OFF-TIME for
-                                            // dividing PLL clk (240 MHz) in
-                                            // generation of MCSPI_A1 func-clk :
-                                            // "000" - 1 "001" - 2 "010" - 3
-                                            // "011" - 4 "100" - 5 "101" - 6
-                                            // "110" - 7 "111" - 8
-
-#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_S 8
-#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_M \
-                                0x000000F8
-
-#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_S 3
-#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_M \
-                                0x00000007  // Configuration of ON-TIME for
-                                            // dividing PLL clk (240 MHz) in
-                                            // generation of MCSPI_A1 func-clk :
-                                            // "000" - 1 "001" - 2 "010" - 3
-                                            // "011" - 4 "100" - 5 "101" - 6
-                                            // "110" - 7 "111" - 8
-
-#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_MCSPI_A1_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_M \
-                                0x00FE0000
-
-#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_S 17
-#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_DSLP_CLK_ENABLE \
-                                0x00010000  // 0 - Disable MCSPI_A1 clk during
-                                            // deep-sleep mode
-
-#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_M \
-                                0x0000FE00
-
-#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_S 9
-#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_SLP_CLK_ENABLE \
-                                0x00000100  // 1- Enable MCSPI_A1 clk during
-                                            // sleep mode ; 0- Disable MCSPI_A1
-                                            // clk during sleep mode
-
-#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_M \
-                                0x000000FE
-
-#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_S 1
-#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_RUN_CLK_ENABLE \
-                                0x00000001  // 1- Enable MCSPI_A1 clk during
-                                            // run mode ; 0- Disable MCSPI_A1
-                                            // clk during run mode
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_MCSPI_A1_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_ENABLED_STATUS \
-                                0x00000002  // 1 - MCSPI_A1 Clocks/Resets are
-                                            // enabled ; 0 - MCSPI_A1
-                                            // Clocks/Resets are disabled
-
-#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_SOFT_RESET \
-                                0x00000001  // 1 - Assert reset for
-                                            // MCSPI_A1-core ; 0 - De-assert
-                                            // reset for MCSPI_A1-core
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_MCSPI_A2_CLK_GEN register.
-//
-//******************************************************************************
-#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_BAUD_CLK_SEL \
-                                0x00010000  // 0 - XTAL clk is used as baud-clk
-                                            // for MCSPI_A2 ; 1 - PLL divclk is
-                                            // used as baud-clk for MCSPI_A2
-
-#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_M \
-                                0x0000F800
-
-#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_S 11
-#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_M \
-                                0x00000700  // Configuration of OFF-TIME for
-                                            // dividing PLL clk (240 MHz) in
-                                            // generation of MCSPI_A2 func-clk :
-                                            // "000" - 1 "001" - 2 "010" - 3
-                                            // "011" - 4 "100" - 5 "101" - 6
-                                            // "110" - 7 "111" - 8
-
-#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_S 8
-#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_M \
-                                0x000000F8
-
-#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_S 3
-#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_M \
-                                0x00000007  // Configuration of OFF-TIME for
-                                            // dividing PLL clk (240 MHz) in
-                                            // generation of MCSPI_A2 func-clk :
-                                            // "000" - 1 "001" - 2 "010" - 3
-                                            // "011" - 4 "100" - 5 "101" - 6
-                                            // "110" - 7 "111" - 8
-
-#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_MCSPI_A2_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_M \
-                                0x00FE0000
-
-#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_S 17
-#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_DSLP_CLK_ENABLE \
-                                0x00010000  // 0 - Disable MCSPI_A2 clk during
-                                            // deep-sleep mode
-
-#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_M \
-                                0x0000FE00
-
-#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_S 9
-#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_SLP_CLK_ENABLE \
-                                0x00000100  // 1- Enable MCSPI_A2 clk during
-                                            // sleep mode ; 0- Disable MCSPI_A2
-                                            // clk during sleep mode
-
-#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_M \
-                                0x000000FE
-
-#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_S 1
-#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_RUN_CLK_ENABLE \
-                                0x00000001  // 1- Enable MCSPI_A2 clk during
-                                            // run mode ; 0- Disable MCSPI_A2
-                                            // clk during run mode
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_MCSPI_A2_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_ENABLED_STATUS \
-                                0x00000002  // 1 - MCSPI_A2 Clocks/Resets are
-                                            // enabled ; 0 - MCSPI_A2
-                                            // Clocks/Resets are disabled
-
-#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_SOFT_RESET \
-                                0x00000001  // 1 - Assert reset for
-                                            // MCSPI_A2-core ; 0 - De-assert
-                                            // reset for MCSPI_A2-core
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_UDMA_A_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_DSLP_CLK_ENABLE \
-                                0x00010000  // 1 - Enable UDMA_A clk during
-                                            // deep-sleep mode 0 - Disable
-                                            // UDMA_A clk during deep-sleep mode
-                                            // ;
-
-#define APPS_RCM_UDMA_A_CLK_GATING_NU1_M \
-                                0x0000FE00
-
-#define APPS_RCM_UDMA_A_CLK_GATING_NU1_S 9
-#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_SLP_CLK_ENABLE \
-                                0x00000100  // 1 - Enable UDMA_A clk during
-                                            // sleep mode 0 - Disable UDMA_A clk
-                                            // during sleep mode ;
-
-#define APPS_RCM_UDMA_A_CLK_GATING_NU2_M \
-                                0x000000FE
-
-#define APPS_RCM_UDMA_A_CLK_GATING_NU2_S 1
-#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_RUN_CLK_ENABLE \
-                                0x00000001  // 1 - Enable UDMA_A clk during run
-                                            // mode 0 - Disable UDMA_A clk
-                                            // during run mode ;
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_UDMA_A_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_ENABLED_STATUS \
-                                0x00000002  // 1 - UDMA_A Clocks/Resets are
-                                            // enabled ; 0 - UDMA_A
-                                            // Clocks/Resets are disabled
-
-#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_SOFT_RESET \
-                                0x00000001  // 1 - Assert reset for DMA_A ; 0 -
-                                            // De-assert reset for DMA_A
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPIO_A_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_DSLP_CLK_ENABLE \
-                                0x00010000  // 1 - Enable GPIO_A clk during
-                                            // deep-sleep mode 0 - Disable
-                                            // GPIO_A clk during deep-sleep mode
-                                            // ;
-
-#define APPS_RCM_GPIO_A_CLK_GATING_NU1_M \
-                                0x0000FE00
-
-#define APPS_RCM_GPIO_A_CLK_GATING_NU1_S 9
-#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_SLP_CLK_ENABLE \
-                                0x00000100  // 1 - Enable GPIO_A clk during
-                                            // sleep mode 0 - Disable GPIO_A clk
-                                            // during sleep mode ;
-
-#define APPS_RCM_GPIO_A_CLK_GATING_NU2_M \
-                                0x000000FE
-
-#define APPS_RCM_GPIO_A_CLK_GATING_NU2_S 1
-#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_RUN_CLK_ENABLE \
-                                0x00000001  // 1 - Enable GPIO_A clk during run
-                                            // mode 0 - Disable GPIO_A clk
-                                            // during run mode ;
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPIO_A_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_ENABLED_STATUS \
-                                0x00000002  // 1 - GPIO_A Clocks/Resets are
-                                            // enabled ; 0 - GPIO_A
-                                            // Clocks/Resets are disabled
-
-#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_SOFT_RESET \
-                                0x00000001  // 1 - Assert reset for GPIO_A ; 0
-                                            // - De-assert reset for GPIO_A
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPIO_B_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_DSLP_CLK_ENABLE \
-                                0x00010000  // 1 - Enable GPIO_B clk during
-                                            // deep-sleep mode 0 - Disable
-                                            // GPIO_B clk during deep-sleep mode
-                                            // ;
-
-#define APPS_RCM_GPIO_B_CLK_GATING_NU1_M \
-                                0x0000FE00
-
-#define APPS_RCM_GPIO_B_CLK_GATING_NU1_S 9
-#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_SLP_CLK_ENABLE \
-                                0x00000100  // 1 - Enable GPIO_B clk during
-                                            // sleep mode 0 - Disable GPIO_B clk
-                                            // during sleep mode ;
-
-#define APPS_RCM_GPIO_B_CLK_GATING_NU2_M \
-                                0x000000FE
-
-#define APPS_RCM_GPIO_B_CLK_GATING_NU2_S 1
-#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_RUN_CLK_ENABLE \
-                                0x00000001  // 1 - Enable GPIO_B clk during run
-                                            // mode 0 - Disable GPIO_B clk
-                                            // during run mode ;
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPIO_B_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_ENABLED_STATUS \
-                                0x00000002  // 1 - GPIO_B Clocks/Resets are
-                                            // enabled ; 0 - GPIO_B
-                                            // Clocks/Resets are disabled
-
-#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_SOFT_RESET \
-                                0x00000001  // 1 - Assert reset for GPIO_B ; 0
-                                            // - De-assert reset for GPIO_B
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPIO_C_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_DSLP_CLK_ENABLE \
-                                0x00010000  // 1 - Enable GPIO_C clk during
-                                            // deep-sleep mode 0 - Disable
-                                            // GPIO_C clk during deep-sleep mode
-                                            // ;
-
-#define APPS_RCM_GPIO_C_CLK_GATING_NU1_M \
-                                0x0000FE00
-
-#define APPS_RCM_GPIO_C_CLK_GATING_NU1_S 9
-#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_SLP_CLK_ENABLE \
-                                0x00000100  // 1 - Enable GPIO_C clk during
-                                            // sleep mode 0 - Disable GPIO_C clk
-                                            // during sleep mode ;
-
-#define APPS_RCM_GPIO_C_CLK_GATING_NU2_M \
-                                0x000000FE
-
-#define APPS_RCM_GPIO_C_CLK_GATING_NU2_S 1
-#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_RUN_CLK_ENABLE \
-                                0x00000001  // 1 - Enable GPIO_C clk during run
-                                            // mode 0 - Disable GPIO_C clk
-                                            // during run mode ;
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPIO_C_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_ENABLED_STATUS \
-                                0x00000002  // 1 - GPIO_C Clocks/Resets are
-                                            // enabled ; 0 - GPIO_C
-                                            // Clocks/Resets are disabled
-
-#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_SOFT_RESET \
-                                0x00000001  // 1 - Assert reset for GPIO_C ; 0
-                                            // - De-assert reset for GPIO_C
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPIO_D_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_DSLP_CLK_ENABLE \
-                                0x00010000  // 1 - Enable GPIO_D clk during
-                                            // deep-sleep mode 0 - Disable
-                                            // GPIO_D clk during deep-sleep mode
-                                            // ;
-
-#define APPS_RCM_GPIO_D_CLK_GATING_NU1_M \
-                                0x0000FE00
-
-#define APPS_RCM_GPIO_D_CLK_GATING_NU1_S 9
-#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_SLP_CLK_ENABLE \
-                                0x00000100  // 1 - Enable GPIO_D clk during
-                                            // sleep mode 0 - Disable GPIO_D clk
-                                            // during sleep mode ;
-
-#define APPS_RCM_GPIO_D_CLK_GATING_NU2_M \
-                                0x000000FE
-
-#define APPS_RCM_GPIO_D_CLK_GATING_NU2_S 1
-#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_RUN_CLK_ENABLE \
-                                0x00000001  // 1 - Enable GPIO_D clk during run
-                                            // mode 0 - Disable GPIO_D clk
-                                            // during run mode ;
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPIO_D_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_ENABLED_STATUS \
-                                0x00000002  // 1 - GPIO_D Clocks/Resets are
-                                            // enabled ; 0 - GPIO_D
-                                            // Clocks/Resets are disabled
-
-#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_SOFT_RESET \
-                                0x00000001  // 1 - Assert reset for GPIO_D ; 0
-                                            // - De-assert reset for GPIO_D
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPIO_E_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_DSLP_CLK_ENABLE \
-                                0x00010000  // 1 - Enable GPIO_E clk during
-                                            // deep-sleep mode 0 - Disable
-                                            // GPIO_E clk during deep-sleep mode
-                                            // ;
-
-#define APPS_RCM_GPIO_E_CLK_GATING_NU1_M \
-                                0x0000FE00
-
-#define APPS_RCM_GPIO_E_CLK_GATING_NU1_S 9
-#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_SLP_CLK_ENABLE \
-                                0x00000100  // 1 - Enable GPIO_E clk during
-                                            // sleep mode 0 - Disable GPIO_E clk
-                                            // during sleep mode ;
-
-#define APPS_RCM_GPIO_E_CLK_GATING_NU2_M \
-                                0x000000FE
-
-#define APPS_RCM_GPIO_E_CLK_GATING_NU2_S 1
-#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_RUN_CLK_ENABLE \
-                                0x00000001  // 1 - Enable GPIO_E clk during run
-                                            // mode 0 - Disable GPIO_E clk
-                                            // during run mode ;
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPIO_E_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_ENABLED_STATUS \
-                                0x00000002  // 1 - GPIO_E Clocks/Resets are
-                                            // enabled ; 0 - GPIO_E
-                                            // Clocks/Resets are disabled
-
-#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_SOFT_RESET \
-                                0x00000001  // 1 - Assert reset for GPIO_E ; 0
-                                            // - De-assert reset for GPIO_E
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_WDOG_A_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_M \
-                                0x03000000  // "00" - Sysclk ; "01" - REF_CLK
-                                            // (38.4 MHz) ; "10/11" - Slow_clk
-
-#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_S 24
-#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_DSLP_CLK_ENABLE \
-                                0x00010000  // 1 - Enable WDOG_A clk during
-                                            // deep-sleep mode 0 - Disable
-                                            // WDOG_A clk during deep-sleep mode
-                                            // ;
-
-#define APPS_RCM_WDOG_A_CLK_GATING_NU1_M \
-                                0x0000FE00
-
-#define APPS_RCM_WDOG_A_CLK_GATING_NU1_S 9
-#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_SLP_CLK_ENABLE \
-                                0x00000100  // 1 - Enable WDOG_A clk during
-                                            // sleep mode 0 - Disable WDOG_A clk
-                                            // during sleep mode ;
-
-#define APPS_RCM_WDOG_A_CLK_GATING_NU2_M \
-                                0x000000FE
-
-#define APPS_RCM_WDOG_A_CLK_GATING_NU2_S 1
-#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_RUN_CLK_ENABLE \
-                                0x00000001  // 1 - Enable WDOG_A clk during run
-                                            // mode 0 - Disable WDOG_A clk
-                                            // during run mode ;
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_WDOG_A_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_ENABLED_STATUS \
-                                0x00000002  // 1 - WDOG_A Clocks/Resets are
-                                            // enabled ; 0 - WDOG_A
-                                            // Clocks/Resets are disabled
-
-#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_SOFT_RESET \
-                                0x00000001  // 1 - Assert reset for WDOG_A ; 0
-                                            // - De-assert reset for WDOG_A
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_UART_A0_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_DSLP_CLK_ENABLE \
-                                0x00010000  // 1 - Enable UART_A0 clk during
-                                            // deep-sleep mode 0 - Disable
-                                            // UART_A0 clk during deep-sleep
-                                            // mode ;
-
-#define APPS_RCM_UART_A0_CLK_GATING_NU1_M \
-                                0x0000FE00
-
-#define APPS_RCM_UART_A0_CLK_GATING_NU1_S 9
-#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_SLP_CLK_ENABLE \
-                                0x00000100  // 1 - Enable UART_A0 clk during
-                                            // sleep mode 0 - Disable UART_A0
-                                            // clk during sleep mode ;
-
-#define APPS_RCM_UART_A0_CLK_GATING_NU2_M \
-                                0x000000FE
-
-#define APPS_RCM_UART_A0_CLK_GATING_NU2_S 1
-#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_RUN_CLK_ENABLE \
-                                0x00000001  // 1 - Enable UART_A0 clk during
-                                            // run mode 0 - Disable UART_A0 clk
-                                            // during run mode ;
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_UART_A0_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_ENABLED_STATUS \
-                                0x00000002  // 1 - UART_A0 Clocks/Resets are
-                                            // enabled ; 0 - UART_A0
-                                            // Clocks/Resets are disabled
-
-#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_SOFT_RESET \
-                                0x00000001  // 1 - Assert reset for UART_A0 ; 0
-                                            // - De-assert reset for UART_A0
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_UART_A1_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_DSLP_CLK_ENABLE \
-                                0x00010000  // 1 - Enable UART_A1 clk during
-                                            // deep-sleep mode 0 - Disable
-                                            // UART_A1 clk during deep-sleep
-                                            // mode ;
-
-#define APPS_RCM_UART_A1_CLK_GATING_NU1_M \
-                                0x0000FE00
-
-#define APPS_RCM_UART_A1_CLK_GATING_NU1_S 9
-#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_SLP_CLK_ENABLE \
-                                0x00000100  // 1 - Enable UART_A1 clk during
-                                            // sleep mode 0 - Disable UART_A1
-                                            // clk during sleep mode ;
-
-#define APPS_RCM_UART_A1_CLK_GATING_NU2_M \
-                                0x000000FE
-
-#define APPS_RCM_UART_A1_CLK_GATING_NU2_S 1
-#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_RUN_CLK_ENABLE \
-                                0x00000001  // 1 - Enable UART_A1 clk during
-                                            // run mode 0 - Disable UART_A1 clk
-                                            // during run mode ;
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_UART_A1_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_ENABLED_STATUS \
-                                0x00000002  // 1 - UART_A1 Clocks/Resets are
-                                            // enabled ; 0 - UART_A1
-                                            // Clocks/Resets are disabled
-
-#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_SOFT_RESET \
-                                0x00000001  // 1 - Assert the soft reset for
-                                            // UART_A1 ; 0 - De-assert the soft
-                                            // reset for UART_A1
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPT_A0_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_DSLP_CLK_ENABLE \
-                                0x00010000  // 1 - Enable the GPT_A0 clock
-                                            // during deep-sleep ; 0 - Disable
-                                            // the GPT_A0 clock during
-                                            // deep-sleep
-
-#define APPS_RCM_GPT_A0_CLK_GATING_NU1_M \
-                                0x0000FE00
-
-#define APPS_RCM_GPT_A0_CLK_GATING_NU1_S 9
-#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_SLP_CLK_ENABLE \
-                                0x00000100  // 1 - Enable the GPT_A0 clock
-                                            // during sleep ; 0 - Disable the
-                                            // GPT_A0 clock during sleep
-
-#define APPS_RCM_GPT_A0_CLK_GATING_NU2_M \
-                                0x000000FE
-
-#define APPS_RCM_GPT_A0_CLK_GATING_NU2_S 1
-#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_RUN_CLK_ENABLE \
-                                0x00000001  // 1 - Enable the GPT_A0 clock
-                                            // during run ; 0 - Disable the
-                                            // GPT_A0 clock during run
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPT_A0_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_ENABLED_STATUS \
-                                0x00000002  // 1 - GPT_A0 clocks/resets are
-                                            // enabled ; 0 - GPT_A0
-                                            // clocks/resets are disabled
-
-#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_SOFT_RESET \
-                                0x00000001  // 1 - Assert the soft reset for
-                                            // GPT_A0 ; 0 - De-assert the soft
-                                            // reset for GPT_A0
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPT_A1_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_DSLP_CLK_ENABLE \
-                                0x00010000  // 1 - Enable the GPT_A1 clock
-                                            // during deep-sleep ; 0 - Disable
-                                            // the GPT_A1 clock during
-                                            // deep-sleep
-
-#define APPS_RCM_GPT_A1_CLK_GATING_NU1_M \
-                                0x0000FE00
-
-#define APPS_RCM_GPT_A1_CLK_GATING_NU1_S 9
-#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_SLP_CLK_ENABLE \
-                                0x00000100  // 1 - Enable the GPT_A1 clock
-                                            // during sleep ; 0 - Disable the
-                                            // GPT_A1 clock during sleep
-
-#define APPS_RCM_GPT_A1_CLK_GATING_NU2_M \
-                                0x000000FE
-
-#define APPS_RCM_GPT_A1_CLK_GATING_NU2_S 1
-#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_RUN_CLK_ENABLE \
-                                0x00000001  // 1 - Enable the GPT_A1 clock
-                                            // during run ; 0 - Disable the
-                                            // GPT_A1 clock during run
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPT_A1_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_ENABLED_STATUS \
-                                0x00000002  // 1 - GPT_A1 clocks/resets are
-                                            // enabled ; 0 - GPT_A1
-                                            // clocks/resets are disabled
-
-#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_SOFT_RESET \
-                                0x00000001  // 1 - Assert the soft reset for
-                                            // GPT_A1 ; 0 - De-assert the soft
-                                            // reset for GPT_A1
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPT_A2_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_DSLP_CLK_ENABLE \
-                                0x00010000  // 1 - Enable the GPT_A2 clock
-                                            // during deep-sleep ; 0 - Disable
-                                            // the GPT_A2 clock during
-                                            // deep-sleep
-
-#define APPS_RCM_GPT_A2_CLK_GATING_NU1_M \
-                                0x0000FE00
-
-#define APPS_RCM_GPT_A2_CLK_GATING_NU1_S 9
-#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_SLP_CLK_ENABLE \
-                                0x00000100  // 1 - Enable the GPT_A2 clock
-                                            // during sleep ; 0 - Disable the
-                                            // GPT_A2 clock during sleep
-
-#define APPS_RCM_GPT_A2_CLK_GATING_NU2_M \
-                                0x000000FE
-
-#define APPS_RCM_GPT_A2_CLK_GATING_NU2_S 1
-#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_RUN_CLK_ENABLE \
-                                0x00000001  // 1 - Enable the GPT_A2 clock
-                                            // during run ; 0 - Disable the
-                                            // GPT_A2 clock during run
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPT_A2_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_ENABLED_STATUS \
-                                0x00000002  // 1 - GPT_A2 clocks/resets are
-                                            // enabled ; 0 - GPT_A2
-                                            // clocks/resets are disabled
-
-#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_SOFT_RESET \
-                                0x00000001  // 1 - Assert the soft reset for
-                                            // GPT_A2 ; 0 - De-assert the soft
-                                            // reset for GPT_A2
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPT_A3_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_DSLP_CLK_ENABLE \
-                                0x00010000  // 1 - Enable the GPT_A3 clock
-                                            // during deep-sleep ; 0 - Disable
-                                            // the GPT_A3 clock during
-                                            // deep-sleep
-
-#define APPS_RCM_GPT_A3_CLK_GATING_NU1_M \
-                                0x0000FE00
-
-#define APPS_RCM_GPT_A3_CLK_GATING_NU1_S 9
-#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_SLP_CLK_ENABLE \
-                                0x00000100  // 1 - Enable the GPT_A3 clock
-                                            // during sleep ; 0 - Disable the
-                                            // GPT_A3 clock during sleep
-
-#define APPS_RCM_GPT_A3_CLK_GATING_NU2_M \
-                                0x000000FE
-
-#define APPS_RCM_GPT_A3_CLK_GATING_NU2_S 1
-#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_RUN_CLK_ENABLE \
-                                0x00000001  // 1 - Enable the GPT_A3 clock
-                                            // during run ; 0 - Disable the
-                                            // GPT_A3 clock during run
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_GPT_A3_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_ENABLED_STATUS \
-                                0x00000002  // 1 - GPT_A3 Clocks/resets are
-                                            // enabled ; 0 - GPT_A3
-                                            // Clocks/resets are disabled
-
-#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_SOFT_RESET \
-                                0x00000001  // 1 - Assert the soft reset for
-                                            // GPT_A3 ; 0 - De-assert the soft
-                                            // reset for GPT_A3
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 register.
-//
-//******************************************************************************
-#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_M \
-                                0x03FF0000
-
-#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_S 16
-#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_M \
-                                0x0000FFFF
-
-#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 register.
-//
-//******************************************************************************
-#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_SOFT_RESET \
-                                0x00010000  // 1 - Assert the reset for MCASP
-                                            // Frac-clk div; 0 - Donot assert
-                                            // the reset for MCASP frac clk-div
-
-#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_M \
-                                0x000003FF
-
-#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_CRYPTO_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_DSLP_CLK_ENABLE \
-                                0x00010000  // 0 - Disable the Crypto clock
-                                            // during deep-sleep
-
-#define APPS_RCM_CRYPTO_CLK_GATING_NU1_M \
-                                0x0000FE00
-
-#define APPS_RCM_CRYPTO_CLK_GATING_NU1_S 9
-#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_SLP_CLK_ENABLE \
-                                0x00000100  // 1 - Enable the Crypto clock
-                                            // during sleep ; 0 - Disable the
-                                            // Crypto clock during sleep
-
-#define APPS_RCM_CRYPTO_CLK_GATING_NU2_M \
-                                0x000000FE
-
-#define APPS_RCM_CRYPTO_CLK_GATING_NU2_S 1
-#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_RUN_CLK_ENABLE \
-                                0x00000001  // 1 - Enable the Crypto clock
-                                            // during run ; 0 - Disable the
-                                            // Crypto clock during run
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_CRYPTO_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_ENABLED_STATUS \
-                                0x00000002  // 1 - Crypto clocks/resets are
-                                            // enabled ; 0 - Crypto
-                                            // clocks/resets are disabled
-
-#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_SOFT_RESET \
-                                0x00000001  // 1 - Assert the soft reset for
-                                            // Crypto ; 0 - De-assert the soft
-                                            // reset for Crypto
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_MCSPI_S0_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_DSLP_CLK_ENABLE \
-                                0x00010000  // 0 - Disable the MCSPI_S0 clock
-                                            // during deep-sleep
-
-#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_M \
-                                0x0000FE00
-
-#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_S 9
-#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_SLP_CLK_ENABLE \
-                                0x00000100  // 1 - Enable the MCSPI_S0 clock
-                                            // during sleep ; 0 - Disable the
-                                            // MCSPI_S0 clock during sleep
-
-#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_M \
-                                0x000000FE
-
-#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_S 1
-#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_RUN_CLK_ENABLE \
-                                0x00000001  // 1 - Enable the MCSPI_S0 clock
-                                            // during run ; 0 - Disable the
-                                            // MCSPI_S0 clock during run
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_MCSPI_S0_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_ENABLED_STATUS \
-                                0x00000002  // 1 - MCSPI_S0 Clocks/Resets are
-                                            // enabled ; 0 - MCSPI_S0
-                                            // Clocks/resets are disabled
-
-#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_SOFT_RESET \
-                                0x00000001  // 1 - Assert the soft reset for
-                                            // MCSPI_S0 ; 0 - De-assert the soft
-                                            // reset for MCSPI_S0
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_MCSPI_S0_CLKDIV_CFG register.
-//
-//******************************************************************************
-#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_BAUD_CLK_SEL \
-                                0x00010000  // 0 - XTAL clk is used as baud-clk
-                                            // for MCSPI_S0 ; 1 - PLL divclk is
-                                            // used as buad-clk for MCSPI_S0
-
-#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_M \
-                                0x0000F800
-
-#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_S 11
-#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_M \
-                                0x00000700  // Configuration of OFF-TIME for
-                                            // dividing PLL clk (240 MHz) in
-                                            // generation of MCSPI_S0 func-clk :
-                                            // "000" - 1 "001" - 2 "010" - 3
-                                            // "011" - 4 "100" - 5 "101" - 6
-                                            // "110" - 7 "111" - 8
-
-#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_S 8
-#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_M \
-                                0x000000F8
-
-#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_S 3
-#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_M \
-                                0x00000007  // Configuration of ON-TIME for
-                                            // dividing PLL clk (240 MHz) in
-                                            // generation of MCSPI_S0 func-clk :
-                                            // "000" - 1 "001" - 2 "010" - 3
-                                            // "011" - 4 "100" - 5 "101" - 6
-                                            // "110" - 7 "111" - 8
-
-#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_I2C_CLK_GATING register.
-//
-//******************************************************************************
-#define APPS_RCM_I2C_CLK_GATING_I2C_DSLP_CLK_ENABLE \
-                                0x00010000  // 1 - Enable the I2C Clock during
-                                            // deep-sleep 0 - Disable the I2C
-                                            // clock during deep-sleep
-
-#define APPS_RCM_I2C_CLK_GATING_NU1_M \
-                                0x0000FE00
-
-#define APPS_RCM_I2C_CLK_GATING_NU1_S 9
-#define APPS_RCM_I2C_CLK_GATING_I2C_SLP_CLK_ENABLE \
-                                0x00000100  // 1 - Enable the I2C clock during
-                                            // sleep ; 0 - Disable the I2C clock
-                                            // during sleep
-
-#define APPS_RCM_I2C_CLK_GATING_NU2_M \
-                                0x000000FE
-
-#define APPS_RCM_I2C_CLK_GATING_NU2_S 1
-#define APPS_RCM_I2C_CLK_GATING_I2C_RUN_CLK_ENABLE \
-                                0x00000001  // 1 - Enable the I2C clock during
-                                            // run ; 0 - Disable the I2C clock
-                                            // during run
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_I2C_SOFT_RESET register.
-//
-//******************************************************************************
-#define APPS_RCM_I2C_SOFT_RESET_I2C_ENABLED_STATUS \
-                                0x00000002  // 1 - I2C Clocks/Resets are
-                                            // enabled ; 0 - I2C clocks/resets
-                                            // are disabled
-
-#define APPS_RCM_I2C_SOFT_RESET_I2C_SOFT_RESET \
-                                0x00000001  // 1 - Assert the soft reset for
-                                            // Shared-I2C ; 0 - De-assert the
-                                            // soft reset for Shared-I2C
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_APPS_LPDS_REQ register.
-//
-//******************************************************************************
-#define APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ \
-                                0x00000001  // 1 - Request for LPDS
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_APPS_TURBO_REQ register.
-//
-//******************************************************************************
-#define APPS_RCM_APPS_TURBO_REQ_APPS_TURBO_REQ \
-                                0x00000001  // 1 - Request for TURBO
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_APPS_DSLP_WAKE_CONFIG register.
-//
-//******************************************************************************
-#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_FROM_NWP_ENABLE \
-                                0x00000002  // 1 - Enable the NWP to wake APPS
-                                            // from deep-sleep ; 0 - Disable NWP
-                                            // to wake APPS from deep-sleep
-
-#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_TIMER_ENABLE \
-                                0x00000001  // 1 - Enable deep-sleep wake timer
-                                            // in APPS RCM for deep-sleep; 0 -
-                                            // Disable deep-sleep wake timer in
-                                            // APPS RCM
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG register.
-//
-//******************************************************************************
-#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_M \
-                                0xFFFF0000  // Configuration (in slow_clks)
-                                            // which says when to request for
-                                            // OPP during deep-sleep exit
-
-#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_S 16
-#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_M \
-                                0x0000FFFF  // Configuration (in slow_clks)
-                                            // which says when to request for
-                                            // WAKE during deep-sleep exit
-
-#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE register.
-//
-//******************************************************************************
-#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_FROM_NWP_ENABLE \
-                                0x00000002  // 1- Enable the sleep wakeup due
-                                            // to NWP request. 0- Disable the
-                                            // sleep wakeup due to NWP request
-
-#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_TIMER_ENABLE \
-                                0x00000001  // 1- Enable the sleep wakeup due
-                                            // to sleep-timer; 0-Disable the
-                                            // sleep wakeup due to sleep-timer
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_APPS_SLP_WAKETIMER_CFG register.
-//
-//******************************************************************************
-#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_M \
-                                0xFFFFFFFF  // Configuration (number of
-                                            // sysclks-80MHz) for the Sleep
-                                            // wakeup timer
-
-#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST register.
-//
-//******************************************************************************
-#define APPS_RCM_APPS_TO_NWP_WAKE_REQUEST_APPS_TO_NWP_WAKEUP_REQUEST \
-                                0x00000001  // When 1 => APPS generated a wake
-                                            // request to NWP (When NWP is in
-                                            // any of its low-power modes :
-                                            // SLP/DSLP/LPDS)
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS register.
-//
-//******************************************************************************
-#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_timer_wake \
-                                0x00000008  // 1 - Indicates that deep-sleep
-                                            // timer expiry had caused the
-                                            // wakeup from deep-sleep
-
-#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_timer_wake \
-                                0x00000004  // 1 - Indicates that sleep timer
-                                            // expiry had caused the wakeup from
-                                            // sleep
-
-#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_wake_from_nwp \
-                                0x00000002  // 1 - Indicates that NWP had
-                                            // caused the wakeup from deep-sleep
-
-#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_wake_from_nwp \
-                                0x00000001  // 1 - Indicates that NWP had
-                                            // caused the wakeup from Sleep
-
-
-
-
-#endif // __HW_APPS_RCM_H__
diff --git a/cc3200/hal/inc/hw_camera.h b/cc3200/hal/inc/hw_camera.h
deleted file mode 100644
index 4461a2846..000000000
--- a/cc3200/hal/inc/hw_camera.h
+++ /dev/null
@@ -1,519 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_CAMERA_H__
-#define __HW_CAMERA_H__
-
-//*****************************************************************************
-//
-// The following are defines for the CAMERA register offsets.
-//
-//*****************************************************************************
-#define CAMERA_O_CC_REVISION    0x00000000  // This register contains the IP
-                                            // revision code ( Parallel Mode)
-#define CAMERA_O_CC_SYSCONFIG   0x00000010  // This register controls the
-                                            // various parameters of the OCP
-                                            // interface (CCP and Parallel Mode)
-#define CAMERA_O_CC_SYSSTATUS   0x00000014  // This register provides status
-                                            // information about the module
-                                            // excluding the interrupt status
-                                            // information (CCP and Parallel
-                                            // Mode)
-#define CAMERA_O_CC_IRQSTATUS   0x00000018  // The interrupt status regroups
-                                            // all the status of the module
-                                            // internal events that can generate
-                                            // an interrupt (CCP & Parallel
-                                            // Mode)
-#define CAMERA_O_CC_IRQENABLE   0x0000001C  // The interrupt enable register
-                                            // allows to enable/disable the
-                                            // module internal sources of
-                                            // interrupt on an event-by-event
-                                            // basis (CCP & Parallel Mode)
-#define CAMERA_O_CC_CTRL        0x00000040  // This register controls the
-                                            // various parameters of the Camera
-                                            // Core block (CCP & Parallel Mode)
-#define CAMERA_O_CC_CTRL_DMA    0x00000044  // This register controls the DMA
-                                            // interface of the Camera Core
-                                            // block (CCP & Parallel Mode)
-#define CAMERA_O_CC_CTRL_XCLK   0x00000048  // This register control the value
-                                            // of the clock divisor used to
-                                            // generate the external clock
-                                            // (Parallel Mode)
-#define CAMERA_O_CC_FIFO_DATA   0x0000004C  // This register allows to write to
-                                            // the FIFO and read from the FIFO
-                                            // (CCP & Parallel Mode)
-#define CAMERA_O_CC_TEST        0x00000050  // This register shows the status
-                                            // of some important variables of
-                                            // the camera core module (CCP &
-                                            // Parallel Mode)
-#define CAMERA_O_CC_GEN_PAR     0x00000054  // This register shows the values
-                                            // of the generic parameters of the
-                                            // module
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// CAMERA_O_CC_REVISION register.
-//
-//******************************************************************************
-#define CAMERA_CC_REVISION_REV_M \
-                                0x000000FF  // IP revision [7:4] Major revision
-                                            // [3:0] Minor revision Examples:
-                                            // 0x10 for 1.0 0x21 for 2.1
-
-#define CAMERA_CC_REVISION_REV_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// CAMERA_O_CC_SYSCONFIG register.
-//
-//******************************************************************************
-#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_M \
-                                0x00000018  // Slave interface power management
-                                            // req/ack control """00""
-                                            // Force-idle. An idle request is
-                                            // acknoledged unconditionally"
-                                            // """01"" No-idle. An idle request
-                                            // is never acknowledged" """10""
-                                            // reserved (Smart-idle not
-                                            // implemented)"
-
-#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_S 3
-#define CAMERA_CC_SYSCONFIG_SOFT_RESET \
-                                0x00000002  // Software reset. Set this bit to
-                                            // 1 to trigger a module reset. The
-                                            // bit is automatically reset by the
-                                            // hardware. During reset it always
-                                            // returns 0. 0 Normal mode 1 The
-                                            // module is reset
-
-#define CAMERA_CC_SYSCONFIG_AUTO_IDLE \
-                                0x00000001  // Internal OCP clock gating
-                                            // strategy 0 OCP clock is
-                                            // free-running 1 Automatic OCP
-                                            // clock gating strategy is applied
-                                            // based on the OCP interface
-                                            // activity
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// CAMERA_O_CC_SYSSTATUS register.
-//
-//******************************************************************************
-#define CAMERA_CC_SYSSTATUS_RESET_DONE2 \
-                                0x00000001  // Internal Reset Monitoring 0
-                                            // Internal module reset is on-going
-                                            // 1 Reset completed
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// CAMERA_O_CC_IRQSTATUS register.
-//
-//******************************************************************************
-#define CAMERA_CC_IRQSTATUS_FS_IRQ \
-                                0x00080000  // Frame Start has occurred 0 Event
-                                            // false "1 Event is true
-                                            // (""pending"")" 0 Event status bit
-                                            // unchanged 1 Event status bit is
-                                            // reset
-
-#define CAMERA_CC_IRQSTATUS_LE_IRQ \
-                                0x00040000  // Line End has occurred 0 Event
-                                            // false "1 Event is true
-                                            // (""pending"")" 0 Event status bit
-                                            // unchanged 1 Event status bit is
-                                            // reset
-
-#define CAMERA_CC_IRQSTATUS_LS_IRQ \
-                                0x00020000  // Line Start has occurred 0 Event
-                                            // false "1 Event is true
-                                            // (""pending"")" 0 Event status bit
-                                            // unchanged 1 Event status bit is
-                                            // reset
-
-#define CAMERA_CC_IRQSTATUS_FE_IRQ \
-                                0x00010000  // Frame End has occurred 0 Event
-                                            // false "1 Event is true
-                                            // (""pending"")" 0 Event status bit
-                                            // unchanged 1 Event status bit is
-                                            // reset
-
-#define CAMERA_CC_IRQSTATUS_FSP_ERR_IRQ \
-                                0x00000800  // FSP code error 0 Event false "1
-                                            // Event is true (""pending"")" 0
-                                            // Event status bit unchanged 1
-                                            // Event status bit is reset
-
-#define CAMERA_CC_IRQSTATUS_FW_ERR_IRQ \
-                                0x00000400  // Frame Height Error 0 Event false
-                                            // "1 Event is true (""pending"")" 0
-                                            // Event status bit unchanged 1
-                                            // Event status bit is reset
-
-#define CAMERA_CC_IRQSTATUS_FSC_ERR_IRQ \
-                                0x00000200  // False Synchronization Code 0
-                                            // Event false "1 Event is true
-                                            // (""pending"")" 0 Event status bit
-                                            // unchanged 1 Event status bit is
-                                            // reset
-
-#define CAMERA_CC_IRQSTATUS_SSC_ERR_IRQ \
-                                0x00000100  // Shifted Synchronization Code 0
-                                            // Event false "1 Event is true
-                                            // (""pending"")" 0 Event status bit
-                                            // unchanged 1 Event status bit is
-                                            // reset
-
-#define CAMERA_CC_IRQSTATUS_FIFO_NONEMPTY_IRQ \
-                                0x00000010  // FIFO is not empty 0 Event false
-                                            // "1 Event is true (""pending"")" 0
-                                            // Event status bit unchanged 1
-                                            // Event status bit is reset
-
-#define CAMERA_CC_IRQSTATUS_FIFO_FULL_IRQ \
-                                0x00000008  // FIFO is full 0 Event false "1
-                                            // Event is true (""pending"")" 0
-                                            // Event status bit unchanged 1
-                                            // Event status bit is reset
-
-#define CAMERA_CC_IRQSTATUS_FIFO_THR_IRQ \
-                                0x00000004  // FIFO threshold has been reached
-                                            // 0 Event false "1 Event is true
-                                            // (""pending"")" 0 Event status bit
-                                            // unchanged 1 Event status bit is
-                                            // reset
-
-#define CAMERA_CC_IRQSTATUS_FIFO_OF_IRQ \
-                                0x00000002  // FIFO overflow has occurred 0
-                                            // Event false "1 Event is true
-                                            // (""pending"")" 0 Event status bit
-                                            // unchanged 1 Event status bit is
-                                            // reset
-
-#define CAMERA_CC_IRQSTATUS_FIFO_UF_IRQ \
-                                0x00000001  // FIFO underflow has occurred 0
-                                            // Event false "1 Event is true
-                                            // (""pending"")" 0 Event status bit
-                                            // unchanged 1 Event status bit is
-                                            // reset
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// CAMERA_O_CC_IRQENABLE register.
-//
-//******************************************************************************
-#define CAMERA_CC_IRQENABLE_FS_IRQ_EN \
-                                0x00080000  // Frame Start Interrupt Enable 0
-                                            // Event is masked 1 Event generates
-                                            // an interrupt when it occurs
-
-#define CAMERA_CC_IRQENABLE_LE_IRQ_EN \
-                                0x00040000  // Line End Interrupt Enable 0
-                                            // Event is masked 1 Event generates
-                                            // an interrupt when it occurs
-
-#define CAMERA_CC_IRQENABLE_LS_IRQ_EN \
-                                0x00020000  // Line Start Interrupt Enable 0
-                                            // Event is masked 1 Event generates
-                                            // an interrupt when it occurs
-
-#define CAMERA_CC_IRQENABLE_FE_IRQ_EN \
-                                0x00010000  // Frame End Interrupt Enable 0
-                                            // Event is masked 1 Event generates
-                                            // an interrupt when it occurs
-
-#define CAMERA_CC_IRQENABLE_FSP_IRQ_EN \
-                                0x00000800  // FSP code Interrupt Enable 0
-                                            // Event is masked 1 Event generates
-                                            // an interrupt when it occurs
-
-#define CAMERA_CC_IRQENABLE_FW_ERR_IRQ_EN \
-                                0x00000400  // Frame Height Error Interrupt
-                                            // Enable 0 Event is masked 1 Event
-                                            // generates an interrupt when it
-                                            // occurs
-
-#define CAMERA_CC_IRQENABLE_FSC_ERR_IRQ_EN \
-                                0x00000200  // False Synchronization Code
-                                            // Interrupt Enable 0 Event is
-                                            // masked 1 Event generates an
-                                            // interrupt when it occurs
-
-#define CAMERA_CC_IRQENABLE_SSC_ERR_IRQ_EN \
-                                0x00000100  // False Synchronization Code
-                                            // Interrupt Enable 0 Event is
-                                            // masked 1 Event generates an
-                                            // interrupt when it occurs
-
-#define CAMERA_CC_IRQENABLE_FIFO_NONEMPTY_IRQ_EN \
-                                0x00000010  // FIFO Threshold Interrupt Enable
-                                            // 0 Event is masked 1 Event
-                                            // generates an interrupt when it
-                                            // occurs
-
-#define CAMERA_CC_IRQENABLE_FIFO_FULL_IRQ_EN \
-                                0x00000008  // FIFO Threshold Interrupt Enable
-                                            // 0 Event is masked 1 Event
-                                            // generates an interrupt when it
-                                            // occurs
-
-#define CAMERA_CC_IRQENABLE_FIFO_THR_IRQ_EN \
-                                0x00000004  // FIFO Threshold Interrupt Enable
-                                            // 0 Event is masked 1 Event
-                                            // generates an interrupt when it
-                                            // occurs
-
-#define CAMERA_CC_IRQENABLE_FIFO_OF_IRQ_EN \
-                                0x00000002  // FIFO Overflow Interrupt Enable 0
-                                            // Event is masked 1 Event generates
-                                            // an interrupt when it occurs
-
-#define CAMERA_CC_IRQENABLE_FIFO_UF_IRQ_EN \
-                                0x00000001  // FIFO Underflow Interrupt Enable
-                                            // 0 Event is masked 1 Event
-                                            // generates an interrupt when it
-                                            // occurs
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the CAMERA_O_CC_CTRL register.
-//
-//******************************************************************************
-#define CAMERA_CC_CTRL_CC_IF_SYNCHRO \
-                                0x00080000  // Synchronize all camera sensor
-                                            // inputs This must be set during
-                                            // the configuration phase before
-                                            // CC_EN set to '1'. This can be
-                                            // used in very high frequency to
-                                            // avoid dependancy to the IO
-                                            // timings. 0 No synchro (most of
-                                            // applications) 1 Synchro enabled
-                                            // (should never be required)
-
-#define CAMERA_CC_CTRL_CC_RST   0x00040000  // Resets all the internal finite
-                                            // states machines of the camera
-                                            // core module - by writing a 1 to
-                                            // this bit. must be applied when
-                                            // CC_EN = 0 Reads returns 0
-#define CAMERA_CC_CTRL_CC_FRAME_TRIG \
-                                0x00020000  // Set the modality in which CC_EN
-                                            // works when a disabling of the
-                                            // sensor camera core is wanted "If
-                                            // CC_FRAME_TRIG = 1 by writing
-                                            // ""0"" to CC_EN" the module is
-                                            // disabled at the end of the frame
-                                            // "If CC_FRAME_TRIG = 0 by writing
-                                            // ""0"" to CC_EN" the module is
-                                            // disabled immediately
-
-#define CAMERA_CC_CTRL_CC_EN    0x00010000  // Enables the sensor interface of
-                                            // the camera core module "By
-                                            // writing ""1"" to this field the
-                                            // module is enabled." "By writing
-                                            // ""0"" to this field the module is
-                                            // disabled at" the end of the frame
-                                            // if CC_FRAM_TRIG =1 and is
-                                            // disabled immediately if
-                                            // CC_FRAM_TRIG = 0
-#define CAMERA_CC_CTRL_NOBT_SYNCHRO \
-                                0x00002000  // Enables to start at the
-                                            // beginning of the frame or not in
-                                            // NoBT 0 Acquisition starts when
-                                            // Vertical synchro is high 1
-                                            // Acquisition starts when Vertical
-                                            // synchro goes from low to high
-                                            // (beginning of the frame) -
-                                            // Recommended.
-
-#define CAMERA_CC_CTRL_BT_CORRECT \
-                                0x00001000  // Enables the correction within
-                                            // the sync codes in BT mode 0
-                                            // correction is not enabled 1
-                                            // correction is enabled
-
-#define CAMERA_CC_CTRL_PAR_ORDERCAM \
-                                0x00000800  // Enables swap between image-data
-                                            // in parallel mode 0 swap is not
-                                            // enabled 1 swap is enabled
-
-#define CAMERA_CC_CTRL_PAR_CLK_POL \
-                                0x00000400  // Inverts the clock coming from
-                                            // the sensor in parallel mode 0
-                                            // clock not inverted - data sampled
-                                            // on rising edge 1 clock inverted -
-                                            // data sampled on falling edge
-
-#define CAMERA_CC_CTRL_NOBT_HS_POL \
-                                0x00000200  // Sets the polarity of the
-                                            // synchronization signals in NOBT
-                                            // parallel mode 0 CAM_P_HS is
-                                            // active high 1 CAM_P_HS is active
-                                            // low
-
-#define CAMERA_CC_CTRL_NOBT_VS_POL \
-                                0x00000100  // Sets the polarity of the
-                                            // synchronization signals in NOBT
-                                            // parallel mode 0 CAM_P_VS is
-                                            // active high 1 CAM_P_VS is active
-                                            // low
-
-#define CAMERA_CC_CTRL_PAR_MODE_M \
-                                0x0000000E  // Sets the Protocol Mode of the
-                                            // Camera Core module in parallel
-                                            // mode (when CCP_MODE = 0) """000""
-                                            // Parallel NOBT 8-bit" """001""
-                                            // Parallel NOBT 10-bit" """010""
-                                            // Parallel NOBT 12-bit" """011""
-                                            // reserved" """100"" Parallet BT
-                                            // 8-bit" """101"" Parallel BT
-                                            // 10-bit" """110"" reserved"
-                                            // """111"" FIFO test mode. Refer to
-                                            // Table 12 - FIFO Write and Read
-                                            // access"
-
-#define CAMERA_CC_CTRL_PAR_MODE_S 1
-#define CAMERA_CC_CTRL_CCP_MODE 0x00000001  // Set the Camera Core in CCP mode
-                                            // 0 CCP mode disabled 1 CCP mode
-                                            // enabled
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// CAMERA_O_CC_CTRL_DMA register.
-//
-//******************************************************************************
-#define CAMERA_CC_CTRL_DMA_DMA_EN \
-                                0x00000100  // Sets the number of dma request
-                                            // lines 0 DMA interface disabled
-                                            // The DMA request line stays
-                                            // inactive 1 DMA interface enabled
-                                            // The DMA request line is
-                                            // operational
-
-#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M \
-                                0x0000007F  // Sets the threshold of the FIFO
-                                            // the assertion of the dmarequest
-                                            // line takes place when the
-                                            // threshold is reached.
-                                            // """0000000"" threshold set to 1"
-                                            // """0000001"" threshold set to 2"
-                                            // … """1111111"" threshold set to
-                                            // 128"
-
-#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// CAMERA_O_CC_CTRL_XCLK register.
-//
-//******************************************************************************
-#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_M \
-                                0x0000001F  // Sets the clock divisor value for
-                                            // CAM_XCLK generation. based on
-                                            // CAM_MCK (value of CAM_MCLK is
-                                            // 96MHz) """00000"" CAM_XCLK Stable
-                                            // Low Level" Divider not enabled
-                                            // """00001"" CAM_XCLK Stable High
-                                            // Level" Divider not enabled from 2
-                                            // to 30 CAM_XCLK = CAM_MCLK /
-                                            // XCLK_DIV """11111"" Bypass -
-                                            // CAM_XCLK = CAM_MCLK"
-
-#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// CAMERA_O_CC_FIFO_DATA register.
-//
-//******************************************************************************
-#define CAMERA_CC_FIFO_DATA_FIFO_DATA_M \
-                                0xFFFFFFFF  // Writes the 32-bit word into the
-                                            // FIFO Reads the 32-bit word from
-                                            // the FIFO
-
-#define CAMERA_CC_FIFO_DATA_FIFO_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the CAMERA_O_CC_TEST register.
-//
-//******************************************************************************
-#define CAMERA_CC_TEST_FIFO_RD_POINTER_M \
-                                0xFF000000  // FIFO READ Pointer This field
-                                            // shows the value of the FIFO read
-                                            // pointer Expected value ranges
-                                            // from 0 to 127
-
-#define CAMERA_CC_TEST_FIFO_RD_POINTER_S 24
-#define CAMERA_CC_TEST_FIFO_WR_POINTER_M \
-                                0x00FF0000  // FIFO WRITE pointer This field
-                                            // shows the value of the FIFO write
-                                            // pointer Expected value ranges
-                                            // from 0 to 127
-
-#define CAMERA_CC_TEST_FIFO_WR_POINTER_S 16
-#define CAMERA_CC_TEST_FIFO_LEVEL_M \
-                                0x0000FF00  // FIFO level (how many 32-bit
-                                            // words the FIFO contains) This
-                                            // field shows the value of the FIFO
-                                            // level and can assume values from
-                                            // 0 to 128
-
-#define CAMERA_CC_TEST_FIFO_LEVEL_S 8
-#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_M \
-                                0x000000FF  // FIFO level peak This field shows
-                                            // the max value of the FIFO level
-                                            // and can assume values from 0 to
-                                            // 128
-
-#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// CAMERA_O_CC_GEN_PAR register.
-//
-//******************************************************************************
-#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_M \
-                                0x00000007  // Camera Core FIFO DEPTH generic
-                                            // parameter
-
-#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_S 0
-
-
-
-#endif // __HW_CAMERA_H__
diff --git a/cc3200/hal/inc/hw_common_reg.h b/cc3200/hal/inc/hw_common_reg.h
deleted file mode 100644
index 417544ad4..000000000
--- a/cc3200/hal/inc/hw_common_reg.h
+++ /dev/null
@@ -1,1117 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_COMMON_REG_H__
-#define __HW_COMMON_REG_H__
-
-//*****************************************************************************
-//
-// The following are defines for the COMMON_REG register offsets.
-//
-//*****************************************************************************
-#define COMMON_REG_O_I2C_Properties_Register \
-                                0x00000000
-
-#define COMMON_REG_O_SPI_Properties_Register \
-                                0x00000004
-
-#define COMMON_REG_O_APPS_sh_resource_Interrupt_enable \
-                                0x0000000C
-
-#define COMMON_REG_O_APPS_sh_resource_Interrupt_status \
-                                0x00000010
-
-#define COMMON_REG_O_NWP_sh_resource_Interrupt_enable \
-                                0x00000014
-
-#define COMMON_REG_O_NWP_sh_resource_Interrupt_status \
-                                0x00000018
-
-#define COMMON_REG_O_Flash_ctrl_reg \
-                                0x0000001C
-
-#define COMMON_REG_O_Bus_matrix_M0_segment_access_config \
-                                0x00000024
-
-#define COMMON_REG_O_Bus_matrix_M1_segment_access_config \
-                                0x00000028
-
-#define COMMON_REG_O_Bus_matrix_M2_segment_access_config \
-                                0x0000002C
-
-#define COMMON_REG_O_Bus_matrix_M3_segment_access_config \
-                                0x00000030
-
-#define COMMON_REG_O_Bus_matrix_M4_segment_access_config \
-                                0x00000034
-
-#define COMMON_REG_O_Bus_matrix_M5_segment_access_config \
-                                0x00000038
-
-#define COMMON_REG_O_GPIO_properties_register \
-                                0x0000003C
-
-#define COMMON_REG_O_APPS_NW_SEMAPHORE1 \
-                                0x00000040
-
-#define COMMON_REG_O_APPS_NW_SEMAPHORE2 \
-                                0x00000044
-
-#define COMMON_REG_O_APPS_NW_SEMAPHORE3 \
-                                0x00000048
-
-#define COMMON_REG_O_APPS_NW_SEMAPHORE4 \
-                                0x0000004C
-
-#define COMMON_REG_O_APPS_NW_SEMAPHORE5 \
-                                0x00000050
-
-#define COMMON_REG_O_APPS_NW_SEMAPHORE6 \
-                                0x00000054
-
-#define COMMON_REG_O_APPS_NW_SEMAPHORE7 \
-                                0x00000058
-
-#define COMMON_REG_O_APPS_NW_SEMAPHORE8 \
-                                0x0000005C
-
-#define COMMON_REG_O_APPS_NW_SEMAPHORE9 \
-                                0x00000060
-
-#define COMMON_REG_O_APPS_NW_SEMAPHORE10 \
-                                0x00000064
-
-#define COMMON_REG_O_APPS_NW_SEMAPHORE11 \
-                                0x00000068
-
-#define COMMON_REG_O_APPS_NW_SEMAPHORE12 \
-                                0x0000006C
-
-#define COMMON_REG_O_APPS_SEMAPPHORE_PEND \
-                                0x00000070
-
-#define COMMON_REG_O_NW_SEMAPPHORE_PEND \
-                                0x00000074
-
-#define COMMON_REG_O_SEMAPHORE_STATUS \
-                                0x00000078
-
-#define COMMON_REG_O_IDMEM_TIM_Update \
-                                0x0000007C
-
-#define COMMON_REG_O_FPGA_ROM_WR_EN \
-                                0x00000080
-
-#define COMMON_REG_O_NW_INT_MASK \
-                                0x00000084
-
-#define COMMON_REG_O_NW_INT_MASK_SET \
-                                0x00000088
-
-#define COMMON_REG_O_NW_INT_MASK_CLR \
-                                0x0000008C
-
-#define COMMON_REG_O_NW_INT_STS_CLR \
-                                0x00000090
-
-#define COMMON_REG_O_NW_INT_ACK 0x00000094
-#define COMMON_REG_O_NW_INT_TRIG \
-                                0x00000098
-
-#define COMMON_REG_O_NW_INT_STS_MASKED \
-                                0x0000009C
-
-#define COMMON_REG_O_NW_INT_STS_RAW \
-                                0x000000A0
-
-#define COMMON_REG_O_APPS_INT_MASK \
-                                0x000000A4
-
-#define COMMON_REG_O_APPS_INT_MASK_SET \
-                                0x000000A8
-
-#define COMMON_REG_O_APPS_INT_MASK_CLR \
-                                0x000000AC
-
-#define COMMON_REG_O_APPS_INT_STS_CLR \
-                                0x000000B0
-
-#define COMMON_REG_O_APPS_INT_ACK \
-                                0x000000B4
-
-#define COMMON_REG_O_APPS_INT_TRIG \
-                                0x000000B8
-
-#define COMMON_REG_O_APPS_INT_STS_MASKED \
-                                0x000000BC
-
-#define COMMON_REG_O_APPS_INT_STS_RAW \
-                                0x000000C0
-
-#define COMMON_REG_O_IDMEM_TIM_Updated \
-                                0x000000C4
-
-#define COMMON_REG_O_APPS_GPIO_TRIG_EN \
-                                0x000000C8
-
-#define COMMON_REG_O_EMU_DEBUG_REG \
-                                0x000000CC
-
-#define COMMON_REG_O_SEMAPHORE_STATUS2 \
-                                0x000000D0
-
-#define COMMON_REG_O_SEMAPHORE_PREV_OWNER1 \
-                                0x000000D4
-
-#define COMMON_REG_O_SEMAPHORE_PREV_OWNER2 \
-                                0x000000D8
-
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_I2C_Properties_Register register.
-//
-//******************************************************************************
-#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_M \
-                                0x00000003  // • Each semaphore register is of
-                                            // 2 bit. • When this register is
-                                            // set to 2’b01 – Apps have access
-                                            // and when set to 2’b10 – NW have
-                                            // access. • Ideally both the master
-                                            // can modify any of this 2 bit, but
-                                            // assumption apps will write only
-                                            // 2’b01 or 2’b00 to this register
-                                            // and nw will write only 2’b10 or
-                                            // 2’b00. • Implementation is when
-                                            // any of the bit of this register
-                                            // is set, only next write
-                                            // allowedvis 2’b00 – Again
-                                            // assumption is one master will not
-                                            // write 2’b00 if other is already
-                                            // holding the semaphore.
-
-#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_SPI_Properties_Register register.
-//
-//******************************************************************************
-#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_M \
-                                0x00000003  // • Each semaphore register is of
-                                            // 2 bit. • When this register is
-                                            // set to 2’b01 – Apps have access
-                                            // and when set to 2’b10 – NW have
-                                            // access. • Ideally both the master
-                                            // can modify any of this 2 bit, but
-                                            // assumption apps will write only
-                                            // 2’b01 or 2’b00 to this register
-                                            // and nw will write only 2’b10 or
-                                            // 2’b00. • Implementation is when
-                                            // any of the bit of this register
-                                            // is set, only next write
-                                            // allowedvis 2’b00 – Again
-                                            // assumption is one master will not
-                                            // write 2’b00 if other is already
-                                            // holding the semaphore.
-
-#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_S 0
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_sh_resource_Interrupt_enable register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_M \
-                                0x0000000F  // Interrupt enable APPS bit 0 ->
-                                            // when '1' enable I2C interrupt bit
-                                            // 1 -> when '1' enable SPI
-                                            // interrupt bit 3 ->
-                                            // when '1' enable GPIO interrupt
-
-#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_sh_resource_Interrupt_status register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_M \
-                                0x0000000F  // Interrupt enable APPS bit 0 ->
-                                            // when '1' enable I2C interrupt bit
-                                            // 1 -> when '1' enable SPI
-                                            // interrupt bit 3 ->
-                                            // when '1' enable GPIO interrupt
-
-#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_NWP_sh_resource_Interrupt_enable register.
-//
-//******************************************************************************
-#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_M \
-                                0x0000000F  // Interrupt enable NWP bit 0 ->
-                                            // when '1' enable I2C interrupt bit
-                                            // 1 -> when '1' enable SPI
-                                            // interrupt bit 3 ->
-                                            // when '1' enable GPIO interrupt
-
-#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_NWP_sh_resource_Interrupt_status register.
-//
-//******************************************************************************
-#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_M \
-                                0x0000000F  // Interrupt enable NWP bit 0 ->
-                                            // when '1' enable I2C interrupt bit
-                                            // 1 -> when '1' enable SPI
-                                            // interrupt bit 3 ->
-                                            // when '1' enable GPIO interrupt
-
-#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_Flash_ctrl_reg register.
-//
-//******************************************************************************
-#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_M \
-                                0x00000003  // • Each semaphore register is of
-                                            // 2 bit. • When this register is
-                                            // set to 2’b01 – Apps have access
-                                            // and when set to 2’b10 – NW have
-                                            // access. • Ideally both the master
-                                            // can modify any of this 2 bit, but
-                                            // assumption apps will write only
-                                            // 2’b01 or 2’b00 to this register
-                                            // and nw will write only 2’b10 or
-                                            // 2’b00. • Implementation is when
-                                            // any of the bit of this register
-                                            // is set, only next write
-                                            // allowedvis 2’b00 – Again
-                                            // assumption is one master will not
-                                            // write 2’b00 if other is already
-                                            // holding the semaphore.
-
-#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_Bus_matrix_M0_segment_access_config register.
-//
-//******************************************************************************
-#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_M \
-                                0x0003FFFF  // Master 0 control word matrix to
-                                            // each segment. Tieoff. Bit value 1
-                                            // indicates segment is accesable.
-
-#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_Bus_matrix_M1_segment_access_config register.
-//
-//******************************************************************************
-#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_M \
-                                0x0003FFFF  // Master 1 control word matrix to
-                                            // each segment. Tieoff. Bit value 1
-                                            // indicates segment is accesable.
-
-#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_Bus_matrix_M2_segment_access_config register.
-//
-//******************************************************************************
-#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_M \
-                                0x0003FFFF  // Master 2 control word matrix to
-                                            // each segment. Tieoff. Bit value 1
-                                            // indicates segment is accesable.
-
-#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_Bus_matrix_M3_segment_access_config register.
-//
-//******************************************************************************
-#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_M \
-                                0x0003FFFF  // Master 3 control word matrix to
-                                            // each segment. Tieoff. Bit value 1
-                                            // indicates segment is accesable.
-
-#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_Bus_matrix_M4_segment_access_config register.
-//
-//******************************************************************************
-#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_M \
-                                0x0003FFFF  // Master 4 control word matrix to
-                                            // each segment. Tieoff. Bit value 1
-                                            // indicates segment is accesable.
-
-#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_Bus_matrix_M5_segment_access_config register.
-//
-//******************************************************************************
-#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_M \
-                                0x0003FFFF  // Master 5 control word matrix to
-                                            // each segment. Tieoff. Bit value 1
-                                            // indicates segment is accesable.
-
-#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_GPIO_properties_register register.
-//
-//******************************************************************************
-#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_M \
-                                0x000003FF  // Shared GPIO configuration
-                                            // register. Bit [1:0] to configure
-                                            // GPIO0 Bit [3:2] to configure
-                                            // GPIO1 Bit [5:4] to configure
-                                            // GPIO2 Bit [7:6] to configure
-                                            // GPIO3 Bit [9:8] to configure
-                                            // GPIO4 each GPIO can be
-                                            // individully selected. When “00”
-                                            // GPIO is free resource. When “01”
-                                            // GPIO is APPS resource. When “10”
-                                            // GPIO is NWP resource. Writing 11
-                                            // doesnt have any affect, i.e. If
-                                            // one write only relevant gpio
-                                            // semaphore and other bits are 1s,
-                                            // it'll not disturb the other
-                                            // semaphore bits. For example : Say
-                                            // If NW wants to take control of
-                                            // gpio-1, one should write
-                                            // 10'b11_1111_1011 and if one wants
-                                            // to release it write
-                                            // 10'b11_1111_0011.
-
-#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_NW_SEMAPHORE1 register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_M \
-                                0xFFFFFFFF  // • Each semaphore register is of
-                                            // 2 bit. • When this register is
-                                            // set to 2’b01 – Apps have access
-                                            // and when set to 2’b10 – NW have
-                                            // access. • Ideally both the master
-                                            // can modify any of this 2 bit, but
-                                            // assumption apps will write only
-                                            // 2’b01 or 2’b00 to this register
-                                            // and nw will write only 2’b10 or
-                                            // 2’b00. • Implementation is when
-                                            // any of the bit of this register
-                                            // is set, only next write
-                                            // allowedvis 2’b00 – Again
-                                            // assumption is one master will not
-                                            // write 2’b00 if other is already
-                                            // holding the semaphore.
-
-#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_NW_SEMAPHORE2 register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_M \
-                                0xFFFFFFFF  // • Each semaphore register is of
-                                            // 2 bit. • When this register is
-                                            // set to 2’b01 – Apps have access
-                                            // and when set to 2’b10 – NW have
-                                            // access. • Ideally both the master
-                                            // can modify any of this 2 bit, but
-                                            // assumption apps will write only
-                                            // 2’b01 or 2’b00 to this register
-                                            // and nw will write only 2’b10 or
-                                            // 2’b00. • Implementation is when
-                                            // any of the bit of this register
-                                            // is set, only next write
-                                            // allowedvis 2’b00 – Again
-                                            // assumption is one master will not
-                                            // write 2’b00 if other is already
-                                            // holding the semaphore.
-
-#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_NW_SEMAPHORE3 register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_M \
-                                0xFFFFFFFF  // • Each semaphore register is of
-                                            // 2 bit. • When this register is
-                                            // set to 2’b01 – Apps have access
-                                            // and when set to 2’b10 – NW have
-                                            // access. • Ideally both the master
-                                            // can modify any of this 2 bit, but
-                                            // assumption apps will write only
-                                            // 2’b01 or 2’b00 to this register
-                                            // and nw will write only 2’b10 or
-                                            // 2’b00. • Implementation is when
-                                            // any of the bit of this register
-                                            // is set, only next write
-                                            // allowedvis 2’b00 – Again
-                                            // assumption is one master will not
-                                            // write 2’b00 if other is already
-                                            // holding the semaphore.
-
-#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_NW_SEMAPHORE4 register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_M \
-                                0xFFFFFFFF  // • Each semaphore register is of
-                                            // 2 bit. • When this register is
-                                            // set to 2’b01 – Apps have access
-                                            // and when set to 2’b10 – NW have
-                                            // access. • Ideally both the master
-                                            // can modify any of this 2 bit, but
-                                            // assumption apps will write only
-                                            // 2’b01 or 2’b00 to this register
-                                            // and nw will write only 2’b10 or
-                                            // 2’b00. • Implementation is when
-                                            // any of the bit of this register
-                                            // is set, only next write
-                                            // allowedvis 2’b00 – Again
-                                            // assumption is one master will not
-                                            // write 2’b00 if other is already
-                                            // holding the semaphore.
-
-#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_NW_SEMAPHORE5 register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_M \
-                                0xFFFFFFFF  // • Each semaphore register is of
-                                            // 2 bit. • When this register is
-                                            // set to 2’b01 – Apps have access
-                                            // and when set to 2’b10 – NW have
-                                            // access. • Ideally both the master
-                                            // can modify any of this 2 bit, but
-                                            // assumption apps will write only
-                                            // 2’b01 or 2’b00 to this register
-                                            // and nw will write only 2’b10 or
-                                            // 2’b00. • Implementation is when
-                                            // any of the bit of this register
-                                            // is set, only next write
-                                            // allowedvis 2’b00 – Again
-                                            // assumption is one master will not
-                                            // write 2’b00 if other is already
-                                            // holding the semaphore.
-
-#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_NW_SEMAPHORE6 register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_M \
-                                0xFFFFFFFF  // • Each semaphore register is of
-                                            // 2 bit. • When this register is
-                                            // set to 2’b01 – Apps have access
-                                            // and when set to 2’b10 – NW have
-                                            // access. • Ideally both the master
-                                            // can modify any of this 2 bit, but
-                                            // assumption apps will write only
-                                            // 2’b01 or 2’b00 to this register
-                                            // and nw will write only 2’b10 or
-                                            // 2’b00. • Implementation is when
-                                            // any of the bit of this register
-                                            // is set, only next write
-                                            // allowedvis 2’b00 – Again
-                                            // assumption is one master will not
-                                            // write 2’b00 if other is already
-                                            // holding the semaphore.
-
-#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_NW_SEMAPHORE7 register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_M \
-                                0xFFFFFFFF  // • Each semaphore register is of
-                                            // 2 bit. • When this register is
-                                            // set to 2’b01 – Apps have access
-                                            // and when set to 2’b10 – NW have
-                                            // access. • Ideally both the master
-                                            // can modify any of this 2 bit, but
-                                            // assumption apps will write only
-                                            // 2’b01 or 2’b00 to this register
-                                            // and nw will write only 2’b10 or
-                                            // 2’b00. • Implementation is when
-                                            // any of the bit of this register
-                                            // is set, only next write
-                                            // allowedvis 2’b00 – Again
-                                            // assumption is one master will not
-                                            // write 2’b00 if other is already
-                                            // holding the semaphore.
-
-#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_NW_SEMAPHORE8 register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_M \
-                                0xFFFFFFFF  // • Each semaphore register is of
-                                            // 2 bit. • When this register is
-                                            // set to 2’b01 – Apps have access
-                                            // and when set to 2’b10 – NW have
-                                            // access. • Ideally both the master
-                                            // can modify any of this 2 bit, but
-                                            // assumption apps will write only
-                                            // 2’b01 or 2’b00 to this register
-                                            // and nw will write only 2’b10 or
-                                            // 2’b00. • Implementation is when
-                                            // any of the bit of this register
-                                            // is set, only next write
-                                            // allowedvis 2’b00 – Again
-                                            // assumption is one master will not
-                                            // write 2’b00 if other is already
-                                            // holding the semaphore.
-
-#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_NW_SEMAPHORE9 register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_M \
-                                0xFFFFFFFF  // • Each semaphore register is of
-                                            // 2 bit. • When this register is
-                                            // set to 2’b01 – Apps have access
-                                            // and when set to 2’b10 – NW have
-                                            // access. • Ideally both the master
-                                            // can modify any of this 2 bit, but
-                                            // assumption apps will write only
-                                            // 2’b01 or 2’b00 to this register
-                                            // and nw will write only 2’b10 or
-                                            // 2’b00. • Implementation is when
-                                            // any of the bit of this register
-                                            // is set, only next write
-                                            // allowedvis 2’b00 – Again
-                                            // assumption is one master will not
-                                            // write 2’b00 if other is already
-                                            // holding the semaphore.
-
-#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_NW_SEMAPHORE10 register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_M \
-                                0xFFFFFFFF  // • Each semaphore register is of
-                                            // 2 bit. • When this register is
-                                            // set to 2’b01 – Apps have access
-                                            // and when set to 2’b10 – NW have
-                                            // access. • Ideally both the master
-                                            // can modify any of this 2 bit, but
-                                            // assumption apps will write only
-                                            // 2’b01 or 2’b00 to this register
-                                            // and nw will write only 2’b10 or
-                                            // 2’b00. • Implementation is when
-                                            // any of the bit of this register
-                                            // is set, only next write
-                                            // allowedvis 2’b00 – Again
-                                            // assumption is one master will not
-                                            // write 2’b00 if other is already
-                                            // holding the semaphore.
-
-#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_NW_SEMAPHORE11 register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_M \
-                                0xFFFFFFFF  // • Each semaphore register is of
-                                            // 2 bit. • When this register is
-                                            // set to 2’b01 – Apps have access
-                                            // and when set to 2’b10 – NW have
-                                            // access. • Ideally both the master
-                                            // can modify any of this 2 bit, but
-                                            // assumption apps will write only
-                                            // 2’b01 or 2’b00 to this register
-                                            // and nw will write only 2’b10 or
-                                            // 2’b00. • Implementation is when
-                                            // any of the bit of this register
-                                            // is set, only next write
-                                            // allowedvis 2’b00 – Again
-                                            // assumption is one master will not
-                                            // write 2’b00 if other is already
-                                            // holding the semaphore.
-
-#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_NW_SEMAPHORE12 register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_M \
-                                0xFFFFFFFF  // APPS NW semaphore register - not
-                                            // reflected in status.
-
-#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_SEMAPPHORE_PEND register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_M \
-                                0xFFFFFFFF  // APPS SEMAPOHORE STATUS
-
-#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_NW_SEMAPPHORE_PEND register.
-//
-//******************************************************************************
-#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_M \
-                                0xFFFFFFFF  // NW SEMAPHORE STATUS
-
-#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_SEMAPHORE_STATUS register.
-//
-//******************************************************************************
-#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_M \
-                                0xFFFFFFFF  // SEMAPHORE STATUS 9:8 :semaphore
-                                            // status of flash_control 7:6
-                                            // :semaphore status of
-                                            // gpio_properties 5:4
-                                            // :semaphore status of
-                                            // spi_propertie 1:0 :semaphore
-                                            // status of i2c_propertie
-
-#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_IDMEM_TIM_Update register.
-//
-//******************************************************************************
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_FPGA_ROM_WR_EN register.
-//
-//******************************************************************************
-#define COMMON_REG_FPGA_ROM_WR_EN_FPGA_ROM_WR_EN \
-                                0x00000001  // when '1' enables Write into
-                                            // IDMEM CORE ROM, APPS ROM, NWP ROM
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_NW_INT_MASK register.
-//
-//******************************************************************************
-#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_M \
-                                0xFFFFFFFF  // 1= disable corresponding
-                                            // interrupt;0 = interrupt enabled
-
-#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_NW_INT_MASK_SET register.
-//
-//******************************************************************************
-#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_M \
-                                0xFFFFFFFF  // write 1 to set corresponding bit
-                                            // in NW_INT_MASK;0 = no effect
-
-#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_NW_INT_MASK_CLR register.
-//
-//******************************************************************************
-#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_M \
-                                0xFFFFFFFF  // write 1 to clear corresponding
-                                            // bit in NW_INT_MASK;0 = no effect
-
-#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_NW_INT_STS_CLR register.
-//
-//******************************************************************************
-#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_M \
-                                0xFFFFFFFF  // write 1 to clear corresponding
-                                            // interrupt; 0 = no effect;
-                                            // interrupt is not lost if coincide
-                                            // with write operation
-
-#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_NW_INT_ACK register.
-//
-//******************************************************************************
-#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_M \
-                                0xFFFFFFFF  // write 1 to clear corresponding
-                                            // interrupt;0 = no effect
-
-#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_NW_INT_TRIG register.
-//
-//******************************************************************************
-#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_M \
-                                0xFFFFFFFF  // Writing a 1 to a bit in this
-                                            // register causes the the Host CPU
-                                            // if enabled (not masked). This
-                                            // register is self-clearing.
-                                            // Writing 0 has no effect
-
-#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_NW_INT_STS_MASKED register.
-//
-//******************************************************************************
-#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_M \
-                                0xFFFFFFFF  // 1= corresponding interrupt is
-                                            // active and not masked. read is
-                                            // non-destructive;0 = corresponding
-                                            // interrupt is inactive or masked
-                                            // by NW_INT mask
-
-#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_NW_INT_STS_RAW register.
-//
-//******************************************************************************
-#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_M \
-                                0xFFFFFFFF  // 1= corresponding interrupt is
-                                            // active. read is non-destructive;0
-                                            // = corresponding interrupt is
-                                            // inactive
-
-#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_INT_MASK register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_M \
-                                0xFFFFFFFF  // 1= disable corresponding
-                                            // interrupt;0 = interrupt enabled
-
-#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_INT_MASK_SET register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_M \
-                                0xFFFFFFFF  // write 1 to set corresponding bit
-                                            // in APPS_INT_MASK;0 = no effect
-
-#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_INT_MASK_CLR register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_M \
-                                0xFFFFFFFF  // write 1 to clear corresponding
-                                            // bit in APPS_INT_MASK;0 = no
-                                            // effect
-
-#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_INT_STS_CLR register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_M \
-                                0xFFFFFFFF  // write 1 to clear corresponding
-                                            // interrupt; 0 = no effect;
-                                            // interrupt is not lost if coincide
-                                            // with write operation
-
-#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_INT_ACK register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_M \
-                                0xFFFFFFFF  // write 1 to clear corresponding
-                                            // interrupt;0 = no effect
-
-#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_INT_TRIG register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_M \
-                                0xFFFFFFFF  // Writing a 1 to a bit in this
-                                            // register causes the the Host CPU
-                                            // if enabled (not masked). This
-                                            // register is self-clearing.
-                                            // Writing 0 has no effect
-
-#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_INT_STS_MASKED register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_M \
-                                0xFFFFFFFF  // 1= corresponding interrupt is
-                                            // active and not masked. read is
-                                            // non-destructive;0 = corresponding
-                                            // interrupt is inactive or masked
-                                            // by APPS_INT mask
-
-#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_INT_STS_RAW register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_M \
-                                0xFFFFFFFF  // 1= corresponding interrupt is
-                                            // active. read is non-destructive;0
-                                            // = corresponding interrupt is
-                                            // inactive
-
-#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_IDMEM_TIM_Updated register.
-//
-//******************************************************************************
-#define COMMON_REG_IDMEM_TIM_Updated_TIM_UPDATED \
-                                0x00000001  // toggle in this signal
-                                            // indicatesIDMEM_TIM_UPDATE
-                                            // register mentioned above is
-                                            // updated.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_APPS_GPIO_TRIG_EN register.
-//
-//******************************************************************************
-#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_M \
-                                0x0000001F  // APPS GPIO Trigger EN control.
-                                            // Bit 0: when '1' enable GPIO 0
-                                            // trigger. This bit enables trigger
-                                            // for all GPIO 0 pins (GPIO 0 to
-                                            // GPIO7). Bit 1: when '1' enable
-                                            // GPIO 1 trigger. This bit enables
-                                            // trigger for all GPIO 1 pins (
-                                            // GPIO8 to GPIO15). Bit 2: when '1'
-                                            // enable GPIO 2 trigger. This bit
-                                            // enables trigger for all GPIO 2
-                                            // pins (GPIO16 to GPIO23). Bit 3:
-                                            // when '1' enable GPIO 3 trigger.
-                                            // This bit enables trigger for all
-                                            // GPIO 3 pins (GPIO24 to GPIO31).
-                                            // Bit 4: when '1' enable GPIO 4
-                                            // trigger. This bit enables trigger
-                                            // for all GPIO 4 pins.(GPIO32 to
-                                            // GPIO39)
-
-#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_EMU_DEBUG_REG register.
-//
-//******************************************************************************
-#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_M \
-                                0xFFFFFFFF  // 0 th bit used for stalling APPS
-                                            // DMA and 1st bit is used for
-                                            // stalling NWP DMA for debug
-                                            // purpose. Other bits are unused.
-
-#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_SEMAPHORE_STATUS2 register.
-//
-//******************************************************************************
-#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_M \
-                                0x00FFFFFF  // SEMAPHORE STATUS 23:22
-                                            // :semaphore status of
-                                            // apps_nw_semaphore11 21:20
-                                            // :semaphore status of
-                                            // apps_nw_semaphore11 19:18
-                                            // :semaphore status of
-                                            // apps_nw_semaphore10 17:16
-                                            // :semaphore status of
-                                            // apps_nw_semaphore9 15:14
-                                            // :semaphore status of
-                                            // apps_nw_semaphore8 13:12
-                                            // :semaphore status of
-                                            // apps_nw_semaphore7 11:10
-                                            // :semaphore status of
-                                            // apps_nw_semaphore6 9:8 :semaphore
-                                            // status of apps_nw_semaphore5 7:6
-                                            // :semaphore status of
-                                            // apps_nw_semaphore4 5:4 :semaphore
-                                            // status of apps_nw_semaphore3 3:2
-                                            // :semaphore status of
-                                            // apps_nw_semaphore2 1:0 :semaphore
-                                            // status of apps_nw_semaphore1
-
-#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_SEMAPHORE_PREV_OWNER1 register.
-//
-//******************************************************************************
-#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_M \
-                                0x0003FFFF  // 1:0 : prvious owner of
-                                            // i2c_properties_reg[1:0] 3:2 :
-                                            // prvious owner of
-                                            // spi_properties_reg[1:0] 5:4 :
-                                            // prvious owner of
-                                            // gpio_properties_reg[1:0] 9:8 :
-                                            // prvious owner of
-                                            // gpio_properties_reg[3:2] 11:10 :
-                                            // prvious owner of
-                                            // gpio_properties_reg[5:4] 13:12 :
-                                            // prvious owner of
-                                            // gpio_properties_reg[7:6] 15:14 :
-                                            // prvious owner of
-                                            // gpio_properties_reg[9:8] 17:16 :
-                                            // prvious owner of
-                                            // flash_control_reg[1:0]
-
-#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// COMMON_REG_O_SEMAPHORE_PREV_OWNER2 register.
-//
-//******************************************************************************
-#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_M \
-                                0x00FFFFFF  // 1:0 : previous owner of
-                                            // apps_nw_semaphore1_reg[1:0] 3:2 :
-                                            // previous owner of
-                                            // apps_nw_semaphore2_reg[1:0] 5:4 :
-                                            // previous owner of
-                                            // apps_nw_semaphore3_reg[1:0] 7:6 :
-                                            // previous owner of
-                                            // apps_nw_semaphore4_reg[1:0] 9:8 :
-                                            // previous owner of
-                                            // apps_nw_semaphore5_reg[1:0] 11:10
-                                            // : previous owner of
-                                            // apps_nw_semaphore6_reg[1:0] 13:12
-                                            // : previous owner of
-                                            // apps_nw_semaphore7_reg[1:0] 15:14
-                                            // : previous owner of
-                                            // apps_nw_semaphore8_reg[1:0] 17:16
-                                            // : previous owner of
-                                            // apps_nw_semaphore9_reg[1:0] 19:18
-                                            // : previous owner of
-                                            // apps_nw_semaphore10_reg[1:0]
-                                            // 21:20 : previous owner of
-                                            // apps_nw_semaphore11_reg[1:0]
-                                            // 23:22 : previous owner of
-                                            // apps_nw_semaphore12_reg[1:0]
-
-#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_S 0
-
-
-
-#endif // __HW_COMMON_REG_H__
diff --git a/cc3200/hal/inc/hw_des.h b/cc3200/hal/inc/hw_des.h
deleted file mode 100644
index c3aed6562..000000000
--- a/cc3200/hal/inc/hw_des.h
+++ /dev/null
@@ -1,339 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_DES_H__
-#define __HW_DES_H__
-
-//*****************************************************************************
-//
-// The following are defines for the DES_P register offsets.
-//
-//*****************************************************************************
-#define DES_O_KEY3_L          0x00000000  // KEY3 (LSW) for 192-bit key
-#define DES_O_KEY3_H          0x00000004  // KEY3 (MSW) for 192-bit key
-#define DES_O_KEY2_L          0x00000008  // KEY2 (LSW) for 192-bit key
-#define DES_O_KEY2_H          0x0000000C  // KEY2 (MSW) for 192-bit key
-#define DES_O_KEY1_L          0x00000010  // KEY1 (LSW) for 128-bit
-                                            // key/192-bit key
-#define DES_O_KEY1_H          0x00000014  // KEY1 (LSW) for 128-bit
-                                            // key/192-bit key
-#define DES_O_IV_L            0x00000018  // Initialization vector LSW
-#define DES_O_IV_H            0x0000001C  // Initialization vector MSW
-#define DES_O_CTRL            0x00000020
-#define DES_O_LENGTH          0x00000024  // Indicates the cryptographic data
-                                            // length in bytes for all modes.
-                                            // Once processing is started with
-                                            // this context this length
-                                            // decrements to zero. Data lengths
-                                            // up to (2^32 – 1) bytes are
-                                            // allowed. A write to this register
-                                            // triggers the engine to start
-                                            // using this context. For a Host
-                                            // read operation these registers
-                                            // return all-zeroes.
-#define DES_O_DATA_L          0x00000028  // Data register(LSW) to read/write
-                                            // encrypted/decrypted data.
-#define DES_O_DATA_H          0x0000002C  // Data register(MSW) to read/write
-                                            // encrypted/decrypted data.
-#define DES_O_REVISION        0x00000030
-#define DES_O_SYSCONFIG       0x00000034
-#define DES_O_SYSSTATUS       0x00000038
-#define DES_O_IRQSTATUS       0x0000003C  // This register indicates the
-                                            // interrupt status. If one of the
-                                            // interrupt bits is set the
-                                            // interrupt output will be asserted
-#define DES_O_IRQENABLE       0x00000040  // This register contains an enable
-                                            // bit for each unique interrupt
-                                            // generated by the module. It
-                                            // matches the layout of
-                                            // DES_IRQSTATUS register. An
-                                            // interrupt is enabled when the bit
-                                            // in this register is set to 1
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DES_O_KEY3_L register.
-//
-//******************************************************************************
-#define DES_KEY3_L_KEY3_L_M   0xFFFFFFFF  // data for key3
-#define DES_KEY3_L_KEY3_L_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DES_O_KEY3_H register.
-//
-//******************************************************************************
-#define DES_KEY3_H_KEY3_H_M   0xFFFFFFFF  // data for key3
-#define DES_KEY3_H_KEY3_H_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DES_O_KEY2_L register.
-//
-//******************************************************************************
-#define DES_KEY2_L_KEY2_L_M   0xFFFFFFFF  // data for key2
-#define DES_KEY2_L_KEY2_L_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DES_O_KEY2_H register.
-//
-//******************************************************************************
-#define DES_KEY2_H_KEY2_H_M   0xFFFFFFFF  // data for key2
-#define DES_KEY2_H_KEY2_H_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DES_O_KEY1_L register.
-//
-//******************************************************************************
-#define DES_KEY1_L_KEY1_L_M   0xFFFFFFFF  // data for key1
-#define DES_KEY1_L_KEY1_L_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DES_O_KEY1_H register.
-//
-//******************************************************************************
-#define DES_KEY1_H_KEY1_H_M   0xFFFFFFFF  // data for key1
-#define DES_KEY1_H_KEY1_H_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DES_O_IV_L register.
-//
-//******************************************************************************
-#define DES_IV_L_IV_L_M       0xFFFFFFFF  // initialization vector for CBC
-                                            // CFB modes
-#define DES_IV_L_IV_L_S       0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DES_O_IV_H register.
-//
-//******************************************************************************
-#define DES_IV_H_IV_H_M       0xFFFFFFFF  // initialization vector for CBC
-                                            // CFB modes
-#define DES_IV_H_IV_H_S       0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DES_O_CTRL register.
-//
-//******************************************************************************
-#define DES_CTRL_CONTEXT      0x80000000  // If ‘1’ this read-only status bit
-                                            // indicates that the context data
-                                            // registers can be overwritten and
-                                            // the host is permitted to write
-                                            // the next context.
-#define DES_CTRL_MODE_M       0x00000030  // Select CBC ECB or CFB mode 0x0
-                                            // ecb mode 0x1 cbc mode 0x2 cfb
-                                            // mode 0x3 reserved
-#define DES_CTRL_MODE_S       4
-#define DES_CTRL_TDES         0x00000008  // Select DES or triple DES
-                                            // encryption/decryption. 0 des mode
-                                            // 1 tdes mode
-#define DES_CTRL_DIRECTION    0x00000004  // select encryption/decryption 0
-                                            // decryption is selected 1
-                                            // Encryption is selected
-#define DES_CTRL_INPUT_READY  0x00000002  // When '1' ready to
-                                            // encrypt/decrypt data
-#define DES_CTRL_OUTPUT_READY 0x00000001  // When '1' Data
-                                            // decrypted/encrypted ready
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DES_O_LENGTH register.
-//
-//******************************************************************************
-#define DES_LENGTH_LENGTH_M   0xFFFFFFFF
-#define DES_LENGTH_LENGTH_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DES_O_DATA_L register.
-//
-//******************************************************************************
-#define DES_DATA_L_DATA_L_M   0xFFFFFFFF  // data for encryption/decryption
-#define DES_DATA_L_DATA_L_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DES_O_DATA_H register.
-//
-//******************************************************************************
-#define DES_DATA_H_DATA_H_M   0xFFFFFFFF  // data for encryption/decryption
-#define DES_DATA_H_DATA_H_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DES_O_REVISION register.
-//
-//******************************************************************************
-#define DES_REVISION_SCHEME_M 0xC0000000
-#define DES_REVISION_SCHEME_S 30
-#define DES_REVISION_FUNC_M   0x0FFF0000  // Function indicates a software
-                                            // compatible module family. If
-                                            // there is no level of software
-                                            // compatibility a new Func number
-                                            // (and hence REVISION) should be
-                                            // assigned.
-#define DES_REVISION_FUNC_S   16
-#define DES_REVISION_R_RTL_M  0x0000F800  // RTL Version (R) maintained by IP
-                                            // design owner. RTL follows a
-                                            // numbering such as X.Y.R.Z which
-                                            // are explained in this table. R
-                                            // changes ONLY when: (1) PDS
-                                            // uploads occur which may have been
-                                            // due to spec changes (2) Bug fixes
-                                            // occur (3) Resets to '0' when X or
-                                            // Y changes. Design team has an
-                                            // internal 'Z' (customer invisible)
-                                            // number which increments on every
-                                            // drop that happens due to DV and
-                                            // RTL updates. Z resets to 0 when R
-                                            // increments.
-#define DES_REVISION_R_RTL_S  11
-#define DES_REVISION_X_MAJOR_M \
-                                0x00000700  // Major Revision (X) maintained by
-                                            // IP specification owner. X changes
-                                            // ONLY when: (1) There is a major
-                                            // feature addition. An example
-                                            // would be adding Master Mode to
-                                            // Utopia Level2. The Func field (or
-                                            // Class/Type in old PID format)
-                                            // will remain the same. X does NOT
-                                            // change due to: (1) Bug fixes (2)
-                                            // Change in feature parameters.
-
-#define DES_REVISION_X_MAJOR_S 8
-#define DES_REVISION_CUSTOM_M 0x000000C0
-#define DES_REVISION_CUSTOM_S 6
-#define DES_REVISION_Y_MINOR_M \
-                                0x0000003F  // Minor Revision (Y) maintained by
-                                            // IP specification owner. Y changes
-                                            // ONLY when: (1) Features are
-                                            // scaled (up or down). Flexibility
-                                            // exists in that this feature
-                                            // scalability may either be
-                                            // represented in the Y change or a
-                                            // specific register in the IP that
-                                            // indicates which features are
-                                            // exactly available. (2) When
-                                            // feature creeps from Is-Not list
-                                            // to Is list. But this may not be
-                                            // the case once it sees silicon; in
-                                            // which case X will change. Y does
-                                            // NOT change due to: (1) Bug fixes
-                                            // (2) Typos or clarifications (3)
-                                            // major functional/feature
-                                            // change/addition/deletion. Instead
-                                            // these changes may be reflected
-                                            // via R S X as applicable. Spec
-                                            // owner maintains a
-                                            // customer-invisible number 'S'
-                                            // which changes due to: (1)
-                                            // Typos/clarifications (2) Bug
-                                            // documentation. Note that this bug
-                                            // is not due to a spec change but
-                                            // due to implementation.
-                                            // Nevertheless the spec tracks the
-                                            // IP bugs. An RTL release (say for
-                                            // silicon PG1.1) that occurs due to
-                                            // bug fix should document the
-                                            // corresponding spec number (X.Y.S)
-                                            // in its release notes.
-
-#define DES_REVISION_Y_MINOR_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DES_O_SYSCONFIG register.
-//
-//******************************************************************************
-#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
-                                0x00000080  // If set to ‘1’ the DMA context
-                                            // request is enabled. 0 Dma
-                                            // disabled 1 Dma enabled
-
-#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
-                                0x00000040  // If set to ‘1’ the DMA output
-                                            // request is enabled. 0 Dma
-                                            // disabled 1 Dma enabled
-
-#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
-                                0x00000020  // If set to ‘1’ the DMA input
-                                            // request is enabled. 0 Dma
-                                            // disabled 1 Dma enabled
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DES_O_SYSSTATUS register.
-//
-//******************************************************************************
-#define DES_SYSSTATUS_RESETDONE \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DES_O_IRQSTATUS register.
-//
-//******************************************************************************
-#define DES_IRQSTATUS_DATA_OUT \
-                                0x00000004  // This bit indicates data output
-                                            // interrupt is active and triggers
-                                            // the interrupt output.
-
-#define DES_IRQSTATUS_DATA_IN 0x00000002  // This bit indicates data input
-                                            // interrupt is active and triggers
-                                            // the interrupt output.
-#define DES_IRQSTATUS_CONTEX_IN \
-                                0x00000001  // This bit indicates context
-                                            // interrupt is active and triggers
-                                            // the interrupt output.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DES_O_IRQENABLE register.
-//
-//******************************************************************************
-#define DES_IRQENABLE_M_DATA_OUT \
-                                0x00000004  // If this bit is set to ‘1’ the
-                                            // secure data output interrupt is
-                                            // enabled.
-
-#define DES_IRQENABLE_M_DATA_IN \
-                                0x00000002  // If this bit is set to ‘1’ the
-                                            // secure data input interrupt is
-                                            // enabled.
-
-#define DES_IRQENABLE_M_CONTEX_IN \
-                                0x00000001  // If this bit is set to ‘1’ the
-                                            // secure context interrupt is
-                                            // enabled.
-
-
-
-
-#endif // __HW_DES_H__
diff --git a/cc3200/hal/inc/hw_dthe.h b/cc3200/hal/inc/hw_dthe.h
deleted file mode 100644
index 1d302f426..000000000
--- a/cc3200/hal/inc/hw_dthe.h
+++ /dev/null
@@ -1,392 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-//*****************************************************************************
-
-#ifndef __HW_DTHE_H__
-#define __HW_DTHE_H__
-
-//*****************************************************************************
-//
-// The following are defines for the DTHE register offsets.
-//
-//*****************************************************************************
-#define DTHE_O_SHA_IM    0x00000810
-#define DTHE_O_SHA_RIS    0x00000814
-#define DTHE_O_SHA_MIS    0x00000818
-#define DTHE_O_SHA_IC    0x0000081C
-#define DTHE_O_AES_IM    0x00000820
-#define DTHE_O_AES_RIS    0x00000824
-#define DTHE_O_AES_MIS    0x00000828
-#define DTHE_O_AES_IC    0x0000082C
-#define DTHE_O_DES_IM    0x00000830
-#define DTHE_O_DES_RIS    0x00000834
-#define DTHE_O_DES_MIS    0x00000838
-#define DTHE_O_DES_IC    0x0000083C
-#define DTHE_O_EIP_CGCFG      0x00000A00
-#define DTHE_O_EIP_CGREQ      0x00000A04
-#define DTHE_O_CRC_CTRL       0x00000C00
-#define DTHE_O_CRC_SEED       0x00000C10
-#define DTHE_O_CRC_DIN        0x00000C14
-#define DTHE_O_CRC_RSLT_PP    0x00000C18
-#define DTHE_O_RAND_KEY0      0x00000F00
-#define DTHE_O_RAND_KEY1      0x00000F04
-#define DTHE_O_RAND_KEY2      0x00000F08
-#define DTHE_O_RAND_KEY3      0x00000F0C
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_SHAMD5_IMST register.
-//
-//******************************************************************************
-#define DTHE_SHAMD5_IMST_DIN  0x00000004  // Data in: this interrupt is
-                                            // raised when DMA writes last word
-                                            // of input data to internal FIFO of
-                                            // the engine
-#define DTHE_SHAMD5_IMST_COUT 0x00000002  // Context out: this interrupt is
-                                            // raised when DMA complets the
-                                            // output context movement from
-                                            // internal register
-#define DTHE_SHAMD5_IMST_CIN  0x00000001  // context in: this interrupt is
-                                            // raised when DMA complets Context
-                                            // write to internal register
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_SHAMD5_IRIS register.
-//
-//******************************************************************************
-#define DTHE_SHAMD5_IRIS_DIN  0x00000004  // input Data movement is done
-#define DTHE_SHAMD5_IRIS_COUT 0x00000002  // Context output is done
-#define DTHE_SHAMD5_IRIS_CIN  0x00000001  // context input is done
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_SHAMD5_IMIS register.
-//
-//******************************************************************************
-#define DTHE_SHAMD5_IMIS_DIN  0x00000004  // input Data movement is done
-#define DTHE_SHAMD5_IMIS_COUT 0x00000002  // Context output is done
-#define DTHE_SHAMD5_IMIS_CIN  0x00000001  // context input is done
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_SHAMD5_ICIS register.
-//
-//******************************************************************************
-#define DTHE_SHAMD5_ICIS_DIN  0x00000004  // Clear “input Data movement done”
-                                            // flag
-#define DTHE_SHAMD5_ICIS_COUT 0x00000002  // Clear “Context output done” flag
-#define DTHE_SHAMD5_ICIS_CIN  0x00000001  // Clear “context input done” flag
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_AES_IMST register.
-//
-//******************************************************************************
-#define DTHE_AES_IMST_DOUT 0x00000008  // Data out: this interrupt is
-                                            // raised when DMA finishes writing
-                                            // last word of the process result
-#define DTHE_AES_IMST_DIN  0x00000004  // Data in: this interrupt is
-                                            // raised when DMA writes last word
-                                            // of input data to internal FIFO of
-                                            // the engine
-#define DTHE_AES_IMST_COUT 0x00000002  // Context out: this interrupt is
-                                            // raised when DMA complets the
-                                            // output context movement from
-                                            // internal register
-#define DTHE_AES_IMST_CIN  0x00000001  // context in: this interrupt is
-                                            // raised when DMA complets Context
-                                            // write to internal register
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_AES_IRIS register.
-//
-//******************************************************************************
-#define DTHE_AES_IRIS_DOUT 0x00000008  // Output Data movement is done
-#define DTHE_AES_IRIS_DIN  0x00000004  // input Data movement is done
-#define DTHE_AES_IRIS_COUT 0x00000002  // Context output is done
-#define DTHE_AES_IRIS_CIN  0x00000001  // context input is done
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_AES_IMIS register.
-//
-//******************************************************************************
-#define DTHE_AES_IMIS_DOUT 0x00000008  // Output Data movement is done
-#define DTHE_AES_IMIS_DIN  0x00000004  // input Data movement is done
-#define DTHE_AES_IMIS_COUT 0x00000002  // Context output is done
-#define DTHE_AES_IMIS_CIN  0x00000001  // context input is done
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_AES_ICIS register.
-//
-//******************************************************************************
-#define DTHE_AES_ICIS_DOUT 0x00000008  // Clear “output Data movement
-                                            // done” flag
-#define DTHE_AES_ICIS_DIN  0x00000004  // Clear “input Data movement done”
-                                            // flag
-#define DTHE_AES_ICIS_COUT 0x00000002  // Clear “Context output done” flag
-#define DTHE_AES_ICIS_CIN  0x00000001  // Clear “context input done” flag
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_DES_IMST register.
-//
-//******************************************************************************
-#define DTHE_DES_IMST_DOUT 0x00000008  // Data out: this interrupt is
-                                            // raised when DMA finishes writing
-                                            // last word of the process result
-#define DTHE_DES_IMST_DIN  0x00000004  // Data in: this interrupt is
-                                            // raised when DMA writes last word
-                                            // of input data to internal FIFO of
-                                            // the engine
-#define DTHE_DES_IMST_CIN  0x00000001  // context in: this interrupt is
-                                            // raised when DMA complets Context
-                                            // write to internal register
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_DES_IRIS register.
-//
-//******************************************************************************
-#define DTHE_DES_IRIS_DOUT 0x00000008  // Output Data movement is done
-#define DTHE_DES_IRIS_DIN  0x00000004  // input Data movement is done
-#define DTHE_DES_IRIS_CIN  0x00000001  // context input is done
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_DES_IMIS register.
-//
-//******************************************************************************
-#define DTHE_DES_IMIS_DOUT 0x00000008  // Output Data movement is done
-#define DTHE_DES_IMIS_DIN  0x00000004  // input Data movement is done
-#define DTHE_DES_IMIS_CIN  0x00000001  // context input is done
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_DES_ICIS register.
-//
-//******************************************************************************
-#define DTHE_DES_ICIS_DOUT 0x00000008  // Clear “output Data movement
-                                            // done” flag
-#define DTHE_DES_ICIS_DIN  0x00000004  // Clear “input Data movement done”
-                                            // flag
-#define DTHE_DES_ICIS_CIN  0x00000001  // Clear "context input done” flag
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_EIP_CGCFG register.
-//
-//******************************************************************************
-#define DTHE_EIP_CGCFG_EIP29_CFG \
-                                0x00000010  // Clock gating protocol setting
-                                            // for EIP29T. 0 – Follow direct
-                                            // protocol 1 – Follow idle_req/ack
-                                            // protocol.
-
-#define DTHE_EIP_CGCFG_EIP75_CFG \
-                                0x00000008  // Clock gating protocol setting
-                                            // for EIP75T. 0 – Follow direct
-                                            // protocol 1 – Follow idle_req/ack
-                                            // protocol.
-
-#define DTHE_EIP_CGCFG_EIP16_CFG \
-                                0x00000004  // Clock gating protocol setting
-                                            // for DES. 0 – Follow direct
-                                            // protocol 1 – Follow idle_req/ack
-                                            // protocol.
-
-#define DTHE_EIP_CGCFG_EIP36_CFG \
-                                0x00000002  // Clock gating protocol setting
-                                            // for AES. 0 – Follow direct
-                                            // protocol 1 – Follow idle_req/ack
-                                            // protocol.
-
-#define DTHE_EIP_CGCFG_EIP57_CFG \
-                                0x00000001  // Clock gating protocol setting
-                                            // for SHAMD5. 0 – Follow direct
-                                            // protocol 1 – Follow idle_req/ack
-                                            // protocol.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_EIP_CGREQ register.
-//
-//******************************************************************************
-#define DTHE_EIP_CGREQ_Key_M  0xF0000000  // When “0x5” write “1” to lower
-                                            // bits [4:0] will set the bit.
-                                            // Write “0” will be ignored When
-                                            // “0x2” write “1” to lower bit
-                                            // [4:0] will clear the bit. Write
-                                            // “0” will be ignored for other key
-                                            // value, regular read write
-                                            // operation
-#define DTHE_EIP_CGREQ_Key_S  28
-#define DTHE_EIP_CGREQ_EIP29_REQ \
-                                0x00000010  // 0 – request clock gating 1 –
-                                            // request to un-gate the clock.
-
-#define DTHE_EIP_CGREQ_EIP75_REQ \
-                                0x00000008  // 0 – request clock gating 1 –
-                                            // request to un-gate the clock.
-
-#define DTHE_EIP_CGREQ_EIP16_REQ \
-                                0x00000004  // 0 – request clock gating 1 –
-                                            // request to un-gate the clock.
-
-#define DTHE_EIP_CGREQ_EIP36_REQ \
-                                0x00000002  // 0 – request clock gating 1 –
-                                            // request to un-gate the clock.
-
-#define DTHE_EIP_CGREQ_EIP57_REQ \
-                                0x00000001  // 0 – request clock gating 1 –
-                                            // request to un-gate the clock.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DTHE_O_CRC_CTRL register.
-//
-//******************************************************************************
-#define DTHE_CRC_CTRL_INIT_M  0x00006000  // Initialize the CRC 00 – use SEED
-                                            // register context as starting
-                                            // value 10 – all “zero” 11 – all
-                                            // “one” This is self clearing. With
-                                            // first write to data register this
-                                            // value clears to zero and remain
-                                            // zero for rest of the operation
-                                            // unless written again
-#define DTHE_CRC_CTRL_INIT_S  13
-#define DTHE_CRC_CTRL_SIZE    0x00001000  // Input data size 0 – 32 bit 1 – 8
-                                            // bit
-#define DTHE_CRC_CTRL_OINV    0x00000200  // Inverse the bits of result
-                                            // before storing to CRC_RSLT_PP0
-#define DTHE_CRC_CTRL_OBR     0x00000100  // Bit reverse the output result
-                                            // byte before storing to
-                                            // CRC_RSLT_PP0. applicable for all
-                                            // bytes in word
-#define DTHE_CRC_CTRL_IBR     0x00000080  // Bit reverse the input byte. For
-                                            // all bytes in word
-#define DTHE_CRC_CTRL_ENDIAN_M \
-                                0x00000030  // Endian control [0] – swap byte
-                                            // in half-word [1] – swap half word
-
-#define DTHE_CRC_CTRL_ENDIAN_S 4
-#define DTHE_CRC_CTRL_TYPE_M  0x0000000F  // Type of operation 0000 –
-                                            // polynomial 0x8005 0001 –
-                                            // polynomial 0x1021 0010 –
-                                            // polynomial 0x4C11DB7 0011 –
-                                            // polynomial 0x1EDC6F41 1000 – TCP
-                                            // checksum TYPE in DTHE_S_CRC_CTRL
-                                            // & DTHE_S_CRC_CTRL should be
-                                            // exclusive
-#define DTHE_CRC_CTRL_TYPE_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DTHE_O_CRC_SEED register.
-//
-//******************************************************************************
-#define DTHE_CRC_SEED_SEED_M  0xFFFFFFFF  // Starting seed of CRC and
-                                            // checksum operation. Please see
-                                            // CTRL register for more detail.
-                                            // This resister also holds the
-                                            // latest result of CRC or checksum
-                                            // operation
-#define DTHE_CRC_SEED_SEED_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the DTHE_O_CRC_DIN register.
-//
-//******************************************************************************
-#define DTHE_CRC_DIN_DATA_IN_M \
-                                0xFFFFFFFF  // Input data for CRC or checksum
-                                            // operation
-
-#define DTHE_CRC_DIN_DATA_IN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_CRC_RSLT_PP register.
-//
-//******************************************************************************
-#define DTHE_CRC_RSLT_PP_RSLT_PP_M \
-                                0xFFFFFFFF  // Input data for CRC or checksum
-                                            // operation
-
-#define DTHE_CRC_RSLT_PP_RSLT_PP_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_RAND_KEY0 register.
-//
-//******************************************************************************
-#define DTHE_RAND_KEY0_KEY_M  0xFFFFFFFF  // Device Specific Randon key
-                                            // [31:0]
-#define DTHE_RAND_KEY0_KEY_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_RAND_KEY1 register.
-//
-//******************************************************************************
-#define DTHE_RAND_KEY1_KEY_M  0xFFFFFFFF  // Device Specific Randon key
-                                            // [63:32]
-#define DTHE_RAND_KEY1_KEY_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_RAND_KEY2 register.
-//
-//******************************************************************************
-#define DTHE_RAND_KEY2_KEY_M  0xFFFFFFFF  // Device Specific Randon key
-                                            // [95:34]
-#define DTHE_RAND_KEY2_KEY_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// DTHE_O_RAND_KEY3 register.
-//
-//******************************************************************************
-#define DTHE_RAND_KEY3_KEY_M  0xFFFFFFFF  // Device Specific Randon key
-                                            // [127:96]
-#define DTHE_RAND_KEY3_KEY_S  0
-
-
-
-#endif // __HW_DTHE_H__
diff --git a/cc3200/hal/inc/hw_flash_ctrl.h b/cc3200/hal/inc/hw_flash_ctrl.h
deleted file mode 100644
index b57044aa1..000000000
--- a/cc3200/hal/inc/hw_flash_ctrl.h
+++ /dev/null
@@ -1,1862 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_FLASH_CTRL_H__
-#define __HW_FLASH_CTRL_H__
-
-//*****************************************************************************
-//
-// The following are defines for the FLASH_CTRL register offsets.
-//
-//*****************************************************************************
-#define FLASH_CTRL_O_FMA        0x00000000  // Flash Memory Address (FMA)
-                                            // offset 0x000 During a write
-                                            // operation this register contains
-                                            // a 4-byte-aligned address and
-                                            // specifies where the data is
-                                            // written. During erase operations
-                                            // this register contains a 1
-                                            // KB-aligned CPU byte address and
-                                            // specifies which block is erased.
-                                            // Note that the alignment
-                                            // requirements must be met by
-                                            // software or the results of the
-                                            // operation are unpredictable.
-#define FLASH_CTRL_O_FMD        0x00000004  // Flash Memory Data (FMD) offset
-                                            // 0x004 This register contains the
-                                            // data to be written during the
-                                            // programming cycle or read during
-                                            // the read cycle. Note that the
-                                            // contents of this register are
-                                            // undefined for a read access of an
-                                            // execute-only block. This register
-                                            // is not used during erase cycles.
-#define FLASH_CTRL_O_FMC        0x00000008  // Flash Memory Control (FMC)
-                                            // offset 0x008 When this register
-                                            // is written the Flash memory
-                                            // controller initiates the
-                                            // appropriate access cycle for the
-                                            // location specified by the Flash
-                                            // Memory Address (FMA) register .
-                                            // If the access is a write access
-                                            // the data contained in the Flash
-                                            // Memory Data (FMD) register is
-                                            // written to the specified address.
-                                            // This register must be the final
-                                            // register written and initiates
-                                            // the memory operation. The four
-                                            // control bits in the lower byte of
-                                            // this register are used to
-                                            // initiate memory operations.
-#define FLASH_CTRL_O_FCRIS      0x0000000C  // Flash Controller Raw Interrupt
-                                            // Status (FCRIS) offset 0x00C This
-                                            // register indicates that the Flash
-                                            // memory controller has an
-                                            // interrupt condition. An interrupt
-                                            // is sent to the interrupt
-                                            // controller only if the
-                                            // corresponding FCIM register bit
-                                            // is set.
-#define FLASH_CTRL_O_FCIM       0x00000010  // Flash Controller Interrupt Mask
-                                            // (FCIM) offset 0x010 This register
-                                            // controls whether the Flash memory
-                                            // controller generates interrupts
-                                            // to the controller.
-#define FLASH_CTRL_O_FCMISC     0x00000014  // Flash Controller Masked
-                                            // Interrupt Status and Clear
-                                            // (FCMISC) offset 0x014 This
-                                            // register provides two functions.
-                                            // First it reports the cause of an
-                                            // interrupt by indicating which
-                                            // interrupt source or sources are
-                                            // signalling the interrupt. Second
-                                            // it serves as the method to clear
-                                            // the interrupt reporting.
-#define FLASH_CTRL_O_FMC2       0x00000020  // Flash Memory Control 2 (FMC2)
-                                            // offset 0x020 When this register
-                                            // is written the Flash memory
-                                            // controller initiates the
-                                            // appropriate access cycle for the
-                                            // location specified by the Flash
-                                            // Memory Address (FMA) register .
-                                            // If the access is a write access
-                                            // the data contained in the Flash
-                                            // Write Buffer (FWB) registers is
-                                            // written. This register must be
-                                            // the final register written as it
-                                            // initiates the memory operation.
-#define FLASH_CTRL_O_FWBVAL     0x00000030  // Flash Write Buffer Valid
-                                            // (FWBVAL) offset 0x030 This
-                                            // register provides a bitwise
-                                            // status of which FWBn registers
-                                            // have been written by the
-                                            // processor since the last write of
-                                            // the Flash memory write buffer.
-                                            // The entries with a 1 are written
-                                            // on the next write of the Flash
-                                            // memory write buffer. This
-                                            // register is cleared after the
-                                            // write operation by hardware. A
-                                            // protection violation on the write
-                                            // operation also clears this
-                                            // status. Software can program the
-                                            // same 32 words to various Flash
-                                            // memory locations by setting the
-                                            // FWB[n] bits after they are
-                                            // cleared by the write operation.
-                                            // The next write operation then
-                                            // uses the same data as the
-                                            // previous one. In addition if a
-                                            // FWBn register change should not
-                                            // be written to Flash memory
-                                            // software can clear the
-                                            // corresponding FWB[n] bit to
-                                            // preserve the existing data when
-                                            // the next write operation occurs.
-#define FLASH_CTRL_O_FWB1       0x00000100  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB2       0x00000104  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB3       0x00000108  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB4       0x0000010C  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB5       0x00000110  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB6       0x00000114  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB7       0x00000118  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB8       0x0000011C  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB9       0x00000120  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB10      0x00000124  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB11      0x00000128  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB12      0x0000012C  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB13      0x00000130  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB14      0x00000134  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB15      0x00000138  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB16      0x0000013C  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB17      0x00000140  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB18      0x00000144  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB19      0x00000148  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB20      0x0000014C  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB21      0x00000150  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB22      0x00000154  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB23      0x00000158  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB24      0x0000015C  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB25      0x00000160  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB26      0x00000164  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB27      0x00000168  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB28      0x0000016C  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB29      0x00000170  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB30      0x00000174  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB31      0x00000178  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FWB32      0x0000017C  // Flash Write Buffer n (FWBn)
-                                            // offset 0x100 - 0x17C These 32
-                                            // registers hold the contents of
-                                            // the data to be written into the
-                                            // Flash memory on a buffered Flash
-                                            // memory write operation. The
-                                            // offset selects one of the 32-bit
-                                            // registers. Only FWBn registers
-                                            // that have been updated since the
-                                            // preceding buffered Flash memory
-                                            // write operation are written into
-                                            // the Flash memory so it is not
-                                            // necessary to write the entire
-                                            // bank of registers in order to
-                                            // write 1 or 2 words. The FWBn
-                                            // registers are written into the
-                                            // Flash memory with the FWB0
-                                            // register corresponding to the
-                                            // address contained in FMA. FWB1 is
-                                            // written to the address FMA+0x4
-                                            // etc. Note that only data bits
-                                            // that are 0 result in the Flash
-                                            // memory being modified. A data bit
-                                            // that is 1 leaves the content of
-                                            // the Flash memory bit at its
-                                            // previous value.
-#define FLASH_CTRL_O_FSIZE      0x00000FC0  // Flash Size (FSIZE) offset 0xFC0
-                                            // This register indicates the size
-                                            // of the on-chip Flash memory.
-                                            // Important: This register should
-                                            // be used to determine the size of
-                                            // the Flash memory that is
-                                            // implemented on this
-                                            // microcontroller. However to
-                                            // support legacy software the DC0
-                                            // register is available. A read of
-                                            // the DC0 register correctly
-                                            // identifies legacy memory sizes.
-                                            // Software must use the FSIZE
-                                            // register for memory sizes that
-                                            // are not listed in the DC0
-                                            // register description.
-#define FLASH_CTRL_O_SSIZE      0x00000FC4  // SRAM Size (SSIZE) offset 0xFC4
-                                            // This register indicates the size
-                                            // of the on-chip SRAM. Important:
-                                            // This register should be used to
-                                            // determine the size of the SRAM
-                                            // that is implemented on this
-                                            // microcontroller. However to
-                                            // support legacy software the DC0
-                                            // register is available. A read of
-                                            // the DC0 register correctly
-                                            // identifies legacy memory sizes.
-                                            // Software must use the SSIZE
-                                            // register for memory sizes that
-                                            // are not listed in the DC0
-                                            // register description.
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_CTRL_O_FMA register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FMA_OFFSET_M 0x0003FFFF  // Address Offset Address offset in
-                                            // Flash memory where operation is
-                                            // performed except for nonvolatile
-                                            // registers
-#define FLASH_CTRL_FMA_OFFSET_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_CTRL_O_FMD register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FMD_DATA_M   0xFFFFFFFF  // Data Value Data value for write
-                                            // operation.
-#define FLASH_CTRL_FMD_DATA_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_CTRL_O_FMC register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FMC_WRKEY_M  0xFFFF0000  // Flash Memory Write Key This
-                                            // field contains a write key which
-                                            // is used to minimize the incidence
-                                            // of accidental Flash memory
-                                            // writes. The value 0xA442 must be
-                                            // written into this field for a
-                                            // Flash memory write to occur.
-                                            // Writes to the FMC register
-                                            // without this WRKEY value are
-                                            // ignored. A read of this field
-                                            // returns the value 0.
-#define FLASH_CTRL_FMC_WRKEY_S  16
-#define FLASH_CTRL_FMC_COMT     0x00000008  // Commit Register Value This bit
-                                            // is used to commit writes to
-                                            // Flash-memory-resident registers
-                                            // and to monitor the progress of
-                                            // that process. Value Description 1
-                                            // Set this bit to commit (write)
-                                            // the register value to a
-                                            // Flash-memory-resident register.
-                                            // When read a 1 indicates that the
-                                            // previous commit access is not
-                                            // complete. 0 A write of 0 has no
-                                            // effect on the state of this bit.
-                                            // When read a 0 indicates that the
-                                            // previous commit access is
-                                            // complete.
-#define FLASH_CTRL_FMC_MERASE1  0x00000004  // Mass Erase Flash Memory This bit
-                                            // is used to mass erase the Flash
-                                            // main memory and to monitor the
-                                            // progress of that process. Value
-                                            // Description 1 Set this bit to
-                                            // erase the Flash main memory. When
-                                            // read a 1 indicates that the
-                                            // previous mass erase access is not
-                                            // complete. 0 A write of 0 has no
-                                            // effect on the state of this bit.
-                                            // When read a 0 indicates that the
-                                            // previous mass erase access is
-                                            // complete.
-#define FLASH_CTRL_FMC_ERASE    0x00000002  // Erase a Page of Flash Memory
-                                            // This bit is used to erase a page
-                                            // of Flash memory and to monitor
-                                            // the progress of that process.
-                                            // Value Description 1 Set this bit
-                                            // to erase the Flash memory page
-                                            // specified by the contents of the
-                                            // FMA register. When read a 1
-                                            // indicates that the previous page
-                                            // erase access is not complete. 0 A
-                                            // write of 0 has no effect on the
-                                            // state of this bit. When read a 0
-                                            // indicates that the previous page
-                                            // erase access is complete.
-#define FLASH_CTRL_FMC_WRITE    0x00000001  // Write a Word into Flash Memory
-                                            // This bit is used to write a word
-                                            // into Flash memory and to monitor
-                                            // the progress of that process.
-                                            // Value Description 1 Set this bit
-                                            // to write the data stored in the
-                                            // FMD register into the Flash
-                                            // memory location specified by the
-                                            // contents of the FMA register.
-                                            // When read a 1 indicates that the
-                                            // write update access is not
-                                            // complete. 0 A write of 0 has no
-                                            // effect on the state of this bit.
-                                            // When read a 0 indicates that the
-                                            // previous write update access is
-                                            // complete.
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FCRIS register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FCRIS_PROGRIS \
-                                0x00002000  // Program Verify Error Raw
-                                            // Interrupt Status Value
-                                            // Description 1 An interrupt is
-                                            // pending because the verify of a
-                                            // PROGRAM operation failed. 0 An
-                                            // interrupt has not occurred. This
-                                            // bit is cleared by writing a 1 to
-                                            // the PROGMISC bit in the FCMISC
-                                            // register.
-
-#define FLASH_CTRL_FCRIS_ERRIS  0x00000800  // Erase Verify Error Raw Interrupt
-                                            // Status Value Description 1 An
-                                            // interrupt is pending because the
-                                            // verify of an ERASE operation
-                                            // failed. 0 An interrupt has not
-                                            // occurred. This bit is cleared by
-                                            // writing a 1 to the ERMISC bit in
-                                            // the FCMISC register.
-#define FLASH_CTRL_FCRIS_INVDRIS \
-                                0x00000400  // Invalid Data Raw Interrupt
-                                            // Status Value Description 1 An
-                                            // interrupt is pending because a
-                                            // bit that was previously
-                                            // programmed as a 0 is now being
-                                            // requested to be programmed as a
-                                            // 1. 0 An interrupt has not
-                                            // occurred. This bit is cleared by
-                                            // writing a 1 to the INVMISC bit in
-                                            // the FCMISC register.
-
-#define FLASH_CTRL_FCRIS_VOLTRIS \
-                                0x00000200  // Pump Voltage Raw Interrupt
-                                            // Status Value Description 1 An
-                                            // interrupt is pending because the
-                                            // regulated voltage of the pump
-                                            // went out of spec during the Flash
-                                            // operation and the operation was
-                                            // terminated. 0 An interrupt has
-                                            // not occurred. This bit is cleared
-                                            // by writing a 1 to the VOLTMISC
-                                            // bit in the FCMISC register.
-
-#define FLASH_CTRL_FCRIS_ERIS   0x00000004  // EEPROM Raw Interrupt Status This
-                                            // bit provides status EEPROM
-                                            // operation. Value Description 1 An
-                                            // EEPROM interrupt has occurred. 0
-                                            // An EEPROM interrupt has not
-                                            // occurred. This bit is cleared by
-                                            // writing a 1 to the EMISC bit in
-                                            // the FCMISC register.
-#define FLASH_CTRL_FCRIS_PRIS   0x00000002  // Programming Raw Interrupt Status
-                                            // This bit provides status on
-                                            // programming cycles which are
-                                            // write or erase actions generated
-                                            // through the FMC or FMC2 register
-                                            // bits (see page 537 and page 549).
-                                            // Value Description 1 The
-                                            // programming or erase cycle has
-                                            // completed. 0 The programming or
-                                            // erase cycle has not completed.
-                                            // This status is sent to the
-                                            // interrupt controller when the
-                                            // PMASK bit in the FCIM register is
-                                            // set. This bit is cleared by
-                                            // writing a 1 to the PMISC bit in
-                                            // the FCMISC register.
-#define FLASH_CTRL_FCRIS_ARIS   0x00000001  // Access Raw Interrupt Status
-                                            // Value Description 1 A program or
-                                            // erase action was attempted on a
-                                            // block of Flash memory that
-                                            // contradicts the protection policy
-                                            // for that block as set in the
-                                            // FMPPEn registers. 0 No access has
-                                            // tried to improperly program or
-                                            // erase the Flash memory. This
-                                            // status is sent to the interrupt
-                                            // controller when the AMASK bit in
-                                            // the FCIM register is set. This
-                                            // bit is cleared by writing a 1 to
-                                            // the AMISC bit in the FCMISC
-                                            // register.
-//******************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_CTRL_O_FCIM register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FCIM_ILLMASK 0x00004000  // Illegal Address Interrupt Mask
-                                            // Value Description 1 An interrupt
-                                            // is sent to the interrupt
-                                            // controller when the ILLARIS bit
-                                            // is set. 0 The ILLARIS interrupt
-                                            // is suppressed and not sent to the
-                                            // interrupt controller.
-#define FLASH_CTRL_FCIM_PROGMASK \
-                                0x00002000  // PROGVER Interrupt Mask Value
-                                            // Description 1 An interrupt is
-                                            // sent to the interrupt controller
-                                            // when the PROGRIS bit is set. 0
-                                            // The PROGRIS interrupt is
-                                            // suppressed and not sent to the
-                                            // interrupt controller.
-
-#define FLASH_CTRL_FCIM_PREMASK 0x00001000  // PREVER Interrupt Mask Value
-                                            // Description 1 An interrupt is
-                                            // sent to the interrupt controller
-                                            // when the PRERIS bit is set. 0 The
-                                            // PRERIS interrupt is suppressed
-                                            // and not sent to the interrupt
-                                            // controller.
-#define FLASH_CTRL_FCIM_ERMASK  0x00000800  // ERVER Interrupt Mask Value
-                                            // Description 1 An interrupt is
-                                            // sent to the interrupt controller
-                                            // when the ERRIS bit is set. 0 The
-                                            // ERRIS interrupt is suppressed and
-                                            // not sent to the interrupt
-                                            // controller.
-#define FLASH_CTRL_FCIM_INVDMASK \
-                                0x00000400  // Invalid Data Interrupt Mask
-                                            // Value Description 1 An interrupt
-                                            // is sent to the interrupt
-                                            // controller when the INVDRIS bit
-                                            // is set. 0 The INVDRIS interrupt
-                                            // is suppressed and not sent to the
-                                            // interrupt controller.
-
-#define FLASH_CTRL_FCIM_VOLTMASK \
-                                0x00000200  // VOLT Interrupt Mask Value
-                                            // Description 1 An interrupt is
-                                            // sent to the interrupt controller
-                                            // when the VOLTRIS bit is set. 0
-                                            // The VOLTRIS interrupt is
-                                            // suppressed and not sent to the
-                                            // interrupt controller.
-
-#define FLASH_CTRL_FCIM_LOCKMASK \
-                                0x00000100  // LOCK Interrupt Mask Value
-                                            // Description 1 An interrupt is
-                                            // sent to the interrupt controller
-                                            // when the LOCKRIS bit is set. 0
-                                            // The LOCKRIS interrupt is
-                                            // suppressed and not sent to the
-                                            // interrupt controller.
-
-#define FLASH_CTRL_FCIM_EMASK   0x00000004  // EEPROM Interrupt Mask Value
-                                            // Description 1 An interrupt is
-                                            // sent to the interrupt controller
-                                            // when the ERIS bit is set. 0 The
-                                            // ERIS interrupt is suppressed and
-                                            // not sent to the interrupt
-                                            // controller.
-#define FLASH_CTRL_FCIM_PMASK   0x00000002  // Programming Interrupt Mask This
-                                            // bit controls the reporting of the
-                                            // programming raw interrupt status
-                                            // to the interrupt controller.
-                                            // Value Description 1 An interrupt
-                                            // is sent to the interrupt
-                                            // controller when the PRIS bit is
-                                            // set. 0 The PRIS interrupt is
-                                            // suppressed and not sent to the
-                                            // interrupt controller.
-#define FLASH_CTRL_FCIM_AMASK   0x00000001  // Access Interrupt Mask This bit
-                                            // controls the reporting of the
-                                            // access raw interrupt status to
-                                            // the interrupt controller. Value
-                                            // Description 1 An interrupt is
-                                            // sent to the interrupt controller
-                                            // when the ARIS bit is set. 0 The
-                                            // ARIS interrupt is suppressed and
-                                            // not sent to the interrupt
-                                            // controller.
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FCMISC register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FCMISC_ILLMISC \
-                                0x00004000  // Illegal Address Masked Interrupt
-                                            // Status and Clear Value
-                                            // Description 1 When read a 1
-                                            // indicates that an unmasked
-                                            // interrupt was signaled. Writing a
-                                            // 1 to this bit clears ILLAMISC and
-                                            // also the ILLARIS bit in the FCRIS
-                                            // register (see page 540). 0 When
-                                            // read a 0 indicates that an
-                                            // interrupt has not occurred. A
-                                            // write of 0 has no effect on the
-                                            // state of this bit.
-
-#define FLASH_CTRL_FCMISC_PROGMISC \
-                                0x00002000  // PROGVER Masked Interrupt Status
-                                            // and Clear Value Description 1
-                                            // When read a 1 indicates that an
-                                            // unmasked interrupt was signaled.
-                                            // Writing a 1 to this bit clears
-                                            // PROGMISC and also the PROGRIS bit
-                                            // in the FCRIS register (see page
-                                            // 540). 0 When read a 0 indicates
-                                            // that an interrupt has not
-                                            // occurred. A write of 0 has no
-                                            // effect on the state of this bit.
-
-#define FLASH_CTRL_FCMISC_PREMISC \
-                                0x00001000  // PREVER Masked Interrupt Status
-                                            // and Clear Value Description 1
-                                            // When read a 1 indicates that an
-                                            // unmasked interrupt was signaled.
-                                            // Writing a 1 to this bit clears
-                                            // PREMISC and also the PRERIS bit
-                                            // in the FCRIS register . 0 When
-                                            // read a 0 indicates that an
-                                            // interrupt has not occurred. A
-                                            // write of 0 has no effect on the
-                                            // state of this bit.
-
-#define FLASH_CTRL_FCMISC_ERMISC \
-                                0x00000800  // ERVER Masked Interrupt Status
-                                            // and Clear Value Description 1
-                                            // When read a 1 indicates that an
-                                            // unmasked interrupt was signaled.
-                                            // Writing a 1 to this bit clears
-                                            // ERMISC and also the ERRIS bit in
-                                            // the FCRIS register 0 When read a
-                                            // 0 indicates that an interrupt has
-                                            // not occurred. A write of 0 has no
-                                            // effect on the state of this bit.
-
-#define FLASH_CTRL_FCMISC_INVDMISC \
-                                0x00000400  // Invalid Data Masked Interrupt
-                                            // Status and Clear Value
-                                            // Description 1 When read a 1
-                                            // indicates that an unmasked
-                                            // interrupt was signaled. Writing a
-                                            // 1 to this bit clears INVDMISC and
-                                            // also the INVDRIS bit in the FCRIS
-                                            // register (see page 540). 0 When
-                                            // read a 0 indicates that an
-                                            // interrupt has not occurred. A
-                                            // write of 0 has no effect on the
-                                            // state of this bit.
-
-#define FLASH_CTRL_FCMISC_VOLTMISC \
-                                0x00000200  // VOLT Masked Interrupt Status and
-                                            // Clear Value Description 1 When
-                                            // read a 1 indicates that an
-                                            // unmasked interrupt was signaled.
-                                            // Writing a 1 to this bit clears
-                                            // VOLTMISC and also the VOLTRIS bit
-                                            // in the FCRIS register (see page
-                                            // 540). 0 When read a 0 indicates
-                                            // that an interrupt has not
-                                            // occurred. A write of 0 has no
-                                            // effect on the state of this bit.
-
-#define FLASH_CTRL_FCMISC_LOCKMISC \
-                                0x00000100  // LOCK Masked Interrupt Status and
-                                            // Clear Value Description 1 When
-                                            // read a 1 indicates that an
-                                            // unmasked interrupt was signaled.
-                                            // Writing a 1 to this bit clears
-                                            // LOCKMISC and also the LOCKRIS bit
-                                            // in the FCRIS register (see page
-                                            // 540). 0 When read a 0 indicates
-                                            // that an interrupt has not
-                                            // occurred. A write of 0 has no
-                                            // effect on the state of this bit.
-
-#define FLASH_CTRL_FCMISC_EMISC 0x00000004  // EEPROM Masked Interrupt Status
-                                            // and Clear Value Description 1
-                                            // When read a 1 indicates that an
-                                            // unmasked interrupt was signaled.
-                                            // Writing a 1 to this bit clears
-                                            // EMISC and also the ERIS bit in
-                                            // the FCRIS register 0 When read a
-                                            // 0 indicates that an interrupt has
-                                            // not occurred. A write of 0 has no
-                                            // effect on the state of this bit.
-#define FLASH_CTRL_FCMISC_PMISC 0x00000002  // Programming Masked Interrupt
-                                            // Status and Clear Value
-                                            // Description 1 When read a 1
-                                            // indicates that an unmasked
-                                            // interrupt was signaled because a
-                                            // programming cycle completed.
-                                            // Writing a 1 to this bit clears
-                                            // PMISC and also the PRIS bit in
-                                            // the FCRIS register 0 When read a
-                                            // 0 indicates that a programming
-                                            // cycle complete interrupt has not
-                                            // occurred. A write of 0 has no
-                                            // effect on the state of this bit.
-#define FLASH_CTRL_FCMISC_AMISC 0x00000001  // Access Masked Interrupt Status
-                                            // and Clear Value Description 1
-                                            // When read a 1 indicates that an
-                                            // unmasked interrupt was signaled
-                                            // because a program or erase action
-                                            // was attempted on a block of Flash
-                                            // memory that contradicts the
-                                            // protection policy for that block
-                                            // as set in the FMPPEn registers.
-                                            // Writing a 1 to this bit clears
-                                            // AMISC and also the ARIS bit in
-                                            // the FCRIS register 0 When read a
-                                            // 0 indicates that no improper
-                                            // accesses have occurred. A write
-                                            // of 0 has no effect on the state
-                                            // of this bit.
-//******************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_CTRL_O_FMC2 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FMC2_WRKEY_M 0xFFFF0000  // Flash Memory Write Key This
-                                            // field contains a write key which
-                                            // is used to minimize the incidence
-                                            // of accidental Flash memory
-                                            // writes. The value 0xA442 must be
-                                            // written into this field for a
-                                            // write to occur. Writes to the
-                                            // FMC2 register without this WRKEY
-                                            // value are ignored. A read of this
-                                            // field returns the value 0.
-#define FLASH_CTRL_FMC2_WRKEY_S 16
-#define FLASH_CTRL_FMC2_WRBUF   0x00000001  // Buffered Flash Memory Write This
-                                            // bit is used to start a buffered
-                                            // write to Flash memory. Value
-                                            // Description 1 Set this bit to
-                                            // write the data stored in the FWBn
-                                            // registers to the location
-                                            // specified by the contents of the
-                                            // FMA register. When read a 1
-                                            // indicates that the previous
-                                            // buffered Flash memory write
-                                            // access is not complete. 0 A write
-                                            // of 0 has no effect on the state
-                                            // of this bit. When read a 0
-                                            // indicates that the previous
-                                            // buffered Flash memory write
-                                            // access is complete.
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWBVAL register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWBVAL_FWBN_M \
-                                0xFFFFFFFF  // Flash Memory Write Buffer Value
-                                            // Description 1 The corresponding
-                                            // FWBn register has been updated
-                                            // since the last buffer write
-                                            // operation and is ready to be
-                                            // written to Flash memory. 0 The
-                                            // corresponding FWBn register has
-                                            // no new data to be written. Bit 0
-                                            // corresponds to FWB0 offset 0x100
-                                            // and bit 31 corresponds to FWB31
-                                            // offset 0x13C.
-
-#define FLASH_CTRL_FWBVAL_FWBN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_CTRL_O_FWB1 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB1_DATA_M  0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB1_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_CTRL_O_FWB2 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB2_DATA_M  0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB2_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_CTRL_O_FWB3 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB3_DATA_M  0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB3_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_CTRL_O_FWB4 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB4_DATA_M  0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB4_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_CTRL_O_FWB5 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB5_DATA_M  0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB5_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_CTRL_O_FWB6 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB6_DATA_M  0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB6_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_CTRL_O_FWB7 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB7_DATA_M  0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB7_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_CTRL_O_FWB8 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB8_DATA_M  0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB8_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_CTRL_O_FWB9 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB9_DATA_M  0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB9_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB10 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB10_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB10_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB11 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB11_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB11_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB12 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB12_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB12_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB13 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB13_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB13_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB14 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB14_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB14_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB15 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB15_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB15_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB16 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB16_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB16_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB17 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB17_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB17_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB18 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB18_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB18_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB19 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB19_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB19_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB20 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB20_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB20_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB21 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB21_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB21_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB22 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB22_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB22_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB23 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB23_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB23_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB24 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB24_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB24_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB25 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB25_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB25_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB26 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB26_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB26_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB27 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB27_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB27_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB28 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB28_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB28_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB29 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB29_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB29_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB30 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB30_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB30_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB31 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB31_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB31_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FWB32 register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FWB32_DATA_M 0xFFFFFFFF  // Data Data to be written into the
-                                            // Flash memory.
-#define FLASH_CTRL_FWB32_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_FSIZE register.
-//
-//******************************************************************************
-#define FLASH_CTRL_FSIZE_SIZE_M 0x0000FFFF  // Flash Size Indicates the size of
-                                            // the on-chip Flash memory. Value
-                                            // Description 0x0003 8 KB of Flash
-                                            // 0x0007 16 KB of Flash 0x000F 32
-                                            // KB of Flash 0x001F 64 KB of Flash
-                                            // 0x002F 96 KB of Flash 0x003F 128
-                                            // KB of Flash 0x005F 192 KB of
-                                            // Flash 0x007F 256 KB of Flash
-#define FLASH_CTRL_FSIZE_SIZE_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// FLASH_CTRL_O_SSIZE register.
-//
-//******************************************************************************
-#define FLASH_CTRL_SSIZE_SRAM_SIZE_M \
-                                0x0000FFFF  // SRAM Size Indicates the size of
-                                            // the on-chip SRAM. Value
-                                            // Description 0x0007 2 KB of SRAM
-                                            // 0x000F 4 KB of SRAM 0x0017 6 KB
-                                            // of SRAM 0x001F 8 KB of SRAM
-                                            // 0x002F 12 KB of SRAM 0x003F 16 KB
-                                            // of SRAM 0x004F 20 KB of SRAM
-                                            // 0x005F 24 KB of SRAM 0x007F 32 KB
-                                            // of SRAM
-
-#define FLASH_CTRL_SSIZE_SRAM_SIZE_S 0
-#define FLASH_CTRL_FMC_WRKEY    0xA4420000  // FLASH write key
-#define FLASH_CTRL_FMC2_WRKEY   0xA4420000  // FLASH write key
-#define FLASH_CTRL_O_FWBN       FLASH_CTRL_O_FWB1
-#define FLASH_ERASE_SIZE        0x00000400
-#define FLASH_PROTECT_SIZE      0x00000800
-#define FLASH_FMP_BLOCK_0       0x00000001  // Enable for block 0
-
-#define FLASH_FMPRE0            0x400FE200  // Flash Memory Protection Read
-                                            // Enable 0
-#define FLASH_FMPRE1            0x400FE204  // Flash Memory Protection Read
-                                            // Enable 1
-#define FLASH_FMPRE2            0x400FE208  // Flash Memory Protection Read
-                                            // Enable 2
-#define FLASH_FMPRE3            0x400FE20C  // Flash Memory Protection Read
-                                            // Enable 3
-#define FLASH_FMPRE4            0x400FE210  // Flash Memory Protection Read
-                                            // Enable 4
-#define FLASH_FMPRE5            0x400FE214  // Flash Memory Protection Read
-                                            // Enable 5
-#define FLASH_FMPRE6            0x400FE218  // Flash Memory Protection Read
-                                            // Enable 6
-#define FLASH_FMPRE7            0x400FE21C  // Flash Memory Protection Read
-                                            // Enable 7
-#define FLASH_FMPRE8            0x400FE220  // Flash Memory Protection Read
-                                            // Enable 8
-#define FLASH_FMPRE9            0x400FE224  // Flash Memory Protection Read
-                                            // Enable 9
-#define FLASH_FMPRE10           0x400FE228  // Flash Memory Protection Read
-                                            // Enable 10
-#define FLASH_FMPRE11           0x400FE22C  // Flash Memory Protection Read
-                                            // Enable 11
-#define FLASH_FMPRE12           0x400FE230  // Flash Memory Protection Read
-                                            // Enable 12
-#define FLASH_FMPRE13           0x400FE234  // Flash Memory Protection Read
-                                            // Enable 13
-#define FLASH_FMPRE14           0x400FE238  // Flash Memory Protection Read
-                                            // Enable 14
-#define FLASH_FMPRE15           0x400FE23C  // Flash Memory Protection Read
-                                            // Enable 15
-
-#define FLASH_FMPPE0            0x400FE400  // Flash Memory Protection Program
-                                            // Enable 0
-#define FLASH_FMPPE1            0x400FE404  // Flash Memory Protection Program
-                                            // Enable 1
-#define FLASH_FMPPE2            0x400FE408  // Flash Memory Protection Program
-                                            // Enable 2
-#define FLASH_FMPPE3            0x400FE40C  // Flash Memory Protection Program
-                                            // Enable 3
-#define FLASH_FMPPE4            0x400FE410  // Flash Memory Protection Program
-                                            // Enable 4
-#define FLASH_FMPPE5            0x400FE414  // Flash Memory Protection Program
-                                            // Enable 5
-#define FLASH_FMPPE6            0x400FE418  // Flash Memory Protection Program
-                                            // Enable 6
-#define FLASH_FMPPE7            0x400FE41C  // Flash Memory Protection Program
-                                            // Enable 7
-#define FLASH_FMPPE8            0x400FE420  // Flash Memory Protection Program
-                                            // Enable 8
-#define FLASH_FMPPE9            0x400FE424  // Flash Memory Protection Program
-                                            // Enable 9
-#define FLASH_FMPPE10           0x400FE428  // Flash Memory Protection Program
-                                            // Enable 10
-#define FLASH_FMPPE11           0x400FE42C  // Flash Memory Protection Program
-                                            // Enable 11
-#define FLASH_FMPPE12           0x400FE430  // Flash Memory Protection Program
-                                            // Enable 12
-#define FLASH_FMPPE13           0x400FE434  // Flash Memory Protection Program
-                                            // Enable 13
-#define FLASH_FMPPE14           0x400FE438  // Flash Memory Protection Program
-                                            // Enable 14
-#define FLASH_FMPPE15           0x400FE43C  // Flash Memory Protection Program
-                                            // Enable 15
-
-#define FLASH_USECRL            0x400FE140  // USec Reload
-#define FLASH_CTRL_ERASE_SIZE   0x00000400
-
-
-#endif // __HW_FLASH_CTRL_H__
diff --git a/cc3200/hal/inc/hw_gpio.h b/cc3200/hal/inc/hw_gpio.h
deleted file mode 100644
index 2bd6e0f3a..000000000
--- a/cc3200/hal/inc/hw_gpio.h
+++ /dev/null
@@ -1,1349 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_GPIO_H__
-#define __HW_GPIO_H__
-
-//*****************************************************************************
-//
-// The following are defines for the GPIO register offsets.
-//
-//*****************************************************************************
-#define GPIO_O_GPIO_DATA        0x00000000  // 0x4000 5000 0x4000 6000 0x4000
-                                            // 7000 0x4002 4000 GPIO Data
-                                            // (GPIODATA)@@ offset 0x000 The
-                                            // GPIODATA register is the data
-                                            // register. In software control
-                                            // mode@@ values written in the
-                                            // GPIODATA register are transferred
-                                            // onto the GPIO port pins if the
-                                            // respective pins have been
-                                            // configured as outputs through the
-                                            // GPIO Direction (GPIODIR) register
-                                            // (see page 653). In order to write
-                                            // to GPIODATA@@ the corresponding
-                                            // bits in the mask@@ resulting from
-                                            // the address bus bits [9:2]@@ must
-                                            // be set. Otherwise@@ the bit
-                                            // values remain unchanged by the
-                                            // write. Similarly@@ the values
-                                            // read from this register are
-                                            // determined for each bit by the
-                                            // mask bit derived from the address
-                                            // used to access the data
-                                            // register@@ bits [9:2]. Bits that
-                                            // are set in the address mask cause
-                                            // the corresponding bits in
-                                            // GPIODATA to be read@@ and bits
-                                            // that are clear in the address
-                                            // mask cause the corresponding bits
-                                            // in GPIODATA to be read as 0@@
-                                            // regardless of their value. A read
-                                            // from GPIODATA returns the last
-                                            // bit value written if the
-                                            // respective pins are configured as
-                                            // outputs@@ or it returns the value
-                                            // on the corresponding input pin
-                                            // when these are configured as
-                                            // inputs. All bits are cleared by a
-                                            // reset.
-#define GPIO_O_GPIO_DIR         0x00000400  // 0x4000 5400 0x4000 6400 0x4000
-                                            // 7400 0x4002 4400 GPIO Direction
-                                            // (GPIODIR)@@ offset 0x400 The
-                                            // GPIODIR register is the data
-                                            // direction register. Setting a bit
-                                            // in the GPIODIR register
-                                            // configures the corresponding pin
-                                            // to be an output@@ while clearing
-                                            // a bit configures the
-                                            // corresponding pin to be an input.
-                                            // All bits are cleared by a reset@@
-                                            // meaning all GPIO pins are inputs
-                                            // by default.
-#define GPIO_O_GPIO_IS          0x00000404  // 0x4000 5404 0x4000 6404 0x4000
-                                            // 7404 0x4002 4404 GPIO Interrupt
-                                            // Sense (GPIOIS)@@ offset 0x404 The
-                                            // GPIOIS register is the interrupt
-                                            // sense register. Setting a bit in
-                                            // the GPIOIS register configures
-                                            // the corresponding pin to detect
-                                            // levels@@ while clearing a bit
-                                            // configures the corresponding pin
-                                            // to detect edges. All bits are
-                                            // cleared by a reset.
-#define GPIO_O_GPIO_IBE         0x00000408  // 0x4000 5408 0x4000 6408 0x4000
-                                            // 7408 0x4002 4408 GPIO Interrupt
-                                            // Both Edges (GPIOIBE)@@ offset
-                                            // 0x408 The GPIOIBE register allows
-                                            // both edges to cause interrupts.
-                                            // When the corresponding bit in the
-                                            // GPIO Interrupt Sense (GPIOIS)
-                                            // register is set to detect edges@@
-                                            // setting a bit in the GPIOIBE
-                                            // register configures the
-                                            // corresponding pin to detect both
-                                            // rising and falling edges@@
-                                            // regardless of the corresponding
-                                            // bit in the GPIO Interrupt Event
-                                            // (GPIOIEV) register . Clearing a
-                                            // bit configures the pin to be
-                                            // controlled by the GPIOIEV
-                                            // register. All bits are cleared by
-                                            // a reset.
-#define GPIO_O_GPIO_IEV         0x0000040C  // 0x4000 540C 0x4000 640C 0x4000
-                                            // 740C 0x4002 440C GPIO Interrupt
-                                            // Event (GPIOIEV)@@ offset 0x40C
-                                            // The GPIOIEV register is the
-                                            // interrupt event register. Setting
-                                            // a bit in the GPIOIEV register
-                                            // configures the corresponding pin
-                                            // to detect rising edges or high
-                                            // levels@@ depending on the
-                                            // corresponding bit value in the
-                                            // GPIO Interrupt Sense (GPIOIS)
-                                            // register . Clearing a bit
-                                            // configures the pin to detect
-                                            // falling edges or low levels@@
-                                            // depending on the corresponding
-                                            // bit value in the GPIOIS register.
-                                            // All bits are cleared by a reset.
-#define GPIO_O_GPIO_IM          0x00000410  // 0x4000 5410 0x4000 6410 0x4000
-                                            // 7410 0x4002 4410 GPIO Interrupt
-                                            // Mask (GPIOIM)@@ offset 0x410 The
-                                            // GPIOIM register is the interrupt
-                                            // mask register. Setting a bit in
-                                            // the GPIOIM register allows
-                                            // interrupts that are generated by
-                                            // the corresponding pin to be sent
-                                            // to the interrupt controller on
-                                            // the combined interrupt signal.
-                                            // Clearing a bit prevents an
-                                            // interrupt on the corresponding
-                                            // pin from being sent to the
-                                            // interrupt controller. All bits
-                                            // are cleared by a reset.
-#define GPIO_O_GPIO_RIS         0x00000414  // 0x4000 5414 0x4000 6414 0x4000
-                                            // 7414 0x4002 4414 GPIO Raw
-                                            // Interrupt Status (GPIORIS)@@
-                                            // offset 0x414 The GPIORIS register
-                                            // is the raw interrupt status
-                                            // register. A bit in this register
-                                            // is set when an interrupt
-                                            // condition occurs on the
-                                            // corresponding GPIO pin. If the
-                                            // corresponding bit in the GPIO
-                                            // Interrupt Mask (GPIOIM) register
-                                            // is set@@ the interrupt is sent to
-                                            // the interrupt controller. Bits
-                                            // read as zero indicate that
-                                            // corresponding input pins have not
-                                            // initiated an interrupt. A bit in
-                                            // this register can be cleared by
-                                            // writing a 1 to the corresponding
-                                            // bit in the GPIO Interrupt Clear
-                                            // (GPIOICR) register.
-#define GPIO_O_GPIO_MIS         0x00000418  // 0x4000 5418 0x4000 6418 0x4000
-                                            // 7418 0x4002 4418 GPIO Masked
-                                            // Interrupt Status (GPIOMIS)@@
-                                            // offset 0x418 The GPIOMIS register
-                                            // is the masked interrupt status
-                                            // register. If a bit is set in this
-                                            // register@@ the corresponding
-                                            // interrupt has triggered an
-                                            // interrupt to the interrupt
-                                            // controller. If a bit is clear@@
-                                            // either no interrupt has been
-                                            // generated@@ or the interrupt is
-                                            // masked. If no port pin@@ other
-                                            // than the one that is being used
-                                            // as an ADC trigger@@ is being used
-                                            // to generate interrupts@@ the
-                                            // appropriate Interrupt Set Enable
-                                            // (ENn) register can disable the
-                                            // interrupts for the port@@ and the
-                                            // ADC interrupt can be used to read
-                                            // back the converted data.
-                                            // Otherwise@@ the port interrupt
-                                            // handler must ignore and clear
-                                            // interrupts on the port pin and
-                                            // wait for the ADC interrupt@@ or
-                                            // the ADC interrupt must be
-                                            // disabled in the EN0 register and
-                                            // the port interrupt handler must
-                                            // poll the ADC registers until the
-                                            // conversion is completed. If no
-                                            // port pin@@ other than the one
-                                            // that is being used as an ADC
-                                            // trigger@@ is being used to
-                                            // generate interrupts@@ the
-                                            // appropriate Interrupt Set Enable
-                                            // (ENn) register can disable the
-                                            // interrupts for the port@@ and the
-                                            // ADC interrupt can be used to read
-                                            // back the converted data.
-                                            // Otherwise@@ the port interrupt
-                                            // handler must ignore and clear
-                                            // interrupts on the port pin and
-                                            // wait for the ADC interrupt@@ or
-                                            // the ADC interrupt must be
-                                            // disabled in the EN0 register and
-                                            // the port interrupt handler must
-                                            // poll the ADC registers until the
-                                            // conversion is completed. Note
-                                            // that if the Port B GPIOADCCTL
-                                            // register is cleared@@ PB4 can
-                                            // still be used as an external
-                                            // trigger for the ADC. This is a
-                                            // legacy mode which allows code
-                                            // written for previous Stellaris
-                                            // devices to operate on this
-                                            // microcontroller. GPIOMIS is the
-                                            // state of the interrupt after
-                                            // masking.
-#define GPIO_O_GPIO_ICR         0x0000041C  // 0x4000 541C 0x4000 641C 0x4000
-                                            // 741C 0x4002 441C GPIO Interrupt
-                                            // Clear (GPIOICR)@@ offset 0x41C
-                                            // The GPIOICR register is the
-                                            // interrupt clear register. Writing
-                                            // a 1 to a bit in this register
-                                            // clears the corresponding
-                                            // interrupt bit in the GPIORIS and
-                                            // GPIOMIS registers. Writing a 0
-                                            // has no effect.
-#define GPIO_O_GPIO_AFSEL       0x00000420  // 0x4000 5420 0x4000 6420 0x4000
-                                            // 7420 0x4002 4420 GPIO Alternate
-                                            // Function Select (GPIOAFSEL)@@
-                                            // offset 0x420 The GPIOAFSEL
-                                            // register is the mode control
-                                            // select register. If a bit is
-                                            // clear@@ the pin is used as a GPIO
-                                            // and is controlled by the GPIO
-                                            // registers. Setting a bit in this
-                                            // register configures the
-                                            // corresponding GPIO line to be
-                                            // controlled by an associated
-                                            // peripheral. Several possible
-                                            // peripheral functions are
-                                            // multiplexed on each GPIO. The
-                                            // GPIO Port Control (GPIOPCTL)
-                                            // register is used to select one of
-                                            // the possible functions.
-#define GPIO_O_GPIO_DR2R        0x00000500  // 0x4000 5500 0x4000 6500 0x4000
-                                            // 7500 0x4002 4500 GPIO 2-mA Drive
-                                            // Select (GPIODR2R)@@ offset 0x500
-                                            // The GPIODR2R register is the 2-mA
-                                            // drive control register. Each GPIO
-                                            // signal in the port can be
-                                            // individually configured without
-                                            // affecting the other pads. When
-                                            // setting the DRV2 bit for a GPIO
-                                            // signal@@ the corresponding DRV4
-                                            // bit in the GPIODR4R register and
-                                            // DRV8 bit in the GPIODR8R register
-                                            // are automatically cleared by
-                                            // hardware. By default@@ all GPIO
-                                            // pins have 2-mA drive.
-#define GPIO_O_GPIO_DR4R        0x00000504  // 0x4000 5504 0x4000 6504 0x4000
-                                            // 7504 0x4002 4504 GPIO 4-mA Drive
-                                            // Select (GPIODR4R)@@ offset 0x504
-                                            // The GPIODR4R register is the 4-mA
-                                            // drive control register. Each GPIO
-                                            // signal in the port can be
-                                            // individually configured without
-                                            // affecting the other pads. When
-                                            // setting the DRV4 bit for a GPIO
-                                            // signal@@ the corresponding DRV2
-                                            // bit in the GPIODR2R register and
-                                            // DRV8 bit in the GPIODR8R register
-                                            // are automatically cleared by
-                                            // hardware.
-#define GPIO_O_GPIO_DR8R        0x00000508  // 0x4000 5508 0x4000 6508 0x4000
-                                            // 7508 0x4002 4508 GPIO 8-mA Drive
-                                            // Select (GPIODR8R)@@ offset 0x508
-                                            // The GPIODR8R register is the 8-mA
-                                            // drive control register. Each GPIO
-                                            // signal in the port can be
-                                            // individually configured without
-                                            // affecting the other pads. When
-                                            // setting the DRV8 bit for a GPIO
-                                            // signal@@ the corresponding DRV2
-                                            // bit in the GPIODR2R register and
-                                            // DRV4 bit in the GPIODR4R register
-                                            // are automatically cleared by
-                                            // hardware. The 8-mA setting is
-                                            // also used for high-current
-                                            // operation. Note: There is no
-                                            // configuration difference between
-                                            // 8-mA and high-current operation.
-                                            // The additional current capacity
-                                            // results from a shift in the
-                                            // VOH/VOL levels.
-#define GPIO_O_GPIO_ODR         0x0000050C  // 0x4000 550C 0x4000 650C 0x4000
-                                            // 750C 0x4002 450C GPIO Open Drain
-                                            // Select (GPIOODR)@@ offset 0x50C
-                                            // The GPIOODR register is the open
-                                            // drain control register. Setting a
-                                            // bit in this register enables the
-                                            // open-drain configuration of the
-                                            // corresponding GPIO pad. When
-                                            // open-drain mode is enabled@@ the
-                                            // corresponding bit should also be
-                                            // set in the GPIO Digital Input
-                                            // Enable (GPIODEN) register .
-                                            // Corresponding bits in the drive
-                                            // strength and slew rate control
-                                            // registers (GPIODR2R@@ GPIODR4R@@
-                                            // GPIODR8R@@ and GPIOSLR) can be
-                                            // set to achieve the desired rise
-                                            // and fall times. The GPIO acts as
-                                            // an open-drain input if the
-                                            // corresponding bit in the GPIODIR
-                                            // register is cleared. If open
-                                            // drain is selected while the GPIO
-                                            // is configured as an input@@ the
-                                            // GPIO will remain an input and the
-                                            // open-drain selection has no
-                                            // effect until the GPIO is changed
-                                            // to an output. When using the I2C
-                                            // module@@ in addition to
-                                            // configuring the pin to open
-                                            // drain@@ the GPIO Alternate
-                                            // Function Select (GPIOAFSEL)
-                                            // register bits for the I2C clock
-                                            // and data pins should be set
-#define GPIO_O_GPIO_PUR         0x00000510  // 0x4000 5510 0x4000 6510 0x4000
-                                            // 7510 0x4002 4510 GPIO Pull-Up
-                                            // Select (GPIOPUR)@@ offset 0x510
-                                            // The GPIOPUR register is the
-                                            // pull-up control register. When a
-                                            // bit is set@@ a weak pull-up
-                                            // resistor on the corresponding
-                                            // GPIO signal is enabled. Setting a
-                                            // bit in GPIOPUR automatically
-                                            // clears the corresponding bit in
-                                            // the GPIO Pull-Down Select
-                                            // (GPIOPDR) register . Write access
-                                            // to this register is protected
-                                            // with the GPIOCR register. Bits in
-                                            // GPIOCR that are cleared prevent
-                                            // writes to the equivalent bit in
-                                            // this register.
-#define GPIO_O_GPIO_PDR         0x00000514  // 0x4000 5514 0x4000 6514 0x4000
-                                            // 7514 0x4002 4514 GPIO Pull-Down
-                                            // Select (GPIOPDR)@@ offset 0x514
-                                            // The GPIOPDR register is the
-                                            // pull-down control register. When
-                                            // a bit is set@@ a weak pull-down
-                                            // resistor on the corresponding
-                                            // GPIO signal is enabled. Setting a
-                                            // bit in GPIOPDR automatically
-                                            // clears the corresponding bit in
-                                            // the GPIO Pull-Up Select (GPIOPUR)
-                                            // register
-#define GPIO_O_GPIO_SLR         0x00000518  // 0x4000 5518 0x4000 6518 0x4000
-                                            // 7518 0x4002 4518 The GPIOSLR
-                                            // register is the slew rate control
-                                            // register. Slew rate control is
-                                            // only available when using the
-                                            // 8-mA drive strength option via
-                                            // the GPIO 8-mA Drive Select
-                                            // (GPIODR8R) register
-#define GPIO_O_GPIO_DEN         0x0000051C  // 0x4000 551C 0x4000 651C 0x4000
-                                            // 751C 0x4002 451C GPIO Digital
-                                            // Enable (GPIODEN)@@ offset 0x51C
-                                            // Note: Pins configured as digital
-                                            // inputs are Schmitt-triggered. The
-                                            // GPIODEN register is the digital
-                                            // enable register. By default@@ all
-                                            // GPIO signals except those listed
-                                            // below are configured out of reset
-                                            // to be undriven (tristate). Their
-                                            // digital function is disabled;
-                                            // they do not drive a logic value
-                                            // on the pin and they do not allow
-                                            // the pin voltage into the GPIO
-                                            // receiver. To use the pin as a
-                                            // digital input or output (either
-                                            // GPIO or alternate function)@@ the
-                                            // corresponding GPIODEN bit must be
-                                            // set.
-#define GPIO_O_GPIO_LOCK        0x00000520  // 0x4000 5520 0x4000 6520 0x4000
-                                            // 7520 0x4002 4520 GPIO Lock
-                                            // (GPIOLOCK)@@ offset 0x520 The
-                                            // GPIOLOCK register enables write
-                                            // access to the GPIOCR register .
-                                            // Writing 0x4C4F.434B to the
-                                            // GPIOLOCK register unlocks the
-                                            // GPIOCR register. Writing any
-                                            // other value to the GPIOLOCK
-                                            // register re-enables the locked
-                                            // state. Reading the GPIOLOCK
-                                            // register returns the lock status
-                                            // rather than the 32-bit value that
-                                            // was previously written.
-                                            // Therefore@@ when write accesses
-                                            // are disabled@@ or locked@@
-                                            // reading the GPIOLOCK register
-                                            // returns 0x0000.0001. When write
-                                            // accesses are enabled@@ or
-                                            // unlocked@@ reading the GPIOLOCK
-                                            // register returns 0x0000.0000.
-#define GPIO_O_GPIO_CR          0x00000524  // 0x4000 5524 0x4000 6524 0x4000
-                                            // 7524 0x4002 4524 GPIO Commit
-                                            // (GPIOCR)@@ offset 0x524 The
-                                            // GPIOCR register is the commit
-                                            // register. The value of the GPIOCR
-                                            // register determines which bits of
-                                            // the GPIOAFSEL@@ GPIOPUR@@
-                                            // GPIOPDR@@ and GPIODEN registers
-                                            // are committed when a write to
-                                            // these registers is performed. If
-                                            // a bit in the GPIOCR register is
-                                            // cleared@@ the data being written
-                                            // to the corresponding bit in the
-                                            // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@
-                                            // or GPIODEN registers cannot be
-                                            // committed and retains its
-                                            // previous value. If a bit in the
-                                            // GPIOCR register is set@@ the data
-                                            // being written to the
-                                            // corresponding bit of the
-                                            // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@
-                                            // or GPIODEN registers is committed
-                                            // to the register and reflects the
-                                            // new value. The contents of the
-                                            // GPIOCR register can only be
-                                            // modified if the status in the
-                                            // GPIOLOCK register is unlocked.
-                                            // Writes to the GPIOCR register are
-                                            // ignored if the status in the
-                                            // GPIOLOCK register is locked.
-#define GPIO_O_GPIO_AMSEL       0x00000528  // 0x4000 5528 0x4000 6528 0x4000
-                                            // 7528 0x4002 4528 The GPIOAMSEL
-                                            // register controls isolation
-                                            // circuits to the analog side of a
-                                            // unified I/O pad. Because the
-                                            // GPIOs may be driven by a 5-V
-                                            // source and affect analog
-                                            // operation@@ analog circuitry
-                                            // requires isolation from the pins
-                                            // when they are not used in their
-                                            // analog function. Each bit of this
-                                            // register controls the isolation
-                                            // circuitry for the corresponding
-                                            // GPIO signal.
-#define GPIO_O_GPIO_PCTL        0x0000052C  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) 0x4000 552C
-                                            // 0x4000 652C 0x4000 752C 0x4002
-                                            // 452C GPIO Port Control
-                                            // (GPIOPCTL)@@ offset 0x52C The
-                                            // GPIOPCTL register is used in
-                                            // conjunction with the GPIOAFSEL
-                                            // register and selects the specific
-                                            // peripheral signal for each GPIO
-                                            // pin when using the alternate
-                                            // function mode. Most bits in the
-                                            // GPIOAFSEL register are cleared on
-                                            // reset@@ therefore most GPIO pins
-                                            // are configured as GPIOs by
-                                            // default. When a bit is set in the
-                                            // GPIOAFSEL register@@ the
-                                            // corresponding GPIO signal is
-                                            // controlled by an associated
-                                            // peripheral. The GPIOPCTL register
-                                            // selects one out of a set of
-                                            // peripheral functions for each
-                                            // GPIO@@ providing additional
-                                            // flexibility in signal definition.
-#define GPIO_O_GPIO_ADCCTL      0x00000530  // This register is not used in
-                                            // cc3xx. ADC trigger via GPIO is
-                                            // not supported. 0x4000 5530 0x4000
-                                            // 6530 0x4000 7530 0x4002 4530 GPIO
-                                            // ADC Control (GPIOADCCTL)@@ offset
-                                            // 0x530 This register is used to
-                                            // configure a GPIO pin as a source
-                                            // for the ADC trigger. Note that if
-                                            // the Port B GPIOADCCTL register is
-                                            // cleared@@ PB4 can still be used
-                                            // as an external trigger for the
-                                            // ADC. This is a legacy mode which
-                                            // allows code written for previous
-                                            // Stellaris devices to operate on
-                                            // this microcontroller.
-#define GPIO_O_GPIO_DMACTL      0x00000534  // 0x4000 5534 0x4000 6534 0x4000
-                                            // 7534 0x4002 4534 GPIO DMA Control
-                                            // (GPIODMACTL)@@ offset 0x534 This
-                                            // register is used to configure a
-                                            // GPIO pin as a source for the ?DMA
-                                            // trigger.
-#define GPIO_O_GPIO_SI          0x00000538  // 0x4000 5538 0x4000 6538 0x4000
-                                            // 7538 0x4002 4538 GPIO Select
-                                            // Interrupt (GPIOSI)@@ offset 0x538
-                                            // This register is used to enable
-                                            // individual interrupts for each
-                                            // pin. Note: This register is only
-                                            // available on Port P and Port Q.
-#define GPIO_O_GPIO_PERIPHID4   0x00000FD0  // 0x4000 5FD0 0x4000 6FD0 0x4000
-                                            // 7FD0 0x4002 4FD0 GPIO Peripheral
-                                            // Identification 4
-                                            // (GPIOPeriphID4)@@ offset 0xFD0
-                                            // The GPIOPeriphID4@@
-                                            // GPIOPeriphID5@@ GPIOPeriphID6@@
-                                            // and GPIOPeriphID7 registers can
-                                            // conceptually be treated as one
-                                            // 32-bit register; each register
-                                            // contains eight bits of the 32-bit
-                                            // register@@ used by software to
-                                            // identify the peripheral.
-#define GPIO_O_GPIO_PERIPHID5   0x00000FD4  // 0x4000 5FD4 0x4000 6FD4 0x4000
-                                            // 7FD4 0x4002 4FD4 GPIO Peripheral
-                                            // Identification 5
-                                            // (GPIOPeriphID5)@@ offset 0xFD4
-                                            // The GPIOPeriphID4@@
-                                            // GPIOPeriphID5@@ GPIOPeriphID6@@
-                                            // and GPIOPeriphID7 registers can
-                                            // conceptually be treated as one
-                                            // 32-bit register; each register
-                                            // contains eight bits of the 32-bit
-                                            // register@@ used by software to
-                                            // identify the peripheral.
-#define GPIO_O_GPIO_PERIPHID6   0x00000FD8  // 0x4000 5FD8 0x4000 6FD8 0x4000
-                                            // 7FD8 0x4002 4FD8 GPIO Peripheral
-                                            // Identification 6
-                                            // (GPIOPeriphID6)@@ offset 0xFD8
-                                            // The GPIOPeriphID4@@
-                                            // GPIOPeriphID5@@ GPIOPeriphID6@@
-                                            // and GPIOPeriphID7 registers can
-                                            // conceptually be treated as one
-                                            // 32-bit register; each register
-                                            // contains eight bits of the 32-bit
-                                            // register@@ used by software to
-                                            // identify the peripheral.
-#define GPIO_O_GPIO_PERIPHID7   0x00000FDC  // 0x4000 5FDC 0x4000 6FDC 0x4000
-                                            // 7FDC 0x4002 4FDC GPIO Peripheral
-                                            // Identification 7
-                                            // (GPIOPeriphID7)@@ offset 0xFDC
-                                            // The GPIOPeriphID4@@
-                                            // GPIOPeriphID5@@ GPIOPeriphID6@@
-                                            // and GPIOPeriphID7 registers can
-                                            // conceptually be treated as one
-                                            // 32-bit register; each register
-                                            // contains eight bits of the 32-bit
-                                            // register@@ used by software to
-                                            // identify the peripheral.
-#define GPIO_O_GPIO_PERIPHID0   0x00000FE0  // 0x4000 5FE0 0x4000 6FE0 0x4000
-                                            // 7FE0 0x4002 4FE0 GPIO Peripheral
-                                            // Identification 0
-                                            // (GPIOPeriphID0)@@ offset 0xFE0
-                                            // The GPIOPeriphID0@@
-                                            // GPIOPeriphID1@@ GPIOPeriphID2@@
-                                            // and GPIOPeriphID3 registers can
-                                            // conceptually be treated as one
-                                            // 32-bit register; each register
-                                            // contains eight bits of the 32-bit
-                                            // register@@ used by software to
-                                            // identify the peripheral.
-#define GPIO_O_GPIO_PERIPHID1   0x00000FE4  // 0x4000 5FE4 0x4000 6FE4 0x4000
-                                            // 7FE4 0x4002 4FE4 GPIO Peripheral
-                                            // Identification 1
-                                            // (GPIOPeriphID1)@@ offset 0xFE4
-                                            // The GPIOPeriphID0@@
-                                            // GPIOPeriphID1@@ GPIOPeriphID2@@
-                                            // and GPIOPeriphID3 registers can
-                                            // conceptually be treated as one
-                                            // 32-bit register; each register
-                                            // contains eight bits of the 32-bit
-                                            // register@@ used by software to
-                                            // identify the peripheral.
-#define GPIO_O_GPIO_PERIPHID2   0x00000FE8  // 0x4000 5FE8 0x4000 6FE8 0x4000
-                                            // 7FE8 0x4002 4FE8 GPIO Peripheral
-                                            // Identification 2
-                                            // (GPIOPeriphID2)@@ offset 0xFE8
-                                            // The GPIOPeriphID0@@
-                                            // GPIOPeriphID1@@ GPIOPeriphID2@@
-                                            // and GPIOPeriphID3 registers can
-                                            // conceptually be treated as one
-                                            // 32-bit register; each register
-                                            // contains eight bits of the 32-bit
-                                            // register@@ used by software to
-                                            // identify the peripheral.
-#define GPIO_O_GPIO_PERIPHID3   0x00000FEC  // 0x4000 5FEC 0x4000 6FEC 0x4000
-                                            // 7FEC 0x4002 4FEC GPIO Peripheral
-                                            // Identification 3
-                                            // (GPIOPeriphID3)@@ offset 0xFEC
-                                            // The GPIOPeriphID0@@
-                                            // GPIOPeriphID1@@ GPIOPeriphID2@@
-                                            // and GPIOPeriphID3 registers can
-                                            // conceptually be treated as one
-                                            // 32-bit register; each register
-                                            // contains eight bits of the 32-bit
-                                            // register@@ used by software to
-                                            // identify the peripheral.
-#define GPIO_O_GPIO_PCELLID0    0x00000FF0  // 0x4000 5FF0 0x4000 6FF0 0x4000
-                                            // 7FF0 0x4002 4FF0 GPIO PrimeCell
-                                            // Identification 0 (GPIOPCellID0)@@
-                                            // offset 0xFF0 The GPIOPCellID0@@
-                                            // GPIOPCellID1@@ GPIOPCellID2@@ and
-                                            // GPIOPCellID3 registers are four
-                                            // 8-bit wide registers@@ that can
-                                            // conceptually be treated as one
-                                            // 32-bit register. The register is
-                                            // used as a standard
-                                            // cross-peripheral identification
-                                            // system.
-#define GPIO_O_GPIO_PCELLID1    0x00000FF4  // 0x4000 5FF4 0x4000 6FF4 0x4000
-                                            // 7FF4 0x4002 4FF4 GPIO PrimeCell
-                                            // Identification 1 (GPIOPCellID1)@@
-                                            // offset 0xFF4 The GPIOPCellID0@@
-                                            // GPIOPCellID1@@ GPIOPCellID2@@ and
-                                            // GPIOPCellID3 registers are four
-                                            // 8-bit wide registers@@ that can
-                                            // conceptually be treated as one
-                                            // 32-bit register. The register is
-                                            // used as a standard
-                                            // cross-peripheral identification
-                                            // system.
-#define GPIO_O_GPIO_PCELLID2    0x00000FF8  // 0x4000 5FF8 0x4000 6FF8 0x4000
-                                            // 7FF8 0x4002 4FF8 GPIO PrimeCell
-                                            // Identification 2 (GPIOPCellID2)@@
-                                            // offset 0xFF8 The GPIOPCellID0@@
-                                            // GPIOPCellID1@@ GPIOPCellID2@@ and
-                                            // GPIOPCellID3 registers are four
-                                            // 8-bit wide registers@@ that can
-                                            // conceptually be treated as one
-                                            // 32-bit register. The register is
-                                            // used as a standard
-                                            // cross-peripheral identification
-                                            // system.
-#define GPIO_O_GPIO_PCELLID3    0x00000FFC  // 0x4000 5FFC 0x4000 6FFC 0x4000
-                                            // 7FFC 0x4002 4FFC GPIO PrimeCell
-                                            // Identification 3 (GPIOPCellID3)@@
-                                            // offset 0xFFC The GPIOPCellID0@@
-                                            // GPIOPCellID1@@ GPIOPCellID2@@ and
-                                            // GPIOPCellID3 registers are four
-                                            // 8-bit wide registers@@ that can
-                                            // conceptually be treated as one
-                                            // 32-bit register. The register is
-                                            // used as a standard
-                                            // cross-peripheral identification
-                                            // system.0xb1
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_DATA register.
-//
-//******************************************************************************
-#define GPIO_GPIO_DATA_DATA_M   0x000000FF  // GPIO Data This register is
-                                            // virtually mapped to 256 locations
-                                            // in the address space. To
-                                            // facilitate the reading and
-                                            // writing of data to these
-                                            // registers by independent
-                                            // drivers@@ the data read from and
-                                            // written to the registers are
-                                            // masked by the eight address lines
-                                            // [9:2]. Reads from this register
-                                            // return its current state. Writes
-                                            // to this register only affect bits
-                                            // that are not masked by ADDR[9:2]
-                                            // and are configured as outputs.
-#define GPIO_GPIO_DATA_DATA_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_DIR register.
-//
-//******************************************************************************
-#define GPIO_GPIO_DIR_DIR_M     0x000000FF  // GPIO Data Direction Value
-                                            // Description 0 Corresponding pin
-                                            // is an input. 1 Corresponding pins
-                                            // is an output.
-#define GPIO_GPIO_DIR_DIR_S     0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_IS register.
-//
-//******************************************************************************
-#define GPIO_GPIO_IS_IS_M       0x000000FF  // GPIO Interrupt Sense Value
-                                            // Description 0 The edge on the
-                                            // corresponding pin is detected
-                                            // (edge-sensitive). 1 The level on
-                                            // the corresponding pin is detected
-                                            // (level-sensitive).
-#define GPIO_GPIO_IS_IS_S       0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_IBE register.
-//
-//******************************************************************************
-#define GPIO_GPIO_IBE_IBE_M     0x000000FF  // GPIO Interrupt Both Edges Value
-                                            // Description 0 Interrupt
-                                            // generation is controlled by the
-                                            // GPIO Interrupt Event (GPIOIEV)
-                                            // register. 1 Both edges on the
-                                            // corresponding pin trigger an
-                                            // interrupt.
-#define GPIO_GPIO_IBE_IBE_S     0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_IEV register.
-//
-//******************************************************************************
-#define GPIO_GPIO_IEV_IEV_M     0x000000FF  // GPIO Interrupt Event Value
-                                            // Description 1 A falling edge or a
-                                            // Low level on the corresponding
-                                            // pin triggers an interrupt. 0 A
-                                            // rising edge or a High level on
-                                            // the corresponding pin triggers an
-                                            // interrupt.
-#define GPIO_GPIO_IEV_IEV_S     0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_IM register.
-//
-//******************************************************************************
-#define GPIO_GPIO_IM_IME_M      0x000000FF  // GPIO Interrupt Mask Enable Value
-                                            // Description 0 The interrupt from
-                                            // the corresponding pin is masked.
-                                            // 1 The interrupt from the
-                                            // corresponding pin is sent to the
-                                            // interrupt controller.
-#define GPIO_GPIO_IM_IME_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_RIS register.
-//
-//******************************************************************************
-#define GPIO_GPIO_RIS_RIS_M     0x000000FF  // GPIO Interrupt Raw Status Value
-                                            // Description 1 An interrupt
-                                            // condition has occurred on the
-                                            // corresponding pin. 0 interrupt
-                                            // condition has not occurred on the
-                                            // corresponding pin. A bit is
-                                            // cleared by writing a 1 to the
-                                            // corresponding bit in the GPIOICR
-                                            // register.
-#define GPIO_GPIO_RIS_RIS_S     0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_MIS register.
-//
-//******************************************************************************
-#define GPIO_GPIO_MIS_MIS_M     0x000000FF  // GPIO Masked Interrupt Status
-                                            // Value Description 1 An interrupt
-                                            // condition on the corresponding
-                                            // pin has triggered an interrupt to
-                                            // the interrupt controller. 0 An
-                                            // interrupt condition on the
-                                            // corresponding pin is masked or
-                                            // has not occurred. A bit is
-                                            // cleared by writing a 1 to the
-                                            // corresponding bit in the GPIOICR
-                                            // register.
-#define GPIO_GPIO_MIS_MIS_S     0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_ICR register.
-//
-//******************************************************************************
-#define GPIO_GPIO_ICR_IC_M      0x000000FF  // GPIO Interrupt Clear Value
-                                            // Description 1 The corresponding
-                                            // interrupt is cleared. 0 The
-                                            // corresponding interrupt is
-                                            // unaffected.
-#define GPIO_GPIO_ICR_IC_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_AFSEL register.
-//
-//******************************************************************************
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_DR2R register.
-//
-//******************************************************************************
-#define GPIO_GPIO_DR2R_DRV2_M   0x000000FF  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) Output Pad
-                                            // 2-mA Drive Enable Value
-                                            // Description 1 The corresponding
-                                            // GPIO pin has 2-mA drive. The
-                                            // drive for the corresponding GPIO
-                                            // pin is controlled by the GPIODR4R
-                                            // or GPIODR8R register. 0 Setting a
-                                            // bit in either the GPIODR4
-                                            // register or the GPIODR8 register
-                                            // clears the corresponding 2-mA
-                                            // enable bit. The change is
-                                            // effective on the second clock
-                                            // cycle after the write if
-                                            // accessing GPIO via the APB memory
-                                            // aperture. If using AHB access@@
-                                            // the change is effective on the
-                                            // next clock cycle.
-#define GPIO_GPIO_DR2R_DRV2_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_DR4R register.
-//
-//******************************************************************************
-#define GPIO_GPIO_DR4R_DRV4_M   0x000000FF  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) Output Pad
-                                            // 4-mA Drive Enable Value
-                                            // Description 1 The corresponding
-                                            // GPIO pin has 4-mA drive. The
-                                            // drive for the corresponding GPIO
-                                            // pin is controlled by the GPIODR2R
-                                            // or GPIODR8R register. 0 Setting a
-                                            // bit in either the GPIODR2
-                                            // register or the GPIODR8 register
-                                            // clears the corresponding 4-mA
-                                            // enable bit. The change is
-                                            // effective on the second clock
-                                            // cycle after the write if
-                                            // accessing GPIO via the APB memory
-                                            // aperture. If using AHB access@@
-                                            // the change is effective on the
-                                            // next clock cycle.
-#define GPIO_GPIO_DR4R_DRV4_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_DR8R register.
-//
-//******************************************************************************
-#define GPIO_GPIO_DR8R_DRV8_M   0x000000FF  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) Output Pad
-                                            // 8-mA Drive Enable Value
-                                            // Description 1 The corresponding
-                                            // GPIO pin has 8-mA drive. The
-                                            // drive for the corresponding GPIO
-                                            // pin is controlled by the GPIODR2R
-                                            // or GPIODR4R register. 0 Setting a
-                                            // bit in either the GPIODR2
-                                            // register or the GPIODR4 register
-                                            // clears the corresponding 8-mA
-                                            // enable bit. The change is
-                                            // effective on the second clock
-                                            // cycle after the write if
-                                            // accessing GPIO via the APB memory
-                                            // aperture. If using AHB access@@
-                                            // the change is effective on the
-                                            // next clock cycle.
-#define GPIO_GPIO_DR8R_DRV8_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_ODR register.
-//
-//******************************************************************************
-#define GPIO_GPIO_ODR_ODE_M     0x000000FF  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) Output Pad
-                                            // Open Drain Enable Value
-                                            // Description 1 The corresponding
-                                            // pin is configured as open drain.
-                                            // 0 The corresponding pin is not
-                                            // configured as open drain.
-#define GPIO_GPIO_ODR_ODE_S     0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_PUR register.
-//
-//******************************************************************************
-#define GPIO_GPIO_PUR_PUE_M     0x000000FF  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) Pad Weak
-                                            // Pull-Up Enable Value Description
-                                            // 1 The corresponding pin has a
-                                            // weak pull-up resistor. 0 The
-                                            // corresponding pin is not
-                                            // affected. Setting a bit in the
-                                            // GPIOPDR register clears the
-                                            // corresponding bit in the GPIOPUR
-                                            // register. The change is effective
-                                            // on the second clock cycle after
-                                            // the write if accessing GPIO via
-                                            // the APB memory aperture. If using
-                                            // AHB access@@ the change is
-                                            // effective on the next clock
-                                            // cycle.
-#define GPIO_GPIO_PUR_PUE_S     0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_PDR register.
-//
-//******************************************************************************
-#define GPIO_GPIO_PDR_PDE_M     0x000000FF  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) Pad Weak
-                                            // Pull-Down Enable Value
-                                            // Description 1 The corresponding
-                                            // pin has a weak pull-down
-                                            // resistor. 0 The corresponding pin
-                                            // is not affected. Setting a bit in
-                                            // the GPIOPUR register clears the
-                                            // corresponding bit in the GPIOPDR
-                                            // register. The change is effective
-                                            // on the second clock cycle after
-                                            // the write if accessing GPIO via
-                                            // the APB memory aperture. If using
-                                            // AHB access@@ the change is
-                                            // effective on the next clock
-                                            // cycle.
-#define GPIO_GPIO_PDR_PDE_S     0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_SLR register.
-//
-//******************************************************************************
-#define GPIO_GPIO_SLR_SRL_M     0x000000FF  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) Slew Rate
-                                            // Limit Enable (8-mA drive only)
-                                            // Value Description 1 Slew rate
-                                            // control is enabled for the
-                                            // corresponding pin. 0 Slew rate
-                                            // control is disabled for the
-                                            // corresponding pin.
-#define GPIO_GPIO_SLR_SRL_S     0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_DEN register.
-//
-//******************************************************************************
-#define GPIO_GPIO_DEN_DEN_M     0x000000FF  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) Digital Enable
-                                            // Value Description 0 The digital
-                                            // functions for the corresponding
-                                            // pin are disabled. 1 The digital
-                                            // functions for the corresponding
-                                            // pin are enabled.
-#define GPIO_GPIO_DEN_DEN_S     0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_LOCK register.
-//
-//******************************************************************************
-#define GPIO_GPIO_LOCK_LOCK_M   0xFFFFFFFF  // This register is not used in
-                                            // cc3xx. GPIO Lock A write of the
-                                            // value 0x4C4F.434B unlocks the
-                                            // GPIO Commit (GPIOCR) register for
-                                            // write access.A write of any other
-                                            // value or a write to the GPIOCR
-                                            // register reapplies the lock@@
-                                            // preventing any register updates.
-                                            // A read of this register returns
-                                            // the following values: Value
-                                            // Description 0x1 The GPIOCR
-                                            // register is locked and may not be
-                                            // modified. 0x0 The GPIOCR register
-                                            // is unlocked and may be modified.
-#define GPIO_GPIO_LOCK_LOCK_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_CR register.
-//
-//******************************************************************************
-#define GPIO_GPIO_CR_CR_M       0x000000FF  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) GPIO Commit
-                                            // Value Description The
-                                            // corresponding GPIOAFSEL@@
-                                            // GPIOPUR@@ GPIOPDR@@ or GPIODEN
-                                            // bits can be written. 1 The
-                                            // corresponding GPIOAFSEL@@
-                                            // GPIOPUR@@ GPIOPDR@@ or GPIODEN
-                                            // bits cannot be written. 0 Note:
-                                            // The default register type for the
-                                            // GPIOCR register is RO for all
-                                            // GPIO pins with the exception of
-                                            // the NMI pin and the four JTAG/SWD
-                                            // pins (PD7@@ PF0@@ and PC[3:0]).
-                                            // These six pins are the only GPIOs
-                                            // that are protected by the GPIOCR
-                                            // register. Because of this@@ the
-                                            // register type for GPIO Port D7@@
-                                            // GPIO Port F0@@ and GPIO Port
-                                            // C[3:0] is R/W. The default reset
-                                            // value for the GPIOCR register is
-                                            // 0x0000.00FF for all GPIO pins@@
-                                            // with the exception of the NMI pin
-                                            // and the four JTAG/SWD pins (PD7@@
-                                            // PF0@@ and PC[3:0]). To ensure
-                                            // that the JTAG port is not
-                                            // accidentally programmed as GPIO
-                                            // pins@@ the PC[3:0] pins default
-                                            // to non-committable. Similarly@@
-                                            // to ensure that the NMI pin is not
-                                            // accidentally programmed as a GPIO
-                                            // pin@@ the PD7 and PF0 pins
-                                            // default to non-committable.
-                                            // Because of this@@ the default
-                                            // reset value of GPIOCR for GPIO
-                                            // Port C is 0x0000.00F0@@ for GPIO
-                                            // Port D is 0x0000.007F@@ and for
-                                            // GPIO Port F is 0x0000.00FE.
-#define GPIO_GPIO_CR_CR_S       0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_AMSEL register.
-//
-//******************************************************************************
-#define GPIO_GPIO_AMSEL_GPIO_AMSEL_M \
-                                0x000000FF  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) GPIO Analog
-                                            // Mode Select Value Description 1
-                                            // The analog function of the pin is
-                                            // enabled@@ the isolation is
-                                            // disabled@@ and the pin is capable
-                                            // of analog functions. 0 The analog
-                                            // function of the pin is disabled@@
-                                            // the isolation is enabled@@ and
-                                            // the pin is capable of digital
-                                            // functions as specified by the
-                                            // other GPIO configuration
-                                            // registers. Note: This register
-                                            // and bits are only valid for GPIO
-                                            // signals that share analog
-                                            // function through a unified I/O
-                                            // pad. The reset state of this
-                                            // register is 0 for all signals.
-
-#define GPIO_GPIO_AMSEL_GPIO_AMSEL_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_PCTL register.
-//
-//******************************************************************************
-#define GPIO_GPIO_PCTL_PMC7_M   0xF0000000  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) Port Mux
-                                            // Control 7 This field controls the
-                                            // configuration for GPIO pin 7.
-#define GPIO_GPIO_PCTL_PMC7_S   28
-#define GPIO_GPIO_PCTL_PMC6_M   0x0F000000  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) Port Mux
-                                            // Control 6 This field controls the
-                                            // configuration for GPIO pin 6.
-#define GPIO_GPIO_PCTL_PMC6_S   24
-#define GPIO_GPIO_PCTL_PMC5_M   0x00F00000  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) Port Mux
-                                            // Control 5 This field controls the
-                                            // configuration for GPIO pin 5.
-#define GPIO_GPIO_PCTL_PMC5_S   20
-#define GPIO_GPIO_PCTL_PMC4_M   0x000F0000  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) Port Mux
-                                            // Control 4 This field controls the
-                                            // configuration for GPIO pin 4.
-#define GPIO_GPIO_PCTL_PMC4_S   16
-#define GPIO_GPIO_PCTL_PMC3_M   0x0000F000  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) Port Mux
-                                            // Control 43 This field controls
-                                            // the configuration for GPIO pin 3.
-#define GPIO_GPIO_PCTL_PMC3_S   12
-#define GPIO_GPIO_PCTL_PMC1_M   0x00000F00  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) Port Mux
-                                            // Control 1 This field controls the
-                                            // configuration for GPIO pin 1.
-#define GPIO_GPIO_PCTL_PMC1_S   8
-#define GPIO_GPIO_PCTL_PMC2_M   0x000000F0  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) Port Mux
-                                            // Control 2 This field controls the
-                                            // configuration for GPIO pin 2.
-#define GPIO_GPIO_PCTL_PMC2_S   4
-#define GPIO_GPIO_PCTL_PMC0_M   0x0000000F  // This register is not used in
-                                            // cc3xx. equivalant register exsist
-                                            // outside GPIO IP (refer
-                                            // PAD*_config register in the
-                                            // shared comn space) Port Mux
-                                            // Control 0 This field controls the
-                                            // configuration for GPIO pin 0.
-#define GPIO_GPIO_PCTL_PMC0_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPIO_O_GPIO_ADCCTL register.
-//
-//******************************************************************************
-#define GPIO_GPIO_ADCCTL_ADCEN_M \
-                                0x000000FF  // This register is not used in
-                                            // cc3xx. ADC trigger via GPIO is
-                                            // not supported. ADC Trigger Enable
-                                            // Value Description 1 The
-                                            // corresponding pin is used to
-                                            // trigger the ADC. 0 The
-                                            // corresponding pin is not used to
-                                            // trigger the ADC.
-
-#define GPIO_GPIO_ADCCTL_ADCEN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPIO_O_GPIO_DMACTL register.
-//
-//******************************************************************************
-#define GPIO_GPIO_DMACTL_DMAEN_M \
-                                0x000000FF  // This register is not used in the
-                                            // cc3xx. Alternate register to
-                                            // support this feature is coded in
-                                            // the APPS_NWP_CMN space. refer
-                                            // register as offset 0x400F70D8
-                                            // ?DMA Trigger Enable Value
-                                            // Description 1 The corresponding
-                                            // pin is used to trigger the ?DMA.
-                                            // 0 The corresponding pin is not
-                                            // used to trigger the ?DMA.
-
-#define GPIO_GPIO_DMACTL_DMAEN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIO_SI register.
-//
-//******************************************************************************
-#define GPIO_GPIO_SI_SUM        0x00000001  // Summary Interrupt Value
-                                            // Description 1 Each pin has its
-                                            // own interrupt vector. 0 All port
-                                            // pin interrupts are OR'ed together
-                                            // to produce a summary interrupt.
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPIO_O_GPIO_PERIPHID4 register.
-//
-//******************************************************************************
-#define GPIO_GPIO_PERIPHID4_PID4_M \
-                                0x000000FF  // This register is not used in
-                                            // CC3XX. GPIO Peripheral ID
-                                            // Register [7:0]
-
-#define GPIO_GPIO_PERIPHID4_PID4_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPIO_O_GPIO_PERIPHID5 register.
-//
-//******************************************************************************
-#define GPIO_GPIO_PERIPHID5_PID5_M \
-                                0x000000FF  // This register is not used in
-                                            // CC3XX. GPIO Peripheral ID
-                                            // Register [15:8]
-
-#define GPIO_GPIO_PERIPHID5_PID5_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPIO_O_GPIO_PERIPHID6 register.
-//
-//******************************************************************************
-#define GPIO_GPIO_PERIPHID6_PID6_M \
-                                0x000000FF  // This register is not used in
-                                            // CC3XX. GPIO Peripheral ID
-                                            // Register [23:16]
-
-#define GPIO_GPIO_PERIPHID6_PID6_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPIO_O_GPIO_PERIPHID7 register.
-//
-//******************************************************************************
-#define GPIO_GPIO_PERIPHID7_PID7_M \
-                                0x000000FF  // This register is not used in
-                                            // CC3XX. GPIO Peripheral ID
-                                            // Register [31:24]
-
-#define GPIO_GPIO_PERIPHID7_PID7_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPIO_O_GPIO_PERIPHID0 register.
-//
-//******************************************************************************
-#define GPIO_GPIO_PERIPHID0_PID0_M \
-                                0x000000FF  // This register is not used in
-                                            // CC3XX. GPIO Peripheral ID
-                                            // Register [7:0] Can be used by
-                                            // software to identify the presence
-                                            // of this peripheral.
-
-#define GPIO_GPIO_PERIPHID0_PID0_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPIO_O_GPIO_PERIPHID1 register.
-//
-//******************************************************************************
-#define GPIO_GPIO_PERIPHID1_PID1_M \
-                                0x000000FF  // GPIO Peripheral ID Register
-                                            // [15:8] Can be used by software to
-                                            // identify the presence of this
-                                            // peripheral.
-
-#define GPIO_GPIO_PERIPHID1_PID1_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPIO_O_GPIO_PERIPHID2 register.
-//
-//******************************************************************************
-#define GPIO_GPIO_PERIPHID2_PID2_M \
-                                0x000000FF  // This register is not used in
-                                            // CC3XX.v GPIO Peripheral ID
-                                            // Register [23:16] Can be used by
-                                            // software to identify the presence
-                                            // of this peripheral.
-
-#define GPIO_GPIO_PERIPHID2_PID2_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPIO_O_GPIO_PERIPHID3 register.
-//
-//******************************************************************************
-#define GPIO_GPIO_PERIPHID3_PID3_M \
-                                0x000000FF  // This register is not used in
-                                            // CC3XX. GPIO Peripheral ID
-                                            // Register [31:24] Can be used by
-                                            // software to identify the presence
-                                            // of this peripheral.
-
-#define GPIO_GPIO_PERIPHID3_PID3_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPIO_O_GPIO_PCELLID0 register.
-//
-//******************************************************************************
-#define GPIO_GPIO_PCELLID0_CID0_M \
-                                0x000000FF  // This register is not used in
-                                            // CC3XX. GPIO PrimeCell ID Register
-                                            // [7:0] Provides software a
-                                            // standard cross-peripheral
-                                            // identification system.
-
-#define GPIO_GPIO_PCELLID0_CID0_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPIO_O_GPIO_PCELLID1 register.
-//
-//******************************************************************************
-#define GPIO_GPIO_PCELLID1_CID1_M \
-                                0x000000FF  // This register is not used in
-                                            // CC3XX. GPIO PrimeCell ID Register
-                                            // [15:8] Provides software a
-                                            // standard cross-peripheral
-                                            // identification system.
-
-#define GPIO_GPIO_PCELLID1_CID1_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPIO_O_GPIO_PCELLID2 register.
-//
-//******************************************************************************
-#define GPIO_GPIO_PCELLID2_CID2_M \
-                                0x000000FF  // This register is not used in
-                                            // CC3XX. GPIO PrimeCell ID Register
-                                            // [23:16] Provides software a
-                                            // standard cross-peripheral
-                                            // identification system.
-
-#define GPIO_GPIO_PCELLID2_CID2_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPIO_O_GPIO_PCELLID3 register.
-//
-//******************************************************************************
-#define GPIO_GPIO_PCELLID3_CID3_M \
-                                0x000000FF  // This register is not used in
-                                            // CC3XX. GPIO PrimeCell ID Register
-                                            // [31:24] Provides software a
-                                            // standard cross-peripheral
-                                            // identification system.
-
-#define GPIO_GPIO_PCELLID3_CID3_S 0
-
-
-
-#endif // __HW_GPIO_H__
diff --git a/cc3200/hal/inc/hw_gprcm.h b/cc3200/hal/inc/hw_gprcm.h
deleted file mode 100644
index 43628f4ab..000000000
--- a/cc3200/hal/inc/hw_gprcm.h
+++ /dev/null
@@ -1,3322 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_GPRCM_H__
-#define __HW_GPRCM_H__
-
-//*****************************************************************************
-//
-// The following are defines for the GPRCM register offsets.
-//
-//*****************************************************************************
-#define GPRCM_O_APPS_SOFT_RESET 0x00000000
-#define GPRCM_O_APPS_LPDS_WAKEUP_CFG \
-                                0x00000004
-
-#define GPRCM_O_APPS_LPDS_WAKEUP_SRC \
-                                0x00000008
-
-#define GPRCM_O_APPS_RESET_CAUSE \
-                                0x0000000C
-
-#define GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG \
-                                0x00000010
-
-#define GPRCM_O_APPS_SRAM_DSLP_CFG \
-                                0x00000018
-
-#define GPRCM_O_APPS_SRAM_LPDS_CFG \
-                                0x0000001C
-
-#define GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG \
-                                0x00000020
-
-#define GPRCM_O_TOP_DIE_ENABLE  0x00000100
-#define GPRCM_O_TOP_DIE_ENABLE_PARAMETERS \
-                                0x00000104
-
-#define GPRCM_O_MCU_GLOBAL_SOFT_RESET \
-                                0x00000108
-
-#define GPRCM_O_ADC_CLK_CONFIG  0x0000010C
-#define GPRCM_O_APPS_GPIO_WAKE_CONF \
-                                0x00000110
-
-#define GPRCM_O_EN_NWP_BOOT_WO_DEVINIT \
-                                0x00000114
-
-#define GPRCM_O_MEM_HCLK_DIV_CFG \
-                                0x00000118
-
-#define GPRCM_O_MEM_SYSCLK_DIV_CFG \
-                                0x0000011C
-
-#define GPRCM_O_APLLMCS_LOCK_TIME_CONF \
-                                0x00000120
-
-#define GPRCM_O_NWP_SOFT_RESET  0x00000400
-#define GPRCM_O_NWP_LPDS_WAKEUP_CFG \
-                                0x00000404
-
-#define GPRCM_O_NWP_LPDS_WAKEUP_SRC \
-                                0x00000408
-
-#define GPRCM_O_NWP_RESET_CAUSE 0x0000040C
-#define GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG \
-                                0x00000410
-
-#define GPRCM_O_NWP_SRAM_DSLP_CFG \
-                                0x00000418
-
-#define GPRCM_O_NWP_SRAM_LPDS_CFG \
-                                0x0000041C
-
-#define GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG \
-                                0x00000420
-
-#define GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL \
-                                0x00000424
-
-#define GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ \
-                                0x00000428
-
-#define GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST \
-                                0x0000042C
-
-#define GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST \
-                                0x00000430
-
-#define GPRCM_O_NWP_GPIO_WAKE_CONF \
-                                0x00000434
-
-#define GPRCM_O_GPRCM_EFUSE_READ_REG12 \
-                                0x00000438
-
-#define GPRCM_O_GPRCM_DIEID_READ_REG5 \
-                                0x00000448
-
-#define GPRCM_O_GPRCM_DIEID_READ_REG6 \
-                                0x0000044C
-
-#define GPRCM_O_REF_FSM_CFG0    0x00000800
-#define GPRCM_O_REF_FSM_CFG1    0x00000804
-#define GPRCM_O_APLLMCS_WLAN_CONFIG0_40 \
-                                0x00000808
-
-#define GPRCM_O_APLLMCS_WLAN_CONFIG1_40 \
-                                0x0000080C
-
-#define GPRCM_O_APLLMCS_WLAN_CONFIG0_26 \
-                                0x00000810
-
-#define GPRCM_O_APLLMCS_WLAN_CONFIG1_26 \
-                                0x00000814
-
-#define GPRCM_O_APLLMCS_WLAN_OVERRIDES \
-                                0x00000818
-
-#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 \
-                                0x0000081C
-
-#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 \
-                                0x00000820
-
-#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 \
-                                0x00000824
-
-#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 \
-                                0x00000828
-
-#define GPRCM_O_SPARE_RW0       0x0000082C
-#define GPRCM_O_SPARE_RW1       0x00000830
-#define GPRCM_O_APLLMCS_MCU_OVERRIDES \
-                                0x00000834
-
-#define GPRCM_O_SYSCLK_SWITCH_STATUS \
-                                0x00000838
-
-#define GPRCM_O_REF_LDO_CONTROLS \
-                                0x0000083C
-
-#define GPRCM_O_REF_RTRIM_CONTROL \
-                                0x00000840
-
-#define GPRCM_O_REF_SLICER_CONTROLS0 \
-                                0x00000844
-
-#define GPRCM_O_REF_SLICER_CONTROLS1 \
-                                0x00000848
-
-#define GPRCM_O_REF_ANA_BGAP_CONTROLS0 \
-                                0x0000084C
-
-#define GPRCM_O_REF_ANA_BGAP_CONTROLS1 \
-                                0x00000850
-
-#define GPRCM_O_REF_ANA_SPARE_CONTROLS0 \
-                                0x00000854
-
-#define GPRCM_O_REF_ANA_SPARE_CONTROLS1 \
-                                0x00000858
-
-#define GPRCM_O_MEMSS_PSCON_OVERRIDES0 \
-                                0x0000085C
-
-#define GPRCM_O_MEMSS_PSCON_OVERRIDES1 \
-                                0x00000860
-
-#define GPRCM_O_PLL_REF_LOCK_OVERRIDES \
-                                0x00000864
-
-#define GPRCM_O_MCU_PSCON_DEBUG 0x00000868
-#define GPRCM_O_MEMSS_PWR_PS    0x0000086C
-#define GPRCM_O_REF_FSM_DEBUG   0x00000870
-#define GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE \
-                                0x00000874
-
-#define GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG \
-                                0x00000878
-
-#define GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES \
-                                0x0000087C
-
-#define GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES \
-                                0x00000880
-
-#define GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES \
-                                0x00000884
-
-#define GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES \
-                                0x00000888
-
-#define GPRCM_O_MEM_REF_FSM_CFG2 \
-                                0x0000088C
-
-#define GPRCM_O_TESTCTRL_POWER_CTRL \
-                                0x00000C10
-
-#define GPRCM_O_SSDIO_POWER_CTRL \
-                                0x00000C14
-
-#define GPRCM_O_MCSPI_N1_POWER_CTRL \
-                                0x00000C18
-
-#define GPRCM_O_WELP_POWER_CTRL 0x00000C1C
-#define GPRCM_O_WL_SDIO_POWER_CTRL \
-                                0x00000C20
-
-#define GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG \
-                                0x00000C24
-
-#define GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG \
-                                0x00000C28
-
-#define GPRCM_O_APPS_SECURE_INIT_DONE \
-                                0x00000C30
-
-#define GPRCM_O_APPS_DEV_MODE_INIT_DONE \
-                                0x00000C34
-
-#define GPRCM_O_EN_APPS_REBOOT  0x00000C38
-#define GPRCM_O_MEM_APPS_PERIPH_PRESENT \
-                                0x00000C3C
-
-#define GPRCM_O_MEM_NWP_PERIPH_PRESENT \
-                                0x00000C40
-
-#define GPRCM_O_MEM_SHARED_PERIPH_PRESENT \
-                                0x00000C44
-
-#define GPRCM_O_NWP_PWR_STATE   0x00000C48
-#define GPRCM_O_APPS_PWR_STATE  0x00000C4C
-#define GPRCM_O_MCU_PWR_STATE   0x00000C50
-#define GPRCM_O_WTOP_PM_PS      0x00000C54
-#define GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG \
-                                0x00000C58
-
-#define GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG \
-                                0x00000C5C
-
-#define GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG \
-                                0x00000C60
-
-#define GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG \
-                                0x00000C64
-
-#define GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG \
-                                0x00000C68
-
-#define GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG \
-                                0x00000C6C
-
-#define GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG \
-                                0x00000C70
-
-#define GPRCM_O_GPRCM_EFUSE_READ_REG0 \
-                                0x00000C78
-
-#define GPRCM_O_GPRCM_EFUSE_READ_REG1 \
-                                0x00000C7C
-
-#define GPRCM_O_GPRCM_EFUSE_READ_REG2 \
-                                0x00000C80
-
-#define GPRCM_O_GPRCM_EFUSE_READ_REG3 \
-                                0x00000C84
-
-#define GPRCM_O_WTOP_MEM_RET_CFG \
-                                0x00000C88
-
-#define GPRCM_O_COEX_CLK_SWALLOW_CFG0 \
-                                0x00000C8C
-
-#define GPRCM_O_COEX_CLK_SWALLOW_CFG1 \
-                                0x00000C90
-
-#define GPRCM_O_COEX_CLK_SWALLOW_CFG2 \
-                                0x00000C94
-
-#define GPRCM_O_COEX_CLK_SWALLOW_ENABLE \
-                                0x00000C98
-
-#define GPRCM_O_DCDC_CLK_GEN_CONFIG \
-                                0x00000C9C
-
-#define GPRCM_O_GPRCM_EFUSE_READ_REG4 \
-                                0x00000CA0
-
-#define GPRCM_O_GPRCM_EFUSE_READ_REG5 \
-                                0x00000CA4
-
-#define GPRCM_O_GPRCM_EFUSE_READ_REG6 \
-                                0x00000CA8
-
-#define GPRCM_O_GPRCM_EFUSE_READ_REG7 \
-                                0x00000CAC
-
-#define GPRCM_O_GPRCM_EFUSE_READ_REG8 \
-                                0x00000CB0
-
-#define GPRCM_O_GPRCM_EFUSE_READ_REG9 \
-                                0x00000CB4
-
-#define GPRCM_O_GPRCM_EFUSE_READ_REG10 \
-                                0x00000CB8
-
-#define GPRCM_O_GPRCM_EFUSE_READ_REG11 \
-                                0x00000CBC
-
-#define GPRCM_O_GPRCM_DIEID_READ_REG0 \
-                                0x00000CC0
-
-#define GPRCM_O_GPRCM_DIEID_READ_REG1 \
-                                0x00000CC4
-
-#define GPRCM_O_GPRCM_DIEID_READ_REG2 \
-                                0x00000CC8
-
-#define GPRCM_O_GPRCM_DIEID_READ_REG3 \
-                                0x00000CCC
-
-#define GPRCM_O_GPRCM_DIEID_READ_REG4 \
-                                0x00000CD0
-
-#define GPRCM_O_APPS_SS_OVERRIDES \
-                                0x00000CD4
-
-#define GPRCM_O_NWP_SS_OVERRIDES \
-                                0x00000CD8
-
-#define GPRCM_O_SHARED_SS_OVERRIDES \
-                                0x00000CDC
-
-#define GPRCM_O_IDMEM_CORE_RST_OVERRIDES \
-                                0x00000CE0
-
-#define GPRCM_O_TOP_DIE_FSM_OVERRIDES \
-                                0x00000CE4
-
-#define GPRCM_O_MCU_PSCON_OVERRIDES \
-                                0x00000CE8
-
-#define GPRCM_O_WTOP_PSCON_OVERRIDES \
-                                0x00000CEC
-
-#define GPRCM_O_WELP_PSCON_OVERRIDES \
-                                0x00000CF0
-
-#define GPRCM_O_WL_SDIO_PSCON_OVERRIDES \
-                                0x00000CF4
-
-#define GPRCM_O_MCSPI_PSCON_OVERRIDES \
-                                0x00000CF8
-
-#define GPRCM_O_SSDIO_PSCON_OVERRIDES \
-                                0x00000CFC
-
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APPS_SOFT_RESET register.
-//
-//******************************************************************************
-#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET1 \
-                                0x00000002  // Soft-reset1 for APPS : Cortex
-                                            // sysrstn is asserted and in
-                                            // addition to that the associated
-                                            // APPS Peripherals are also reset.
-                                            // This is an auto-clear bit.
-
-#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET0 \
-                                0x00000001  // Soft-reset0 for APPS : Only
-                                            // sys-resetn for Cortex will be
-                                            // asserted. This is an auto-clear
-                                            // bit.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APPS_LPDS_WAKEUP_CFG register.
-//
-//******************************************************************************
-#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_M \
-                                0x000000FF  // Mask for LPDS Wakeup interrupt :
-                                            // [7] - Host IRQ from NWP [6] -
-                                            // NWP_LPDS_Wake_irq (TRUE_LPDS) [5]
-                                            // - NWP Wake-request to APPS [4] -
-                                            // GPIO [3:1] - Reserved [0] - LPDS
-                                            // Wakeup-timer
-
-#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APPS_LPDS_WAKEUP_SRC register.
-//
-//******************************************************************************
-#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_M \
-                                0x000000FF  // Indicates the cause for wakeup
-                                            // from LPDS : [7] - Host IRQ from
-                                            // NWP [6] - NWP_LPDS_Wake_irq
-                                            // (TRUE_LPDS) [5] - NWP
-                                            // Wake-request to APPS [4] - GPIO
-                                            // [3:1] - Reserved [0] - LPDS
-                                            // Wakeup-timer
-
-#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APPS_RESET_CAUSE register.
-//
-//******************************************************************************
-#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_M \
-                                0x000000FF  // Indicates the reset cause for
-                                            // APPS : "0000" - Wake from HIB/OFF
-                                            // mode; "0001" - Wake from LPDS ;
-                                            // "0010" - Reserved ; "0011" -
-                                            // Soft-reset0 (Only APPS
-                                            // Cortex-sysrstn is asserted);
-                                            // "0100" - Soft-reset1 (APPS
-                                            // Cortex-sysrstn and APPS
-                                            // peripherals are reset); "0101" -
-                                            // WDOG0 (APPS Cortex-sysrstn and
-                                            // APPS peripherals are reset);
-                                            // "0110" - MCU Soft-reset (APPS +
-                                            // NWP Cortex-sysrstn + Peripherals
-                                            // are reset); "0111" - Secure Init
-                                            // done (Indication that reset has
-                                            // happened after DevInit); "1000" -
-                                            // Dev Mode Patch Init done (During
-                                            // development mode, patch
-                                            // downloading and Cortex
-                                            // re-vectoring is completed)
-
-#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG register.
-//
-//******************************************************************************
-#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_M \
-                                0xFFFFFFFF  // OPP Request Configuration
-                                            // (Number of slow-clk cycles) for
-                                            // LPDS Wake-timer : This
-                                            // configuration implies the RTC
-                                            // time-stamp, which must be few
-                                            // slow-clks prior to
-                                            // APPS_LPDS_WAKETIME_WAKE_CFG, such
-                                            // that by the time actual wakeup is
-                                            // given, OPP is already switched to
-                                            // ACTIVE (RUN).
-
-#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APPS_SRAM_DSLP_CFG register.
-//
-//******************************************************************************
-#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_M \
-                                0x000FFFFF  // Configuration of APPS Memories
-                                            // during Deep-sleep : 0 - SRAMs are
-                                            // OFF ; 1 - SRAMs are Retained.
-                                            // APPS SRAM Cluster information :
-                                            // [0] - 1st column in MEMSS
-                                            // (Applicable only when owned by
-                                            // APPS); [1] - 2nd column in MEMSS
-                                            // (Applicable only when owned by
-                                            // APPS); [2] - 3rd column in MEMSS
-                                            // (Applicable only when owned by
-                                            // APPS) ; [3] - 4th column in MEMSS
-                                            // (Applicable only when owned by
-                                            // APPS) ; [16] - MCU-PD - Apps
-                                            // cluster 0 (TBD); [19:18] -
-                                            // Reserved.
-
-#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APPS_SRAM_LPDS_CFG register.
-//
-//******************************************************************************
-#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_M \
-                                0x000FFFFF  // Configuration of APPS Memories
-                                            // during LPDS : 0 - SRAMs are OFF ;
-                                            // 1 - SRAMs are Retained. APPS SRAM
-                                            // Cluster information : [0] - 1st
-                                            // column in MEMSS (Applicable only
-                                            // when owned by APPS); [1] - 2nd
-                                            // column in MEMSS (Applicable only
-                                            // when owned by APPS); [2] - 3rd
-                                            // column in MEMSS (Applicable only
-                                            // when owned by APPS) ; [3] - 4th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by APPS) ; [16] -
-                                            // MCU-PD - Apps cluster 0 (TBD);
-                                            // [19:18] - Reserved.
-
-#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG register.
-//
-//******************************************************************************
-#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_M \
-                                0xFFFFFFFF  // Configuration (in no of
-                                            // slow_clks) which says when the
-                                            // actual wakeup request for
-                                            // removing the PD-reset be given.
-
-#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_TOP_DIE_ENABLE register.
-//
-//******************************************************************************
-#define GPRCM_TOP_DIE_ENABLE_FLASH_BUSY \
-                                0x00001000
-
-#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_M \
-                                0x00000F00
-
-#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_S 8
-#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE_STATUS \
-                                0x00000002  // 1 - Top-die is enabled ;
-
-#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE \
-                                0x00000001  // 1 - Enable the top-die ; 0 -
-                                            // Disable the top-die
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_TOP_DIE_ENABLE_PARAMETERS register.
-//
-//******************************************************************************
-#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_M \
-                                0xF0000000  // Configuration (in slow_clks) for
-                                            // number of clks between
-                                            // Flash-3p3-rstn to D2D POR Resetn.
-
-#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_S 28
-#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_M \
-                                0x00FF0000  // Configuration (in slow_clks) for
-                                            // number of clks between Top-die
-                                            // Switch-Enable and Top-die Flash
-                                            // 3p3 Reset removal
-
-#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_S 16
-#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_M \
-                                0x000000FF  // Configuration (in slow_clks) for
-                                            // number of clks between D2D POR
-                                            // Reset removal and bottom die FMC
-                                            // reset removal
-
-#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MCU_GLOBAL_SOFT_RESET register.
-//
-//******************************************************************************
-#define GPRCM_MCU_GLOBAL_SOFT_RESET_MCU_GLOBAL_SOFT_RESET \
-                                0x00000001  // 1 - Assert the global reset for
-                                            // MCU (APPS + NWP) ; Asserts both
-                                            // Cortex sysrstn and its
-                                            // peripherals 0 - Deassert the
-                                            // global reset for MCU (APPS + NWP)
-                                            // ; Asserts both Cortex sysrstn and
-                                            // its peripherals Note : Reset for
-                                            // shared peripherals is not
-                                            // affected here.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_ADC_CLK_CONFIG register.
-//
-//******************************************************************************
-#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_M \
-                                0x000007C0  // Configuration (in number of 38.4
-                                            // MHz clks) for the OFF-Time in
-                                            // generation of ADC_CLK
-
-#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_S 6
-#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_M \
-                                0x0000003E  // Configuration (in number of 38.4
-                                            // MHz clks) for the ON-Time in
-                                            // generation of ADC_CLK
-
-#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_S 1
-#define GPRCM_ADC_CLK_CONFIG_ADC_CLK_ENABLE \
-                                0x00000001  // 1 - Enable the ADC_CLK ; 0 -
-                                            // Disable the ADC_CLK
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APPS_GPIO_WAKE_CONF register.
-//
-//******************************************************************************
-#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_M \
-                                0x00000003  // "00" - Wake on Level0 on
-                                            // selected GPIO pin (GPIO is
-                                            // selected inside the HIB3p3
-                                            // module); "01" - Wakeup on
-                                            // fall-edge of GPIO pin.
-
-#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_EN_NWP_BOOT_WO_DEVINIT register.
-//
-//******************************************************************************
-#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_M \
-                                0xFFFFFFFE
-
-#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_S 1
-#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_mem_en_nwp_boot_wo_devinit \
-                                0x00000001  // 1 - Override the secure-mode
-                                            // done for booting up NWP (Wakeup
-                                            // NWP on its event independent of
-                                            // CM4 state) ; 0 - Donot override
-                                            // the secure-mode done for NWP boot
-                                            // (NWP must be enabled by CM4 only)
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MEM_HCLK_DIV_CFG register.
-//
-//******************************************************************************
-#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_M \
-                                0x00000007  // Division configuration for
-                                            // HCLKDIVOUT : "000" - Divide by 1
-                                            // ; "001" - Divide by 2 ; "010" -
-                                            // Divide by 3 ; "011" - Divide by 4
-                                            // ; "100" - Divide by 5 ; "101" -
-                                            // Divide by 6 ; "110" - Divide by 7
-                                            // ; "111" - Divide by 8
-
-#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MEM_SYSCLK_DIV_CFG register.
-//
-//******************************************************************************
-#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_M \
-                                0x00000038
-
-#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_S 3
-#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_M \
-                                0x00000007
-
-#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APLLMCS_LOCK_TIME_CONF register.
-//
-//******************************************************************************
-#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_M \
-                                0x0000FF00
-
-#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_S 8
-#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_M \
-                                0x000000FF
-
-#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_NWP_SOFT_RESET register.
-//
-//******************************************************************************
-#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET1 \
-                                0x00000002  // Soft-reset1 for NWP - Cortex
-                                            // sysrstn and NWP associated
-                                            // peripherals are - This is an
-                                            // auto-clr bit.
-
-#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET0 \
-                                0x00000001  // Soft-reset0 for NWP - Only
-                                            // Cortex-sysrstn is asserted - This
-                                            // is an auto-clear bit.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_NWP_LPDS_WAKEUP_CFG register.
-//
-//******************************************************************************
-#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_M \
-                                0x000000FF  // Mask for LPDS Wakeup interrupt :
-                                            // 7 - WLAN Host Interrupt ; 6 -
-                                            // WLAN to NWP Wake request ; 5 -
-                                            // APPS to NWP Wake request; 4 -
-                                            // GPIO Wakeup ; 3 - Autonomous UART
-                                            // Wakeup ; 2 - SSDIO Wakeup ; 1 -
-                                            // Autonomous SPI Wakeup ; 0 - LPDS
-                                            // Wakeup-timer
-
-#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_NWP_LPDS_WAKEUP_SRC register.
-//
-//******************************************************************************
-#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_M \
-                                0x000000FF  // Indicates the cause for NWP
-                                            // LPDS-Wakeup : 7 - WLAN Host
-                                            // Interrupt ; 6 - WLAN to NWP Wake
-                                            // request ; 5 - APPS to NWP Wake
-                                            // request; 4 - GPIO Wakeup ; 3 -
-                                            // Autonomous UART Wakeup ; 2 -
-                                            // SSDIO Wakeup ; 1 - Autonomous SPI
-                                            // Wakeup ; 0 - LPDS Wakeup-timer
-
-#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_NWP_RESET_CAUSE register.
-//
-//******************************************************************************
-#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_M \
-                                0x000000FF  // Indicates the reset cause for
-                                            // NWP : "0000" - Wake from HIB/OFF
-                                            // mode; "0001" - Wake from LPDS ;
-                                            // "0010" - Reserved ; "0011" -
-                                            // Soft-reset0 (Only NWP
-                                            // Cortex-sysrstn is asserted);
-                                            // "0100" - Soft-reset1 (NWP
-                                            // Cortex-sysrstn and NWP
-                                            // peripherals are reset); "0101" -
-                                            // WDOG0 (NWP Cortex-sysrstn and NWP
-                                            // peripherals are reset); "0110" -
-                                            // MCU Soft-reset (APPS + NWP
-                                            // Cortex-sysrstn + Peripherals are
-                                            // reset); "0111" - SSDIO Function2
-                                            // reset (Only Cortex-sysrstn is
-                                            // asserted) ; "1000" - Reset due to
-                                            // WDOG of APPS (NWP Cortex-sysrstn
-                                            // and NWP peripherals are reset);
-
-#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG register.
-//
-//******************************************************************************
-#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_M \
-                                0xFFFFFFFF  // OPP Request Configuration
-                                            // (Number of slow-clk cycles) for
-                                            // LPDS Wake-timer
-
-#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_NWP_SRAM_DSLP_CFG register.
-//
-//******************************************************************************
-#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_M \
-                                0x000FFFFF  // Configuration of NWP Memories
-                                            // during DSLP : 0 - SRAMs are OFF ;
-                                            // 1 - SRAMs are Retained. NWP SRAM
-                                            // Cluster information : [2] - 3rd
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [3] - 4th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [4] - 5th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [5] - 6th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [6] - 7th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [7] - 8th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [8] - 9th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [9] - 10th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [10] - 11th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [11] - 12th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [12] - 13th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [13] - 14th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [14] - 15th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [19:18] -
-                                            // Reserved.
-
-#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_NWP_SRAM_LPDS_CFG register.
-//
-//******************************************************************************
-#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_M \
-                                0x000FFFFF  // Configuration of NWP Memories
-                                            // during LPDS : 0 - SRAMs are OFF ;
-                                            // 1 - SRAMs are Retained. NWP SRAM
-                                            // Cluster information : [2] - 3rd
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [3] - 4th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [4] - 5th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [5] - 6th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [6] - 7th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [7] - 8th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [8] - 9th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [9] - 10th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [10] - 11th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [11] - 12th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [12] - 13th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [13] - 14th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [14] - 15th
-                                            // column in MEMSS (Applicable only
-                                            // when owned by NWP) ; [19:18] -
-                                            // Reserved.
-
-#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG register.
-//
-//******************************************************************************
-#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_M \
-                                0xFFFFFFFF  // Wake time configuration (no of
-                                            // slow clks) for NWP wake from
-                                            // LPDS.
-
-#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL register.
-//
-//******************************************************************************
-#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_M \
-                                0xFFFE0000
-
-#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_S 17
-#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_MEM_AUTONMS_SPI_MASTER_SEL \
-                                0x00010000  // 0 - APPS is selected as host for
-                                            // Autonms SPI ; 1 - External host
-                                            // is selected as host for Autonms
-                                            // SPI
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ register.
-//
-//******************************************************************************
-#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_WAKEUP \
-                                0x00010000
-
-#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_ACK \
-                                0x00000002  // When 1 => IDLE-mode is
-                                            // acknowledged by the SPI-IP. (This
-                                            // is for MCSPI_N1)
-
-#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_REQ \
-                                0x00000001  // When 1 => Request for IDLE-mode
-                                            // for autonomous SPI. (This is for
-                                            // MCSPI_N1)
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST register.
-//
-//******************************************************************************
-#define GPRCM_WLAN_TO_NWP_WAKE_REQUEST_WLAN_TO_NWP_WAKE_REQUEST \
-                                0x00000001  // 1 - Request for waking up NWP
-                                            // from any of its low-power modes
-                                            // (SLP/DSLP/LPDS)
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST register.
-//
-//******************************************************************************
-#define GPRCM_NWP_TO_WLAN_WAKE_REQUEST_NWP_TO_WLAN_WAKE_REQUEST \
-                                0x00000001  // 1 - Request for wakinp up WLAN
-                                            // from its ELP Mode (This gets
-                                            // triggered to ELP-logic of WLAN)
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_NWP_GPIO_WAKE_CONF register.
-//
-//******************************************************************************
-#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_M \
-                                0x00000003  // "00" - Wakeup on level0 of the
-                                            // selected GPIO (GPIO gets selected
-                                            // inside HIB3P3-module); "01" -
-                                            // Wakeup on fall-edge of selected
-                                            // GPIO.
-
-#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_EFUSE_READ_REG12 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_M \
-                                0x0000FFFF  // This corrsponds to ROW_32
-                                            // [31:16] of the FUSEFARM. SPARE
-
-#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_DIEID_READ_REG5 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_M \
-                                0xFFFFFFFF  // Corresponds to ROW10 of FUSEFARM
-                                            // : [5:0] - ADC OFFSET ; [13:6] -
-                                            // TEMP_SENSE ; [14:14] - DFT_GSG ;
-                                            // [15:15] - FMC_DISABLE ; [31:16] -
-                                            // WLAN_MAC ID
-
-#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_DIEID_READ_REG6 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_M \
-                                0xFFFFFFFF  // Corresponds to ROW11 of FUSEFARM
-                                            // : [31:0] : WLAN MAC ID
-
-#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_REF_FSM_CFG0 register.
-//
-//******************************************************************************
-#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_M \
-                                0x00FF0000  // ANA-BGAP Settling time (In
-                                            // number of slow_clks)
-
-#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_S 16
-#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_M \
-                                0x0000FF00  // Slicer LDO settling time (In
-                                            // number of slow clks)
-
-#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_S 8
-#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_M \
-                                0x000000FF  // Dig-buffer settling time (In
-                                            // number of slow clks)
-
-#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_REF_FSM_CFG1 register.
-//
-//******************************************************************************
-#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_M \
-                                0xFF000000  // XTAL settling time (In number of
-                                            // slow clks)
-
-#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_S 24
-#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_M \
-                                0x00FF0000  // LV Slicer settling time
-
-#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_S 16
-#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_M \
-                                0x0000FF00  // HV Slicer Pull-down settling
-                                            // time
-
-#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_S 8
-#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_M \
-                                0x000000FF  // HV Slicer settling time
-
-#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APLLMCS_WLAN_CONFIG0_40 register.
-//
-//******************************************************************************
-#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_M \
-                                0x00007F00  // Configuration for WLAN APLLMCS -
-                                            // N[6:0], if the XTAL frequency is
-                                            // 40 MHz (Selected by efuse)
-
-#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_S 8
-#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_M \
-                                0x000000FF  // Configuration for WLAN APLLMCS -
-                                            // M[7:0], if the XTAL frequency is
-                                            // 40 MHz (Selected by efuse)
-
-#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APLLMCS_WLAN_CONFIG1_40 register.
-//
-//******************************************************************************
-#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_HISPEED_40 \
-                                0x00000010  // Configuration for WLAN APLLMCS -
-                                            // if the XTAL frequency if 40 MHz
-                                            // (Selected by Efuse)
-
-#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SEL96_40 \
-                                0x00000008  // Configuration for WLAN APLLMCS -
-                                            // Sel96, if the XTAL frequency is
-                                            // 40 MHz (Selected by Efuse)
-
-#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_M \
-                                0x00000007  // Configuration for WLAN APLLMCS -
-                                            // Selinpfreq, if the XTAL frequency
-                                            // is 40 MHz (Selected by Efuse)
-
-#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APLLMCS_WLAN_CONFIG0_26 register.
-//
-//******************************************************************************
-#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_M \
-                                0x00007F00  // Configuration for WLAN APLLMCS -
-                                            // N[6:0], if the XTAL frequency is
-                                            // 26 MHz (Selected by efuse)
-
-#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_S 8
-#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_M \
-                                0x000000FF  // Configuration for WLAN APLLMCS -
-                                            // M[7:0], if the XTAL frequency is
-                                            // 26 MHz (Selected by efuse)
-
-#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APLLMCS_WLAN_CONFIG1_26 register.
-//
-//******************************************************************************
-#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_HISPEED_26 \
-                                0x00000010  // Configuration for WLAN APLLMCS -
-                                            // if the XTAL frequency if 26 MHz
-                                            // (Selected by Efuse)
-
-#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SEL96_26 \
-                                0x00000008  // Configuration for WLAN APLLMCS -
-                                            // Sel96, if the XTAL frequency is
-                                            // 26 MHz (Selected by Efuse)
-
-#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_M \
-                                0x00000007  // Configuration for WLAN APLLMCS -
-                                            // Selinpfreq, if the XTAL frequency
-                                            // is 26 MHz (Selected by Efuse)
-
-#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APLLMCS_WLAN_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_CTRL \
-                                0x00080000
-
-#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_M \
-                                0x00070000
-
-#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_S 16
-#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_M \
-                                0x00000700
-
-#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_S 8
-#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE_CTRL \
-                                0x00000020  // Override control for
-                                            // WLAN_APLLMCS_M[8]. When set to1,
-                                            // M[8] will be selected by bit [3].
-                                            // (Else controlled from WTOP)
-
-#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE \
-                                0x00000010  // Override for WLAN_APLLMCS_M[8].
-                                            // Applicable only when bit [4] is
-                                            // set to 1. (Else controlled from
-                                            // WTOP)
-
-#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_CTRL \
-                                0x00000004  // Override control for
-                                            // WLAN_APLLMCS_N[8:7]. When set
-                                            // to1, N[8:7] will be selected by
-                                            // bits [2:1]. (Else controlled from
-                                            // WTOP)
-
-#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_M \
-                                0x00000003  // Override value for
-                                            // WLAN_APLLMCS_N[8:7] bits.
-                                            // Applicable only when bit [1] is
-                                            // set to 1. (Else controlled from
-                                            // WTOP)
-
-#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 register.
-//
-//******************************************************************************
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_M \
-                                0x38000000
-
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_S 27
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_M \
-                                0x07000000
-
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_S 24
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_M \
-                                0x007F0000  // Configuration for MCU-APLLMCS :
-                                            // N during RUN mode. Selected if
-                                            // the XTAL frequency is 38.4 MHz
-                                            // (from Efuse)
-
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_S 16
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_M \
-                                0x0000FF00  // Configuration for MCU-APLLMCS :
-                                            // M during RUN mode. Selected if
-                                            // the XTAL frequency is 38.4 MHz
-                                            // (from Efuse)
-
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_S 8
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_8_38P4 \
-                                0x00000010  // Configuration for MCU-APLLMCS :
-                                            // M[8] during RUN mode. Selected if
-                                            // the XTAL frequency is 38.4 MHz
-                                            // (From Efuse)
-
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_M \
-                                0x00000003  // Configuration for MCU-APLLMCS :
-                                            // N[8:7] during RUN mode. Selected
-                                            // if the XTAL frequency is 38.4 MHz
-                                            // (From Efuse)
-
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 register.
-//
-//******************************************************************************
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_HISPEED_38P4 \
-                                0x00000010  // Configuration for MCU-APLLMCS :
-                                            // HISPEED during RUN mode. Selected
-                                            // if the XTAL frequency is 38.4 MHz
-                                            // (from Efuse)
-
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SEL96_38P4 \
-                                0x00000008  // Configuration for MCU-APLLMCS :
-                                            // SEL96 during RUN mode. Selected
-                                            // if the XTAL frequency is 38.4 MHz
-                                            // (from Efuse)
-
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_M \
-                                0x00000007  // Configuration for MCU-APLLMCS :
-                                            // SELINPFREQ during RUN mode.
-                                            // Selected if the XTAL frequency is
-                                            // 38.4 MHz (from Efuse)
-
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 register.
-//
-//******************************************************************************
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_M \
-                                0x007F0000  // Configuration for MCU-APLLMCS :
-                                            // N during RUN mode. Selected if
-                                            // the XTAL frequency is 26 MHz
-                                            // (from Efuse)
-
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_S 16
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_M \
-                                0x0000FF00  // Configuration for MCU-APLLMCS :
-                                            // M during RUN mode. Selected if
-                                            // the XTAL frequency is 26 MHz
-                                            // (from Efuse)
-
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_S 8
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_8_26 \
-                                0x00000010  // Configuration for MCU-APLLMCS :
-                                            // M[8] during RUN mode. Selected if
-                                            // the XTAL frequency is 26 MHz
-                                            // (From Efuse)
-
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_M \
-                                0x00000003  // Configuration for MCU-APLLMCS :
-                                            // N[8:7] during RUN mode. Selected
-                                            // if the XTAL frequency is 26 MHz
-                                            // (From Efuse)
-
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 register.
-//
-//******************************************************************************
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_HISPEED_26 \
-                                0x00000010  // Configuration for MCU-APLLMCS :
-                                            // HISPEED during RUN mode. Selected
-                                            // if the XTAL frequency is 26 MHz
-                                            // (from Efuse)
-
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SEL96_26 \
-                                0x00000008  // Configuration for MCU-APLLMCS :
-                                            // SEL96 during RUN mode. Selected
-                                            // if the XTAL frequency is 26 MHz
-                                            // (from Efuse)
-
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_M \
-                                0x00000007  // Configuration for MCU-APLLMCS :
-                                            // SELINPFREQ during RUN mode.
-                                            // Selected if the XTAL frequency is
-                                            // 26 MHz (from Efuse)
-
-#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPRCM_O_SPARE_RW0 register.
-//
-//******************************************************************************
-//******************************************************************************
-//
-// The following are defines for the bit fields in the GPRCM_O_SPARE_RW1 register.
-//
-//******************************************************************************
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APLLMCS_MCU_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_LOCK \
-                                0x00000400  // 1 - APLLMCS_MCU is locked ; 0 -
-                                            // APLLMCS_MCU is not locked
-
-#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE \
-                                0x00000200  // Override for APLLMCS_MCU Enable.
-                                            // Applicable if bit [8] is set
-
-#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE_CTRL \
-                                0x00000100  // 1 - Enable for APLLMCS_MCU comes
-                                            // from bit [9]. 0 - Enable for
-                                            // APLLMCS_MCU comes from FSM.
-
-#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_M \
-                                0x00000006  // Override for sysclk src
-                                            // (applicable only if bit [0] is
-                                            // set to 1. "00"- SLOW_CLK "01"-
-                                            // XTAL_CLK "10"- PLL_CLK
-
-#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_S 1
-#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_CTRL \
-                                0x00000001  // 1 - Sysclk src is selected from
-                                            // bits [2:1] of this register. 0 -
-                                            // Sysclk src is selected from FSM
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_SYSCLK_SWITCH_STATUS register.
-//
-//******************************************************************************
-#define GPRCM_SYSCLK_SWITCH_STATUS_SYSCLK_SWITCH_STATUS \
-                                0x00000001  // 1 - Sysclk switching is
-                                            // complete. 0 - Sysclk switching is
-                                            // in progress.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_REF_LDO_CONTROLS register.
-//
-//******************************************************************************
-#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE_OVERRIDE_CTRL \
-                                0x00010000  // 1 - Enable for REF_LDO comes
-                                            // from bit [0] of this register ; 0
-                                            // - Enable for REF_LDO comes from
-                                            // the FSM. Note : Final REF_LDO_EN
-                                            // reaches on the port
-                                            // TOP_PM_REG2[0] of gprcm.
-
-#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_M \
-                                0x0000C000  // Spare bits for REF_CTRL_FSM.
-                                            // Reaches directly on port
-                                            // TOP_PM_REG2[15:14] of gprcm.
-
-#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_S 14
-#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_M \
-                                0x00003800  // REF TLOAD Enable. Reaches
-                                            // directly on port
-                                            // TOP_PM_REG2[13:11] of gprcm.
-
-#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_S 11
-#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_M \
-                                0x00000700  // REF_LDO Test-mux control.
-                                            // Reaches directly on port
-                                            // TOP_PM_REG2[10:8] of gprcm.
-
-#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_S 8
-#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_M \
-                                0x000000C0  // REF BW Control. Reaches directly
-                                            // on port TOP_PM_REG2[7:6] of
-                                            // gprcm.
-
-#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_S 6
-#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_M \
-                                0x0000003C  // REF VTRIM Control. Reaches
-                                            // directly on port TOP_PM_REG2[5:2]
-                                            // of gprcm.
-
-#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_S 2
-#define GPRCM_REF_LDO_CONTROLS_REF_LDO_BYPASS_ENABLE \
-                                0x00000002  // REF LDO Bypass Enable. Reaches
-                                            // directly on port TOP_PM_REG2[1]
-                                            // of gprcm.
-
-#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE \
-                                0x00000001  // Override for REF_LDO Enable.
-                                            // Applicable only if bit [16] of
-                                            // this register is set. Note :
-                                            // Final REF_LDO_EN reaches on the
-                                            // port TOP_PM_REG2[0] of gprcm.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_REF_RTRIM_CONTROL register.
-//
-//******************************************************************************
-#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_M \
-                                0x18000000  // This is [5:4] bits of
-                                            // TOP_PM_REG0
-
-#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_S 27
-#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_M \
-                                0x07FF0000  // This is [15:5] bits of
-                                            // TOP_CLKM_REG0
-
-#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_S 16
-#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_OVERRIDE_CTRL \
-                                0x00000100  // 1 - CLKM_RTRIM comes for
-                                            // bits[4:0] of this register. 0 -
-                                            // CLKM_RTRIM comes from Efuse
-                                            // (after efuse_done = 1).
-
-#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_M \
-                                0x0000001F  // CLKM_TRIM Override. Applicable
-                                            // when efuse_done = 0 or bit[8] is
-                                            // set to 1.
-
-#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_REF_SLICER_CONTROLS0 register.
-//
-//******************************************************************************
-#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV_OVERRIDE_CTRL \
-                                0x00200000  // 1 - EN_DIG_BUF_TOP comes from
-                                            // bit [14] of this register. 0 -
-                                            // EN_DIG_BUF_TOP comes from the
-                                            // FSM. Note : Final EN_DIG_BUF_WLAN
-                                            // reaches on TOP_CLKM_REG1_IN[14]
-                                            // port of gprcm
-
-#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV_OVERRIDE_CTRL \
-                                0x00100000  // 1 - EN_DIG_BUF_TOP comes from
-                                            // bit [15] of this register. 0 -
-                                            // EN_DIG_BUF_TOP comes from the
-                                            // FSM. Note : Final EN_DIG_BUF_TOP
-                                            // reaches on TOP_CLKM_REG1_IN[15]
-                                            // port of gprcm
-
-#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL_OVERRIDE_CTRL \
-                                0x00080000  // 1 - EN_XTAL comes from bit [3]
-                                            // of this register. 0 - EN_XTAL
-                                            // comes from FSM. Note : Final
-                                            // XTAL_EN reaches on
-                                            // TOP_CLKM_REG1_IN[3] of gprcm.
-
-#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_OVERRIDE_CTRL \
-                                0x00040000  // 1 - Enable HV Slicer comes from
-                                            // bit [2] of this register. 0 -
-                                            // Enable HV Slicer comes from FSM.
-                                            // Note : Final HV_SLICER_EN reaches
-                                            // on port TOP_CLKM_REG1_IN[1] of
-                                            // gprcm.
-
-#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_LV_OVERRIDE_CTRL \
-                                0x00020000  // 1 - Enable LV Slicer comes from
-                                            // bit[1] of this register. 0 -
-                                            // Enable LV Slicer comes from FSM.
-                                            // Note : final LV_SLICER_EN reaches
-                                            // on port TOP_CLKM_REG1_IN[2] of
-                                            // gprcm.
-
-#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_PDN_OVERRIDE_CTRL \
-                                0x00010000  // 1 - Enable HV Pull-down comes
-                                            // from bit[0] of this register. 0 -
-                                            // Enable HV Pull-down comes from
-                                            // FSM. Note : Final HV_PULL_DOWN
-                                            // reaches on port
-                                            // TOP_CLKM_REG1_IN[0] of gprcm.
-
-#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV \
-                                0x00008000  // Override for EN_DIG_BUF_TOP.
-                                            // Applicable if bit[20] is set to
-                                            // 1. Note : Final EN_DIG_BUF_TOP
-                                            // reaches on TOP_CLKM_REG1_IN[15]
-                                            // port of gprcm
-
-#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV \
-                                0x00004000  // Override for EN_DIG_BUF_WLAN.
-                                            // Applicable if bit[19] is set to
-                                            // 1. Note : Final EN_DIG_BUF_WLAN
-                                            // reaches on TOP_CLKM_REG1_IN[14]
-                                            // port of gprcm
-
-#define GPRCM_REF_SLICER_CONTROLS0_CLKOUT_FLIP_EN \
-                                0x00002000  // CLKOUT Flip Enable. Reaches on
-                                            // bit[13] of TOP_CLKM_REG1_IN[13]
-                                            // port of gprcm.
-
-#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV2_WLAN_CLK \
-                                0x00001000  // Enable divide2 in WLAN Clk-path.
-                                            // Reaches on TOP_CLKM_REG1_IN[12]
-                                            // port of gprcm
-
-#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV3_WLAN_CLK \
-                                0x00000800  // Enable divide3 in WLAN Clk-path.
-                                            // Reaches on TOP_CLKM_REG1_IN[11]
-                                            // port of gprcm
-
-#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV4_WLAN_CLK \
-                                0x00000400  // Enable divide4 in WLAN Clk-path.
-                                            // Reaches on TOP_CLKM_REG1_IN[10]
-                                            // port of gprcm
-
-#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_M \
-                                0x000003C0  // CM Test-mux select. Reaches on
-                                            // TOP_CLMM_REG1_IN[9:6] port of
-                                            // gprcm
-
-#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_S 6
-#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_M \
-                                0x00000030  // Slicer spare0 control. Reaches
-                                            // on TOP_CLKM_REG1_IN[5:4] port of
-                                            // gprcm
-
-#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_S 4
-#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL \
-                                0x00000008  // Enable XTAL override. Reaches on
-                                            // TOP_CLKM_REG1_IN[3] port of gprcm
-
-#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV \
-                                0x00000004  // Enable HV Slicer override.
-                                            // Reaches on TOP_CLKM_REG1_IN[1]
-                                            // port of gprcm
-
-#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_LV \
-                                0x00000002  // Enable LV Slicer override.
-                                            // Reaches on TOP_CLKM_REG1_IN[2]
-                                            // port of gprcm
-
-#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV_PDN \
-                                0x00000001  // Enable HV Pull-down override.
-                                            // Reaches on TOP_CLKM_REG1_IN[0]
-                                            // port of gprcm
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_REF_SLICER_CONTROLS1 register.
-//
-//******************************************************************************
-#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_M \
-                                0x0000FC00  // Slicer spare1. Reaches on port
-                                            // TOP_CLKM_REG2_IN[15:10] of gprcm.
-
-#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_S 10
-#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_M \
-                                0x000003F0  // XOSC Trim. Reaches on port
-                                            // TOP_CLKM_REG2_IN[9:4] of gprcm
-
-#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_S 4
-#define GPRCM_REF_SLICER_CONTROLS1_SLICER_ITRIM_CHANGE_TOGGLE \
-                                0x00000008  // Slicer ITRIM Toggle. Reaches on
-                                            // port TOP_CLKM_REG2_IN[3] of
-                                            // gprcm.
-
-#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_M \
-                                0x00000007  // LV Slicer trim. Reaches on port
-                                            // TOP_CLKM_REG2_IN[2:0] of gprcm.
-
-#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_REF_ANA_BGAP_CONTROLS0 register.
-//
-//******************************************************************************
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_M \
-                                0xFF800000
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_S 23
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_mag_trim_override_ctrl \
-                                0x00400000  // 1 - REF_MAG_TRIM comes from
-                                            // bit[4:0] of register
-                                            // REF_ANA_BGAP_CONTROLS1 [Addr :
-                                            // 0x0850]; 0 - REF_MAG_TRIM comes
-                                            // from efuse (After efc_done = 1).
-                                            // Note : Final REF_MAG_TRIM reaches
-                                            // on port TOP_PM_REG1[4:0] of gprcm
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_override_ctrl \
-                                0x00200000  // 1 - REF_V2I_TRIM comes from
-                                            // bit[9:6] of this register ; 0 -
-                                            // REF_V2I_TRIM comes from efuse
-                                            // (After efc_done = 1). Note :
-                                            // Final REF_V2I_TRIM reaches on
-                                            // port TOP_PM_REG0[9:6] of gprcm.
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_override_ctrl \
-                                0x00100000  // 1 - REF_TEMP_TRIM comes from
-                                            // bit[15:10] of this register ; 0 -
-                                            // REF_TEMP_TRIM comes from efuse
-                                            // (After efc_done = 1). Note :
-                                            // Final REF_TEMP_TRIM reaches on
-                                            // port TOP_PM_REG0[15:10] of gprcm.
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en_override_ctrl \
-                                0x00080000  // 1 - REF_STARTUP_EN comes from
-                                            // bit [3] of this register ; 0 -
-                                            // REF_STARTUP_EN comes from FSM.
-                                            // Note : Final REF_STARTUP_EN
-                                            // reaches on port TOP_PM_REG0[3] of
-                                            // gprcm
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en_override_ctrl \
-                                0x00040000  // 1 - REF_V2I_EN comes from bit
-                                            // [2] of this register ; 0 -
-                                            // REF_V2I_EN comes from FSM. Note :
-                                            // Final REF_V2I_EN reaches on port
-                                            // TOP_PM_REG0[2] of gprcm.
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en_override_ctrl \
-                                0x00020000  // 1 - REF_FC_EN comes from bit [1]
-                                            // of this register ; 0 - REF_FC_EN
-                                            // comes from FSM. Note : Final
-                                            // REF_FC_EN reaches on port
-                                            // TOP_PM_REG0[1] of gprcm.
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en_override_ctrl \
-                                0x00010000  // 1 - REF_BGAP_EN comes from bit
-                                            // [0] of this register ; 0 -
-                                            // REF_BGAP_EN comes from FSM. Note
-                                            // : Final REF_BGAP_EN reaches on
-                                            // port TOP_PM_REG0[0] of gprcm.
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_M \
-                                0x0000FC00  // REF_TEMP_TRIM override.
-                                            // Applicable when bit [20] of this
-                                            // register set to 1. (or efc_done =
-                                            // 0) Note : Final REF_TEMP_TRIM
-                                            // reaches on port
-                                            // TOP_PM_REG0[15:10] of gprcm.
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_S 10
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_M \
-                                0x000003C0  // REF_V2I_TRIM Override.
-                                            // Applicable when bit [21] of this
-                                            // register set to 1 . (of efc_done
-                                            // = 0) Note : Final REF_V2I_TRIM
-                                            // reaches on port TOP_PM_REG0[9:6]
-                                            // of gprcm.
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_S 6
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_M \
-                                0x00000030
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_S 4
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en \
-                                0x00000008  // REF_STARTUP_EN override.
-                                            // Applicable when bit [19] of this
-                                            // register is set to 1. Note :
-                                            // Final REF_STARTUP_EN reaches on
-                                            // port TOP_PM_REG0[3] of gprcm
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en \
-                                0x00000004  // REF_V2I_EN override. Applicable
-                                            // when bit [21] of this register is
-                                            // set to 1. Note : Final REF_V2I_EN
-                                            // reaches on port TOP_PM_REG0[2] of
-                                            // gprcm.
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en \
-                                0x00000002  // REF_FC_EN override. Applicable
-                                            // when bit [17] of this register is
-                                            // set to 1. Note : Final REF_FC_EN
-                                            // reaches on port TOP_PM_REG0[1] of
-                                            // gprcm.
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en \
-                                0x00000001  // REF_BGAP_EN override. Applicable
-                                            // when bit [16] of this register
-                                            // set to 1. Note : Final
-                                            // REF_BGAP_EN reaches on port
-                                            // TOP_PM_REG0[0] of gprcm.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_REF_ANA_BGAP_CONTROLS1 register.
-//
-//******************************************************************************
-#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_M \
-                                0xFFFF0000
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_S 16
-#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_M \
-                                0x0000C000  // REF_BGAP_SPARE. Reaches on port
-                                            // TOP_PM_REG1[15:14] of gprcm.
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_S 14
-#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_M \
-                                0x00003E00  // REF_BGAP_TMUX_CTRL. Reaches on
-                                            // port TOP_PM_REG1[13:9] of gprcm.
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_S 9
-#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_M \
-                                0x000001E0  // REF_FILT_TRIM. Reaches on port
-                                            // TOP_PM_REG1[8:5] of gprcm.
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_S 5
-#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_M \
-                                0x0000001F  // REF_MAG_TRIM Override.
-                                            // Applicable when bit[22] of
-                                            // REF_ANA_BGAP_CONTROLS0 [0x084C]
-                                            // set to 1 (of efc_done = 0). Note
-                                            // : Final REF_MAG_TRIM reaches on
-                                            // port TOP_PM_REG1[4:0] of gprcm
-
-#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_REF_ANA_SPARE_CONTROLS0 register.
-//
-//******************************************************************************
-#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_M \
-                                0xFFFF0000
-
-#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_S 16
-#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_M \
-                                0x0000FFFF  // Spare control. Reaches on
-                                            // TOP_PM_REG3 [15:0] of gprcm.
-
-#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_REF_ANA_SPARE_CONTROLS1 register.
-//
-//******************************************************************************
-#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_M \
-                                0xFFFF0000  // Spare control. Reaches on
-                                            // TOP_CLKM_REG3 [15:0] of gprcm.
-
-#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_S 16
-#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_M \
-                                0x0000FFFF  // Spare control. Reaches on
-                                            // TOP_CLKM_REG4 [15:0] of gprcm.
-
-#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MEMSS_PSCON_OVERRIDES0 register.
-//
-//******************************************************************************
-#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_M \
-                                0xFFFF0000
-
-#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_S 16
-#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_M \
-                                0x0000FFFF
-
-#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MEMSS_PSCON_OVERRIDES1 register.
-//
-//******************************************************************************
-#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_M \
-                                0xFFFFFFC0
-
-#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_S 6
-#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override_ctrl \
-                                0x00000020
-
-#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override \
-                                0x00000010
-
-#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override_ctrl \
-                                0x00000008
-
-#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override \
-                                0x00000004
-
-#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_off_override_ctrl \
-                                0x00000002
-
-#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memms_pscon_mem_retain_override_ctrl \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_PLL_REF_LOCK_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_M \
-                                0xFFFFFFF8
-
-#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_S 3
-#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_mcu_apllmcs_lock_override \
-                                0x00000004
-
-#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_wlan_apllmcs_lock_override \
-                                0x00000002
-
-#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_ref_clk_valid_override \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MCU_PSCON_DEBUG register.
-//
-//******************************************************************************
-#define GPRCM_MCU_PSCON_DEBUG_reserved_M \
-                                0xFFFFFFC0
-
-#define GPRCM_MCU_PSCON_DEBUG_reserved_S 6
-#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_M \
-                                0x00000038  // MCU_PSCON_RTC_ON = "0000";
-                                            // MCU_PSCON_RTC_OFF = "0001";
-                                            // MCU_PSCON_RTC_RET = "0010";
-                                            // MCU_PSCON_RTC_OFF_TO_ON = "0011";
-                                            // MCU_PSCON_RTC_RET_TO_ON = "0100";
-                                            // MCU_PSCON_RTC_ON_TO_RET = "0101";
-                                            // MCU_PSCON_RTC_ON_TO_OFF = "0110";
-                                            // MCU_PSCON_RTC_RET_TO_ON_WAIT_OPP
-                                            // = "0111";
-                                            // MCU_PSCON_RTC_OFF_TO_ON_WAIT_OPP
-                                            // = "1000";
-
-#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_S 3
-#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_M \
-                                0x00000007
-
-#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MEMSS_PWR_PS register.
-//
-//******************************************************************************
-#define GPRCM_MEMSS_PWR_PS_reserved_M \
-                                0xFFFFFFF8
-
-#define GPRCM_MEMSS_PWR_PS_reserved_S 3
-#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_M \
-                                0x00000007  // MEMSS_PM_SLEEP = "000";
-                                            // MEMSS_PM_WAIT_OPP = "010";
-                                            // MEMSS_PM_ACTIVE = "011";
-                                            // MEMSS_PM_SLEEP_TO_ACTIVE = "100";
-                                            // MEMSS_PM_ACTIVE_TO_SLEEP = "101";
-
-#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_REF_FSM_DEBUG register.
-//
-//******************************************************************************
-#define GPRCM_REF_FSM_DEBUG_reserved_M \
-                                0xFFFFFFC0
-
-#define GPRCM_REF_FSM_DEBUG_reserved_S 6
-#define GPRCM_REF_FSM_DEBUG_fref_mode_M \
-                                0x00000030  // 01 - HV Mode ; 10 - LV Mode ; 11
-                                            // - XTAL Mode
-
-#define GPRCM_REF_FSM_DEBUG_fref_mode_S 4
-#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_M \
-                                0x0000000F  // constant FREF_CLK_OFF = "00000";
-                                            // constant FREF_EN_BGAP = "00001";
-                                            // constant FREF_EN_LDO = "00010";
-                                            // constant FREF_EN_SLI_HV =
-                                            // "00011"; constant
-                                            // FREF_EN_SLI_HV_PD = "00100";
-                                            // constant FREF_EN_DIG_BUF =
-                                            // "00101"; constant FREF_EN_OSC =
-                                            // "00110"; constant FREF_EN_SLI_LV
-                                            // = "00111"; constant
-                                            // FREF_EN_CLK_REQ = "01000";
-                                            // constant FREF_CLK_VALID =
-                                            // "01001"; constant FREF_MODE_DET0
-                                            // = "01010"; constant
-                                            // FREF_MODE_DET1 = "01011";
-                                            // constant FREF_MODE_DET2 =
-                                            // "10010"; constant FREF_MODE_DET3
-                                            // = "10011"; constant FREF_VALID =
-                                            // "01100"; constant FREF_VALID0 =
-                                            // "01101"; constant FREF_VALID1 =
-                                            // "01110"; constant FREF_VALID2 =
-                                            // "01111"; constant
-                                            // FREF_WAIT_EXT_TCXO0 = "10000";
-                                            // constant FREF_WAIT_EXT_TCXO1 =
-                                            // "10001";
-
-#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE register.
-//
-//******************************************************************************
-#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_M \
-                                0xFFFFFFE0
-
-#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_S 5
-#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_ctrl \
-                                0x00000010  // 1 - Override the sytem-opp
-                                            // request to ANATOP using bit0 of
-                                            // this register
-
-#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_M \
-                                0x0000000F  // "0001" - RUN ; "0010" - DSLP ;
-                                            // "0100" - LPDS ; Others - NA
-
-#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG register.
-//
-//******************************************************************************
-#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_M \
-                                0xFFFFFFFE
-
-#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_S 1
-#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_mem_sleep_opp_enter_with_testpd_on \
-                                0x00000001  // 1 - Enable sleep-opp (DSLP/LPDS)
-                                            // entry even if Test-Pd is kept ON
-                                            // ; 0 - Donot enable sleep-opp
-                                            // (DSLP/LPDS) entry with Test-Pd
-                                            // ON.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_M \
-                                0xFFFFFFF8
-
-#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_S 3
-#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override_ctrl \
-                                0x00000004  // NA
-
-#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override \
-                                0x00000002  // NA
-
-#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_sleep_with_clk_req_override \
-                                0x00000001  // NA
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_mode_req_override_ctrl \
-                                0x00000004  // 1 - Override the MCU-PD power
-                                            // modes using bits [1] & [0] ;
-
-#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_pwrdn_req_override \
-                                0x00000002  // 1 - Request for power-down of
-                                            // MCU-PD ;
-
-#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_ret_req_override \
-                                0x00000001  // 1 - Request for retention mode
-                                            // of MCU-PD.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override_ctrl \
-                                0x00000002  // 1- Override the MCSPI
-                                            // (Autonomous SPI) memory state
-                                            // using bit [0]
-
-#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override \
-                                0x00000001  // 1 - Request for power-down of
-                                            // Autonomous SPI 8k memory ; 0 -
-                                            // Donot request power-down of
-                                            // Autonomous SPI 8k Memory
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_wlan_apllmcs_lock \
-                                0x00000100
-
-#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override \
-                                0x00000002
-
-#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override_ctrl \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MEM_REF_FSM_CFG2 register.
-//
-//******************************************************************************
-#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_M \
-                                0x00380000  // Number of RTC clocks for keeping
-                                            // the FC_EN asserted high
-
-#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_S 19
-#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_M \
-                                0x00070000  // Number of RTC clocks for keeping
-                                            // the STARTUP_EN asserted high
-
-#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_S 16
-#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_M \
-                                0x0000FFFF  // Number of RTC clocks for waiting
-                                            // for clock to settle.
-
-#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_TESTCTRL_POWER_CTRL register.
-//
-//******************************************************************************
-#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_M \
-                                0x00000006
-
-#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_S 1
-#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_ENABLE \
-                                0x00000001  // 0 - Disable the TestCtrl-pd ; 1
-                                            // - Enable the TestCtrl-pd.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_SSDIO_POWER_CTRL register.
-//
-//******************************************************************************
-#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_M \
-                                0x00000006  // 1 - SSDIO-PD is ON ; 0 -
-                                            // SSDIO-PD is OFF
-
-#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_S 1
-#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_ENABLE \
-                                0x00000001  // 0 - Disable the SSDIO-pd ; 1 -
-                                            // Enable the SSDIO-pd.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MCSPI_N1_POWER_CTRL register.
-//
-//******************************************************************************
-#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_M \
-                                0x00000006  // 1 - MCSPI_N1-PD is ON ; 0 -
-                                            // MCSPI_N1-PD if OFF
-
-#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_S 1
-#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_ENABLE \
-                                0x00000001  // 0 - Disable the MCSPI_N1-pd ; 1
-                                            // - Enable the MCSPI_N1-pd.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_WELP_POWER_CTRL register.
-//
-//******************************************************************************
-#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_M \
-                                0x00001C00
-
-#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_S 10
-#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE \
-                                0x00000200
-
-#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE_CTRL \
-                                0x00000100
-
-#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_M \
-                                0x00000006
-
-#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_S 1
-#define GPRCM_WELP_POWER_CTRL_WELP_PD_ENABLE \
-                                0x00000001  // 0 - Disable the WELP-pd ; 1 -
-                                            // Enable the WELP-pd.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_WL_SDIO_POWER_CTRL register.
-//
-//******************************************************************************
-#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_M \
-                                0x00000006
-
-#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_S 1
-#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_ENABLE \
-                                0x00000001  // 0 - Disable the WL_SDIO-pd ; 1 -
-                                            // Enable the WL_SDIO-pd.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG register.
-//
-//******************************************************************************
-#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_M \
-                                0x00FFFFFF  // SRAM (WTOP+DRP) state during
-                                            // Active-mode : 1 - SRAMs are ON ;
-                                            // 0 - SRAMs are OFF. Cluster
-                                            // information : [0] - 1st column of
-                                            // MEMSS (Applicable only when owned
-                                            // by WTOP/PHY) [1] - 2nd column of
-                                            // MEMSS (Applicable only when owned
-                                            // by WTOP/PHY) ; [2] - 3rd column
-                                            // of MEMSS (Applicable only when
-                                            // owned by WTOP/PHY) ; [3] - 4th
-                                            // column of MEMSS (Applicable only
-                                            // when owned by WTOP/PHY) ; [4] -
-                                            // 5th column of MEMSS (Applicable
-                                            // only when owned by WTOP/PHY) ;
-                                            // [5] - 6th column of MEMSS
-                                            // (Applicable only when owned by
-                                            // WTOP/PHY) ; [6] - 7th column of
-                                            // MEMSS (Applicable only when owned
-                                            // by WTOP/PHY) ; [7] - 8th column
-                                            // of MEMSS (Applicable only when
-                                            // owned by WTOP/PHY) ; [8] - 9th
-                                            // column of MEMSS (Applicable only
-                                            // when owned by WTOP/PHY) ; [9] -
-                                            // 10th column of MEMSS (Applicable
-                                            // only when owned by WTOP/PHY) ;
-                                            // [10] - 11th column of MEMSS
-                                            // (Applicable only when owned by
-                                            // WTOP/PHY) ; [11] - 12th column of
-                                            // MEMSS (Applicable only when owned
-                                            // by WTOP/PHY) ; [12] - 13th column
-                                            // of MEMSS (Applicable only when
-                                            // owned by WTOP/PHY) ; [13] - 14th
-                                            // column of MEMSS (Applicable only
-                                            // when owned by WTOP/PHY) ; [14] -
-                                            // 15th column of MEMSS (Applicable
-                                            // only when owned by WTOP/PHY) ;
-                                            // [15] - 16th column of MEMSS
-                                            // (Applicable only when owned by
-                                            // WTOP/PHY) ; [23:16] - Internal to
-                                            // WTOP Cluster
-
-#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG register.
-//
-//******************************************************************************
-#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_M \
-                                0x00FFFFFF  // SRAM (WTOP+DRP) state during
-                                            // Sleep-mode : 1 - SRAMs are RET ;
-                                            // 0 - SRAMs are OFF. Cluster
-                                            // information : [0] - 1st column of
-                                            // MEMSS (Applicable only when owned
-                                            // by WTOP/PHY) [1] - 2nd column of
-                                            // MEMSS (Applicable only when owned
-                                            // by WTOP/PHY) ; [2] - 3rd column
-                                            // of MEMSS (Applicable only when
-                                            // owned by WTOP/PHY) ; [3] - 4th
-                                            // column of MEMSS (Applicable only
-                                            // when owned by WTOP/PHY) ; [4] -
-                                            // 5th column of MEMSS (Applicable
-                                            // only when owned by WTOP/PHY) ;
-                                            // [5] - 6th column of MEMSS
-                                            // (Applicable only when owned by
-                                            // WTOP/PHY) ; [6] - 7th column of
-                                            // MEMSS (Applicable only when owned
-                                            // by WTOP/PHY) ; [7] - 8th column
-                                            // of MEMSS (Applicable only when
-                                            // owned by WTOP/PHY) ; [8] - 9th
-                                            // column of MEMSS (Applicable only
-                                            // when owned by WTOP/PHY) ; [9] -
-                                            // 10th column of MEMSS (Applicable
-                                            // only when owned by WTOP/PHY) ;
-                                            // [10] - 11th column of MEMSS
-                                            // (Applicable only when owned by
-                                            // WTOP/PHY) ; [11] - 12th column of
-                                            // MEMSS (Applicable only when owned
-                                            // by WTOP/PHY) ; [12] - 13th column
-                                            // of MEMSS (Applicable only when
-                                            // owned by WTOP/PHY) ; [13] - 14th
-                                            // column of MEMSS (Applicable only
-                                            // when owned by WTOP/PHY) ; [14] -
-                                            // 15th column of MEMSS (Applicable
-                                            // only when owned by WTOP/PHY) ;
-                                            // [15] - 16th column of MEMSS
-                                            // (Applicable only when owned by
-                                            // WTOP/PHY) ; [23:16] - Internal to
-                                            // WTOP Cluster
-
-#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APPS_SECURE_INIT_DONE register.
-//
-//******************************************************************************
-#define GPRCM_APPS_SECURE_INIT_DONE_SECURE_INIT_DONE_STATUS \
-                                0x00000002  // 1-Secure mode init is done ;
-                                            // 0-Secure mode init is not done
-
-#define GPRCM_APPS_SECURE_INIT_DONE_APPS_SECURE_INIT_DONE \
-                                0x00000001  // Must be programmed 1 in order to
-                                            // say that secure-mode device init
-                                            // is done
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APPS_DEV_MODE_INIT_DONE register.
-//
-//******************************************************************************
-#define GPRCM_APPS_DEV_MODE_INIT_DONE_APPS_DEV_MODE_INIT_DONE \
-                                0x00000001  // 1 - Patch download and other
-                                            // initializations are done (before
-                                            // removing APPS resetn) for
-                                            // development mode (#3) . 0 -
-                                            // Development mode (#3) init is not
-                                            // done yet
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_EN_APPS_REBOOT register.
-//
-//******************************************************************************
-#define GPRCM_EN_APPS_REBOOT_EN_APPS_REBOOT \
-                                0x00000001  // 1 - When 1, disable the reboot
-                                            // of APPS after DevInit is
-                                            // completed. In this case, APPS
-                                            // will permanantly help in reset. 0
-                                            // - When 0, enable the reboot of
-                                            // APPS after DevInit is completed.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MEM_APPS_PERIPH_PRESENT register.
-//
-//******************************************************************************
-#define GPRCM_MEM_APPS_PERIPH_PRESENT_WLAN_GEM_PP \
-                                0x00010000  // 1 - Enable ; 0 - Disable
-
-#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_AES_PP \
-                                0x00008000
-
-#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_DES_PP \
-                                0x00004000
-
-#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_SHA_PP \
-                                0x00002000
-
-#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_CAMERA_PP \
-                                0x00001000
-
-#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MMCHS_PP \
-                                0x00000800
-
-#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCASP_PP \
-                                0x00000400
-
-#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A1_PP \
-                                0x00000200
-
-#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A2_PP \
-                                0x00000100
-
-#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UDMA_PP \
-                                0x00000080
-
-#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_WDOG_PP \
-                                0x00000040
-
-#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A0_PP \
-                                0x00000020
-
-#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A1_PP \
-                                0x00000010
-
-#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A0_PP \
-                                0x00000008
-
-#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A1_PP \
-                                0x00000004
-
-#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A2_PP \
-                                0x00000002
-
-#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A3_PP \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MEM_NWP_PERIPH_PRESENT register.
-//
-//******************************************************************************
-#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_ASYNC_BRIDGE_PP \
-                                0x00000200
-
-#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N2_PP \
-                                0x00000100
-
-#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N0_PP \
-                                0x00000080
-
-#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N1_PP \
-                                0x00000040
-
-#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_WDOG_PP \
-                                0x00000020
-
-#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UDMA_PP \
-                                0x00000010
-
-#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N0_PP \
-                                0x00000008
-
-#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N1_PP \
-                                0x00000004
-
-#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_SSDIO_PP \
-                                0x00000002
-
-#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N1_PP \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MEM_SHARED_PERIPH_PRESENT register.
-//
-//******************************************************************************
-
-#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_MCSPI_PP \
-                                0x00000040
-
-#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_I2C_PP \
-                                0x00000020
-
-#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_A_PP \
-                                0x00000010
-
-#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_B_PP \
-                                0x00000008
-
-#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_C_PP \
-                                0x00000004
-
-#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_D_PP \
-                                0x00000002
-
-#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_E_PP \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_NWP_PWR_STATE register.
-//
-//******************************************************************************
-#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_M \
-                                0x00000F00  // "0000"- PORZ :- NWP is yet to be
-                                            // enabled by APPS during powerup
-                                            // (from HIB/OFF) ; "0011"- ACTIVE
-                                            // :- NWP is enabled, clocks and
-                                            // resets to NWP-SubSystem are
-                                            // enabled ; "0010"- LPDS :- NWP is
-                                            // in LPDS-mode ; Clocks and reset
-                                            // to NWP-SubSystem are gated ;
-                                            // "0101"- WAIT_FOR_OPP :- NWP is in
-                                            // transition from LPDS to ACTIVE,
-                                            // where it is waiting for OPP to be
-                                            // stable ; "1000"-
-                                            // WAKE_TIMER_OPP_REQ :- NWP is in
-                                            // transition from LPDS, where the
-                                            // wakeup cause is LPDS_Wake timer
-                                            // OTHERS : NA
-
-#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_S 8
-#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_M \
-                                0x00000007  // "000" - NWP_RUN : NWP is in RUN
-                                            // state (default) - Applicable only
-                                            // when NWP_PWR_STATE_PS = ACTIVE ;
-                                            // "001" - NWP_SLP : NWP is in SLEEP
-                                            // state (default) - Applicable only
-                                            // when NWP_PWR_STATE_PS = ACTIVE ;
-                                            // "010" - NWP_DSLP : NWP is in
-                                            // Deep-Sleep state (default) -
-                                            // Applicable only when
-                                            // NWP_PWR_STATE_PS = ACTIVE ; "011"
-                                            // - WAIT_FOR_ACTIVE : NWP is in
-                                            // transition from Deep-sleep to
-                                            // Run, where it is waiting for OPP
-                                            // to be stable ; "100" -
-                                            // WAIT_FOR_DSLP_TIMER_WAKE_REQ :
-                                            // NWP is in transition from
-                                            // Deep-sleep to Run, where the
-                                            // wakeup cause is deep-sleep
-                                            // wake-timer
-
-#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APPS_PWR_STATE register.
-//
-//******************************************************************************
-#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_M \
-                                0x00000F00  // "0000"- PORZ :- APPS is waiting
-                                            // for PLL_clock during powerup
-                                            // (from HIB/OFF) ; "0011"- ACTIVE
-                                            // :- APPS is enabled, clocks and
-                                            // resets to APPS-SubSystem are
-                                            // enabled ; APPS might be either in
-                                            // Secure or Un-secure mode during
-                                            // this state. "1001" -
-                                            // SECURE_MODE_LPDS :- While in
-                                            // ACTIVE (Secure-mode), APPS had to
-                                            // program the DevInit_done bit at
-                                            // the end, after which it enters
-                                            // into this state, where the reset
-                                            // to APPS will be asserted. From
-                                            // this state APPS might either
-                                            // re-boot itself or enter into LPDS
-                                            // depending upon whether the device
-                                            // is 3200 or 3100. "0010"- LPDS :-
-                                            // APPS is in LPDS-mode ; Clocks and
-                                            // reset to APPS-SubSystem are gated
-                                            // ; "0101"- WAIT_FOR_OPP :- APPS is
-                                            // in transition from LPDS to
-                                            // ACTIVE, where it is waiting for
-                                            // OPP to be stable ; "1000" -
-                                            // WAKE_TIMER_OPP_REQ : APPS is in
-                                            // transition from LPDS, where the
-                                            // wakeup cause is LPDS_Wake timer ;
-                                            // "1010" - WAIT_FOR_PATCH_INIT :
-                                            // APPS enters into this state
-                                            // during development-mode #3 (SOP =
-                                            // 3), where it is waiting for patch
-                                            // download to complete and 0x4 hack
-                                            // is programmed. OTHERS : NA
-
-#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_S 8
-#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_M \
-                                0x00000007  // "000" - APPS_RUN : APPS is in
-                                            // RUN state (default) - Applicable
-                                            // only when APPS_PWR_STATE_PS =
-                                            // ACTIVE ; "001" - APPS_SLP : APPS
-                                            // is in SLEEP state (default) -
-                                            // Applicable only when
-                                            // APPS_PWR_STATE_PS = ACTIVE ;
-                                            // "010" - APPS_DSLP : APPS is in
-                                            // Deep-Sleep state (default) -
-                                            // Applicable only when
-                                            // APPS_PWR_STATE_PS = ACTIVE ;
-                                            // "011" - WAIT_FOR_ACTIVE : APPS is
-                                            // in transition from Deep-sleep to
-                                            // Run, where it is waiting for OPP
-                                            // to be stable ; "100" -
-                                            // WAIT_FOR_DSLP_TIMER_WAKE_REQ :
-                                            // APPS is in transition from
-                                            // Deep-sleep to Run, where the
-                                            // wakeup cause is deep-sleep
-                                            // wake-timer
-
-#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MCU_PWR_STATE register.
-//
-//******************************************************************************
-#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_M \
-                                0x0000001F  // TBD
-
-#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_WTOP_PM_PS register.
-//
-//******************************************************************************
-#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_M \
-                                0x00000007  // "011" - WTOP_PM_ACTIVE (Default)
-                                            // :- WTOP_Pd is in ACTIVE mode;
-                                            // "100" - WTOP_PM_ACTIVE_TO_SLEEP
-                                            // :- WTOP_Pd is in transition from
-                                            // ACTIVE to SLEEP ; "000" -
-                                            // WTOP_PM_SLEEP : WTOP-Pd is in
-                                            // Sleep-state ; "100" -
-                                            // WTOP_PM_SLEEP_TO_ACTIVE : WTOP_Pd
-                                            // is in transition from SLEEP to
-                                            // ACTIVE ; "000" -
-                                            // WTOP_PM_WAIT_FOR_OPP : Wait for
-                                            // OPP to be stable ;
-
-#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG register.
-//
-//******************************************************************************
-#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE_CTRL \
-                                0x00000100  // Override control for WTOP PD
-                                            // Resetz. When set to 1,
-                                            // WTOP_Resetz will be controlled by
-                                            // bit [0]
-
-#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE \
-                                0x00000001  // Override for WTOP PD Resetz.
-                                            // Applicable only when bit[8] is
-                                            // set to 1
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG register.
-//
-//******************************************************************************
-#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE_CTRL \
-                                0x00000100  // Override control for WELP PD
-                                            // Resetz. When set to 1,
-                                            // WELP_Resetz will be controlled by
-                                            // bit [0]
-
-#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE \
-                                0x00000001  // Override for WELP PD Resetz.
-                                            // Applicable only when bit[8] is
-                                            // set to 1
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG register.
-//
-//******************************************************************************
-#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE_CTRL \
-                                0x00000100  // Override control for WL_SDIO
-                                            // Resetz. When set to 1,
-                                            // WL_SDIO_Resetz will be controlled
-                                            // by bit [0]
-
-#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE \
-                                0x00000001  // Override for WL_SDIO Resetz.
-                                            // Applicable only when bit[8] is
-                                            // set to 1
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG register.
-//
-//******************************************************************************
-#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE_CTRL \
-                                0x00000100  // Override control for SSDIO
-                                            // Resetz. When set to 1,
-                                            // SSDIO_Resetz will be controlled
-                                            // by bit [0]
-
-#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE \
-                                0x00000001  // Override for SSDIO Resetz.
-                                            // Applicable only when bit[8] is
-                                            // set to 1
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG register.
-//
-//******************************************************************************
-#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE_CTRL \
-                                0x00000100  // Override control for MCSPI_N1
-                                            // Resetz. When set to 1,
-                                            // MCSPI_N1_Resetz will be
-                                            // controlled by bit [0]
-
-#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE \
-                                0x00000001  // Override for MCSPI_N1 Resetz.
-                                            // Applicable only when bit[8] is
-                                            // set to 1
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG register.
-//
-//******************************************************************************
-#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE_CTRL \
-                                0x00000100  // Override control for TESTCTRL-PD
-                                            // Resetz. When set to 1,
-                                            // TESTCTRL_Resetz will be
-                                            // controlled by bit [0]
-
-#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE \
-                                0x00000001  // Override for TESTCTRL Resetz.
-                                            // Applicable only when bit[8] is
-                                            // set to 1
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG register.
-//
-//******************************************************************************
-#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE_CTRL \
-                                0x00000100  // Override control for MCU-PD
-                                            // Resetz. When set to 1, MCU_Resetz
-                                            // will be controlled by bit [0]
-
-#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE \
-                                0x00000001  // Override for MCU Resetz.
-                                            // Applicable only when bit[8] is
-                                            // set to 1
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_EFUSE_READ_REG0 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_M \
-                                0xFFFFFFFF  // This is ROW_14 [31:0] of
-                                            // FUSEFARM. [0:0] : XTAL_IS_26MHZ
-                                            // [5:1] : TOP_CLKM_RTRIM[4:0]
-                                            // [10:6] : ANA_BGAP_MAG_TRIM[4:0]
-                                            // [16:11] : ANA_BGAP_TEMP_TRIM[5:0]
-                                            // [20:17] : ANA_BGAP_V2I_TRIM[3:0]
-                                            // [25:22] : PROCESS INDICATOR
-                                            // [26:26] : Reserved [31:27] :
-                                            // FUSEROM Version
-
-#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_EFUSE_READ_REG1 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_M \
-                                0x0000FFFF  // This is ROW_15[15:0] of FUSEFARM
-                                            // 1. NWP Peripheral Present bits
-                                            // [15:8] NWP_GPT_N0_PP [15:15]
-                                            // NWP_GPT_N1_PP [14:14] NWP_WDOG_PP
-                                            // [13:13] NWP_UDMA_PP [12:12]
-                                            // NWP_UART_N0_PP [11:11]
-                                            // NWP_UART_N1_PP [10:10]
-                                            // NWP_SSDIO_PP [9:9]
-                                            // NWP_MCSPI_N1_PP [8:8] 2. Shared
-                                            // Peripheral Present bits [7:0]
-                                            // SHARED SPI PP [6:6]
-                                            // SHARED I2C PP [5:5] SHARED
-                                            // GPIO-A PP [4:4] SHARED GPIO-B PP
-                                            // [3:3] SHARED GPIO-C PP [2:2]
-                                            // SHARED GPIO-D PP [1:1] SHARED
-                                            // GPIO-E PP [0:0]
-
-#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_EFUSE_READ_REG2 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_M \
-                                0xFFFFFFFF  // This is ROW_16[15:0] &
-                                            // ROW_15[31:16] of FUSEFARM.
-                                            // [31:21] - Reserved [20:16] -
-                                            // CHIP_ID [15:15] - SSBD SOP
-                                            // Control [14:14] - SSBD TAP
-                                            // Control [13:2] - APPS Peripheral
-                                            // Present bits : APPS_CAMERA_PP
-                                            // [13:13] APPS_MMCHS_PP [12:12]
-                                            // APPS_MCASP_PP [11:11]
-                                            // APPS_MCSPI_A1_PP [10:10]
-                                            // APPS_MCSPI_A2_PP [9:9]
-                                            // APPS_UDMA_PP [8:8] APPS_WDOG_PP
-                                            // [7:7] APPS_UART_A0_PP [6:6]
-                                            // APPS_UART_A1_PP [5:5]
-                                            // APPS_GPT_A0_PP [4:4]
-                                            // APPS_GPT_A1_PP [3:3]
-                                            // APPS_GPT_A2_PP [2:2]
-                                            // APPS_GPT_A3_PP [1:1] [0:0] - NWP
-                                            // Peripheral present bits
-                                            // NWP_ACSPI_PP [0:0]
-
-#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_EFUSE_READ_REG3 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_M \
-                                0xFFFFFFFF  // This is ROW_17[15:0] &
-                                            // ROW_16[31:16] of FUSEFARM :
-                                            // [31:16] - TEST_TAP_KEY(15:0)
-                                            // [15:0] - Reserved
-
-#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_WTOP_MEM_RET_CFG register.
-//
-//******************************************************************************
-#define GPRCM_WTOP_MEM_RET_CFG_WTOP_MEM_RET_CFG \
-                                0x00000001  // 1 - Soft-compile memories in
-                                            // WTOP can be turned-off during
-                                            // WTOP-sleep mode ; 0 -
-                                            // Soft-compile memories in WTOP
-                                            // must be kept on during WTOP-sleep
-                                            // mode.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_COEX_CLK_SWALLOW_CFG0 register.
-//
-//******************************************************************************
-#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_M \
-                                0x007FFFFF  // TBD
-
-#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_COEX_CLK_SWALLOW_CFG1 register.
-//
-//******************************************************************************
-#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_M \
-                                0x000FFFFF  // TBD
-
-#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_COEX_CLK_SWALLOW_CFG2 register.
-//
-//******************************************************************************
-#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_M \
-                                0x00000018
-
-#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_S 3
-#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_GAIN \
-                                0x00000004
-
-#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_ENABLE \
-                                0x00000002
-
-#define GPRCM_COEX_CLK_SWALLOW_CFG2_SWALLOW_ENABLE \
-                                0x00000001  // TBD
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_COEX_CLK_SWALLOW_ENABLE register.
-//
-//******************************************************************************
-#define GPRCM_COEX_CLK_SWALLOW_ENABLE_COEX_CLK_SWALLOW_ENABLE \
-                                0x00000001  // 1 - Enable switching of sysclk
-                                            // to Coex-clk path ; 0 - Disable
-                                            // switching of sysclk to Coex-clk
-                                            // path.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_DCDC_CLK_GEN_CONFIG register.
-//
-//******************************************************************************
-#define GPRCM_DCDC_CLK_GEN_CONFIG_DCDC_CLK_ENABLE \
-                                0x00000001  // 1 - Enable the clock for DCDC
-                                            // (PWM-mode) ; 0 - Disable the
-                                            // clock for DCDC (PWM-mode)
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_EFUSE_READ_REG4 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_M \
-                                0x0000FFFF  // This corresponds to
-                                            // ROW_17[31:16] of the FUSEFARM :
-                                            // [15:0] : TEST_TAP_KEY(31:16)
-
-#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_EFUSE_READ_REG5 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_M \
-                                0xFFFFFFFF  // Corresponds to ROW_18 of
-                                            // FUSEFARM. [29:0] -
-                                            // MEMSS_COLUMN_SEL_LSW ; [30:30] -
-                                            // WLAN GEM DISABLE ; [31:31] -
-                                            // SERIAL WIRE JTAG SELECT
-
-#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_EFUSE_READ_REG6 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_M \
-                                0x0000FFFF  // Corresponds to ROW_19[15:0] of
-                                            // FUSEFARM. [15:0] :
-                                            // MEMSS_COLUMN_SEL_MSW
-
-#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_EFUSE_READ_REG7 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_M \
-                                0xFFFFFFFF  // Corresponds to ROW_20[15:0] &
-                                            // ROW_19[31:16] of FUSEFARM.
-                                            // FLASH_REGION0
-
-#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_EFUSE_READ_REG8 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_M \
-                                0xFFFFFFFF  // Corresponds to ROW_21[15:0] &
-                                            // ROW_20[31:16] of FUSEFARM.
-                                            // FLASH_REGION1
-
-#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_EFUSE_READ_REG9 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_M \
-                                0xFFFFFFFF  // Corresponds to ROW_22[15:0] &
-                                            // ROW_21[31:16] of FUSEFARM.
-                                            // FLASH_REGION2
-
-#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_EFUSE_READ_REG10 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_M \
-                                0xFFFFFFFF  // Corresponds to ROW_23[15:0] &
-                                            // ROW_22[31:16] of FUSEFARM.
-                                            // FLASH_REGION3
-
-#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_EFUSE_READ_REG11 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_M \
-                                0xFFFFFFFF  // Corresponds to ROW_24[15:0] &
-                                            // ROW_23[31:16] of FUSEFARM.
-                                            // FLASH_DESCRIPTOR
-
-#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_DIEID_READ_REG0 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_M \
-                                0xFFFFFFFF  // Corresponds to bits [191:160] of
-                                            // the FUSEFARM. This is ROW_5 of
-                                            // FUSEFARM [191:160] : [31:0] :
-                                            // DIE_ID0 [31:0] : DEVX [11:0] DEVY
-                                            // [23:12] DEVWAF [29:24] DEV_SPARE
-                                            // [31:30]
-
-#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_DIEID_READ_REG1 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_M \
-                                0xFFFFFFFF  // Corresponds to bits [223:192] of
-                                            // the FUSEFARM. This is ROW_6 of
-                                            // FUSEFARM :- DEVLOT [23:0] DEVFAB
-                                            // [28:24] DEVFABBE [31:29]
-
-#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_DIEID_READ_REG2 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_M \
-                                0xFFFFFFFF  // Corresponds to bits [255:224] of
-                                            // the FUSEFARM. This is ROW_7 of
-                                            // FUSEFARM:- DEVDESREV[4:0]
-                                            // Memrepair[5:5] MakeDefined[16:6]
-                                            // CHECKSUM[30:17] Reserved :
-                                            // [31:31]
-
-#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_DIEID_READ_REG3 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_M \
-                                0xFFFFFFFF  // Corresponds to bits [287:256] of
-                                            // the FUSEFARM. This is ROW_8 of
-                                            // FUSEFARM :- DIEID0 - DEVREG
-                                            // [31:0]
-
-#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_GPRCM_DIEID_READ_REG4 register.
-//
-//******************************************************************************
-#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_M \
-                                0xFFFFFFFF  // Corresponds to bits [319:288] of
-                                            // the FUSEFARM. This is ROW_9 of
-                                            // FUSEFARM :- [7:0] - VBATMON ;
-                                            // [13:8] - BUFF_OFFSET ; [15:15] -
-                                            // DFT_GXG ; [14:14] - DFT_GLX ;
-                                            // [19:16] - PHY ROM Version ;
-                                            // [23:20] - MAC ROM Version ;
-                                            // [27:24] - NWP ROM Version ;
-                                            // [31:28] - APPS ROM Version
-
-#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_APPS_SS_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_APPS_SS_OVERRIDES_reserved_M \
-                                0xFFFFFC00
-
-#define GPRCM_APPS_SS_OVERRIDES_reserved_S 10
-#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override \
-                                0x00000200
-
-#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override_ctrl \
-                                0x00000100
-
-#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override \
-                                0x00000080
-
-#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override_ctrl \
-                                0x00000040
-
-#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override \
-                                0x00000020
-
-#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override \
-                                0x00000010
-
-#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override \
-                                0x00000008
-
-#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override_ctrl \
-                                0x00000004
-
-#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override_ctrl \
-                                0x00000002
-
-#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override_ctrl \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_NWP_SS_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_NWP_SS_OVERRIDES_reserved_M \
-                                0xFFFFFC00
-
-#define GPRCM_NWP_SS_OVERRIDES_reserved_S 10
-#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override \
-                                0x00000200
-
-#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override_ctrl \
-                                0x00000100
-
-#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override \
-                                0x00000080
-
-#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override_ctrl \
-                                0x00000040
-
-#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override \
-                                0x00000020
-
-#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override \
-                                0x00000010
-
-#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override \
-                                0x00000008
-
-#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override_ctrl \
-                                0x00000004
-
-#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override_ctrl \
-                                0x00000002
-
-#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override_ctrl \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_SHARED_SS_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_SHARED_SS_OVERRIDES_reserved_M \
-                                0xFFFFFF00
-
-#define GPRCM_SHARED_SS_OVERRIDES_reserved_S 8
-#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override_ctrl \
-                                0x00000080
-
-#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override \
-                                0x00000040
-
-#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override_ctrl \
-                                0x00000020
-
-#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override \
-                                0x00000010
-
-#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override \
-                                0x00000008
-
-#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override \
-                                0x00000004
-
-#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override_ctrl \
-                                0x00000002
-
-#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override_ctrl \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_IDMEM_CORE_RST_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_M \
-                                0xFFFFFF00
-
-#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_S 8
-#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override \
-                                0x00000080
-
-#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override \
-                                0x00000040
-
-#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW1 \
-                                0x00000020
-
-#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override \
-                                0x00000010
-
-#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override_ctrl \
-                                0x00000008
-
-#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override_ctrl \
-                                0x00000004
-
-#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW0 \
-                                0x00000002
-
-#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override_ctrl \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_TOP_DIE_FSM_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_M \
-                                0xFFFFF000
-
-#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_S 12
-#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override_ctrl \
-                                0x00000800
-
-#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override \
-                                0x00000400
-
-#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override \
-                                0x00000200
-
-#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override \
-                                0x00000100
-
-#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override \
-                                0x00000080
-
-#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override \
-                                0x00000040
-
-#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override \
-                                0x00000020
-
-#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override_ctrl \
-                                0x00000010
-
-#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override_ctrl \
-                                0x00000008
-
-#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override_ctrl \
-                                0x00000004
-
-#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override_ctrl \
-                                0x00000002
-
-#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override_ctrl \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MCU_PSCON_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_MCU_PSCON_OVERRIDES_reserved_M \
-                                0xFFF00000
-
-#define GPRCM_MCU_PSCON_OVERRIDES_reserved_S 20
-#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_sleep_override_ctrl \
-                                0x00080000
-
-#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override_ctrl \
-                                0x00040000
-
-#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_ctrl \
-                                0x00020000
-
-#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_ctrl \
-                                0x00010000
-
-#define GPRCM_MCU_PSCON_OVERRIDES_NU1_M \
-                                0x0000FC00
-
-#define GPRCM_MCU_PSCON_OVERRIDES_NU1_S 10
-#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_sleep_override \
-                                0x00000200
-
-#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override \
-                                0x00000100
-
-#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_M \
-                                0x000000F0
-
-#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_S 4
-#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_M \
-                                0x0000000F
-
-#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_WTOP_PSCON_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_M \
-                                0xFFC00000
-
-#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_S 22
-#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override_ctrl \
-                                0x00200000
-
-#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override_ctrl \
-                                0x00100000
-
-#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_ctrl \
-                                0x00080000
-
-#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_ctrl \
-                                0x00040000
-
-#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override \
-                                0x00020000
-
-#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override \
-                                0x00010000
-
-#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_M \
-                                0x0000FF00
-
-#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_S 8
-#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_M \
-                                0x000000FF
-
-#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_WELP_PSCON_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_WELP_PSCON_OVERRIDES_reserved_M \
-                                0xFFFFFFFC
-
-#define GPRCM_WELP_PSCON_OVERRIDES_reserved_S 2
-#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override_ctrl \
-                                0x00000002
-
-#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_WL_SDIO_PSCON_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_M \
-                                0xFFFFFFFC
-
-#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_S 2
-#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override_ctrl \
-                                0x00000002
-
-#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_MCSPI_PSCON_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_M \
-                                0xFFFFFF00
-
-#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_S 8
-#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override_ctrl \
-                                0x00000080
-
-#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override_ctrl \
-                                0x00000040
-
-#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override \
-                                0x00000020
-
-#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override \
-                                0x00000010
-
-#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override_ctrl \
-                                0x00000008
-
-#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override \
-                                0x00000004
-
-#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override_ctrl \
-                                0x00000002
-
-#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// GPRCM_O_SSDIO_PSCON_OVERRIDES register.
-//
-//******************************************************************************
-#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_M \
-                                0xFFFFFFFC
-
-#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_S 2
-#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override_ctrl \
-                                0x00000002
-
-#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override \
-                                0x00000001
-
-
-
-
-#endif // __HW_GPRCM_H__
diff --git a/cc3200/hal/inc/hw_hib1p2.h b/cc3200/hal/inc/hw_hib1p2.h
deleted file mode 100644
index 95e25ff7c..000000000
--- a/cc3200/hal/inc/hw_hib1p2.h
+++ /dev/null
@@ -1,1750 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_HIB1P2_H__
-#define __HW_HIB1P2_H__
-
-//*****************************************************************************
-//
-// The following are defines for the HIB1P2 register offsets.
-//
-//*****************************************************************************
-#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 \
-                                0x00000000
-
-#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 \
-                                0x00000004
-
-#define HIB1P2_O_DIG_DCDC_PARAMETERS0 \
-                                0x00000008
-
-#define HIB1P2_O_DIG_DCDC_PARAMETERS1 \
-                                0x0000000C
-
-#define HIB1P2_O_DIG_DCDC_PARAMETERS2 \
-                                0x00000010
-
-#define HIB1P2_O_DIG_DCDC_PARAMETERS3 \
-                                0x00000014
-
-#define HIB1P2_O_DIG_DCDC_PARAMETERS4 \
-                                0x00000018
-
-#define HIB1P2_O_DIG_DCDC_PARAMETERS5 \
-                                0x0000001C
-
-#define HIB1P2_O_DIG_DCDC_PARAMETERS6 \
-                                0x00000020
-
-#define HIB1P2_O_ANA_DCDC_PARAMETERS0 \
-                                0x00000024
-
-#define HIB1P2_O_ANA_DCDC_PARAMETERS1 \
-                                0x00000028
-
-#define HIB1P2_O_ANA_DCDC_PARAMETERS16 \
-                                0x00000064
-
-#define HIB1P2_O_ANA_DCDC_PARAMETERS17 \
-                                0x00000068
-
-#define HIB1P2_O_ANA_DCDC_PARAMETERS18 \
-                                0x0000006C
-
-#define HIB1P2_O_ANA_DCDC_PARAMETERS19 \
-                                0x00000070
-
-#define HIB1P2_O_FLASH_DCDC_PARAMETERS0 \
-                                0x00000074
-
-#define HIB1P2_O_FLASH_DCDC_PARAMETERS1 \
-                                0x00000078
-
-#define HIB1P2_O_FLASH_DCDC_PARAMETERS2 \
-                                0x0000007C
-
-#define HIB1P2_O_FLASH_DCDC_PARAMETERS3 \
-                                0x00000080
-
-#define HIB1P2_O_FLASH_DCDC_PARAMETERS4 \
-                                0x00000084
-
-#define HIB1P2_O_FLASH_DCDC_PARAMETERS5 \
-                                0x00000088
-
-#define HIB1P2_O_FLASH_DCDC_PARAMETERS6 \
-                                0x0000008C
-
-#define HIB1P2_O_PMBIST_PARAMETERS0 \
-                                0x00000094
-
-#define HIB1P2_O_PMBIST_PARAMETERS1 \
-                                0x00000098
-
-#define HIB1P2_O_PMBIST_PARAMETERS2 \
-                                0x0000009C
-
-#define HIB1P2_O_PMBIST_PARAMETERS3 \
-                                0x000000A0
-
-#define HIB1P2_O_FLASH_DCDC_PARAMETERS8 \
-                                0x000000A4
-
-#define HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE \
-                                0x000000A8
-
-#define HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE \
-                                0x000000AC
-
-#define HIB1P2_O_DIG_DCDC_VTRIM_CFG \
-                                0x000000B0
-
-#define HIB1P2_O_DIG_DCDC_FSM_PARAMETERS \
-                                0x000000B4
-
-#define HIB1P2_O_ANA_DCDC_FSM_PARAMETERS \
-                                0x000000B8
-
-#define HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS \
-                                0x000000BC
-
-#define HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG \
-                                0x000000C0
-
-#define HIB1P2_O_CM_OSC_16M_CONFIG \
-                                0x000000C4
-
-#define HIB1P2_O_SOP_SENSE_VALUE \
-                                0x000000C8
-
-#define HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 \
-                                0x000000CC
-
-#define HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 \
-                                0x000000D0
-
-#define HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES \
-                                0x000000D4
-
-#define HIB1P2_O_HIB1P2_EFUSE_READ_REG0 \
-                                0x000000D8
-
-#define HIB1P2_O_HIB1P2_EFUSE_READ_REG1 \
-                                0x000000DC
-
-#define HIB1P2_O_HIB1P2_POR_TEST_CTRL \
-                                0x000000E0
-
-#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 \
-                                0x000000E4
-
-#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 \
-                                0x000000E8
-
-#define HIB1P2_O_HIB_TIMER_SYNC_CFG2 \
-                                0x000000EC
-
-#define HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL \
-                                0x000000F0
-
-#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW \
-                                0x000000F4
-
-#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW \
-                                0x000000F8
-
-#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW \
-                                0x000000FC
-
-#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW \
-                                0x00000100
-
-#define HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR \
-                                0x00000104
-
-#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW \
-                                0x00000108
-
-#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW \
-                                0x0000010C
-
-#define HIB1P2_O_CM_SPARE       0x00000110
-#define HIB1P2_O_PORPOL_SPARE   0x00000114
-#define HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG \
-                                0x00000118
-
-#define HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG \
-                                0x0000011C
-
-#define HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG \
-                                0x00000120
-
-#define HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG \
-                                0x00000124
-
-#define HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE \
-                                0x00000128
-
-#define HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE \
-                                0x0000012C
-
-#define HIB1P2_O_MEM_HIB_FSM_DEBUG \
-                                0x00000130
-
-#define HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL \
-                                0x00000134
-
-#define HIB1P2_O_MEM_SLDO_WEAK_PROCESS \
-                                0x00000138
-
-#define HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS \
-                                0x0000013C
-
-#define HIB1P2_O_MEM_CM_TEST_MODE \
-                                0x00000140
-
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 register.
-//
-//******************************************************************************
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_M \
-                                0xC0000000
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_S 30
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_M \
-                                0x30000000
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_S 28
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_prot_lowv \
-                                0x08000000
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_override \
-                                0x04000000  // FSM Override value for SLDO_EN :
-                                            // Applicable only when bit [4] of
-                                            // this register is set to 1.
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_low_pwr_lowv \
-                                0x02000000
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_int_cap_sel_lowv \
-                                0x01000000
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_M \
-                                0x00FC0000
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_S 18
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_M \
-                                0x0003FF00
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_S 8
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_override \
-                                0x00000080  // FSM Override value for
-                                            // SKA_LDO_EN : Applicable only when
-                                            // bit [3] of this register is set
-                                            // to 1.
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_cap_ref_lowv \
-                                0x00000040
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_resdiv_ref_lowv \
-                                0x00000020
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_fsm_override_ctrl \
-                                0x00000010  // When 1, bit[26] of this register
-                                            // will be used as SLDO_EN
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_fsm_override_ctrl \
-                                0x00000008  // When 1, bit[26] of this register
-                                            // will be used as SKA_LDO_EN
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_M \
-                                0x00000007
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 register.
-//
-//******************************************************************************
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_M \
-                                0xFFC00000
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_S 22
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_M \
-                                0x003F0000
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_S 16
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_sldo_en_tload_lowv \
-                                0x00008000
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_tload_lowv \
-                                0x00004000
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_cap_sw_en_lowv \
-                                0x00002000
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_hib_lowv \
-                                0x00001000
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_vref_buf_lowv \
-                                0x00000800
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_M \
-                                0x000007FF
-
-#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_DIG_DCDC_PARAMETERS0 register.
-//
-//******************************************************************************
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_lowv_override \
-                                0x80000000  // Override value for DCDC_DIG_EN :
-                                            // Applicable only when bit [31] of
-                                            // DIG_DCDC_PARAMETERS1 [0x000C] is
-                                            // set to 1. Else from FSM
-
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_delayed_en_lowv \
-                                0x40000000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p8v_lowv_override \
-                                0x20000000  // Override value for
-                                            // DCDC_DIG_EN_SUBREG_1P8V :
-                                            // Applicable only when bit [30] of
-                                            // DIG_DCDC_PARAMETERS1 [0x000C] is
-                                            // set to 1. Else from FSM
-
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p2v_lowv_override \
-                                0x10000000  // Override value for
-                                            // DCDC_DIG_EN_SUBREG_1P2V :
-                                            // Applicable only when bit [29] of
-                                            // DIG_DCDC_PARAMETERS1 [0x000C] is
-                                            // set to 1. Else from FSM
-
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_slp_mode_lowv_override \
-                                0x08000000  // Override value for
-                                            // DCDC_DIG_SLP_EN : Applicable only
-                                            // when bit [28] of
-                                            // DIG_DCDC_PARAMETERS1 [0x000C] is
-                                            // set to 1. Else from FSM
-
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_ldo_mode_lowv \
-                                0x04000000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_nfet_rds_mode_lowv \
-                                0x02000000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_pfet_rds_mode_lowv \
-                                0x01000000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_ext_smps_override_mode_lowv \
-                                0x00800000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_clk_in_lowv_enable \
-                                0x00400000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_M \
-                                0x003F0000  // Override value for
-                                            // DCDC_DIG_VTRIM : Applicable only
-                                            // when bit [27] of
-                                            // DIG_DCDC_PARAMETERS1 [0x000C] is
-                                            // set to 1.
-
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_S 16
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_M \
-                                0x0000C000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_S 14
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_M \
-                                0x00003000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_S 12
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_cl_non_ov_lowv \
-                                0x00000800
-
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_M \
-                                0x00000780
-
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_S 7
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_M \
-                                0x00000078
-
-#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_S 3
-#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_M \
-                                0x00000007
-
-#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_DIG_DCDC_PARAMETERS1 register.
-//
-//******************************************************************************
-#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_lowv_fsm_override_ctrl \
-                                0x80000000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p8v_fsm_override_ctrl \
-                                0x40000000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p2v_fsm_override_ctrl \
-                                0x20000000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_slp_mode_lowv_fsm_override_ctrl \
-                                0x10000000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_vtrim_fsm_override_ctrl \
-                                0x08000000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_cot_mode_en_lowv_fsm_override_ctrl \
-                                0x04000000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_ilim_trim_lowv_efc_override_ctrl \
-                                0x02000000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_M \
-                                0x01FFFFFF
-
-#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_DIG_DCDC_PARAMETERS2 register.
-//
-//******************************************************************************
-#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_M \
-                                0xF0000000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_S 28
-#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_M \
-                                0x0F000000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_S 24
-#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_M \
-                                0x00C00000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_S 22
-#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_M \
-                                0x00300000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_S 20
-#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_M \
-                                0x000F0000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_S 16
-#define HIB1P2_DIG_DCDC_PARAMETERS2_NA5 \
-                                0x00008000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_M \
-                                0x00007800
-
-#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_S 11
-#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_en_shootthru_ctrl_lowv \
-                                0x00000400
-
-#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_M \
-                                0x000003FC
-
-#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_S 2
-#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_swcap_res_hf_clk_lowv \
-                                0x00000002
-
-#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_cot_mode_en_lowv_override \
-                                0x00000001  // Override value for
-                                            // DCDC_DIG_COT_EN : Applicable only
-                                            // when bit[26] of
-                                            // DIG_DCDC_PARAMETERS1 [0x000C] is
-                                            // set to 1.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_DIG_DCDC_PARAMETERS3 register.
-//
-//******************************************************************************
-#define HIB1P2_DIG_DCDC_PARAMETERS3_NA6 \
-                                0x80000000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_M \
-                                0x7F800000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_S 23
-#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_lowv \
-                                0x00400000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_hib_lowv \
-                                0x00200000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_M \
-                                0x001FE000  // Override value for
-                                            // DCDC_DIG_ILIM_TRIM : Applicable
-                                            // only when bit [25] of
-                                            // DIG_DCDC_PARAMETERS1 [0x000C] is
-                                            // set to 1
-
-#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_S 13
-#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_M \
-                                0x00001800
-
-#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_S 11
-#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_lowv \
-                                0x00000400
-
-#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_hib_lowv \
-                                0x00000200
-
-#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_M \
-                                0x000001F0
-
-#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_S 4
-#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_M \
-                                0x0000000C
-
-#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_S 2
-#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_uv_prot_lowv \
-                                0x00000002
-
-#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ov_prot_lowv \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_DIG_DCDC_PARAMETERS4 register.
-//
-//******************************************************************************
-#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_uv_prot_out_lowv \
-                                0x80000000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_ov_prot_out_lowv \
-                                0x40000000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS4_mem_dcdc_dig_en_tmux_lowv \
-                                0x20000000
-
-#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_M \
-                                0x1FFFFFFF
-
-#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_DIG_DCDC_PARAMETERS5 register.
-//
-//******************************************************************************
-#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_M \
-                                0xFFFFFFFF
-
-#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_DIG_DCDC_PARAMETERS6 register.
-//
-//******************************************************************************
-#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_M \
-                                0xFFFFFFFF
-
-#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_ANA_DCDC_PARAMETERS0 register.
-//
-//******************************************************************************
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_lowv_override \
-                                0x80000000  // Override for ANA DCDC EN
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_delayed_en_lowv \
-                                0x40000000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p8v_lowv \
-                                0x20000000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p2v_lowv \
-                                0x10000000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pwm_mode_lowv_override \
-                                0x08000000  // Override for ANA DCDC PWM
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_slp_mode_lowv_override \
-                                0x04000000  // Override for ANA DCDC SLP
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_ldo_mode_lowv \
-                                0x02000000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pfet_rds_mode_lowv \
-                                0x01000000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_nfet_rds_mode_lowv \
-                                0x00800000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_ext_smps_override_mode_lowv \
-                                0x00400000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_clk_in_lowv_enable \
-                                0x00200000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_M \
-                                0x001E0000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_S 17
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_M \
-                                0x00018000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_S 15
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_M \
-                                0x00006000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_S 13
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_cl_non_ov_lowv \
-                                0x00001000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_M \
-                                0x00000F00
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_S 8
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_M \
-                                0x000000F0
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_S 4
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_M \
-                                0x0000000F
-
-#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_ANA_DCDC_PARAMETERS1 register.
-//
-//******************************************************************************
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_M \
-                                0xF0000000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_S 28
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_M \
-                                0x0C000000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_S 26
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_M \
-                                0x03000000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_S 24
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_M \
-                                0x00F00000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_S 20
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_M \
-                                0x000F0000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_S 16
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_rtrim_lowv \
-                                0x00008000  // (Earlier SHOOTTHRU CTRL)
-
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_apwm_en_lowv \
-                                0x00004000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_M \
-                                0x00003E00
-
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_S 9
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_anti_glitch_lowv \
-                                0x00000100
-
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_hi_clamp_lowv \
-                                0x00000080
-
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_M \
-                                0x00000060
-
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_S 5
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_lo_clamp_lowv \
-                                0x00000010
-
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_M \
-                                0x0000000C
-
-#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_S 2
-#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_M \
-                                0x00000003
-
-#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_ANA_DCDC_PARAMETERS16 register.
-//
-//******************************************************************************
-#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_lowv \
-                                0x00200000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_hib_lowv \
-                                0x00100000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_M \
-                                0x000FF000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_S 12
-#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_M \
-                                0x00000C00
-
-#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_S 10
-#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_lowv \
-                                0x00000200
-
-#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_hib_lowv \
-                                0x00000100
-
-#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_M \
-                                0x000000F8
-
-#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_S 3
-#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_M \
-                                0x00000006
-
-#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_S 1
-#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ov_prot_lowv \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_ANA_DCDC_PARAMETERS17 register.
-//
-//******************************************************************************
-#define HIB1P2_ANA_DCDC_PARAMETERS17_dcdc_ana_ov_prot_out_lowv \
-                                0x80000000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS17_mem_dcdc_ana_en_tmux_lowv \
-                                0x40000000
-
-#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_M \
-                                0x3FFFFFFF
-
-#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_ANA_DCDC_PARAMETERS18 register.
-//
-//******************************************************************************
-#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_M \
-                                0xFFFFFFFF
-
-#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_ANA_DCDC_PARAMETERS19 register.
-//
-//******************************************************************************
-#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_M \
-                                0xFFFFFFFF
-
-#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_FLASH_DCDC_PARAMETERS0 register.
-//
-//******************************************************************************
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_lowv \
-                                0x80000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_delayed_en_lowv \
-                                0x40000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_clk_in_lowv_enable \
-                                0x20000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_M \
-                                0x18000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_S 27
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_mode_lowv \
-                                0x04000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_boost_mode_lowv \
-                                0x02000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_boost_mode_lowv \
-                                0x01000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_bb_alt_cycles_lowv \
-                                0x00800000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_cl_non_ov_lowv \
-                                0x00400000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_M \
-                                0x003C0000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_S 18
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_drv_lowv \
-                                0x00020000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pwm_mode_lowv \
-                                0x00010000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pfm_comp_lowv \
-                                0x00008000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_slp_mode_lowv \
-                                0x00004000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n1fet_rds_mode_lowv \
-                                0x00002000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n2fet_rds_mode_lowv \
-                                0x00001000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p1fet_rds_mode_lowv \
-                                0x00000800
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p2fet_rds_mode_lowv \
-                                0x00000400
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_ext_smps_mode_override_lowv \
-                                0x00000200
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_M \
-                                0x000001E0
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_S 5
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_M \
-                                0x0000001E
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_S 1
-#define HIB1P2_FLASH_DCDC_PARAMETERS0_NA18 \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_FLASH_DCDC_PARAMETERS1 register.
-//
-//******************************************************************************
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_M \
-                                0xF0000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_S 28
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_M \
-                                0x0F000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_S 24
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_M \
-                                0x00F00000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_S 20
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_M \
-                                0x000F0000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_S 16
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_M \
-                                0x0000F000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_S 12
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_M \
-                                0x00000F00
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_S 8
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_M \
-                                0x000000C0
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_S 6
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_M \
-                                0x00000030
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_S 4
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_M \
-                                0x0000000C
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_S 2
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_M \
-                                0x00000003
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_FLASH_DCDC_PARAMETERS2 register.
-//
-//******************************************************************************
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_M \
-                                0xC0000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_S 30
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_M \
-                                0x30000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_S 28
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_M \
-                                0x0C000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_S 26
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_M \
-                                0x03000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_S 24
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_shoot_thru_ctrl_lowv \
-                                0x00800000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_lowv \
-                                0x00400000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_hib_lowv \
-                                0x00200000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_M \
-                                0x001F0000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_S 16
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_M \
-                                0x0000F000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_S 12
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_lowv \
-                                0x00000800
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_hib_lowv \
-                                0x00000400
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_M \
-                                0x000003FC
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_S 2
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_M \
-                                0x00000003
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_FLASH_DCDC_PARAMETERS3 register.
-//
-//******************************************************************************
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_anti_glitch_lowv \
-                                0x80000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_hi_clamp_lowv \
-                                0x40000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_lo_clamp_lowv \
-                                0x20000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_M \
-                                0x1F000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_S 24
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_M \
-                                0x00E00000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_S 21
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_M \
-                                0x001C0000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_S 18
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_M \
-                                0x0003C000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_S 14
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_M \
-                                0x00003C00
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_S 10
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_M \
-                                0x00000300
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_S 8
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_ov_prot_lowv \
-                                0x00000080
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_uv_prot_lowv \
-                                0x00000040
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_tmux_lowv \
-                                0x00000020
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_M \
-                                0x0000001F
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_FLASH_DCDC_PARAMETERS4 register.
-//
-//******************************************************************************
-#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_M \
-                                0xFFFFFFFF
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_FLASH_DCDC_PARAMETERS5 register.
-//
-//******************************************************************************
-#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_M \
-                                0xFFFFFFFF
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_FLASH_DCDC_PARAMETERS6 register.
-//
-//******************************************************************************
-#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_ov_prot_out_lowv \
-                                0x80000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_uv_prot_out_lowv \
-                                0x40000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_M \
-                                0x3FFFFFFF
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_PMBIST_PARAMETERS0 register.
-//
-//******************************************************************************
-#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_en_lowv \
-                                0x80000000
-
-#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_M \
-                                0x7FFFF800
-
-#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_S 11
-#define HIB1P2_PMBIST_PARAMETERS0_NA21_M \
-                                0x000007FF
-
-#define HIB1P2_PMBIST_PARAMETERS0_NA21_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_PMBIST_PARAMETERS1 register.
-//
-//******************************************************************************
-#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_M \
-                                0xFFFF0000
-
-#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_S 16
-#define HIB1P2_PMBIST_PARAMETERS1_mem_pmtest_en_lowv \
-                                0x00008000
-
-#define HIB1P2_PMBIST_PARAMETERS1_NA22_M \
-                                0x00007FFF
-
-#define HIB1P2_PMBIST_PARAMETERS1_NA22_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_PMBIST_PARAMETERS2 register.
-//
-//******************************************************************************
-#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_M \
-                                0xFFFFFFFF
-
-#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_PMBIST_PARAMETERS3 register.
-//
-//******************************************************************************
-#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_M \
-                                0xFFFF0000
-
-#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_S 16
-#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_M \
-                                0x0000E000
-
-#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_S 13
-#define HIB1P2_PMBIST_PARAMETERS3_mem_rnwell_calib_en_lowv \
-                                0x00001000
-
-#define HIB1P2_PMBIST_PARAMETERS3_NA23_M \
-                                0x00000FFF
-
-#define HIB1P2_PMBIST_PARAMETERS3_NA23_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_FLASH_DCDC_PARAMETERS8 register.
-//
-//******************************************************************************
-#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_en_flash_sup_comp_lowv \
-                                0x80000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_M \
-                                0x7C000000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_S 26
-#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_M \
-                                0x03E00000
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_S 21
-#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_M \
-                                0x001FFFFF
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE register.
-//
-//******************************************************************************
-#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_M \
-                                0xFFFFFFC0
-
-#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_S 6
-#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p2v_lowv_override_ctrl \
-                                0x00000020
-
-#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p8v_lowv_override_ctrl \
-                                0x00000010
-
-#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_ilim_trim_lowv_efc_override_ctrl \
-                                0x00000008
-
-#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_slp_mode_lowv_fsm_override_ctrl \
-                                0x00000004
-
-#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_pwm_mode_lowv_fsm_override_ctrl \
-                                0x00000002
-
-#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_lowv_fsm_override_ctrl \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE register.
-//
-//******************************************************************************
-#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_M \
-                                0xFFFFFFFC
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_S 2
-#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_en_lowv_override_ctrl \
-                                0x00000002
-
-#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_ilim_trim_lowv_override_ctrl \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_DIG_DCDC_VTRIM_CFG register.
-//
-//******************************************************************************
-#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_M \
-                                0xFF000000
-
-#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_S 24
-#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_M \
-                                0x00FC0000
-
-#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_S 18
-#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_M \
-                                0x0003F000
-
-#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_S 12
-#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_M \
-                                0x00000FC0
-
-#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_S 6
-#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_M \
-                                0x0000003F
-
-#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_DIG_DCDC_FSM_PARAMETERS register.
-//
-//******************************************************************************
-#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_M \
-                                0xFFFF8000
-
-#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_S 15
-#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_M \
-                                0x00007000
-
-#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_S 12
-#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_M \
-                                0x00000E00
-
-#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_S 9
-#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_M \
-                                0x000001C0
-
-#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_S 6
-#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_M \
-                                0x00000038
-
-#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_S 3
-#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_M \
-                                0x00000007
-
-#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_ANA_DCDC_FSM_PARAMETERS register.
-//
-//******************************************************************************
-#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_M \
-                                0xFFFFFFF8
-
-#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_S 3
-#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_M \
-                                0x00000007
-
-#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS register.
-//
-//******************************************************************************
-#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_M \
-                                0xFFFFFFC0
-
-#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_S 6
-#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_M \
-                                0x00000038
-
-#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_S 3
-#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_M \
-                                0x00000007
-
-#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG register.
-//
-//******************************************************************************
-#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_M \
-                                0xFFFFFFF8
-
-#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_S 3
-#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_M \
-                                0x00000007
-
-#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_CM_OSC_16M_CONFIG register.
-//
-//******************************************************************************
-#define HIB1P2_CM_OSC_16M_CONFIG_reserved_M \
-                                0xFFFC0000
-
-#define HIB1P2_CM_OSC_16M_CONFIG_reserved_S 18
-#define HIB1P2_CM_OSC_16M_CONFIG_cm_clk_good_16m \
-                                0x00020000
-
-#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_en_osc_16m \
-                                0x00010000
-
-#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_M \
-                                0x0000FC00
-
-#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_S 10
-#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_M \
-                                0x000003F0
-
-#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_S 4
-#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_en_sli_16m \
-                                0x00000008
-
-#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_M \
-                                0x00000007
-
-#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_SOP_SENSE_VALUE register.
-//
-//******************************************************************************
-#define HIB1P2_SOP_SENSE_VALUE_reserved_M \
-                                0xFFFFFF00
-
-#define HIB1P2_SOP_SENSE_VALUE_reserved_S 8
-#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_M \
-                                0x000000FF
-
-#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 register.
-//
-//******************************************************************************
-#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_M \
-                                0xFFFFFFFF
-
-#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 register.
-//
-//******************************************************************************
-#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_M \
-                                0x0000FFFF
-
-#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES register.
-//
-//******************************************************************************
-#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_M \
-                                0xFF800000
-
-#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_S 23
-#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_ctrl \
-                                0x00400000
-
-#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_M \
-                                0x003FC000
-
-#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_S 14
-#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_ctrl \
-                                0x00002000
-
-#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_M \
-                                0x00001FC0
-
-#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_S 6
-#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_ctrl \
-                                0x00000020
-
-#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_M \
-                                0x0000001F
-
-#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_HIB1P2_EFUSE_READ_REG0 register.
-//
-//******************************************************************************
-#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_M \
-                                0xFFFFFFFF  // Corresponds to ROW_12 of
-                                            // FUSEFARM. [7:0] :
-                                            // DCDC_DIG_ILIM_TRIM_LOWV(7:0)
-                                            // [15:8] :
-                                            // DCDC_ANA_ILIM_TRIM_LOWV(7:0)
-                                            // [23:16] :
-                                            // DCDC_FLASH_ILIM_TRIM_LOWV(7:0)
-                                            // [24:24] : DTHE SHA DISABLE
-                                            // [25:25] : DTHE DES DISABLE
-                                            // [26:26] : DTHE AES DISABLE
-                                            // [31:27] : HD_BG_RTRIM (4:0)
-
-#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_HIB1P2_EFUSE_READ_REG1 register.
-//
-//******************************************************************************
-#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_M \
-                                0xFFFFFFFF  // Corresponds to ROW_13 of the
-                                            // FUSEFARM. [7:0] : HD_BG_MAG_TRIM
-                                            // (7:0) [14:8] : HD_BG_TEMP_TRIM
-                                            // (6:0) [15:15] : GREYOUT ENABLE
-                                            // DUTY CYCLING [31:16] :
-                                            // Reserved/Checksum
-
-#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_HIB1P2_POR_TEST_CTRL register.
-//
-//******************************************************************************
-#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_M \
-                                0xFFFFFF00
-
-#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_S 8
-#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_M \
-                                0x000000FF
-
-#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 register.
-//
-//******************************************************************************
-#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_M \
-                                0xFFFF0000
-
-#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_S 16
-#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_M \
-                                0x0000FF00
-
-#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_S 8
-#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_M \
-                                0x000000FE
-
-#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_S 1
-#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_start \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 register.
-//
-//******************************************************************************
-#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_M \
-                                0xFFF00000
-
-#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_S 20
-#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_M \
-                                0x000FFFFF
-
-#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_HIB_TIMER_SYNC_CFG2 register.
-//
-//******************************************************************************
-#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_M \
-                                0xFFFFFE00
-
-#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_S 9
-#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_hib_unload \
-                                0x00000100
-
-#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_M \
-                                0x000000FC
-
-#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_S 2
-#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_tsf_adj \
-                                0x00000002
-
-#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_update_tsf \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL register.
-//
-//******************************************************************************
-#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_M \
-                                0xFFFFFFFF
-
-#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW register.
-//
-//******************************************************************************
-#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_M \
-                                0xFFFFFFFF
-
-#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW register.
-//
-//******************************************************************************
-#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_M \
-                                0xFFFF0000
-
-#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_S 16
-#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_M \
-                                0x0000FFFF
-
-#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW register.
-//
-//******************************************************************************
-#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_M \
-                                0xFFFFFFFF
-
-#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW register.
-//
-//******************************************************************************
-#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_M \
-                                0xFFFF0000
-
-#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_S 16
-#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_M \
-                                0x0000FFFF
-
-#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR register.
-//
-//******************************************************************************
-#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_M \
-                                0xFFFFF000
-
-#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_S 12
-#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_M \
-                                0x00000FFF
-
-#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW register.
-//
-//******************************************************************************
-#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_M \
-                                0xFFFFFFFF
-
-#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW register.
-//
-//******************************************************************************
-#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_M \
-                                0xFFFFFFFF
-
-#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the HIB1P2_O_CM_SPARE register.
-//
-//******************************************************************************
-#define HIB1P2_CM_SPARE_CM_SPARE_OUT_M \
-                                0xFF000000
-
-#define HIB1P2_CM_SPARE_CM_SPARE_OUT_S 24
-#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_M \
-                                0x00FF0000
-
-#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_S 16
-#define HIB1P2_CM_SPARE_MEM_CM_SPARE_M \
-                                0x0000FFFF
-
-#define HIB1P2_CM_SPARE_MEM_CM_SPARE_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_PORPOL_SPARE register.
-//
-//******************************************************************************
-#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_M \
-                                0xFFFFFFFF
-
-#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG register.
-//
-//******************************************************************************
-#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_ENABLE \
-                                0x00000100
-
-#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_M \
-                                0x000000F0
-
-#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_S 4
-#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_M \
-                                0x0000000F
-
-#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG register.
-//
-//******************************************************************************
-#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_ENABLE \
-                                0x00000100
-
-#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_M \
-                                0x000000F0
-
-#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_S 4
-#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_M \
-                                0x0000000F
-
-#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG register.
-//
-//******************************************************************************
-#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_ENABLE \
-                                0x00000100
-
-#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_M \
-                                0x000000F0
-
-#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_S 4
-#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_M \
-                                0x0000000F
-
-#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG register.
-//
-//******************************************************************************
-#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_ENABLE \
-                                0x00000100
-
-#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_M \
-                                0x000000F0
-
-#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_S 4
-#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_M \
-                                0x0000000F
-
-#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE register.
-//
-//******************************************************************************
-#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE_CTRL \
-                                0x00000002
-
-#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE register.
-//
-//******************************************************************************
-#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE_CTRL \
-                                0x00000002
-
-#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_MEM_HIB_FSM_DEBUG register.
-//
-//******************************************************************************
-#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_M \
-                                0x00000700
-
-#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_S 8
-#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_M \
-                                0x000000F0
-
-#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_S 4
-#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_M \
-                                0x0000000F
-
-#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL register.
-//
-//******************************************************************************
-#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_M \
-                                0x000FFFFF
-
-#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_MEM_SLDO_WEAK_PROCESS register.
-//
-//******************************************************************************
-#define HIB1P2_MEM_SLDO_WEAK_PROCESS_MEM_SLDO_WEAK_PROCESS \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS register.
-//
-//******************************************************************************
-#define HIB1P2_MEM_PA_DCDC_OV_UV_STATUS_dcdc_pa_ov_prot_out_lowv \
-                                0x00000002
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB1P2_O_MEM_CM_TEST_MODE register.
-//
-//******************************************************************************
-#define HIB1P2_MEM_CM_TEST_MODE_mem_cm_test_mode \
-                                0x00000001
-
-
-
-
-#endif // __HW_HIB1P2_H__
diff --git a/cc3200/hal/inc/hw_hib3p3.h b/cc3200/hal/inc/hw_hib3p3.h
deleted file mode 100644
index 970168916..000000000
--- a/cc3200/hal/inc/hw_hib3p3.h
+++ /dev/null
@@ -1,1138 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_HIB3P3_H__
-#define __HW_HIB3P3_H__
-
-//*****************************************************************************
-//
-// The following are defines for the HIB3P3 register offsets.
-//
-//*****************************************************************************
-#define HIB3P3_O_MEM_HIB_REQ    0x00000000
-#define HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE \
-                                0x00000004
-
-#define HIB3P3_O_MEM_HIB_RTC_TIMER_RESET \
-                                0x00000008
-
-#define HIB3P3_O_MEM_HIB_RTC_TIMER_READ \
-                                0x0000000C
-
-#define HIB3P3_O_MEM_HIB_RTC_TIMER_LSW \
-                                0x00000010
-
-#define HIB3P3_O_MEM_HIB_RTC_TIMER_MSW \
-                                0x00000014
-
-#define HIB3P3_O_MEM_HIB_RTC_WAKE_EN \
-                                0x00000018
-
-#define HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF \
-                                0x0000001C
-
-#define HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF \
-                                0x00000020
-
-#define HIB3P3_O_MEM_INT_OSC_CONF \
-                                0x0000002C
-
-#define HIB3P3_O_MEM_XTAL_OSC_CONF \
-                                0x00000034
-
-#define HIB3P3_O_MEM_BGAP_PARAMETERS0 \
-                                0x00000038
-
-#define HIB3P3_O_MEM_BGAP_PARAMETERS1 \
-                                0x0000003C
-
-#define HIB3P3_O_MEM_HIB_DETECTION_STATUS \
-                                0x00000040
-
-#define HIB3P3_O_MEM_HIB_MISC_CONTROLS \
-                                0x00000044
-
-#define HIB3P3_O_MEM_HIB_CONFIG 0x00000050
-#define HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE \
-                                0x00000054
-
-#define HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF \
-                                0x00000058
-
-#define HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF \
-                                0x0000005C
-
-#define HIB3P3_O_MEM_HIB_UART_CONF \
-                                0x00000400
-
-#define HIB3P3_O_MEM_GPIO_WAKE_EN \
-                                0x00000404
-
-#define HIB3P3_O_MEM_GPIO_WAKE_CONF \
-                                0x00000408
-
-#define HIB3P3_O_MEM_PAD_OEN_RET33_CONF \
-                                0x0000040C
-
-#define HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF \
-                                0x00000410
-
-#define HIB3P3_O_MEM_JTAG_CONF  0x00000414
-#define HIB3P3_O_MEM_HIB_REG0   0x00000418
-#define HIB3P3_O_MEM_HIB_REG1   0x0000041C
-#define HIB3P3_O_MEM_HIB_REG2   0x00000420
-#define HIB3P3_O_MEM_HIB_REG3   0x00000424
-#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 \
-                                0x0000045C
-
-#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 \
-                                0x00000460
-
-#define HIB3P3_O_MEM_HIB_MISC_CONFIG \
-                                0x00000464
-
-#define HIB3P3_O_MEM_HIB_WAKE_STATUS \
-                                0x00000468
-
-#define HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL \
-                                0x0000046C
-
-#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 \
-                                0x00000470
-
-#define HIB3P3_O_HIBANA_SPARE_LOWV \
-                                0x00000474
-
-#define HIB3P3_O_HIB_TMUX_CTRL  0x00000478
-#define HIB3P3_O_HIB_1P2_1P8_LDO_TRIM \
-                                0x0000047C
-
-#define HIB3P3_O_HIB_COMP_TRIM  0x00000480
-#define HIB3P3_O_HIB_EN_TS      0x00000484
-#define HIB3P3_O_HIB_1P8V_DET_EN \
-                                0x00000488
-
-#define HIB3P3_O_HIB_VBAT_MON_EN \
-                                0x0000048C
-
-#define HIB3P3_O_HIB_NHIB_ENABLE \
-                                0x00000490
-
-#define HIB3P3_O_HIB_UART_RTS_SW_ENABLE \
-                                0x00000494
-
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_REQ register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_REQ_reserved_M \
-                                0xFFFFFE00
-
-#define HIB3P3_MEM_HIB_REQ_reserved_S 9
-#define HIB3P3_MEM_HIB_REQ_NU1_M \
-                                0x000001FC
-
-#define HIB3P3_MEM_HIB_REQ_NU1_S 2
-#define HIB3P3_MEM_HIB_REQ_mem_hib_clk_disable \
-                                0x00000002  // 1 - Specifies that the Hiberante
-                                            // mode is without clocks ; 0 -
-                                            // Specified that the Hibernate mode
-                                            // is with clocks This register will
-                                            // be reset during Hibernate
-                                            // -WO-Clks mode (but not during
-                                            // Hibernate-W-Clks mode).
-
-#define HIB3P3_MEM_HIB_REQ_mem_hib_req \
-                                0x00000001  // 1 - Request for hibernate mode
-                                            // (This is an auto-clear bit) ; 0 -
-                                            // Donot request for hibernate mode
-                                            // This register will be reset
-                                            // during Hibernate -WO-Clks mode
-                                            // (but not during Hibernate-W-Clks
-                                            // mode).
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_M \
-                                0xFFFFFFFE
-
-#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_S 1
-#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_mem_hib_rtc_timer_enable \
-                                0x00000001  // 1 - Enable the RTC timer to
-                                            // start running ; 0 - Keep the RTC
-                                            // timer disabled This register will
-                                            // be reset during Hibernate
-                                            // -WO-Clks mode (but not during
-                                            // Hibernate-W-Clks mode).
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_RTC_TIMER_RESET register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_M \
-                                0xFFFFFFFE
-
-#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_S 1
-#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_mem_hib_rtc_timer_reset \
-                                0x00000001  // 1 - Reset the RTC timer ; 0 -
-                                            // Donot reset the RTC timer. This
-                                            // is an auto-clear bit. This
-                                            // register will be reset during
-                                            // Hibernate -WO-Clks mode (but not
-                                            // during Hibernate-W-Clks mode).
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_RTC_TIMER_READ register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_M \
-                                0xFFFFFFFE
-
-#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_S 1
-#define HIB3P3_MEM_HIB_RTC_TIMER_READ_mem_hib_rtc_timer_read \
-                                0x00000001  // 1 - Latch the running RTC timer
-                                            // into local registers. After
-                                            // programming this bit to 1, the
-                                            // F/w can read the latched RTC
-                                            // timer values from
-                                            // MEM_HIB_RTC_TIMER_LSW and
-                                            // MEM_HIB_RTC_TIMER_MSW. Before the
-                                            // F/w (APPS or NWP) wants to read
-                                            // the RTC-Timer, it has to program
-                                            // this bit to 1, then only read the
-                                            // MSW and LSW values. This is an
-                                            // auto-clear bit. This register
-                                            // will be reset during Hibernate
-                                            // -WO-Clks mode (but not during
-                                            // Hibernate-W-Clks mode).
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_RTC_TIMER_LSW register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_M \
-                                0xFFFFFFFF  // Lower 32b value of the latched
-                                            // RTC-Timer.
-
-#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_RTC_TIMER_MSW register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_M \
-                                0xFFFF0000
-
-#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_S 16
-#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_M \
-                                0x0000FFFF  // Upper 32b value of the latched
-                                            // RTC-Timer.
-
-#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_RTC_WAKE_EN register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_M \
-                                0xFFFFFFFE
-
-#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_S 1
-#define HIB3P3_MEM_HIB_RTC_WAKE_EN_mem_hib_rtc_wake_en \
-                                0x00000001  // 1 - Enable the RTC timer based
-                                            // wakeup during Hibernate mode ; 0
-                                            // - Disable the RTC timer based
-                                            // wakeup during Hibernate mode This
-                                            // register will be reset during
-                                            // Hibernate-WO-Clks mode (but not
-                                            // during Hibernate-W-Clks mode).
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_M \
-                                0xFFFFFFFF  // Configuration for RTC-Timer
-                                            // Wakeup (Lower 32b word)
-
-#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_M \
-                                0xFFFF0000
-
-#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_S 16
-#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_M \
-                                0x0000FFFF  // Configuration for RTC-Timer
-                                            // Wakeup (Upper 16b word)
-
-#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_INT_OSC_CONF register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_INT_OSC_CONF_reserved_M \
-                                0xFFFF0000
-
-#define HIB3P3_MEM_INT_OSC_CONF_reserved_S 16
-#define HIB3P3_MEM_INT_OSC_CONF_cm_clk_good_32k_int \
-                                0x00008000  // 1 - Internal 32kHz Oscillator is
-                                            // valid ; 0 - Internal 32k
-                                            // oscillator clk is not valid
-
-#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_M \
-                                0x00007E00
-
-#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_S 9
-#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k_override_ctrl \
-                                0x00000100  // When 1, the INT_32K_OSC_EN comes
-                                            // from bit [0] of this register,
-                                            // else comes from the FSM. This
-                                            // register will be reset during
-                                            // Hibernate-WO-Clks mode (but not
-                                            // during Hibernate-W-Clks mode)
-
-#define HIB3P3_MEM_INT_OSC_CONF_NU1 \
-                                0x00000080
-
-#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_M \
-                                0x0000007E
-
-#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_S 1
-#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k \
-                                0x00000001  // Override value for INT_OSC_EN.
-                                            // Applicable only when bit [3] of
-                                            // this register is set to 1.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_XTAL_OSC_CONF register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_M \
-                                0xFFF00000
-
-#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_S 20
-#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k_override_ctrl \
-                                0x00080000  // When 1, the SLICER_EN comes from
-                                            // bit [10] of this register, else
-                                            // comes from the FSM.
-
-#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k_override_ctrl \
-                                0x00040000  // When 1, the XTAL_EN comes from
-                                            // bit [0] of this register, else
-                                            // comes from the FSM.
-
-#define HIB3P3_MEM_XTAL_OSC_CONF_cm_clk_good_xtal \
-                                0x00020000  // 1 - XTAL Clk is good ; 0 - XTAL
-                                            // Clk is yet to be valid.
-
-#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_M \
-                                0x0001F800
-
-#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_S 11
-#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k \
-                                0x00000400  // SLICER_EN Override value :
-                                            // Applicable only when bit [19] of
-                                            // this register is set to 1.
-
-#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_M \
-                                0x00000380
-
-#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_S 7
-#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_M \
-                                0x00000070
-
-#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_S 4
-#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_fref_32k_slicer \
-                                0x00000008
-
-#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_M \
-                                0x00000006
-
-#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_S 1
-#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k \
-                                0x00000001  // XTAL_EN Override value :
-                                            // Applicable only when bit [18] of
-                                            // this register is set to 1.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_BGAP_PARAMETERS0 register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_M \
-                                0xFFF80000
-
-#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_S 19
-#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_en_seq \
-                                0x00040000
-
-#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_M \
-                                0x0001C000
-
-#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_S 14
-#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbat_ok_4bg \
-                                0x00001000
-
-#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp \
-                                0x00000800
-
-#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp_ref \
-                                0x00000400
-
-#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_M \
-                                0x000003FF
-
-#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_BGAP_PARAMETERS1 register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_M \
-                                0xE0000000
-
-#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_S 29
-#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_M \
-                                0x1F000000
-
-#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_S 24
-#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_act_iref \
-                                0x00000008
-
-#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_v2i \
-                                0x00000004
-
-#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_cap_sw \
-                                0x00000002
-
-#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_DETECTION_STATUS register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_M \
-                                0xFFFFFF80
-
-#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_S 7
-#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_ana_status \
-                                0x00000040  // 1 - 1.8 V supply forced mode.
-
-#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_flash_status \
-                                0x00000004  // 1 - 3.3 V supply forced mode for
-                                            // Flash supply
-
-#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_ext_clk_det_out_status \
-                                0x00000002  // 1 - Forced clock mode
-
-#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_xtal_det_out_status \
-                                0x00000001  // 1 - XTAL clock mode
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_MISC_CONTROLS register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_M \
-                                0xFFFFF800
-
-#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_S 11
-#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp \
-                                0x00000400
-
-#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp_ref \
-                                0x00000200
-
-#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_M \
-                                0x000001C0
-
-#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_S 6
-#define HIB3P3_MEM_HIB_MISC_CONTROLS_NU1 \
-                                0x00000020
-
-#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_flash_det_en \
-                                0x00000010
-
-#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_tmux \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_CONFIG register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_M \
-                                0xFF000000
-
-#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_S 24
-#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED3 \
-                                0x00080000  // 1 - Enable VDD_FLASH_INDP_PAD
-                                            // for digital path (SHARED4) ; 0 -
-                                            // Disable VDD_FLASH_INDP_PAD for
-                                            // digital path (SHARED4) ; Before
-                                            // programming this bit to 1, ensure
-                                            // that the device is in FORCED 3.3
-                                            // supply Mode, which can be
-                                            // inferred from the register :
-                                            // MEM_HIB_DETECTION_STATUS : 0x0040
-
-#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED2 \
-                                0x00040000  // 1 - Enable the
-                                            // VDD_FB_GPIO_MUX_PAD for digital
-                                            // path (SHARED3) ; 0 - Disable the
-                                            // VDD_FB_GPIO_MUX_PAD for digital
-                                            // path (SHARED3) ; This pin can be
-                                            // used only in modes other than
-                                            // SOP("111")
-
-#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED1 \
-                                0x00020000  // 1 - Enable the PM_TEST_PAD for
-                                            // digital GPIO path (SHARED2) ; 0 -
-                                            // Disable the PM_TEST_PAD for
-                                            // digital GPIO path (SHARED2) This
-                                            // pin can be used for digital only
-                                            // in modes other then SOP-111
-
-#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED0 \
-                                0x00010000  // 1 - Enable the XTAL_N pin
-                                            // digital GPIO path (SHARED1); 0 -
-                                            // Disable the XTAL_N pin digital
-                                            // GPIO path (SHARED1). Before
-                                            // programming this bit to 1, ensure
-                                            // that the device is in FORCED CLK
-                                            // Mode, which can inferred from the
-                                            // register :
-                                            // MEM_HIB_DETECTION_STATUS :
-                                            // 0x0040.
-
-#define HIB3P3_MEM_HIB_CONFIG_mem_hib_xtal_enable \
-                                0x00000100  // 1 - Enable the XTAL Clock ; 0 -
-                                            // Donot enable the XTAL Clock. This
-                                            // bit has to be programmed to 1 (by
-                                            // APPS Devinit F/w), during exit
-                                            // from OFF or Hib_wo_clks modes,
-                                            // after checking if the slow_clk
-                                            // mode is XTAL_CLK mode. Once
-                                            // enabled the XTAL will be disabled
-                                            // only after entering HIB_WO_CLKS
-                                            // mode. This register will be reset
-                                            // during Hibernate -WO-Clks mode
-                                            // (but not during Hibernate-W-Clks
-                                            // mode).
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_RTC_IRQ_ENABLE_HIB_RTC_IRQ_ENABLE \
-                                0x00000001  // 1 - Enable the HIB RTC - IRQ ; 0
-                                            // - Disable the HIB RTC - IRQ
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_M \
-                                0xFFFFFFFF  // Configuration for LSW of the
-                                            // RTC-Timestamp at which interrupt
-                                            // need to be generated
-
-#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_M \
-                                0x0000FFFF  // Configuration for MSW of thr
-                                            // RTC-Timestamp at which the
-                                            // interrupt need to be generated
-
-#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_UART_CONF register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_UART_CONF_reserved_M \
-                                0xFFFFFFFE
-
-#define HIB3P3_MEM_HIB_UART_CONF_reserved_S 1
-#define HIB3P3_MEM_HIB_UART_CONF_mem_hib_uart_wake_en \
-                                0x00000001  // 1 - Enable the UART-Autonomous
-                                            // mode wakeup during Hibernate mode
-                                            // ; This is an auto-clear bit, once
-                                            // programmed to 1, it will latched
-                                            // into an internal register which
-                                            // remain asserted until the
-                                            // Hib-wakeup is initiated.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_GPIO_WAKE_EN register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_M \
-                                0xFFFFFF00
-
-#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_S 8
-#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_M \
-                                0x000000FF  // 1 - Enable the GPIO-Autonomous
-                                            // mode wakeup during Hibernate mode
-                                            // ; This is an auto-clear bit, once
-                                            // programmed to 1, it will latched
-                                            // into an internal register which
-                                            // remain asserted until the
-                                            // Hib-wakeup is initiated.
-
-#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_GPIO_WAKE_CONF register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_M \
-                                0xFFFF0000
-
-#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_S 16
-#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_M \
-                                0x0000FFFF  // Configuration to say whether the
-                                            // GPIO wakeup has to happen on
-                                            // Level0 or falling-edge for the
-                                            // given group. “00” – Level0 “01” –
-                                            // Level1 “10”- Fall-edge “11”-
-                                            // Rise-edge [1:0] – Conf for GPIO0
-                                            // [3:2] – Conf for GPIO1 [5:4] –
-                                            // Conf for GPIO2 [7:6] – Conf for
-                                            // GPIO3 [9:8] – Conf for GPIO4
-                                            // [11:10] – Conf for GPIO5 [13:12]
-                                            // – Conf for GPIO6
-
-#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_PAD_OEN_RET33_CONF register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_PAD_OEN_RET33_CONF_mem_pad_oen_ret33_override_ctrl \
-                                0x00000004  // 1 - Override the OEN33 and RET33
-                                            // controls of GPIOs during
-                                            // SOP-Bootdebug mode ; 0 - Donot
-                                            // override the OEN33 and RET33
-                                            // controls of GPIOs during
-                                            // SOP-Bootdebug mode
-
-#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_OEN33_CONF \
-                                0x00000002
-
-#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_RET33_CONF \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_mem_uart_nrts_oen_ret33_override_ctrl \
-                                0x00000004  // 1 - Override the OEN33 and RET33
-                                            // controls of UART NRTS GPIO during
-                                            // SOP-Bootdebug mode ; 0 - Donot
-                                            // override the OEN33 and RET33
-                                            // controls of UART NRTS GPIO during
-                                            // SOP-Bootdebug mode
-
-#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_OEN33_CONF \
-                                0x00000002
-
-#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_RET33_CONF \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_JTAG_CONF register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_JTAG_CONF_mem_jtag1_oen_ret33_override_ctrl \
-                                0x00000200
-
-#define HIB3P3_MEM_JTAG_CONF_mem_jtag0_oen_ret33_override_ctrl \
-                                0x00000100
-
-#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_OEN33_CONF \
-                                0x00000008
-
-#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_RET33_CONF \
-                                0x00000004
-
-#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_OEN33_CONF \
-                                0x00000002
-
-#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_RET33_CONF \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_REG0 register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_M \
-                                0xFFFFFFFF
-
-#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_REG1 register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_M \
-                                0xFFFFFFFF
-
-#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_REG2 register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_M \
-                                0xFFFFFFFF
-
-#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_REG3 register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_M \
-                                0xFFFFFFFF
-
-#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_M \
-                                0xFFFF0000  // Configuration for the number of
-                                            // slow-clks between de-assertion of
-                                            // EN_BG_3P3V to assertion of
-                                            // EN_BG_3P3V
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_S 16
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_NU1 \
-                                0x00008000
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_M \
-                                0x00006000  // Configuration for the number of
-                                            // slow-clks between assertion of
-                                            // EN_COMP_3P3V and assertion of
-                                            // EN_COMP_LATCH_3P3V
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_S 13
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_M \
-                                0x00001800  // Configuration for the number of
-                                            // slow-clks between assertion of
-                                            // (EN_CAP_SW_3P3V,EN_COMP_REF) and
-                                            // assertion of (EN_COMP_3P3V)
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_S 11
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_M \
-                                0x00000600  // Configuration for the number of
-                                            // slow-clks between assertion of
-                                            // (EN_BG_3P3V) and assertion of
-                                            // (EN_CAP_SW_3P3V,
-                                            // EN_COMP_REF_3P3V)
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_S 9
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_crude_ref_comp \
-                                0x00000100
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_ref_override_ctrl \
-                                0x00000080  // 1 - EN_VBOK4BG_REF comes from
-                                            // bit[10] of the register
-                                            // MEM_BGAP_PARAMETERS0 [0x0038]. 0
-                                            // - EN_VBOK4BG_REF comes directly
-                                            // from the Hib-Sequencer.
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_comp_override_ctrl \
-                                0x00000040  // 1 - EN_VBOK4BG comes from
-                                            // bit[11] of the register
-                                            // MEM_BGAP_PARAMETERS0 [0x0038]. 0
-                                            // - EN_VBOK4BG comes directly from
-                                            // the Hib-Sequencer.
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_v2i_override_ctrl \
-                                0x00000020  // 1 - EN_V2I comes from bit[2] of
-                                            // the register MEM_BGAP_PARAMETERS1
-                                            // [0x003C]. 0 - EN_V2I comes
-                                            // directly from the Hib-Sequencer.
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_por_comp_ref_override_ctrl \
-                                0x00000010  // 1 - EN_POR_COMP_REF comes from
-                                            // bit[9] of the register
-                                            // MEM_HIB_MISC_CONTROLS [0x0044]. 0
-                                            // - EN_POR_COMP_REF comes directly
-                                            // from the Hib-Sequencer.
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_por_comp_override_ctrl \
-                                0x00000008  // 1 - EN_POR_COMP comes from
-                                            // bit[10] of the register
-                                            // MEM_HIB_MISC_CONTROLS [0x044]. 0
-                                            // - EN_POR_COMP comes directly from
-                                            // the Hib-Sequencer.
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_cap_sw_override_ctrl \
-                                0x00000004  // 1 - EN_CAP_SW comes from bit[1]
-                                            // of the register
-                                            // MEM_BGAP_PARAMETERS1 [0x003C]. 0
-                                            // - EN_CAP_SW comes directly from
-                                            // Hib-Sequencer.
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bg_override_ctrl \
-                                0x00000002  // 1 - EN_BGAP comes from bit[0] of
-                                            // the register MEM_BGAP_PARAMETERS1
-                                            // [0x003C]. 0 - EN_BGAP comes
-                                            // directly from Hib-Sequencer.
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_act_iref_override_ctrl \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_M \
-                                0xFFFF0000
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_S 16
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_M \
-                                0x0000C000  // Configuration for number of
-                                            // slow-clks between de-assertion of
-                                            // EN_COMP_LATCH and assertion of
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_S 14
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_M \
-                                0x00003000  // Configuration for number of
-                                            // slow-clks between assertion of
-                                            // EN_COMP_REF to assertion of
-                                            // EN_COMP during HIB-Exit
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_S 12
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_M \
-                                0x00000C00  // TBD
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_S 10
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_M \
-                                0x00000300  // Configuration in number of
-                                            // slow-clks between assertion of
-                                            // (EN_BGAP_3P3V, EN_CAP_SW_3P3V,
-                                            // EN_ACT_IREF_3P3V, EN_COMP_REF) to
-                                            // assertion of EN_COMP_3P3V
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_S 8
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_M \
-                                0x000000C0  // Configuration in number of
-                                            // slow-clks between de-assertion of
-                                            // (EN_COMP_3P3V, EN_COMP_REF_3P3V,
-                                            // EN_ACT_IREF_3P3V, EN_CAP_SW_3P3V)
-                                            // to deassertion of EN_BGAP_3P3V.
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_S 6
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_M \
-                                0x0000003F
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_MISC_CONFIG register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_MISC_CONFIG_mem_en_pll_untrim_current \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_WAKE_STATUS register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_M \
-                                0x0000001E  // "0100" - GPIO ; "0010" - RTC ;
-                                            // "0001" - UART Others - Reserved
-
-#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_S 1
-#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_status \
-                                0x00000001  // 1 - Wake from Hibernate ; 0 -
-                                            // Wake from OFF
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_M \
-                                0x00000007
-
-#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 register.
-//
-//******************************************************************************
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_M \
-                                0xFFFFF800
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_S 11
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_M \
-                                0x00000600  // Deassertion of EN_COMP_LATCH_3P3
-                                            // to deassertion of (EN_COMP_3P3,
-                                            // EN_COMP_REF_3P3, EN_ACT_IREF_3P3,
-                                            // EN_CAP_SW_3P3)
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_S 9
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_M \
-                                0x000001C0  // Assertion of EN_COMP_LATCH_3P3
-                                            // to deassertion of
-                                            // EN_COMP_LATCH_3P3
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_S 6
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_M \
-                                0x00000030  // Deassertion of (EN_CAP_SW_3P3,
-                                            // EN_COMP_REF_3P3, EN_COMP_3P3,
-                                            // EN_COMP_OUT_LATCH_3P3) to
-                                            // deassertion of EN_BGAP_3P3
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_S 4
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_M \
-                                0x0000000C  // Assertion of EN_COMP_3P3 to
-                                            // assertion of EN_COMPOUT_LATCH_3P3
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_S 2
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_M \
-                                0x00000003  // Assertion of EN_COMP_3P3 to
-                                            // assertion of EN_COMPOUT_LATCH_3P3
-
-#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_HIBANA_SPARE_LOWV register.
-//
-//******************************************************************************
-#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_M \
-                                0xFFC00000
-
-#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_S 22
-#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_M \
-                                0x0001FFFF
-
-#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_HIB_TMUX_CTRL register.
-//
-//******************************************************************************
-#define HIB3P3_HIB_TMUX_CTRL_reserved_M \
-                                0xFFFFFC00
-
-#define HIB3P3_HIB_TMUX_CTRL_reserved_S 10
-#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_M \
-                                0x000003FF
-
-#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_HIB_1P2_1P8_LDO_TRIM register.
-//
-//******************************************************************************
-#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_M \
-                                0xFFFFF000
-
-#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_S 12
-#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override_ctrl \
-                                0x00000800
-
-#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override_ctrl \
-                                0x00000400
-
-#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override \
-                                0x00000200
-
-#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override \
-                                0x00000100
-
-#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_M \
-                                0x000000F0
-
-#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_S 4
-#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_M \
-                                0x0000000F
-
-#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_HIB_COMP_TRIM register.
-//
-//******************************************************************************
-#define HIB3P3_HIB_COMP_TRIM_reserved_M \
-                                0xFFFFFFF8
-
-#define HIB3P3_HIB_COMP_TRIM_reserved_S 3
-#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_M \
-                                0x00000007
-
-#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_HIB_EN_TS register.
-//
-//******************************************************************************
-#define HIB3P3_HIB_EN_TS_reserved_M \
-                                0xFFFFFFFE
-
-#define HIB3P3_HIB_EN_TS_reserved_S 1
-#define HIB3P3_HIB_EN_TS_mem_hd_en_ts \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_HIB_1P8V_DET_EN register.
-//
-//******************************************************************************
-#define HIB3P3_HIB_1P8V_DET_EN_reserved_M \
-                                0xFFFFFFFE
-
-#define HIB3P3_HIB_1P8V_DET_EN_reserved_S 1
-#define HIB3P3_HIB_1P8V_DET_EN_mem_hib_1p8v_det_en \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_HIB_VBAT_MON_EN register.
-//
-//******************************************************************************
-#define HIB3P3_HIB_VBAT_MON_EN_reserved_M \
-                                0xFFFFFFFC
-
-#define HIB3P3_HIB_VBAT_MON_EN_reserved_S 2
-#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_del_en \
-                                0x00000002
-
-#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_en \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_HIB_NHIB_ENABLE register.
-//
-//******************************************************************************
-#define HIB3P3_HIB_NHIB_ENABLE_mem_hib_nhib_enable \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// HIB3P3_O_HIB_UART_RTS_SW_ENABLE register.
-//
-//******************************************************************************
-#define HIB3P3_HIB_UART_RTS_SW_ENABLE_mem_hib_uart_rts_sw_enable \
-                                0x00000001
-
-
-
-
-#endif // __HW_HIB3P3_H__
diff --git a/cc3200/hal/inc/hw_i2c.h b/cc3200/hal/inc/hw_i2c.h
deleted file mode 100644
index 17536d3e9..000000000
--- a/cc3200/hal/inc/hw_i2c.h
+++ /dev/null
@@ -1,503 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_I2C_H__
-#define __HW_I2C_H__
-
-//*****************************************************************************
-//
-// The following are defines for the I2C register offsets.
-//
-//*****************************************************************************
-#define I2C_O_MSA               0x00000000
-#define I2C_O_MCS               0x00000004
-#define I2C_O_MDR               0x00000008
-#define I2C_O_MTPR              0x0000000C
-#define I2C_O_MIMR              0x00000010
-#define I2C_O_MRIS              0x00000014
-#define I2C_O_MMIS              0x00000018
-#define I2C_O_MICR              0x0000001C
-#define I2C_O_MCR               0x00000020
-#define I2C_O_MCLKOCNT          0x00000024
-#define I2C_O_MBMON             0x0000002C
-#define I2C_O_MBLEN             0x00000030
-#define I2C_O_MBCNT             0x00000034
-#define I2C_O_SOAR              0x00000800
-#define I2C_O_SCSR              0x00000804
-#define I2C_O_SDR               0x00000808
-#define I2C_O_SIMR              0x0000080C
-#define I2C_O_SRIS              0x00000810
-#define I2C_O_SMIS              0x00000814
-#define I2C_O_SICR              0x00000818
-#define I2C_O_SOAR2             0x0000081C
-#define I2C_O_SACKCTL           0x00000820
-#define I2C_O_FIFODATA          0x00000F00
-#define I2C_O_FIFOCTL           0x00000F04
-#define I2C_O_FIFOSTATUS        0x00000F08
-#define I2C_O_OBSMUXSEL0        0x00000F80
-#define I2C_O_OBSMUXSEL1        0x00000F84
-#define I2C_O_MUXROUTE          0x00000F88
-#define I2C_O_PV                0x00000FB0
-#define I2C_O_PP                0x00000FC0
-#define I2C_O_PC                0x00000FC4
-#define I2C_O_CC                0x00000FC8
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MSA register.
-//
-//******************************************************************************
-#define I2C_MSA_SA_M          0x000000FE  // I2C Slave Address
-#define I2C_MSA_SA_S          1
-#define I2C_MSA_RS              0x00000001  // Receive not send
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MCS register.
-//
-//******************************************************************************
-#define I2C_MCS_ACTDMARX        0x80000000  // DMA RX Active Status
-#define I2C_MCS_ACTDMATX        0x40000000  // DMA TX Active Status
-#define I2C_MCS_CLKTO           0x00000080  // Clock Timeout Error
-#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy
-#define I2C_MCS_IDLE            0x00000020  // I2C Idle
-#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost
-#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable
-#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address
-#define I2C_MCS_ERROR           0x00000002  // Error
-#define I2C_MCS_BUSY            0x00000001  // I2C Busy
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MDR register.
-//
-//******************************************************************************
-#define I2C_MDR_DATA_M        0x000000FF  // Data Transferred
-#define I2C_MDR_DATA_S        0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MTPR register.
-//
-//******************************************************************************
-#define I2C_MTPR_HS             0x00000080  // High-Speed Enable
-#define I2C_MTPR_TPR_M        0x0000007F  // SCL Clock Period
-#define I2C_MTPR_TPR_S        0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MIMR register.
-//
-//******************************************************************************
-#define I2C_MIMR_RXFFIM         0x00000800  // Receive FIFO Full Interrupt Mask
-#define I2C_MIMR_TXFEIM         0x00000400  // Transmit FIFO Empty Interrupt
-                                            // Mask
-#define I2C_MIMR_RXIM           0x00000200  // Receive FIFO Request Interrupt
-                                            // Mask
-#define I2C_MIMR_TXIM           0x00000100  // Transmit FIFO Request Interrupt
-                                            // Mask
-#define I2C_MIMR_ARBLOSTIM      0x00000080  // Arbitration Lost Interrupt Mask
-#define I2C_MIMR_STOPIM         0x00000040  // STOP Detection Interrupt Mask
-#define I2C_MIMR_STARTIM        0x00000020  // START Detection Interrupt Mask
-#define I2C_MIMR_NACKIM         0x00000010  // Address/Data NACK Interrupt Mask
-#define I2C_MIMR_DMATXIM        0x00000008  // Transmit DMA Interrupt Mask
-#define I2C_MIMR_DMARXIM        0x00000004  // Receive DMA Interrupt Mask
-#define I2C_MIMR_CLKIM          0x00000002  // Clock Timeout Interrupt Mask
-#define I2C_MIMR_IM             0x00000001  // Master Interrupt Mask
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MRIS register.
-//
-//******************************************************************************
-#define I2C_MRIS_RXFFRIS        0x00000800  // Receive FIFO Full Raw Interrupt
-                                            // Status
-#define I2C_MRIS_TXFERIS        0x00000400  // Transmit FIFO Empty Raw
-                                            // Interrupt Status
-#define I2C_MRIS_RXRIS          0x00000200  // Receive FIFO Request Raw
-                                            // Interrupt Status
-#define I2C_MRIS_TXRIS          0x00000100  // Transmit Request Raw Interrupt
-                                            // Status
-#define I2C_MRIS_ARBLOSTRIS     0x00000080  // Arbitration Lost Raw Interrupt
-                                            // Status
-#define I2C_MRIS_STOPRIS        0x00000040  // STOP Detection Raw Interrupt
-                                            // Status
-#define I2C_MRIS_STARTRIS       0x00000020  // START Detection Raw Interrupt
-                                            // Status
-#define I2C_MRIS_NACKRIS        0x00000010  // Address/Data NACK Raw Interrupt
-                                            // Status
-#define I2C_MRIS_DMATXRIS       0x00000008  // Transmit DMA Raw Interrupt
-                                            // Status
-#define I2C_MRIS_DMARXRIS       0x00000004  // Receive DMA Raw Interrupt Status
-#define I2C_MRIS_CLKRIS         0x00000002  // Clock Timeout Raw Interrupt
-                                            // Status
-#define I2C_MRIS_RIS            0x00000001  // Master Raw Interrupt Status
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MMIS register.
-//
-//******************************************************************************
-#define I2C_MMIS_RXFFMIS        0x00000800  // Receive FIFO Full Interrupt Mask
-#define I2C_MMIS_TXFEMIS        0x00000400  // Transmit FIFO Empty Interrupt
-                                            // Mask
-#define I2C_MMIS_RXMIS          0x00000200  // Receive FIFO Request Interrupt
-                                            // Mask
-#define I2C_MMIS_TXMIS          0x00000100  // Transmit Request Interrupt Mask
-#define I2C_MMIS_ARBLOSTMIS     0x00000080  // Arbitration Lost Interrupt Mask
-#define I2C_MMIS_STOPMIS        0x00000040  // STOP Detection Interrupt Mask
-#define I2C_MMIS_STARTMIS       0x00000020  // START Detection Interrupt Mask
-#define I2C_MMIS_NACKMIS        0x00000010  // Address/Data NACK Interrupt Mask
-#define I2C_MMIS_DMATXMIS       0x00000008  // Transmit DMA Interrupt Status
-#define I2C_MMIS_DMARXMIS       0x00000004  // Receive DMA Interrupt Status
-#define I2C_MMIS_CLKMIS         0x00000002  // Clock Timeout Masked Interrupt
-                                            // Status
-#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MICR register.
-//
-//******************************************************************************
-#define I2C_MICR_RXFFIC         0x00000800  // Receive FIFO Full Interrupt
-                                            // Clear
-#define I2C_MICR_TXFEIC         0x00000400  // Transmit FIFO Empty Interrupt
-                                            // Clear
-#define I2C_MICR_RXIC           0x00000200  // Receive FIFO Request Interrupt
-                                            // Clear
-#define I2C_MICR_TXIC           0x00000100  // Transmit FIFO Request Interrupt
-                                            // Clear
-#define I2C_MICR_ARBLOSTIC      0x00000080  // Arbitration Lost Interrupt Clear
-#define I2C_MICR_STOPIC         0x00000040  // STOP Detection Interrupt Clear
-#define I2C_MICR_STARTIC        0x00000020  // START Detection Interrupt Clear
-#define I2C_MICR_NACKIC         0x00000010  // Address/Data NACK Interrupt
-                                            // Clear
-#define I2C_MICR_DMATXIC        0x00000008  // Transmit DMA Interrupt Clear
-#define I2C_MICR_DMARXIC        0x00000004  // Receive DMA Interrupt Clear
-#define I2C_MICR_CLKIC          0x00000002  // Clock Timeout Interrupt Clear
-#define I2C_MICR_IC             0x00000001  // Master Interrupt Clear
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MCR register.
-//
-//******************************************************************************
-#define I2C_MCR_MMD             0x00000040  // Multi-master Disable
-#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable
-#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable
-#define I2C_MCR_LPBK            0x00000001  // I2C Loopback
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
-//
-//******************************************************************************
-#define I2C_MCLKOCNT_CNTL_M   0x000000FF  // I2C Master Count
-#define I2C_MCLKOCNT_CNTL_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MBMON register.
-//
-//******************************************************************************
-#define I2C_MBMON_SDA           0x00000002  // I2C SDA Status
-#define I2C_MBMON_SCL           0x00000001  // I2C SCL Status
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MBLEN register.
-//
-//******************************************************************************
-#define I2C_MBLEN_CNTL_M      0x000000FF  // I2C Burst Length
-#define I2C_MBLEN_CNTL_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MBCNT register.
-//
-//******************************************************************************
-#define I2C_MBCNT_CNTL_M      0x000000FF  // I2C Master Burst Count
-#define I2C_MBCNT_CNTL_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SOAR register.
-//
-//******************************************************************************
-#define I2C_SOAR_OAR_M        0x0000007F  // I2C Slave Own Address
-#define I2C_SOAR_OAR_S        0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SCSR register.
-//
-//******************************************************************************
-#define I2C_SCSR_ACTDMARX       0x80000000  // DMA RX Active Status
-#define I2C_SCSR_ACTDMATX       0x40000000  // DMA TX Active Status
-#define I2C_SCSR_QCMDRW         0x00000020  // Quick Command Read / Write
-#define I2C_SCSR_QCMDST         0x00000010  // Quick Command Status
-#define I2C_SCSR_OAR2SEL        0x00000008  // OAR2 Address Matched
-#define I2C_SCSR_FBR            0x00000004  // First Byte Received
-#define I2C_SCSR_TREQ           0x00000002  // Transmit Request
-#define I2C_SCSR_DA             0x00000001  // Device Active
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SDR register.
-//
-//******************************************************************************
-#define I2C_SDR_DATA_M        0x000000FF  // Data for Transfer
-#define I2C_SDR_DATA_S        0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SIMR register.
-//
-//******************************************************************************
-#define I2C_SIMR_IM             0x00000100  // Interrupt Mask
-#define I2C_SIMR_TXFEIM         0x00000080  // Transmit FIFO Empty Interrupt
-                                            // Mask
-#define I2C_SIMR_RXIM           0x00000040  // Receive FIFO Request Interrupt
-                                            // Mask
-#define I2C_SIMR_TXIM           0x00000020  // Transmit FIFO Request Interrupt
-                                            // Mask
-#define I2C_SIMR_DMATXIM        0x00000010  // Transmit DMA Interrupt Mask
-#define I2C_SIMR_DMARXIM        0x00000008  // Receive DMA Interrupt Mask
-#define I2C_SIMR_STOPIM         0x00000004  // Stop Condition Interrupt Mask
-#define I2C_SIMR_STARTIM        0x00000002  // Start Condition Interrupt Mask
-#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SRIS register.
-//
-//******************************************************************************
-#define I2C_SRIS_RIS            0x00000100  // Raw Interrupt Status
-#define I2C_SRIS_TXFERIS        0x00000080  // Transmit FIFO Empty Raw
-                                            // Interrupt Status
-#define I2C_SRIS_RXRIS          0x00000040  // Receive FIFO Request Raw
-                                            // Interrupt Status
-#define I2C_SRIS_TXRIS          0x00000020  // Transmit Request Raw Interrupt
-                                            // Status
-#define I2C_SRIS_DMATXRIS       0x00000010  // Transmit DMA Raw Interrupt
-                                            // Status
-#define I2C_SRIS_DMARXRIS       0x00000008  // Receive DMA Raw Interrupt Status
-#define I2C_SRIS_STOPRIS        0x00000004  // Stop Condition Raw Interrupt
-                                            // Status
-#define I2C_SRIS_STARTRIS       0x00000002  // Start Condition Raw Interrupt
-                                            // Status
-#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SMIS register.
-//
-//******************************************************************************
-#define I2C_SMIS_RXFFMIS        0x00000100  // Receive FIFO Full Interrupt Mask
-#define I2C_SMIS_TXFEMIS        0x00000080  // Transmit FIFO Empty Interrupt
-                                            // Mask
-#define I2C_SMIS_RXMIS          0x00000040  // Receive FIFO Request Interrupt
-                                            // Mask
-#define I2C_SMIS_TXMIS          0x00000020  // Transmit FIFO Request Interrupt
-                                            // Mask
-#define I2C_SMIS_DMATXMIS       0x00000010  // Transmit DMA Masked Interrupt
-                                            // Status
-#define I2C_SMIS_DMARXMIS       0x00000008  // Receive DMA Masked Interrupt
-                                            // Status
-#define I2C_SMIS_STOPMIS        0x00000004  // Stop Condition Masked Interrupt
-                                            // Status
-#define I2C_SMIS_STARTMIS       0x00000002  // Start Condition Masked Interrupt
-                                            // Status
-#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SICR register.
-//
-//******************************************************************************
-#define I2C_SICR_RXFFIC         0x00000100  // Receive FIFO Full Interrupt Mask
-#define I2C_SICR_TXFEIC         0x00000080  // Transmit FIFO Empty Interrupt
-                                            // Mask
-#define I2C_SICR_RXIC           0x00000040  // Receive Request Interrupt Mask
-#define I2C_SICR_TXIC           0x00000020  // Transmit Request Interrupt Mask
-#define I2C_SICR_DMATXIC        0x00000010  // Transmit DMA Interrupt Clear
-#define I2C_SICR_DMARXIC        0x00000008  // Receive DMA Interrupt Clear
-#define I2C_SICR_STOPIC         0x00000004  // Stop Condition Interrupt Clear
-#define I2C_SICR_STARTIC        0x00000002  // Start Condition Interrupt Clear
-#define I2C_SICR_DATAIC         0x00000001  // Data Interrupt Clear
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SOAR2 register.
-//
-//******************************************************************************
-#define I2C_SOAR2_OAR2EN        0x00000080  // I2C Slave Own Address 2 Enable
-#define I2C_SOAR2_OAR2_M      0x0000007F  // I2C Slave Own Address 2
-#define I2C_SOAR2_OAR2_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SACKCTL register.
-//
-//******************************************************************************
-#define I2C_SACKCTL_ACKOVAL     0x00000002  // I2C Slave ACK Override Value
-#define I2C_SACKCTL_ACKOEN      0x00000001  // I2C Slave ACK Override Enable
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_FIFODATA register.
-//
-//******************************************************************************
-#define I2C_FIFODATA_DATA_M   0x000000FF  // I2C FIFO Data Byte
-#define I2C_FIFODATA_DATA_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_FIFOCTL register.
-//
-//******************************************************************************
-#define I2C_FIFOCTL_RXASGNMT    0x80000000  // RX Control Assignment
-#define I2C_FIFOCTL_RXFLUSH     0x40000000  // RX FIFO Flush
-#define I2C_FIFOCTL_DMARXENA    0x20000000  // DMA RX Channel Enable
-#define I2C_FIFOCTL_RXTRIG_M  0x00070000  // RX FIFO Trigger
-#define I2C_FIFOCTL_RXTRIG_S  16
-#define I2C_FIFOCTL_TXASGNMT    0x00008000  // TX Control Assignment
-#define I2C_FIFOCTL_TXFLUSH     0x00004000  // TX FIFO Flush
-#define I2C_FIFOCTL_DMATXENA    0x00002000  // DMA TX Channel Enable
-#define I2C_FIFOCTL_TXTRIG_M  0x00000007  // TX FIFO Trigger
-#define I2C_FIFOCTL_TXTRIG_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_FIFOSTATUS register.
-//
-//******************************************************************************
-#define I2C_FIFOSTATUS_RXABVTRIG \
-                                0x00040000  // RX FIFO Above Trigger Level
-
-#define I2C_FIFOSTATUS_RXFF     0x00020000  // RX FIFO Full
-#define I2C_FIFOSTATUS_RXFE     0x00010000  // RX FIFO Empty
-#define I2C_FIFOSTATUS_TXBLWTRIG \
-                                0x00000004  // TX FIFO Below Trigger Level
-
-#define I2C_FIFOSTATUS_TXFF     0x00000002  // TX FIFO Full
-#define I2C_FIFOSTATUS_TXFE     0x00000001  // TX FIFO Empty
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_OBSMUXSEL0 register.
-//
-//******************************************************************************
-#define I2C_OBSMUXSEL0_LN3_M  0x07000000  // Observation Mux Lane 3
-#define I2C_OBSMUXSEL0_LN3_S  24
-#define I2C_OBSMUXSEL0_LN2_M  0x00070000  // Observation Mux Lane 2
-#define I2C_OBSMUXSEL0_LN2_S  16
-#define I2C_OBSMUXSEL0_LN1_M  0x00000700  // Observation Mux Lane 1
-#define I2C_OBSMUXSEL0_LN1_S  8
-#define I2C_OBSMUXSEL0_LN0_M  0x00000007  // Observation Mux Lane 0
-#define I2C_OBSMUXSEL0_LN0_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_OBSMUXSEL1 register.
-//
-//******************************************************************************
-#define I2C_OBSMUXSEL1_LN7_M  0x07000000  // Observation Mux Lane 7
-#define I2C_OBSMUXSEL1_LN7_S  24
-#define I2C_OBSMUXSEL1_LN6_M  0x00070000  // Observation Mux Lane 6
-#define I2C_OBSMUXSEL1_LN6_S  16
-#define I2C_OBSMUXSEL1_LN5_M  0x00000700  // Observation Mux Lane 5
-#define I2C_OBSMUXSEL1_LN5_S  8
-#define I2C_OBSMUXSEL1_LN4_M  0x00000007  // Observation Mux Lane 4
-#define I2C_OBSMUXSEL1_LN4_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MUXROUTE register.
-//
-//******************************************************************************
-#define I2C_MUXROUTE_LN7ROUTE_M \
-                                0x70000000  // Lane 7 output is routed to the
-                                            // lane pointed to by the offset in
-                                            // this bit field
-
-#define I2C_MUXROUTE_LN7ROUTE_S 28
-#define I2C_MUXROUTE_LN6ROUTE_M \
-                                0x07000000  // Lane 6 output is routed to the
-                                            // lane pointed to by the offset in
-                                            // this bit field
-
-#define I2C_MUXROUTE_LN6ROUTE_S 24
-#define I2C_MUXROUTE_LN5ROUTE_M \
-                                0x00700000  // Lane 5 output is routed to the
-                                            // lane pointed to by the offset in
-                                            // this bit field
-
-#define I2C_MUXROUTE_LN5ROUTE_S 20
-#define I2C_MUXROUTE_LN4ROUTE_M \
-                                0x00070000  // Lane 4 output is routed to the
-                                            // lane pointed to by the offset in
-                                            // this bit field
-
-#define I2C_MUXROUTE_LN4ROUTE_S 16
-#define I2C_MUXROUTE_LN3ROUTE_M \
-                                0x00007000  // Lane 3 output is routed to the
-                                            // lane pointed to by the offset in
-                                            // this bit field
-
-#define I2C_MUXROUTE_LN3ROUTE_S 12
-#define I2C_MUXROUTE_LN2ROUTE_M \
-                                0x00000700  // Lane 2 output is routed to the
-                                            // lane pointed to by the offset in
-                                            // this bit field
-
-#define I2C_MUXROUTE_LN2ROUTE_S 8
-#define I2C_MUXROUTE_LN1ROUTE_M \
-                                0x00000070  // Lane 1 output is routed to the
-                                            // lane pointed to by the offset in
-                                            // this bit field
-
-#define I2C_MUXROUTE_LN1ROUTE_S 4
-#define I2C_MUXROUTE_LN0ROUTE_M \
-                                0x00000007  // Lane 0 output is routed to the
-                                            // lane pointed to by the offset in
-                                            // this bit field
-
-#define I2C_MUXROUTE_LN0ROUTE_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_PV register.
-//
-//******************************************************************************
-#define I2C_PV_MAJOR_M        0x0000FF00  // Major Revision
-#define I2C_PV_MAJOR_S        8
-#define I2C_PV_MINOR_M        0x000000FF  // Minor Revision
-#define I2C_PV_MINOR_S        0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_PP register.
-//
-//******************************************************************************
-#define I2C_PP_HS               0x00000001  // High-Speed Capable
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_PC register.
-//
-//******************************************************************************
-#define I2C_PC_HS               0x00000001  // High-Speed Capable
-//******************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_CC register.
-//
-//******************************************************************************
-
-
-
-#endif // __HW_I2C_H__
diff --git a/cc3200/hal/inc/hw_ints.h b/cc3200/hal/inc/hw_ints.h
deleted file mode 100644
index 6b4019355..000000000
--- a/cc3200/hal/inc/hw_ints.h
+++ /dev/null
@@ -1,117 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-// hw_ints.h - Macros that define the interrupt assignment on CC3200.
-//
-//*****************************************************************************
-
-#ifndef __HW_INTS_H__
-#define __HW_INTS_H__
-
-//*****************************************************************************
-//
-// The following are defines for the fault assignments.
-//
-//*****************************************************************************
-#define FAULT_NMI               2           // NMI fault
-#define FAULT_HARD              3           // Hard fault
-#define FAULT_MPU               4           // MPU fault
-#define FAULT_BUS               5           // Bus fault
-#define FAULT_USAGE             6           // Usage fault
-#define FAULT_SVCALL            11          // SVCall
-#define FAULT_DEBUG             12          // Debug monitor
-#define FAULT_PENDSV            14          // PendSV
-#define FAULT_SYSTICK           15          // System Tick
-
-//*****************************************************************************
-//
-// The following are defines for the interrupt assignments.
-//
-//*****************************************************************************
-#define INT_GPIOA0              16          // GPIO Port S0
-#define INT_GPIOA1              17          // GPIO Port S1
-#define INT_GPIOA2              18          // GPIO Port S2
-#define INT_GPIOA3              19          // GPIO Port S3
-#define INT_UARTA0              21          // UART0 Rx and Tx
-#define INT_UARTA1              22          // UART1 Rx and Tx
-#define INT_I2CA0               24          // I2C controller
-#define INT_ADCCH0              30          // ADC Sequence 0
-#define INT_ADCCH1              31          // ADC Sequence 1
-#define INT_ADCCH2              32          // ADC Sequence 2
-#define INT_ADCCH3              33          // ADC Sequence 3
-#define INT_WDT                 34          // Watchdog Timer0
-#define INT_TIMERA0A            35          // Timer 0 subtimer A
-#define INT_TIMERA0B            36          // Timer 0 subtimer B
-#define INT_TIMERA1A            37          // Timer 1 subtimer A
-#define INT_TIMERA1B            38          // Timer 1 subtimer B
-#define INT_TIMERA2A            39          // Timer 2 subtimer A
-#define INT_TIMERA2B            40          // Timer 2 subtimer B
-#define INT_FLASH               45          // FLASH Control
-#define INT_TIMERA3A            51          // Timer 3 subtimer A
-#define INT_TIMERA3B            52          // Timer 3 subtimer B
-#define INT_UDMA                62          // uDMA controller
-#define INT_UDMAERR             63          // uDMA Error
-#define INT_SHA                 164         // SHA
-#define INT_AES                 167         // AES
-#define INT_DES                 169         // DES
-#define INT_MMCHS               175         // SDIO
-#define INT_I2S                 177         // McAPS
-#define INT_CAMERA              179         // Camera
-#define INT_NWPIC               187         // Interprocessor communication
-#define INT_PRCM                188         // Power, Reset and Clock Module
-#define INT_SSPI                191         // Shared SPI
-#define INT_GSPI                192         // Generic SPI
-#define INT_LSPI                193         // Link SPI
-
-//*****************************************************************************
-//
-// The following are defines for the total number of interrupts.
-//
-//*****************************************************************************
-#define NUM_INTERRUPTS          195 //The above number plus 2?
-
-
-//*****************************************************************************
-//
-// The following are defines for the total number of priority levels.
-//
-//*****************************************************************************
-#define NUM_PRIORITY            8
-#define NUM_PRIORITY_BITS       3
-
-
-#endif // __HW_INTS_H__
diff --git a/cc3200/hal/inc/hw_mcasp.h b/cc3200/hal/inc/hw_mcasp.h
deleted file mode 100644
index c27a00779..000000000
--- a/cc3200/hal/inc/hw_mcasp.h
+++ /dev/null
@@ -1,1706 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_MCASP_H__
-#define __HW_MCASP_H__
-
-//*****************************************************************************
-//
-// The following are defines for the MCASP register offsets.
-//
-//*****************************************************************************
-#define MCASP_O_PID             0x00000000
-#define MCASP_O_ESYSCONFIG      0x00000004  // Power Idle SYSCONFIG register.
-#define MCASP_O_PFUNC           0x00000010
-#define MCASP_O_PDIR            0x00000014
-#define MCASP_O_PDOUT           0x00000018
-#define MCASP_O_PDSET           0x0000001C  // The pin data set register
-                                            // (PDSET) is an alias of the pin
-                                            // data output register (PDOUT) for
-                                            // writes only. Writing a 1 to the
-                                            // PDSET bit sets the corresponding
-                                            // bit in PDOUT and if PFUNC = 1
-                                            // (GPIO function) and PDIR = 1
-                                            // (output) drives a logic high on
-                                            // the pin.
-#define MCASP_O_PDIN            0x0000001C  // The pin data input register
-                                            // (PDIN) holds the I/O pin state of
-                                            // each of the McASP pins. PDIN
-                                            // allows the actual value of the
-                                            // pin to be read regardless of the
-                                            // state of PFUNC and PDIR.
-#define MCASP_O_PDCLR           0x00000020  // The pin data clear register
-                                            // (PDCLR) is an alias of the pin
-                                            // data output register (PDOUT) for
-                                            // writes only. Writing a 1 to the
-                                            // PDCLR bit clears the
-                                            // corresponding bit in PDOUT and if
-                                            // PFUNC = 1 (GPIO function) and
-                                            // PDIR = 1 (output) drives a logic
-                                            // low on the pin.
-#define MCASP_O_TLGC            0x00000030  // for IODFT
-#define MCASP_O_TLMR            0x00000034  // for IODFT
-#define MCASP_O_TLEC            0x00000038  // for IODFT
-#define MCASP_O_GBLCTL          0x00000044
-#define MCASP_O_AMUTE           0x00000048
-#define MCASP_O_LBCTL           0x0000004C
-#define MCASP_O_TXDITCTL        0x00000050
-#define MCASP_O_GBLCTLR         0x00000060
-#define MCASP_O_RXMASK          0x00000064
-#define MCASP_O_RXFMT           0x00000068
-#define MCASP_O_RXFMCTL         0x0000006C
-#define MCASP_O_ACLKRCTL        0x00000070
-#define MCASP_O_AHCLKRCTL       0x00000074
-#define MCASP_O_RXTDM           0x00000078
-#define MCASP_O_EVTCTLR         0x0000007C
-#define MCASP_O_RXSTAT          0x00000080
-#define MCASP_O_RXTDMSLOT       0x00000084
-#define MCASP_O_RXCLKCHK        0x00000088
-#define MCASP_O_REVTCTL         0x0000008C
-#define MCASP_O_GBLCTLX         0x000000A0
-#define MCASP_O_TXMASK          0x000000A4
-#define MCASP_O_TXFMT           0x000000A8
-#define MCASP_O_TXFMCTL         0x000000AC
-#define MCASP_O_ACLKXCTL        0x000000B0
-#define MCASP_O_AHCLKXCTL       0x000000B4
-#define MCASP_O_TXTDM           0x000000B8
-#define MCASP_O_EVTCTLX         0x000000BC
-#define MCASP_O_TXSTAT          0x000000C0
-#define MCASP_O_TXTDMSLOT       0x000000C4
-#define MCASP_O_TXCLKCHK        0x000000C8
-#define MCASP_O_XEVTCTL         0x000000CC
-#define MCASP_O_CLKADJEN        0x000000D0
-#define MCASP_O_DITCSRA0        0x00000100
-#define MCASP_O_DITCSRA1        0x00000104
-#define MCASP_O_DITCSRA2        0x00000108
-#define MCASP_O_DITCSRA3        0x0000010C
-#define MCASP_O_DITCSRA4        0x00000110
-#define MCASP_O_DITCSRA5        0x00000114
-#define MCASP_O_DITCSRB0        0x00000118
-#define MCASP_O_DITCSRB1        0x0000011C
-#define MCASP_O_DITCSRB2        0x00000120
-#define MCASP_O_DITCSRB3        0x00000124
-#define MCASP_O_DITCSRB4        0x00000128
-#define MCASP_O_DITCSRB5        0x0000012C
-#define MCASP_O_DITUDRA0        0x00000130
-#define MCASP_O_DITUDRA1        0x00000134
-#define MCASP_O_DITUDRA2        0x00000138
-#define MCASP_O_DITUDRA3        0x0000013C
-#define MCASP_O_DITUDRA4        0x00000140
-#define MCASP_O_DITUDRA5        0x00000144
-#define MCASP_O_DITUDRB0        0x00000148
-#define MCASP_O_DITUDRB1        0x0000014C
-#define MCASP_O_DITUDRB2        0x00000150
-#define MCASP_O_DITUDRB3        0x00000154
-#define MCASP_O_DITUDRB4        0x00000158
-#define MCASP_O_DITUDRB5        0x0000015C
-#define MCASP_O_XRSRCTL0        0x00000180
-#define MCASP_O_XRSRCTL1        0x00000184
-#define MCASP_O_XRSRCTL2        0x00000188
-#define MCASP_O_XRSRCTL3        0x0000018C
-#define MCASP_O_XRSRCTL4        0x00000190
-#define MCASP_O_XRSRCTL5        0x00000194
-#define MCASP_O_XRSRCTL6        0x00000198
-#define MCASP_O_XRSRCTL7        0x0000019C
-#define MCASP_O_XRSRCTL8        0x000001A0
-#define MCASP_O_XRSRCTL9        0x000001A4
-#define MCASP_O_XRSRCTL10       0x000001A8
-#define MCASP_O_XRSRCTL11       0x000001AC
-#define MCASP_O_XRSRCTL12       0x000001B0
-#define MCASP_O_XRSRCTL13       0x000001B4
-#define MCASP_O_XRSRCTL14       0x000001B8
-#define MCASP_O_XRSRCTL15       0x000001BC
-#define MCASP_O_TXBUF0          0x00000200
-#define MCASP_O_TXBUF1          0x00000204
-#define MCASP_O_TXBUF2          0x00000208
-#define MCASP_O_TXBUF3          0x0000020C
-#define MCASP_O_TXBUF4          0x00000210
-#define MCASP_O_TXBUF5          0x00000214
-#define MCASP_O_TXBUF6          0x00000218
-#define MCASP_O_TXBUF7          0x0000021C
-#define MCASP_O_TXBUF8          0x00000220
-#define MCASP_O_TXBUF9          0x00000224
-#define MCASP_O_TXBUF10         0x00000228
-#define MCASP_O_TXBUF11         0x0000022C
-#define MCASP_O_TXBUF12         0x00000230
-#define MCASP_O_TXBUF13         0x00000234
-#define MCASP_O_TXBUF14         0x00000238
-#define MCASP_O_TXBUF15         0x0000023C
-#define MCASP_O_RXBUF0          0x00000280
-#define MCASP_O_RXBUF1          0x00000284
-#define MCASP_O_RXBUF2          0x00000288
-#define MCASP_O_RXBUF3          0x0000028C
-#define MCASP_O_RXBUF4          0x00000290
-#define MCASP_O_RXBUF5          0x00000294
-#define MCASP_O_RXBUF6          0x00000298
-#define MCASP_O_RXBUF7          0x0000029C
-#define MCASP_O_RXBUF8          0x000002A0
-#define MCASP_O_RXBUF9          0x000002A4
-#define MCASP_O_RXBUF10         0x000002A8
-#define MCASP_O_RXBUF11         0x000002AC
-#define MCASP_O_RXBUF12         0x000002B0
-#define MCASP_O_RXBUF13         0x000002B4
-#define MCASP_O_RXBUF14         0x000002B8
-#define MCASP_O_RXBUF15         0x000002BC
-#define	MCASP_0_WFIFOCTL	0x00001000
-#define	MCASP_0_WFIFOSTS	0x00001004
-#define	MCASP_0_RFIFOCTL	0x00001008
-#define	MCASP_0_RFIFOSTS	0x0000100C
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_PID register.
-//
-//******************************************************************************
-#define MCASP_PID_SCHEME_M      0xC0000000
-#define MCASP_PID_SCHEME_S      30
-#define MCASP_PID_RESV_M        0x30000000
-#define MCASP_PID_RESV_S        28
-#define MCASP_PID_FUNCTION_M    0x0FFF0000  // McASP
-#define MCASP_PID_FUNCTION_S    16
-#define MCASP_PID_RTL_M         0x0000F800
-#define MCASP_PID_RTL_S         11
-#define MCASP_PID_REVMAJOR_M    0x00000700
-#define MCASP_PID_REVMAJOR_S    8
-#define MCASP_PID_CUSTOM_M      0x000000C0  // non-custom
-#define MCASP_PID_CUSTOM_S      6
-#define MCASP_PID_REVMINOR_M    0x0000003F
-#define MCASP_PID_REVMINOR_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// MCASP_O_ESYSCONFIG register.
-//
-//******************************************************************************
-#define MCASP_ESYSCONFIG_RSV_M  0xFFFFFFC0  // Reserved as per PDR 3.5
-#define MCASP_ESYSCONFIG_RSV_S  6
-#define MCASP_ESYSCONFIG_OTHER_M \
-                                0x0000003C  // Reserved for future expansion
-
-#define MCASP_ESYSCONFIG_OTHER_S 2
-#define MCASP_ESYSCONFIG_IDLE_MODE_M \
-                                0x00000003  // Idle Mode
-
-#define MCASP_ESYSCONFIG_IDLE_MODE_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_PFUNC register.
-//
-//******************************************************************************
-#define MCASP_PFUNC_AFSR        0x80000000  // AFSR PFUNC 31 0 1
-#define MCASP_PFUNC_AHCLKR      0x40000000  // AHCLKR PFUNC 30 0 1
-#define MCASP_PFUNC_ACLKR       0x20000000  // ACLKR PFUNC 29 0 1
-#define MCASP_PFUNC_AFSX        0x10000000  // AFSX PFUNC 28 0 1
-#define MCASP_PFUNC_AHCLKX      0x08000000  // AHCLKX PFUNC 27 0 1
-#define MCASP_PFUNC_ACLKX       0x04000000  // ACLKX PFUNC 26 0 1
-#define MCASP_PFUNC_AMUTE       0x02000000  // AMUTE PFUNC 25 0 1
-#define MCASP_PFUNC_RESV1_M     0x01FF0000  // Reserved
-#define MCASP_PFUNC_RESV1_S     16
-#define MCASP_PFUNC_AXR15       0x00008000  // AXR PFUNC BIT 15 0 1
-#define MCASP_PFUNC_AXR14       0x00004000  // AXR PFUNC BIT 14 0 1
-#define MCASP_PFUNC_AXR13       0x00002000  // AXR PFUNC BIT 13 0 1
-#define MCASP_PFUNC_AXR12       0x00001000  // AXR PFUNC BIT 12 0 1
-#define MCASP_PFUNC_AXR11       0x00000800  // AXR PFUNC BIT 11 0 1
-#define MCASP_PFUNC_AXR10       0x00000400  // AXR PFUNC BIT 10 0 1
-#define MCASP_PFUNC_AXR9        0x00000200  // AXR PFUNC BIT 9 0 1
-#define MCASP_PFUNC_AXR8        0x00000100  // AXR PFUNC BIT 8 0 1
-#define MCASP_PFUNC_AXR7        0x00000080  // AXR PFUNC BIT 7 0 1
-#define MCASP_PFUNC_AXR6        0x00000040  // AXR PFUNC BIT 6 0 1
-#define MCASP_PFUNC_AXR5        0x00000020  // AXR PFUNC BIT 5 0 1
-#define MCASP_PFUNC_AXR4        0x00000010  // AXR PFUNC BIT 4 0 1
-#define MCASP_PFUNC_AXR3        0x00000008  // AXR PFUNC BIT 3 0 1
-#define MCASP_PFUNC_AXR2        0x00000004  // AXR PFUNC BIT 2 0 1
-#define MCASP_PFUNC_AXR1        0x00000002  // AXR PFUNC BIT 1 0 1
-#define MCASP_PFUNC_AXR0        0x00000001  // AXR PFUNC BIT 0 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_PDIR register.
-//
-//******************************************************************************
-#define MCASP_PDIR_AFSR         0x80000000  // AFSR PDIR 31 0 1
-#define MCASP_PDIR_AHCLKR       0x40000000  // AHCLKR PDIR 30 0 1
-#define MCASP_PDIR_ACLKR        0x20000000  // ACLKR PDIR 29 0 1
-#define MCASP_PDIR_AFSX         0x10000000  // AFSX PDIR 28 0 1
-#define MCASP_PDIR_AHCLKX       0x08000000  // AHCLKX PDIR 27 0 1
-#define MCASP_PDIR_ACLKX        0x04000000  // ACLKX PDIR 26 0 1
-#define MCASP_PDIR_AMUTE        0x02000000  // AMUTE PDIR 25 0 1
-#define MCASP_PDIR_RESV_M       0x01FF0000  // Reserved
-#define MCASP_PDIR_RESV_S       16
-#define MCASP_PDIR_AXR15        0x00008000  // AXR PDIR BIT 15 0 1
-#define MCASP_PDIR_AXR14        0x00004000  // AXR PDIR BIT 14 0 1
-#define MCASP_PDIR_AXR13        0x00002000  // AXR PDIR BIT 13 0 1
-#define MCASP_PDIR_AXR12        0x00001000  // AXR PDIR BIT 12 0 1
-#define MCASP_PDIR_AXR11        0x00000800  // AXR PDIR BIT 11 0 1
-#define MCASP_PDIR_AXR10        0x00000400  // AXR PDIR BIT 10 0 1
-#define MCASP_PDIR_AXR9         0x00000200  // AXR PDIR BIT 9 0 1
-#define MCASP_PDIR_AXR8         0x00000100  // AXR PDIR BIT 8 0 1
-#define MCASP_PDIR_AXR7         0x00000080  // AXR PDIR BIT 7 0 1
-#define MCASP_PDIR_AXR6         0x00000040  // AXR PDIR BIT 6 0 1
-#define MCASP_PDIR_AXR5         0x00000020  // AXR PDIR BIT 5 0 1
-#define MCASP_PDIR_AXR4         0x00000010  // AXR PDIR BIT 4 0 1
-#define MCASP_PDIR_AXR3         0x00000008  // AXR PDIR BIT 3 0 1
-#define MCASP_PDIR_AXR2         0x00000004  // AXR PDIR BIT 2 0 1
-#define MCASP_PDIR_AXR1         0x00000002  // AXR PDIR BIT 1 0 1
-#define MCASP_PDIR_AXR0         0x00000001  // AXR PDIR BIT 0 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_PDOUT register.
-//
-//******************************************************************************
-#define MCASP_PDOUT_AFSR        0x80000000  // AFSR PDOUT 31 0 1
-#define MCASP_PDOUT_AHCLKR      0x40000000  // AHCLKR PDOUT 30 0 1
-#define MCASP_PDOUT_ACLKR       0x20000000  // ACLKR PDOUT 29 0 1
-#define MCASP_PDOUT_AFSX        0x10000000  // AFSX PDOUT 28 0 1
-#define MCASP_PDOUT_AHCLKX      0x08000000  // AHCLKX PDOUT 27 0 1
-#define MCASP_PDOUT_ACLKX       0x04000000  // ACLKX PDOUT 26 0 1
-#define MCASP_PDOUT_AMUTE       0x02000000  // AMUTE PDOUT 25 0 1
-#define MCASP_PDOUT_RESV_M      0x01FF0000  // Reserved
-#define MCASP_PDOUT_RESV_S      16
-#define MCASP_PDOUT_AXR15       0x00008000  // AXR PDOUT BIT 15 0 1
-#define MCASP_PDOUT_AXR14       0x00004000  // AXR PDOUT BIT 14 0 1
-#define MCASP_PDOUT_AXR13       0x00002000  // AXR PDOUT BIT 13 0 1
-#define MCASP_PDOUT_AXR12       0x00001000  // AXR PDOUT BIT 12 0 1
-#define MCASP_PDOUT_AXR11       0x00000800  // AXR PDOUT BIT 11 0 1
-#define MCASP_PDOUT_AXR10       0x00000400  // AXR PDOUT BIT 10 0 1
-#define MCASP_PDOUT_AXR9        0x00000200  // AXR PDOUT BIT 9 0 1
-#define MCASP_PDOUT_AXR8        0x00000100  // AXR PDOUT BIT 8 0 1
-#define MCASP_PDOUT_AXR7        0x00000080  // AXR PDOUT BIT 7 0 1
-#define MCASP_PDOUT_AXR6        0x00000040  // AXR PDOUT BIT 6 0 1
-#define MCASP_PDOUT_AXR5        0x00000020  // AXR PDOUT BIT 5 0 1
-#define MCASP_PDOUT_AXR4        0x00000010  // AXR PDOUT BIT 4 0 1
-#define MCASP_PDOUT_AXR3        0x00000008  // AXR PDOUT BIT 3 0 1
-#define MCASP_PDOUT_AXR2        0x00000004  // AXR PDOUT BIT 2 0 1
-#define MCASP_PDOUT_AXR1        0x00000002  // AXR PDOUT BIT 1 0 1
-#define MCASP_PDOUT_AXR0        0x00000001  // AXR PDOUT BIT 0 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_PDSET register.
-//
-//******************************************************************************
-#define MCASP_PDSET_AFSR        0x80000000
-#define MCASP_PDSET_AHCLKR      0x40000000
-#define MCASP_PDSET_ACLKR       0x20000000
-#define MCASP_PDSET_AFSX        0x10000000
-#define MCASP_PDSET_AHCLKX      0x08000000
-#define MCASP_PDSET_ACLKX       0x04000000
-#define MCASP_PDSET_AMUTE       0x02000000
-#define MCASP_PDSET_RESV_M      0x01FF0000  // Reserved
-#define MCASP_PDSET_RESV_S      16
-#define MCASP_PDSET_AXR15       0x00008000
-#define MCASP_PDSET_AXR14       0x00004000
-#define MCASP_PDSET_AXR13       0x00002000
-#define MCASP_PDSET_AXR12       0x00001000
-#define MCASP_PDSET_AXR11       0x00000800
-#define MCASP_PDSET_AXR10       0x00000400
-#define MCASP_PDSET_AXR9        0x00000200
-#define MCASP_PDSET_AXR8        0x00000100
-#define MCASP_PDSET_AXR7        0x00000080
-#define MCASP_PDSET_AXR6        0x00000040
-#define MCASP_PDSET_AXR5        0x00000020
-#define MCASP_PDSET_AXR4        0x00000010
-#define MCASP_PDSET_AXR3        0x00000008
-#define MCASP_PDSET_AXR2        0x00000004
-#define MCASP_PDSET_AXR1        0x00000002
-#define MCASP_PDSET_AXR0        0x00000001
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_PDIN register.
-//
-//******************************************************************************
-#define MCASP_PDIN_AFSR         0x80000000
-#define MCASP_PDIN_AHCLKR       0x40000000
-#define MCASP_PDIN_ACLKR        0x20000000
-#define MCASP_PDIN_AFSX         0x10000000
-#define MCASP_PDIN_AHCLKX       0x08000000
-#define MCASP_PDIN_ACLKX        0x04000000
-#define MCASP_PDIN_AMUTE        0x02000000
-#define MCASP_PDIN_RESV_M       0x01FF0000  // Reserved
-#define MCASP_PDIN_RESV_S       16
-#define MCASP_PDIN_AXR15        0x00008000
-#define MCASP_PDIN_AXR14        0x00004000
-#define MCASP_PDIN_AXR13        0x00002000
-#define MCASP_PDIN_AXR12        0x00001000
-#define MCASP_PDIN_AXR11        0x00000800
-#define MCASP_PDIN_AXR10        0x00000400
-#define MCASP_PDIN_AXR9         0x00000200
-#define MCASP_PDIN_AXR8         0x00000100
-#define MCASP_PDIN_AXR7         0x00000080
-#define MCASP_PDIN_AXR6         0x00000040
-#define MCASP_PDIN_AXR5         0x00000020
-#define MCASP_PDIN_AXR4         0x00000010
-#define MCASP_PDIN_AXR3         0x00000008
-#define MCASP_PDIN_AXR2         0x00000004
-#define MCASP_PDIN_AXR1         0x00000002
-#define MCASP_PDIN_AXR0         0x00000001
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_PDCLR register.
-//
-//******************************************************************************
-#define MCASP_PDCLR_AFSR        0x80000000  // AFSR PDCLR 31 0 1
-#define MCASP_PDCLR_AHCLKR      0x40000000  // AHCLKR PDCLR 30 0 1
-#define MCASP_PDCLR_ACLKR       0x20000000  // ACLKR PDCLR 29 0 1
-#define MCASP_PDCLR_AFSX        0x10000000  // AFSX PDCLR 28 0 1
-#define MCASP_PDCLR_AHCLKX      0x08000000  // AHCLKX PDCLR 27 0 1
-#define MCASP_PDCLR_ACLKX       0x04000000  // ACLKX PDCLR 26 0 1
-#define MCASP_PDCLR_AMUTE       0x02000000  // AMUTE PDCLR 25 0 1
-#define MCASP_PDCLR_RESV_M      0x01FF0000  // Reserved
-#define MCASP_PDCLR_RESV_S      16
-#define MCASP_PDCLR_AXR15       0x00008000  // AXR PDCLR BIT 15 0 1
-#define MCASP_PDCLR_AXR14       0x00004000  // AXR PDCLR BIT 14 0 1
-#define MCASP_PDCLR_AXR13       0x00002000  // AXR PDCLR BIT 13 0 1
-#define MCASP_PDCLR_AXR12       0x00001000  // AXR PDCLR BIT 12 0 1
-#define MCASP_PDCLR_AXR11       0x00000800  // AXR PDCLR BIT 11 0 1
-#define MCASP_PDCLR_AXR10       0x00000400  // AXR PDCLR BIT 10 0 1
-#define MCASP_PDCLR_AXR9        0x00000200  // AXR PDCLR BIT 9 0 1
-#define MCASP_PDCLR_AXR8        0x00000100  // AXR PDCLR BIT 8 0 1
-#define MCASP_PDCLR_AXR7        0x00000080  // AXR PDCLR BIT 7 0 1
-#define MCASP_PDCLR_AXR6        0x00000040  // AXR PDCLR BIT 6 0 1
-#define MCASP_PDCLR_AXR5        0x00000020  // AXR PDCLR BIT 5 0 1
-#define MCASP_PDCLR_AXR4        0x00000010  // AXR PDCLR BIT 4 0 1
-#define MCASP_PDCLR_AXR3        0x00000008  // AXR PDCLR BIT 3 0 1
-#define MCASP_PDCLR_AXR2        0x00000004  // AXR PDCLR BIT 2 0 1
-#define MCASP_PDCLR_AXR1        0x00000002  // AXR PDCLR BIT 1 0 1
-#define MCASP_PDCLR_AXR0        0x00000001  // AXR PDCLR BIT 0 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TLGC register.
-//
-//******************************************************************************
-#define MCASP_TLGC_RESV_M       0xFFFF0000  // Reserved
-#define MCASP_TLGC_RESV_S       16
-#define MCASP_TLGC_MT_M         0x0000C000  // MISR on/off trigger command 0x0
-                                            // 0x1 0x2 0x3
-#define MCASP_TLGC_MT_S         14
-#define MCASP_TLGC_RESV1_M      0x00003E00  // Reserved
-#define MCASP_TLGC_RESV1_S      9
-#define MCASP_TLGC_MMS          0x00000100  // Source of MISR input 0 1
-#define MCASP_TLGC_ESEL         0x00000080  // Output enable select 0 1
-#define MCASP_TLGC_TOEN         0x00000040  // Test output enable control. 0 1
-#define MCASP_TLGC_MC_M         0x00000030  // States of MISR 0x0 0x1 0x2 0x3
-#define MCASP_TLGC_MC_S         4
-#define MCASP_TLGC_PC_M         0x0000000E  // Pattern code 0x0 0x1 0x2 0x3 0x4
-                                            // 0x5 0x6 0x7
-#define MCASP_TLGC_PC_S         1
-#define MCASP_TLGC_TM           0x00000001  // Tie high; do not write to this
-                                            // bit 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TLMR register.
-//
-//******************************************************************************
-#define MCASP_TLMR_TLMR_M       0xFFFFFFFF  // Contains test result signature.
-#define MCASP_TLMR_TLMR_S       0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TLEC register.
-//
-//******************************************************************************
-#define MCASP_TLEC_TLEC_M       0xFFFFFFFF  // Contains number of cycles during
-                                            // which MISR sig will be
-                                            // accumulated.
-#define MCASP_TLEC_TLEC_S       0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_GBLCTL register.
-//
-//******************************************************************************
-#define MCASP_GBLCTL_XFRST      0x00001000  // Frame sync generator reset 0 1
-#define MCASP_GBLCTL_XSMRST     0x00000800  // XMT state machine reset 0 1
-#define MCASP_GBLCTL_XSRCLR     0x00000400  // XMT serializer clear 0 1
-#define MCASP_GBLCTL_XHCLKRST   0x00000200  // XMT High Freq. clk Divider 0 1
-#define MCASP_GBLCTL_XCLKRST    0x00000100  // XMT clock divder reset 0 1
-#define MCASP_GBLCTL_RFRST      0x00000010  // Frame sync generator reset 0 1
-#define MCASP_GBLCTL_RSMRST     0x00000008  // RCV state machine reset 0 1
-#define MCASP_GBLCTL_RSRCLR     0x00000004  // RCV serializer clear 0 1
-#define MCASP_GBLCTL_RHCLKRST   0x00000002  // RCV High Freq. clk Divider 0 1
-#define MCASP_GBLCTL_RCLKRST    0x00000001  // RCV clock divder reset 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_AMUTE register.
-//
-//******************************************************************************
-#define MCASP_AMUTE_XDMAERR     0x00001000  // MUTETXDMAERR occur 0 1
-#define MCASP_AMUTE_RDMAERR     0x00000800  // MUTERXDMAERR occur 0 1
-#define MCASP_AMUTE_XCKFAIL     0x00000400  // XMT bad clock 0 1
-#define MCASP_AMUTE_RCKFAIL     0x00000200  // RCV bad clock 0 1
-#define MCASP_AMUTE_XSYNCERR    0x00000100  // XMT unexpected FS 0 1
-#define MCASP_AMUTE_RSYNCERR    0x00000080  // RCV unexpected FS 0 1
-#define MCASP_AMUTE_XUNDRN      0x00000040  // XMT underrun occurs 0 1
-#define MCASP_AMUTE_ROVRN       0x00000020  // RCV overun occurs 0 1
-#define MCASP_AMUTE_INSTAT      0x00000010
-#define MCASP_AMUTE_INEN        0x00000008  // drive AMUTE active on mute in
-                                            // active 0 1
-#define MCASP_AMUTE_INPOL       0x00000004  // Mute input polarity 0 1
-#define MCASP_AMUTE_MUTEN_M     0x00000003  // AMUTE pin enable 0x0 0x1 0x2
-#define MCASP_AMUTE_MUTEN_S     0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_LBCTL register.
-//
-//******************************************************************************
-#define MCASP_LBCTL_IOLBEN      0x00000010  // IO loopback enable 0 1
-#define MCASP_LBCTL_MODE_M      0x0000000C  // Loop back clock source generator
-                                            // 0x0 0x1 0x2 0x3
-#define MCASP_LBCTL_MODE_S      2
-#define MCASP_LBCTL_ORD         0x00000002  // Loopback order 0 1
-#define MCASP_LBCTL_DLBEN       0x00000001  // Loop back mode 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXDITCTL register.
-//
-//******************************************************************************
-#define MCASP_TXDITCTL_VB       0x00000008  // Valib bit for odd TDM 0 1
-#define MCASP_TXDITCTL_VA       0x00000004  // Valib bit for even TDM 0 1
-#define MCASP_TXDITCTL_DITEN    0x00000001  // XMT DIT Mode Enable 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_GBLCTLR register.
-//
-//******************************************************************************
-#define MCASP_GBLCTLR_XFRST     0x00001000
-#define MCASP_GBLCTLR_XSMRST    0x00000800
-#define MCASP_GBLCTLR_XSRCLR    0x00000400
-#define MCASP_GBLCTLR_XHCLKRST  0x00000200
-#define MCASP_GBLCTLR_XCLKRST   0x00000100
-#define MCASP_GBLCTLR_RFRST     0x00000010  // Frame sync generator reset 0 1
-#define MCASP_GBLCTLR_RSMRST    0x00000008  // RCV state machine reset 0 1
-#define MCASP_GBLCTLR_RSRCLR    0x00000004  // RCV serializer clear 0 1
-#define MCASP_GBLCTLR_RHCLKRST  0x00000002  // RCV High Freq. clk Divider 0 1
-#define MCASP_GBLCTLR_RCLKRST   0x00000001  // RCV clock divder reset 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXMASK register.
-//
-//******************************************************************************
-#define MCASP_RXMASK_RMASK31    0x80000000  // RMASK BIT 31 0 1
-#define MCASP_RXMASK_RMASK30    0x40000000  // RMASK BIT 30 0 1
-#define MCASP_RXMASK_RMASK29    0x20000000  // RMASK BIT 29 0 1
-#define MCASP_RXMASK_RMASK28    0x10000000  // RMASK BIT 28 0 1
-#define MCASP_RXMASK_RMASK27    0x08000000  // RMASK BIT 27 0 1
-#define MCASP_RXMASK_RMASK26    0x04000000  // RMASK BIT 26 0 1
-#define MCASP_RXMASK_RMASK25    0x02000000  // RMASK BIT 25 0 1
-#define MCASP_RXMASK_RMASK24    0x01000000  // RMASK BIT 24 0 1
-#define MCASP_RXMASK_RMASK23    0x00800000  // RMASK BIT 23 0 1
-#define MCASP_RXMASK_RMASK22    0x00400000  // RMASK BIT 22 0 1
-#define MCASP_RXMASK_RMASK21    0x00200000  // RMASK BIT 21 0 1
-#define MCASP_RXMASK_RMASK20    0x00100000  // RMASK BIT 20 0 1
-#define MCASP_RXMASK_RMASK19    0x00080000  // RMASK BIT 19 0 1
-#define MCASP_RXMASK_RMASK18    0x00040000  // RMASK BIT 18 0 1
-#define MCASP_RXMASK_RMASK17    0x00020000  // RMASK BIT 17 0 1
-#define MCASP_RXMASK_RMASK16    0x00010000  // RMASK BIT 16 0 1
-#define MCASP_RXMASK_RMASK15    0x00008000  // RMASK BIT 15 0 1
-#define MCASP_RXMASK_RMASK14    0x00004000  // RMASK BIT 14 0 1
-#define MCASP_RXMASK_RMASK13    0x00002000  // RMASK BIT 13 0 1
-#define MCASP_RXMASK_RMASK12    0x00001000  // RMASK BIT 12 0 1
-#define MCASP_RXMASK_RMASK11    0x00000800  // RMASK BIT 11 0 1
-#define MCASP_RXMASK_RMASK10    0x00000400  // RMASK BIT 10 0 1
-#define MCASP_RXMASK_RMASK9     0x00000200  // RMASK BIT 9 0 1
-#define MCASP_RXMASK_RMASK8     0x00000100  // RMASK BIT 8 0 1
-#define MCASP_RXMASK_RMASK7     0x00000080  // RMASK BIT 7 0 1
-#define MCASP_RXMASK_RMASK6     0x00000040  // RMASK BIT 6 0 1
-#define MCASP_RXMASK_RMASK5     0x00000020  // RMASK BIT 5 0 1
-#define MCASP_RXMASK_RMASK4     0x00000010  // RMASK BIT 4 0 1
-#define MCASP_RXMASK_RMASK3     0x00000008  // RMASK BIT 3 0 1
-#define MCASP_RXMASK_RMASK2     0x00000004  // RMASK BIT 2 0 1
-#define MCASP_RXMASK_RMASK1     0x00000002  // RMASK BIT 1 0 1
-#define MCASP_RXMASK_RMASK0     0x00000001  // RMASK BIT 0 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXFMT register.
-//
-//******************************************************************************
-#define MCASP_RXFMT_RDATDLY_M   0x00030000  // RCV Frame sync delay 0x0 0 Bit
-                                            // delay 0x1 1 Bit delay 0x2 2 Bit
-                                            // delay
-#define MCASP_RXFMT_RDATDLY_S   16
-#define MCASP_RXFMT_RRVRS       0x00008000  // RCV serial stream bit order 0 1
-#define MCASP_RXFMT_RPAD_M      0x00006000  // Pad value 0x0 0x1 0x2
-#define MCASP_RXFMT_RPAD_S      13
-#define MCASP_RXFMT_RPBIT_M     0x00001F00  // Pad bit position
-#define MCASP_RXFMT_RPBIT_S     8
-#define MCASP_RXFMT_RSSZ_M      0x000000F0  // RCV slot Size 0x0 0x1 0x2 0x3
-                                            // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB
-                                            // 0xC 0xD 0xE 0xF
-#define MCASP_RXFMT_RSSZ_S      4
-#define MCASP_RXFMT_RBUSEL      0x00000008  // Write to RBUF using CPU/DMA 0
-                                            // DMA port access 1 CPU port Access
-#define MCASP_RXFMT_RROT_M      0x00000007  // Right Rotate Value 0x0 0x1 0x2
-                                            // 0x3 0x4 0x5 0x6 0x7
-#define MCASP_RXFMT_RROT_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXFMCTL register.
-//
-//******************************************************************************
-#define MCASP_RXFMCTL_RMOD_M    0x0000FF80  // RCV Frame sync mode
-#define MCASP_RXFMCTL_RMOD_S    7
-#define MCASP_RXFMCTL_FRWID     0x00000010  // RCV Frame sync Duration 0 1
-#define MCASP_RXFMCTL_FSRM      0x00000002  // RCV frame sync External 0 1
-#define MCASP_RXFMCTL_FSRP      0x00000001  // RCV Frame sync Polarity 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_ACLKRCTL register.
-//
-//******************************************************************************
-#define MCASP_ACLKRCTL_BUSY     0x00100000
-#define MCASP_ACLKRCTL_DIVBUSY  0x00080000
-#define MCASP_ACLKRCTL_ADJBUSY  0x00040000
-#define MCASP_ACLKRCTL_CLKRADJ_M \
-                                0x00030000
-
-#define MCASP_ACLKRCTL_CLKRADJ_S 16
-#define MCASP_ACLKRCTL_CLKRP    0x00000080  // RCV Clock Polarity 0 1
-#define MCASP_ACLKRCTL_CLKRM    0x00000020  // RCV clock source 0 1
-#define MCASP_ACLKRCTL_CLKRDIV_M \
-                                0x0000001F  // RCV clock devide ratio
-
-#define MCASP_ACLKRCTL_CLKRDIV_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_AHCLKRCTL register.
-//
-//******************************************************************************
-#define MCASP_AHCLKRCTL_BUSY    0x00100000
-#define MCASP_AHCLKRCTL_DIVBUSY 0x00080000
-#define MCASP_AHCLKRCTL_ADJBUSY 0x00040000
-#define MCASP_AHCLKRCTL_HCLKRADJ_M \
-                                0x00030000
-
-#define MCASP_AHCLKRCTL_HCLKRADJ_S 16
-#define MCASP_AHCLKRCTL_HCLKRM  0x00008000  // High Freq. RCV clock Source 0 1
-#define MCASP_AHCLKRCTL_HCLKRP  0x00004000  // High Freq. clock Polarity Before
-                                            // diviser 0 1
-#define MCASP_AHCLKRCTL_HCLKRDIV_M \
-                                0x00000FFF  // RCV clock Divide Ratio
-
-#define MCASP_AHCLKRCTL_HCLKRDIV_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXTDM register.
-//
-//******************************************************************************
-#define MCASP_RXTDM_RTDMS31     0x80000000  // RCV mode during TDM time slot 31
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS30     0x40000000  // RCV mode during TDM time slot 30
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS29     0x20000000  // RCV mode during TDM time slot 29
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS28     0x10000000  // RCV mode during TDM time slot 28
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS27     0x08000000  // RCV mode during TDM time slot 27
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS26     0x04000000  // RCV mode during TDM time slot 26
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS25     0x02000000  // RCV mode during TDM time slot 25
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS24     0x01000000  // RCV mode during TDM time slot 24
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS23     0x00800000  // RCV mode during TDM time slot 23
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS22     0x00400000  // RCV mode during TDM time slot 22
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS21     0x00200000  // RCV mode during TDM time slot 21
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS20     0x00100000  // RCV mode during TDM time slot 20
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS19     0x00080000  // RCV mode during TDM time slot 19
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS18     0x00040000  // RCV mode during TDM time slot 18
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS17     0x00020000  // RCV mode during TDM time slot 17
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS16     0x00010000  // RCV mode during TDM time slot 16
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS15     0x00008000  // RCV mode during TDM time slot 15
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS14     0x00004000  // RCV mode during TDM time slot 14
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS13     0x00002000  // RCV mode during TDM time slot 13
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS12     0x00001000  // RCV mode during TDM time slot 12
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS11     0x00000800  // RCV mode during TDM time slot 11
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS10     0x00000400  // RCV mode during TDM time slot 10
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS9      0x00000200  // RCV mode during TDM time slot 9
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS8      0x00000100  // RCV mode during TDM time slot 8
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS7      0x00000080  // RCV mode during TDM time slot 7
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS6      0x00000040  // RCV mode during TDM time slot 6
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS5      0x00000020  // RCV mode during TDM time slot 5
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS4      0x00000010  // RCV mode during TDM time slot 4
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS3      0x00000008  // RCV mode during TDM time slot 3
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS2      0x00000004  // RCV mode during TDM time slot 2
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS1      0x00000002  // RCV mode during TDM time slot 1
-                                            // 0 1
-#define MCASP_RXTDM_RTDMS0      0x00000001  // RCV mode during TDM time slot 0
-                                            // 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_EVTCTLR register.
-//
-//******************************************************************************
-#define MCASP_EVTCTLR_RSTAFRM   0x00000080  // RCV Start of Frame Interrupt 0 1
-#define MCASP_EVTCTLR_RDATA     0x00000020  // RCV Data Interrupt 0 1
-#define MCASP_EVTCTLR_RLAST     0x00000010  // RCV Last Slot Interrupt 0 1
-#define MCASP_EVTCTLR_RDMAERR   0x00000008  // RCV DMA Bus Error 0 1
-#define MCASP_EVTCTLR_RCKFAIL   0x00000004  // Bad Clock Interrupt 0 1
-#define MCASP_EVTCTLR_RSYNCERR  0x00000002  // RCV Unexpected FSR Interrupt 0 1
-#define MCASP_EVTCTLR_ROVRN     0x00000001  // RCV Underrun Flag 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXSTAT register.
-//
-//******************************************************************************
-#define MCASP_RXSTAT_RERR       0x00000100  // RCV Error 0 1
-#define MCASP_RXSTAT_RDMAERR    0x00000080  // RCV DMA bus error 0 1
-#define MCASP_RXSTAT_RSTAFRM    0x00000040  // Start of Frame-RCV 0 1
-#define MCASP_RXSTAT_RDATA      0x00000020  // Data Ready Flag 0 1
-#define MCASP_RXSTAT_RLAST      0x00000010  // Last Slot Interrupt Flag 0 1
-#define MCASP_RXSTAT_RTDMSLOT   0x00000008  // EvenOdd Slot 0 1
-#define MCASP_RXSTAT_RCKFAIL    0x00000004  // Bad Transmit Flag 0 1
-#define MCASP_RXSTAT_RSYNCERR   0x00000002  // Unexpected RCV Frame sync flag 0
-                                            // 1
-#define MCASP_RXSTAT_ROVRN      0x00000001  // RCV Underrun Flag 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXTDMSLOT register.
-//
-//******************************************************************************
-#define MCASP_RXTDMSLOT_RSLOTCNT_M \
-                                0x000003FF  // Current RCV time slot count
-
-#define MCASP_RXTDMSLOT_RSLOTCNT_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXCLKCHK register.
-//
-//******************************************************************************
-#define MCASP_RXCLKCHK_RCNT_M   0xFF000000  // RCV clock count value
-#define MCASP_RXCLKCHK_RCNT_S   24
-#define MCASP_RXCLKCHK_RMAX_M   0x00FF0000  // RCV clock maximum boundary
-#define MCASP_RXCLKCHK_RMAX_S   16
-#define MCASP_RXCLKCHK_RMIN_M   0x0000FF00  // RCV clock minimum boundary
-#define MCASP_RXCLKCHK_RMIN_S   8
-#define MCASP_RXCLKCHK_RPS_M    0x0000000F  // RCV clock check prescaler 0x0
-                                            // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8
-#define MCASP_RXCLKCHK_RPS_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_REVTCTL register.
-//
-//******************************************************************************
-#define MCASP_REVTCTL_RDATDMA   0x00000001  // RCV data DMA request 0 Enable
-                                            // DMA Transfer 1 Disable DMA
-                                            // Transfer
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_GBLCTLX register.
-//
-//******************************************************************************
-#define MCASP_GBLCTLX_XFRST     0x00001000  // Frame sync generator reset 0 1
-#define MCASP_GBLCTLX_XSMRST    0x00000800  // XMT state machine reset 0 1
-#define MCASP_GBLCTLX_XSRCLR    0x00000400  // XMT serializer clear 0 1
-#define MCASP_GBLCTLX_XHCLKRST  0x00000200  // XMT High Freq. clk Divider 0 1
-#define MCASP_GBLCTLX_XCLKRST   0x00000100  // XMT clock divder reset 0 1
-#define MCASP_GBLCTLX_RFRST     0x00000010
-#define MCASP_GBLCTLX_RSMRST    0x00000008
-#define MCASP_GBLCTLX_RSRCLKR   0x00000004
-#define MCASP_GBLCTLX_RHCLKRST  0x00000002
-#define MCASP_GBLCTLX_RCLKRST   0x00000001
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXMASK register.
-//
-//******************************************************************************
-#define MCASP_TXMASK_XMASK31    0x80000000  // XMASK BIT 31 0 1
-#define MCASP_TXMASK_XMASK30    0x40000000  // XMASK BIT 30 0 1
-#define MCASP_TXMASK_XMASK29    0x20000000  // XMASK BIT 29 0 1
-#define MCASP_TXMASK_XMASK28    0x10000000  // XMASK BIT 28 0 1
-#define MCASP_TXMASK_XMASK27    0x08000000  // XMASK BIT 27 0 1
-#define MCASP_TXMASK_XMASK26    0x04000000  // XMASK BIT 26 0 1
-#define MCASP_TXMASK_XMASK25    0x02000000  // XMASK BIT 25 0 1
-#define MCASP_TXMASK_XMASK24    0x01000000  // XMASK BIT 24 0 1
-#define MCASP_TXMASK_XMASK23    0x00800000  // XMASK BIT 23 0 1
-#define MCASP_TXMASK_XMASK22    0x00400000  // XMASK BIT 22 0 1
-#define MCASP_TXMASK_XMASK21    0x00200000  // XMASK BIT 21 0 1
-#define MCASP_TXMASK_XMASK20    0x00100000  // XMASK BIT 20 0 1
-#define MCASP_TXMASK_XMASK19    0x00080000  // XMASK BIT 19 0 1
-#define MCASP_TXMASK_XMASK18    0x00040000  // XMASK BIT 18 0 1
-#define MCASP_TXMASK_XMASK17    0x00020000  // XMASK BIT 17 0 1
-#define MCASP_TXMASK_XMASK16    0x00010000  // XMASK BIT 16 0 1
-#define MCASP_TXMASK_XMASK15    0x00008000  // XMASK BIT 15 0 1
-#define MCASP_TXMASK_XMASK14    0x00004000  // XMASK BIT 14 0 1
-#define MCASP_TXMASK_XMASK13    0x00002000  // XMASK BIT 13 0 1
-#define MCASP_TXMASK_XMASK12    0x00001000  // XMASK BIT 12 0 1
-#define MCASP_TXMASK_XMASK11    0x00000800  // XMASK BIT 11 0 1
-#define MCASP_TXMASK_XMASK10    0x00000400  // XMASK BIT 10 0 1
-#define MCASP_TXMASK_XMASK9     0x00000200  // XMASK BIT 9 0 1
-#define MCASP_TXMASK_XMASK8     0x00000100  // XMASK BIT 8 0 1
-#define MCASP_TXMASK_XMASK7     0x00000080  // XMASK BIT 7 0 1
-#define MCASP_TXMASK_XMASK6     0x00000040  // XMASK BIT 6 0 1
-#define MCASP_TXMASK_XMASK5     0x00000020  // XMASK BIT 5 0 1
-#define MCASP_TXMASK_XMASK4     0x00000010  // XMASK BIT 4 0 1
-#define MCASP_TXMASK_XMASK3     0x00000008  // XMASK BIT 3 0 1
-#define MCASP_TXMASK_XMASK2     0x00000004  // XMASK BIT 2 0 1
-#define MCASP_TXMASK_XMASK1     0x00000002  // XMASK BIT 1 0 1
-#define MCASP_TXMASK_XMASK0     0x00000001  // XMASK BIT 0 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXFMT register.
-//
-//******************************************************************************
-#define MCASP_TXFMT_XDATDLY_M   0x00030000  // XMT Frame sync delay 0x0 0 Bit
-                                            // delay 0x1 1 Bit delay 0x2 2 Bit
-                                            // delay
-#define MCASP_TXFMT_XDATDLY_S   16
-#define MCASP_TXFMT_XRVRS       0x00008000  // XMT serial stream bit order 0 1
-#define MCASP_TXFMT_XPAD_M      0x00006000  // Pad value 0x0 0x1 0x2
-#define MCASP_TXFMT_XPAD_S      13
-#define MCASP_TXFMT_XPBIT_M     0x00001F00  // Pad bit position
-#define MCASP_TXFMT_XPBIT_S     8
-#define MCASP_TXFMT_XSSZ_M      0x000000F0  // XMT slot Size 0x0 0x1 0x2 0x3
-                                            // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB
-                                            // 0xC 0xD 0xE 0xF
-#define MCASP_TXFMT_XSSZ_S      4
-#define MCASP_TXFMT_XBUSEL      0x00000008  // Write to XBUF using CPU/DMA 0
-                                            // DMA port access 1 CPU port Access
-#define MCASP_TXFMT_XROT_M      0x00000007  // Right Rotate Value 0x0 0x1 0x2
-                                            // 0x3 0x4 0x5 0x6 0x7
-#define MCASP_TXFMT_XROT_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXFMCTL register.
-//
-//******************************************************************************
-#define MCASP_TXFMCTL_XMOD_M    0x0000FF80  // XMT Frame sync mode
-#define MCASP_TXFMCTL_XMOD_S    7
-#define MCASP_TXFMCTL_FXWID     0x00000010  // XMT Frame sync Duration 0 1
-#define MCASP_TXFMCTL_FSXM      0x00000002  // XMT frame sync External 0 1
-#define MCASP_TXFMCTL_FSXP      0x00000001  // XMT Frame sync Polarity 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_ACLKXCTL register.
-//
-//******************************************************************************
-#define MCASP_ACLKXCTL_BUSY     0x00100000
-#define MCASP_ACLKXCTL_DIVBUSY  0x00080000
-#define MCASP_ACLKXCTL_ADJBUSY  0x00040000
-#define MCASP_ACLKXCTL_CLKXADJ_M \
-                                0x00030000
-
-#define MCASP_ACLKXCTL_CLKXADJ_S 16
-#define MCASP_ACLKXCTL_CLKXP    0x00000080  // XMT Clock Polarity 0 1
-#define MCASP_ACLKXCTL_ASYNC    0x00000040  // XMT/RCV operation sync /Async 0
-                                            // 1
-#define MCASP_ACLKXCTL_CLKXM    0x00000020  // XMT clock source 0 1
-#define MCASP_ACLKXCTL_CLKXDIV_M \
-                                0x0000001F  // XMT clock devide ratio
-
-#define MCASP_ACLKXCTL_CLKXDIV_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_AHCLKXCTL register.
-//
-//******************************************************************************
-#define MCASP_AHCLKXCTL_BUSY    0x00100000
-#define MCASP_AHCLKXCTL_DIVBUSY 0x00080000
-#define MCASP_AHCLKXCTL_ADJBUSY 0x00040000
-#define MCASP_AHCLKXCTL_HCLKXADJ_M \
-                                0x00030000
-
-#define MCASP_AHCLKXCTL_HCLKXADJ_S 16
-#define MCASP_AHCLKXCTL_HCLKXM  0x00008000  // High Freq. XMT clock Source 0 1
-#define MCASP_AHCLKXCTL_HCLKXP  0x00004000  // High Freq. clock Polarity Before
-                                            // diviser 0 1
-#define MCASP_AHCLKXCTL_HCLKXDIV_M \
-                                0x00000FFF  // XMT clock Divide Ratio
-
-#define MCASP_AHCLKXCTL_HCLKXDIV_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXTDM register.
-//
-//******************************************************************************
-#define MCASP_TXTDM_XTDMS31     0x80000000  // XMT mode during TDM time slot 31
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS30     0x40000000  // XMT mode during TDM time slot 30
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS29     0x20000000  // XMT mode during TDM time slot 29
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS28     0x10000000  // XMT mode during TDM time slot 28
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS27     0x08000000  // XMT mode during TDM time slot 27
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS26     0x04000000  // XMT mode during TDM time slot 26
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS25     0x02000000  // XMT mode during TDM time slot 25
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS24     0x01000000  // XMT mode during TDM time slot 24
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS23     0x00800000  // XMT mode during TDM time slot 23
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS22     0x00400000  // XMT mode during TDM time slot 22
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS21     0x00200000  // XMT mode during TDM time slot 21
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS20     0x00100000  // XMT mode during TDM time slot 20
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS19     0x00080000  // XMT mode during TDM time slot 19
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS18     0x00040000  // XMT mode during TDM time slot 18
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS17     0x00020000  // XMT mode during TDM time slot 17
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS16     0x00010000  // XMT mode during TDM time slot 16
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS15     0x00008000  // XMT mode during TDM time slot 15
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS14     0x00004000  // XMT mode during TDM time slot 14
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS13     0x00002000  // XMT mode during TDM time slot 13
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS12     0x00001000  // XMT mode during TDM time slot 12
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS11     0x00000800  // XMT mode during TDM time slot 11
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS10     0x00000400  // XMT mode during TDM time slot 10
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS9      0x00000200  // XMT mode during TDM time slot 9
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS8      0x00000100  // XMT mode during TDM time slot 8
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS7      0x00000080  // XMT mode during TDM time slot 7
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS6      0x00000040  // XMT mode during TDM time slot 6
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS5      0x00000020  // XMT mode during TDM time slot 5
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS4      0x00000010  // XMT mode during TDM time slot 4
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS3      0x00000008  // XMT mode during TDM time slot 3
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS2      0x00000004  // XMT mode during TDM time slot 2
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS1      0x00000002  // XMT mode during TDM time slot 1
-                                            // 0 1
-#define MCASP_TXTDM_XTDMS0      0x00000001  // XMT mode during TDM time slot 0
-                                            // 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_EVTCTLX register.
-//
-//******************************************************************************
-#define MCASP_EVTCTLX_XSTAFRM   0x00000080  // XMT Start of Frame Interrupt 0 1
-#define MCASP_EVTCTLX_XDATA     0x00000020  // XMT Data Interrupt 0 1
-#define MCASP_EVTCTLX_XLAST     0x00000010  // XMT Last Slot Interrupt 0 1
-#define MCASP_EVTCTLX_XDMAERR   0x00000008  // XMT DMA Bus Error 0 1
-#define MCASP_EVTCTLX_XCKFAIL   0x00000004  // Bad Clock Interrupt 0 1
-#define MCASP_EVTCTLX_XSYNCERR  0x00000002  // XMT Unexpected FSR Interrupt 0 1
-#define MCASP_EVTCTLX_XUNDRN    0x00000001  // XMT Underrun Interrupt 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXSTAT register.
-//
-//******************************************************************************
-#define MCASP_TXSTAT_XERR       0x00000100  // XMT Error 0 1
-#define MCASP_TXSTAT_XDMAERR    0x00000080  // XMT DMA bus error 0 1
-#define MCASP_TXSTAT_XSTAFRM    0x00000040  // Start of Frame-XMT 0 1
-#define MCASP_TXSTAT_XDATA      0x00000020  // Data Ready Flag 0 1
-#define MCASP_TXSTAT_XLAST      0x00000010  // Last Slot Interrupt Flag 0 1
-#define MCASP_TXSTAT_XTDMSLOT   0x00000008  // EvenOdd Slot 0 1
-#define MCASP_TXSTAT_XCKFAIL    0x00000004  // Bad Transmit Flag 0 1
-#define MCASP_TXSTAT_XSYNCERR   0x00000002  // Unexpected XMT Frame sync flag 0
-                                            // 1
-#define MCASP_TXSTAT_XUNDRN     0x00000001  // XMT Underrun Flag 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXTDMSLOT register.
-//
-//******************************************************************************
-#define MCASP_TXTDMSLOT_XSLOTCNT_M \
-                                0x000003FF  // Current XMT time slot count
-                                            // during reset the value of this
-                                            // register is 0b0101111111 (0x17f)
-                                            // and after reset 0
-
-#define MCASP_TXTDMSLOT_XSLOTCNT_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXCLKCHK register.
-//
-//******************************************************************************
-#define MCASP_TXCLKCHK_XCNT_M   0xFF000000  // XMT clock count value
-#define MCASP_TXCLKCHK_XCNT_S   24
-#define MCASP_TXCLKCHK_XMAX_M   0x00FF0000  // XMT clock maximum boundary
-#define MCASP_TXCLKCHK_XMAX_S   16
-#define MCASP_TXCLKCHK_XMIN_M   0x0000FF00  // XMT clock minimum boundary
-#define MCASP_TXCLKCHK_XMIN_S   8
-#define MCASP_TXCLKCHK_RESV     0x00000080  // Reserved
-#define MCASP_TXCLKCHK_XPS_M    0x0000000F  // XMT clock check prescaler 0x0
-                                            // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8
-#define MCASP_TXCLKCHK_XPS_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_XEVTCTL register.
-//
-//******************************************************************************
-#define MCASP_XEVTCTL_XDATDMA   0x00000001  // XMT data DMA request 0 Enable
-                                            // DMA Transfer 1 Disable DMA
-                                            // Transfer
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_CLKADJEN register.
-//
-//******************************************************************************
-#define MCASP_CLKADJEN_ENABLE   0x00000001  // One-shot clock adjust enable 0 1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITCSRA0 register.
-//
-//******************************************************************************
-#define MCASP_DITCSRA0_DITCSRA0_M \
-                                0xFFFFFFFF  // Left (Even TDM slot ) Channel
-                                            // status
-
-#define MCASP_DITCSRA0_DITCSRA0_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITCSRA1 register.
-//
-//******************************************************************************
-#define MCASP_DITCSRA1_DITCSRA1_M \
-                                0xFFFFFFFF  // Left (Even TDM slot ) Channel
-                                            // status
-
-#define MCASP_DITCSRA1_DITCSRA1_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITCSRA2 register.
-//
-//******************************************************************************
-#define MCASP_DITCSRA2_DITCSRA2_M \
-                                0xFFFFFFFF  // Left (Even TDM slot ) Channel
-                                            // status Register
-
-#define MCASP_DITCSRA2_DITCSRA2_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITCSRA3 register.
-//
-//******************************************************************************
-#define MCASP_DITCSRA3_DITCSRA3_M \
-                                0xFFFFFFFF  // Left (Even TDM slot ) Channel
-                                            // status Register
-
-#define MCASP_DITCSRA3_DITCSRA3_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITCSRA4 register.
-//
-//******************************************************************************
-#define MCASP_DITCSRA4_DITCSRA4_M \
-                                0xFFFFFFFF  // Left (Even TDM slot ) Channel
-                                            // status
-
-#define MCASP_DITCSRA4_DITCSRA4_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITCSRA5 register.
-//
-//******************************************************************************
-#define MCASP_DITCSRA5_DITCSRA5_M \
-                                0xFFFFFFFF  // Left (Even TDM slot ) Channel
-                                            // status
-
-#define MCASP_DITCSRA5_DITCSRA5_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITCSRB0 register.
-//
-//******************************************************************************
-#define MCASP_DITCSRB0_DITCSRB0_M \
-                                0xFFFFFFFF  // Right (odd TDM slot ) Channel
-                                            // status
-
-#define MCASP_DITCSRB0_DITCSRB0_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITCSRB1 register.
-//
-//******************************************************************************
-#define MCASP_DITCSRB1_DITCSRB1_M \
-                                0xFFFFFFFF  // Right (odd TDM slot ) Channel
-                                            // status
-
-#define MCASP_DITCSRB1_DITCSRB1_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITCSRB2 register.
-//
-//******************************************************************************
-#define MCASP_DITCSRB2_DITCSRB2_M \
-                                0xFFFFFFFF  // Right (odd TDM slot ) Channel
-                                            // status
-
-#define MCASP_DITCSRB2_DITCSRB2_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITCSRB3 register.
-//
-//******************************************************************************
-#define MCASP_DITCSRB3_DITCSRB3_M \
-                                0xFFFFFFFF  // Right (odd TDM slot ) Channel
-                                            // status
-
-#define MCASP_DITCSRB3_DITCSRB3_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITCSRB4 register.
-//
-//******************************************************************************
-#define MCASP_DITCSRB4_DITCSRB4_M \
-                                0xFFFFFFFF  // Right (odd TDM slot ) Channel
-                                            // status
-
-#define MCASP_DITCSRB4_DITCSRB4_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITCSRB5 register.
-//
-//******************************************************************************
-#define MCASP_DITCSRB5_DITCSRB5_M \
-                                0xFFFFFFFF  // Right (odd TDM slot ) Channel
-                                            // status
-
-#define MCASP_DITCSRB5_DITCSRB5_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITUDRA0 register.
-//
-//******************************************************************************
-#define MCASP_DITUDRA0_DITUDRA0_M \
-                                0xFFFFFFFF  // Left (Even TDM slot ) User Data
-
-#define MCASP_DITUDRA0_DITUDRA0_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITUDRA1 register.
-//
-//******************************************************************************
-#define MCASP_DITUDRA1_DITUDRA1_M \
-                                0xFFFFFFFF  // Left (Even TDM slot ) User Data
-
-#define MCASP_DITUDRA1_DITUDRA1_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITUDRA2 register.
-//
-//******************************************************************************
-#define MCASP_DITUDRA2_DITUDRA2_M \
-                                0xFFFFFFFF  // Left (Even TDM slot ) User Data
-
-#define MCASP_DITUDRA2_DITUDRA2_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITUDRA3 register.
-//
-//******************************************************************************
-#define MCASP_DITUDRA3_DITUDRA3_M \
-                                0xFFFFFFFF  // Left (Even TDM slot ) User Data
-
-#define MCASP_DITUDRA3_DITUDRA3_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITUDRA4 register.
-//
-//******************************************************************************
-#define MCASP_DITUDRA4_DITUDRA4_M \
-                                0xFFFFFFFF  // Left (Even TDM slot ) User Data
-
-#define MCASP_DITUDRA4_DITUDRA4_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITUDRA5 register.
-//
-//******************************************************************************
-#define MCASP_DITUDRA5_DITUDRA5_M \
-                                0xFFFFFFFF  // Left (Even TDM slot ) User Data
-
-#define MCASP_DITUDRA5_DITUDRA5_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITUDRB0 register.
-//
-//******************************************************************************
-#define MCASP_DITUDRB0_DITUDRB0_M \
-                                0xFFFFFFFF  // Right (odd TDM slot ) User Data
-
-#define MCASP_DITUDRB0_DITUDRB0_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITUDRB1 register.
-//
-//******************************************************************************
-#define MCASP_DITUDRB1_DITUDRB1_M \
-                                0xFFFFFFFF  // Right (odd TDM slot ) User Data
-
-#define MCASP_DITUDRB1_DITUDRB1_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITUDRB2 register.
-//
-//******************************************************************************
-#define MCASP_DITUDRB2_DITUDRB2_M \
-                                0xFFFFFFFF  // Right (odd TDM slot ) User Data
-
-#define MCASP_DITUDRB2_DITUDRB2_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITUDRB3 register.
-//
-//******************************************************************************
-#define MCASP_DITUDRB3_DITUDRB3_M \
-                                0xFFFFFFFF  // Right (odd TDM slot ) User Data
-
-#define MCASP_DITUDRB3_DITUDRB3_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITUDRB4 register.
-//
-//******************************************************************************
-#define MCASP_DITUDRB4_DITUDRB4_M \
-                                0xFFFFFFFF  // Right (odd TDM slot ) User Data
-
-#define MCASP_DITUDRB4_DITUDRB4_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_DITUDRB5 register.
-//
-//******************************************************************************
-#define MCASP_DITUDRB5_DITUDRB5_M \
-                                0xFFFFFFFF  // Right (odd TDM slot ) User Data
-
-#define MCASP_DITUDRB5_DITUDRB5_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_XRSRCTL0 register.
-//
-//******************************************************************************
-#define MCASP_XRSRCTL0_RRDY     0x00000020
-#define MCASP_XRSRCTL0_XRDY     0x00000010
-#define MCASP_XRSRCTL0_DISMOD_M 0x0000000C  // Serializer drive state 0x0 Tri
-                                            // state 0x1 Reserved 0x2 Drive pin
-                                            // low 0x3 Drive pin high
-#define MCASP_XRSRCTL0_DISMOD_S 2
-#define MCASP_XRSRCTL0_SRMOD_M  0x00000003  // Serializer Mode 0x0 InActive
-                                            // mode 0x1 Transmit mode 0x2
-                                            // Receive mode
-#define MCASP_XRSRCTL0_SRMOD_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_XRSRCTL1 register.
-//
-//******************************************************************************
-#define MCASP_XRSRCTL1_RRDY     0x00000020
-#define MCASP_XRSRCTL1_XRDY     0x00000010
-#define MCASP_XRSRCTL1_DISMOD_M 0x0000000C  // Serializer drive state 0x0 Tri
-                                            // state 0x1 Reserved 0x2 Drive pin
-                                            // low 0x3 Drive pin high
-#define MCASP_XRSRCTL1_DISMOD_S 2
-#define MCASP_XRSRCTL1_SRMOD_M  0x00000003  // Serializer Mode 0x0 InActive
-                                            // mode 0x1 Transmit mode 0x2
-                                            // Receive mode
-#define MCASP_XRSRCTL1_SRMOD_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_XRSRCTL2 register.
-//
-//******************************************************************************
-#define MCASP_XRSRCTL2_RRDY     0x00000020
-#define MCASP_XRSRCTL2_XRDY     0x00000010
-#define MCASP_XRSRCTL2_DISMOD_M 0x0000000C  // Serializer drive state 0x0 Tri
-                                            // state 0x1 Reserved 0x2 Drive pin
-                                            // low 0x3 Drive pin high
-#define MCASP_XRSRCTL2_DISMOD_S 2
-#define MCASP_XRSRCTL2_SRMOD_M  0x00000003  // Serializer Mode 0x0 InActive
-                                            // mode 0x1 Transmit mode 0x2
-                                            // Receive mode
-#define MCASP_XRSRCTL2_SRMOD_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_XRSRCTL3 register.
-//
-//******************************************************************************
-#define MCASP_XRSRCTL3_RRDY     0x00000020
-#define MCASP_XRSRCTL3_XRDY     0x00000010
-#define MCASP_XRSRCTL3_DISMOD_M 0x0000000C  // Serializer drive state 0x0 Tri
-                                            // state 0x1 Reserved 0x2 Drive pin
-                                            // low 0x3 Drive pin high
-#define MCASP_XRSRCTL3_DISMOD_S 2
-#define MCASP_XRSRCTL3_SRMOD_M  0x00000003  // Serializer Mode 0x0 InActive
-                                            // mode 0x1 Transmit mode 0x2
-                                            // Receive mode
-#define MCASP_XRSRCTL3_SRMOD_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_XRSRCTL4 register.
-//
-//******************************************************************************
-#define MCASP_XRSRCTL4_RRDY     0x00000020
-#define MCASP_XRSRCTL4_XRDY     0x00000010
-#define MCASP_XRSRCTL4_DISMOD_M 0x0000000C  // Serializer drive state 0x0 Tri
-                                            // state 0x1 Reserved 0x2 Drive pin
-                                            // low 0x3 Drive pin high
-#define MCASP_XRSRCTL4_DISMOD_S 2
-#define MCASP_XRSRCTL4_SRMOD_M  0x00000003  // Serializer Mode 0x0 InActive
-                                            // mode 0x1 Transmit mode 0x2
-                                            // Receive mode
-#define MCASP_XRSRCTL4_SRMOD_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_XRSRCTL5 register.
-//
-//******************************************************************************
-#define MCASP_XRSRCTL5_RRDY     0x00000020
-#define MCASP_XRSRCTL5_XRDY     0x00000010
-#define MCASP_XRSRCTL5_DISMOD_M 0x0000000C  // Serializer drive state 0x0 Tri
-                                            // state 0x1 Reserved 0x2 Drive pin
-                                            // low 0x3 Drive pin high
-#define MCASP_XRSRCTL5_DISMOD_S 2
-#define MCASP_XRSRCTL5_SRMOD_M  0x00000003  // Serializer Mode 0x0 InActive
-                                            // mode 0x1 Transmit mode 0x2
-                                            // Receive mode
-#define MCASP_XRSRCTL5_SRMOD_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_XRSRCTL6 register.
-//
-//******************************************************************************
-#define MCASP_XRSRCTL6_RRDY     0x00000020
-#define MCASP_XRSRCTL6_XRDY     0x00000010
-#define MCASP_XRSRCTL6_DISMOD_M 0x0000000C  // Serializer drive state 0x0 Tri
-                                            // state 0x1 Reserved 0x2 Drive pin
-                                            // low 0x3 Drive pin high
-#define MCASP_XRSRCTL6_DISMOD_S 2
-#define MCASP_XRSRCTL6_SRMOD_M  0x00000003  // Serializer Mode 0x0 InActive
-                                            // mode 0x1 Transmit mode 0x2
-                                            // Receive mode
-#define MCASP_XRSRCTL6_SRMOD_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_XRSRCTL7 register.
-//
-//******************************************************************************
-#define MCASP_XRSRCTL7_RRDY     0x00000020
-#define MCASP_XRSRCTL7_XRDY     0x00000010
-#define MCASP_XRSRCTL7_DISMOD_M 0x0000000C  // Serializer drive state 0x0 Tri
-                                            // state 0x1 Reserved 0x2 Drive pin
-                                            // low 0x3 Drive pin high
-#define MCASP_XRSRCTL7_DISMOD_S 2
-#define MCASP_XRSRCTL7_SRMOD_M  0x00000003  // Serializer Mode 0x0 InActive
-                                            // mode 0x1 Transmit mode 0x2
-                                            // Receive mode
-#define MCASP_XRSRCTL7_SRMOD_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_XRSRCTL8 register.
-//
-//******************************************************************************
-#define MCASP_XRSRCTL8_RRDY     0x00000020
-#define MCASP_XRSRCTL8_XRDY     0x00000010
-#define MCASP_XRSRCTL8_DISMOD_M 0x0000000C  // Serializer drive state 0x0 Tri
-                                            // state 0x1 Reserved 0x2 Drive pin
-                                            // low 0x3 Drive pin high
-#define MCASP_XRSRCTL8_DISMOD_S 2
-#define MCASP_XRSRCTL8_SRMOD_M  0x00000003  // Serializer Mode 0x0 InActive
-                                            // mode 0x1 Transmit mode 0x2
-                                            // Receive mode
-#define MCASP_XRSRCTL8_SRMOD_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_XRSRCTL9 register.
-//
-//******************************************************************************
-#define MCASP_XRSRCTL9_RRDY     0x00000020
-#define MCASP_XRSRCTL9_XRDY     0x00000010
-#define MCASP_XRSRCTL9_DISMOD_M 0x0000000C  // Serializer drive state 0x0 Tri
-                                            // state 0x1 Reserved 0x2 Drive pin
-                                            // low 0x3 Drive pin high
-#define MCASP_XRSRCTL9_DISMOD_S 2
-#define MCASP_XRSRCTL9_SRMOD_M  0x00000003  // Serializer Mode 0x0 InActive
-                                            // mode 0x1 Transmit mode 0x2
-                                            // Receive mode
-#define MCASP_XRSRCTL9_SRMOD_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_XRSRCTL10 register.
-//
-//******************************************************************************
-#define MCASP_XRSRCTL10_RRDY    0x00000020
-#define MCASP_XRSRCTL10_XRDY    0x00000010
-#define MCASP_XRSRCTL10_DISMOD_M \
-                                0x0000000C  // Serializer drive state 0x0 Tri
-                                            // state 0x1 Reserved 0x2 Drive pin
-                                            // low 0x3 Drive pin high
-
-#define MCASP_XRSRCTL10_DISMOD_S 2
-#define MCASP_XRSRCTL10_SRMOD_M 0x00000003  // Serializer Mode 0x0 InActive
-                                            // mode 0x1 Transmit mode 0x2
-                                            // Receive mode
-#define MCASP_XRSRCTL10_SRMOD_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_XRSRCTL11 register.
-//
-//******************************************************************************
-#define MCASP_XRSRCTL11_RRDY    0x00000020
-#define MCASP_XRSRCTL11_XRDY    0x00000010
-#define MCASP_XRSRCTL11_DISMOD_M \
-                                0x0000000C  // Serializer drive state 0x0 Tri
-                                            // state 0x1 Reserved 0x2 Drive pin
-                                            // low 0x3 Drive pin high
-
-#define MCASP_XRSRCTL11_DISMOD_S 2
-#define MCASP_XRSRCTL11_SRMOD_M 0x00000003  // Serializer Mode 0x0 InActive
-                                            // mode 0x1 Transmit mode 0x2
-                                            // Receive mode
-#define MCASP_XRSRCTL11_SRMOD_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_XRSRCTL12 register.
-//
-//******************************************************************************
-#define MCASP_XRSRCTL12_RRDY    0x00000020
-#define MCASP_XRSRCTL12_XRDY    0x00000010
-#define MCASP_XRSRCTL12_DISMOD_M \
-                                0x0000000C  // Serializer drive state 0x0 Tri
-                                            // state 0x1 Reserved 0x2 Drive pin
-                                            // low 0x3 Drive pin high
-
-#define MCASP_XRSRCTL12_DISMOD_S 2
-#define MCASP_XRSRCTL12_SRMOD_M 0x00000003  // Serializer Mode 0x0 InActive
-                                            // mode 0x1 Transmit mode 0x2
-                                            // Receive mode
-#define MCASP_XRSRCTL12_SRMOD_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_XRSRCTL13 register.
-//
-//******************************************************************************
-#define MCASP_XRSRCTL13_RRDY    0x00000020
-#define MCASP_XRSRCTL13_XRDY    0x00000010
-#define MCASP_XRSRCTL13_DISMOD_M \
-                                0x0000000C  // Serializer drive state 0x0 Tri
-                                            // state 0x1 Reserved 0x2 Drive pin
-                                            // low 0x3 Drive pin high
-
-#define MCASP_XRSRCTL13_DISMOD_S 2
-#define MCASP_XRSRCTL13_SRMOD_M 0x00000003  // Serializer Mode 0x0 InActive
-                                            // mode 0x1 Transmit mode 0x2
-                                            // Receive mode
-#define MCASP_XRSRCTL13_SRMOD_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_XRSRCTL14 register.
-//
-//******************************************************************************
-#define MCASP_XRSRCTL14_RRDY    0x00000020
-#define MCASP_XRSRCTL14_XRDY    0x00000010
-#define MCASP_XRSRCTL14_DISMOD_M \
-                                0x0000000C  // Serializer drive state 0x0 Tri
-                                            // state 0x1 Reserved 0x2 Drive pin
-                                            // low 0x3 Drive pin high
-
-#define MCASP_XRSRCTL14_DISMOD_S 2
-#define MCASP_XRSRCTL14_SRMOD_M 0x00000003  // Serializer Mode 0x0 InActive
-                                            // mode 0x1 Transmit mode 0x2
-                                            // Receive mode
-#define MCASP_XRSRCTL14_SRMOD_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_XRSRCTL15 register.
-//
-//******************************************************************************
-#define MCASP_XRSRCTL15_RRDY    0x00000020
-#define MCASP_XRSRCTL15_XRDY    0x00000010
-#define MCASP_XRSRCTL15_DISMOD_M \
-                                0x0000000C  // Serializer drive state 0x0 Tri
-                                            // state 0x1 Reserved 0x2 Drive pin
-                                            // low 0x3 Drive pin high
-
-#define MCASP_XRSRCTL15_DISMOD_S 2
-#define MCASP_XRSRCTL15_SRMOD_M 0x00000003  // Serializer Mode 0x0 InActive
-                                            // mode 0x1 Transmit mode 0x2
-                                            // Receive mode
-#define MCASP_XRSRCTL15_SRMOD_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXBUF0 register.
-//
-//******************************************************************************
-#define MCASP_TXBUF0_XBUF0_M    0xFFFFFFFF  // Transmit Buffer 0
-#define MCASP_TXBUF0_XBUF0_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXBUF1 register.
-//
-//******************************************************************************
-#define MCASP_TXBUF1_XBUF1_M    0xFFFFFFFF  // Transmit Buffer 1
-#define MCASP_TXBUF1_XBUF1_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXBUF2 register.
-//
-//******************************************************************************
-#define MCASP_TXBUF2_XBUF2_M    0xFFFFFFFF  // Transmit Buffer 2
-#define MCASP_TXBUF2_XBUF2_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXBUF3 register.
-//
-//******************************************************************************
-#define MCASP_TXBUF3_XBUF3_M    0xFFFFFFFF  // Transmit Buffer 3
-#define MCASP_TXBUF3_XBUF3_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXBUF4 register.
-//
-//******************************************************************************
-#define MCASP_TXBUF4_XBUF4_M    0xFFFFFFFF  // Transmit Buffer 4
-#define MCASP_TXBUF4_XBUF4_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXBUF5 register.
-//
-//******************************************************************************
-#define MCASP_TXBUF5_XBUF5_M    0xFFFFFFFF  // Transmit Buffer 5
-#define MCASP_TXBUF5_XBUF5_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXBUF6 register.
-//
-//******************************************************************************
-#define MCASP_TXBUF6_XBUF6_M    0xFFFFFFFF  // Transmit Buffer 6
-#define MCASP_TXBUF6_XBUF6_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXBUF7 register.
-//
-//******************************************************************************
-#define MCASP_TXBUF7_XBUF7_M    0xFFFFFFFF  // Transmit Buffer 7
-#define MCASP_TXBUF7_XBUF7_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXBUF8 register.
-//
-//******************************************************************************
-#define MCASP_TXBUF8_XBUF8_M    0xFFFFFFFF  // Transmit Buffer 8
-#define MCASP_TXBUF8_XBUF8_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXBUF9 register.
-//
-//******************************************************************************
-#define MCASP_TXBUF9_XBUF9_M    0xFFFFFFFF  // Transmit Buffer 9
-#define MCASP_TXBUF9_XBUF9_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXBUF10 register.
-//
-//******************************************************************************
-#define MCASP_TXBUF10_XBUF10_M  0xFFFFFFFF  // Transmit Buffer 10
-#define MCASP_TXBUF10_XBUF10_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXBUF11 register.
-//
-//******************************************************************************
-#define MCASP_TXBUF11_XBUF11_M  0xFFFFFFFF  // Transmit Buffer 11
-#define MCASP_TXBUF11_XBUF11_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXBUF12 register.
-//
-//******************************************************************************
-#define MCASP_TXBUF12_XBUF12_M  0xFFFFFFFF  // Transmit Buffer 12
-#define MCASP_TXBUF12_XBUF12_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXBUF13 register.
-//
-//******************************************************************************
-#define MCASP_TXBUF13_XBUF13_M  0xFFFFFFFF  // Transmit Buffer 13
-#define MCASP_TXBUF13_XBUF13_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXBUF14 register.
-//
-//******************************************************************************
-#define MCASP_TXBUF14_XBUF14_M  0xFFFFFFFF  // Transmit Buffer 14
-#define MCASP_TXBUF14_XBUF14_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_TXBUF15 register.
-//
-//******************************************************************************
-#define MCASP_TXBUF15_XBUF15_M  0xFFFFFFFF  // Transmit Buffer 15
-#define MCASP_TXBUF15_XBUF15_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXBUF0 register.
-//
-//******************************************************************************
-#define MCASP_RXBUF0_RBUF0_M    0xFFFFFFFF  // Receive Buffer 0
-#define MCASP_RXBUF0_RBUF0_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXBUF1 register.
-//
-//******************************************************************************
-#define MCASP_RXBUF1_RBUF1_M    0xFFFFFFFF  // Receive Buffer 1
-#define MCASP_RXBUF1_RBUF1_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXBUF2 register.
-//
-//******************************************************************************
-#define MCASP_RXBUF2_RBUF2_M    0xFFFFFFFF  // Receive Buffer 2
-#define MCASP_RXBUF2_RBUF2_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXBUF3 register.
-//
-//******************************************************************************
-#define MCASP_RXBUF3_RBUF3_M    0xFFFFFFFF  // Receive Buffer 3
-#define MCASP_RXBUF3_RBUF3_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXBUF4 register.
-//
-//******************************************************************************
-#define MCASP_RXBUF4_RBUF4_M    0xFFFFFFFF  // Receive Buffer 4
-#define MCASP_RXBUF4_RBUF4_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXBUF5 register.
-//
-//******************************************************************************
-#define MCASP_RXBUF5_RBUF5_M    0xFFFFFFFF  // Receive Buffer 5
-#define MCASP_RXBUF5_RBUF5_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXBUF6 register.
-//
-//******************************************************************************
-#define MCASP_RXBUF6_RBUF6_M    0xFFFFFFFF  // Receive Buffer 6
-#define MCASP_RXBUF6_RBUF6_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXBUF7 register.
-//
-//******************************************************************************
-#define MCASP_RXBUF7_RBUF7_M    0xFFFFFFFF  // Receive Buffer 7
-#define MCASP_RXBUF7_RBUF7_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXBUF8 register.
-//
-//******************************************************************************
-#define MCASP_RXBUF8_RBUF8_M    0xFFFFFFFF  // Receive Buffer 8
-#define MCASP_RXBUF8_RBUF8_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXBUF9 register.
-//
-//******************************************************************************
-#define MCASP_RXBUF9_RBUF9_M    0xFFFFFFFF  // Receive Buffer 9
-#define MCASP_RXBUF9_RBUF9_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXBUF10 register.
-//
-//******************************************************************************
-#define MCASP_RXBUF10_RBUF10_M  0xFFFFFFFF  // Receive Buffer 10
-#define MCASP_RXBUF10_RBUF10_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXBUF11 register.
-//
-//******************************************************************************
-#define MCASP_RXBUF11_RBUF11_M  0xFFFFFFFF  // Receive Buffer 11
-#define MCASP_RXBUF11_RBUF11_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXBUF12 register.
-//
-//******************************************************************************
-#define MCASP_RXBUF12_RBUF12_M  0xFFFFFFFF  // Receive Buffer 12
-#define MCASP_RXBUF12_RBUF12_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXBUF13 register.
-//
-//******************************************************************************
-#define MCASP_RXBUF13_RBUF13_M  0xFFFFFFFF  // Receive Buffer 13
-#define MCASP_RXBUF13_RBUF13_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXBUF14 register.
-//
-//******************************************************************************
-#define MCASP_RXBUF14_RBUF14_M  0xFFFFFFFF  // Receive Buffer 14
-#define MCASP_RXBUF14_RBUF14_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCASP_O_RXBUF15 register.
-//
-//******************************************************************************
-#define MCASP_RXBUF15_RBUF15_M  0xFFFFFFFF  // Receive Buffer 15
-#define MCASP_RXBUF15_RBUF15_S  0
-
-
-
-#endif // __HW_MCASP_H__
diff --git a/cc3200/hal/inc/hw_mcspi.h b/cc3200/hal/inc/hw_mcspi.h
deleted file mode 100644
index 079e4b6b6..000000000
--- a/cc3200/hal/inc/hw_mcspi.h
+++ /dev/null
@@ -1,1745 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_MCSPI_H__
-#define __HW_MCSPI_H__
-
-//*****************************************************************************
-//
-// The following are defines for the MCSPI register offsets.
-//
-//*****************************************************************************
-#define MCSPI_O_HL_REV          0x00000000  // IP Revision Identifier (X.Y.R)
-                                            // Used by software to track
-                                            // features bugs and compatibility
-#define MCSPI_O_HL_HWINFO       0x00000004  // Information about the IP
-                                            // module's hardware configuration
-                                            // i.e. typically the module's HDL
-                                            // generics (if any). Actual field
-                                            // format and encoding is up to the
-                                            // module's designer to decide.
-#define MCSPI_O_HL_SYSCONFIG    0x00000010  // 0x4402 1010 0x4402 2010 Clock
-                                            // management configuration
-#define MCSPI_O_REVISION        0x00000100  // 0x4402 1100 0x4402 2100 This
-                                            // register contains the hard coded
-                                            // RTL revision number.
-#define MCSPI_O_SYSCONFIG       0x00000110  // 0x4402 1110 0x4402 2110 This
-                                            // register allows controlling
-                                            // various parameters of the OCP
-                                            // interface.
-#define MCSPI_O_SYSSTATUS       0x00000114  // 0x4402 1114 0x4402 2114 This
-                                            // register provides status
-                                            // information about the module
-                                            // excluding the interrupt status
-                                            // information
-#define MCSPI_O_IRQSTATUS       0x00000118  // 0x4402 1118 0x4402 2118 The
-                                            // interrupt status regroups all the
-                                            // status of the module internal
-                                            // events that can generate an
-                                            // interrupt
-#define MCSPI_O_IRQENABLE       0x0000011C  // 0x4402 111C 0x4402 211C This
-                                            // register allows to enable/disable
-                                            // the module internal sources of
-                                            // interrupt on an event-by-event
-                                            // basis.
-#define MCSPI_O_WAKEUPENABLE    0x00000120  // 0x4402 1120 0x4402 2120 The
-                                            // wakeup enable register allows to
-                                            // enable/disable the module
-                                            // internal sources of wakeup on
-                                            // event-by-event basis.
-#define MCSPI_O_SYST            0x00000124  // 0x4402 1124 0x4402 2124 This
-                                            // register is used to check the
-                                            // correctness of the system
-                                            // interconnect either internally to
-                                            // peripheral bus or externally to
-                                            // device IO pads when the module is
-                                            // configured in system test
-                                            // (SYSTEST) mode.
-#define MCSPI_O_MODULCTRL       0x00000128  // 0x4402 1128 0x4402 2128 This
-                                            // register is dedicated to the
-                                            // configuration of the serial port
-                                            // interface.
-#define MCSPI_O_CH0CONF         0x0000012C  // 0x4402 112C 0x4402 212C This
-                                            // register is dedicated to the
-                                            // configuration of the channel 0
-#define MCSPI_O_CH0STAT         0x00000130  // 0x4402 1130 0x4402 2130 This
-                                            // register provides status
-                                            // information about transmitter and
-                                            // receiver registers of channel 0
-#define MCSPI_O_CH0CTRL         0x00000134  // 0x4402 1134 0x4402 2134 This
-                                            // register is dedicated to enable
-                                            // the channel 0
-#define MCSPI_O_TX0             0x00000138  // 0x4402 1138 0x4402 2138 This
-                                            // register contains a single SPI
-                                            // word to transmit on the serial
-                                            // link what ever SPI word length
-                                            // is.
-#define MCSPI_O_RX0             0x0000013C  // 0x4402 113C 0x4402 213C This
-                                            // register contains a single SPI
-                                            // word received through the serial
-                                            // link what ever SPI word length
-                                            // is.
-#define MCSPI_O_CH1CONF         0x00000140  // 0x4402 1140 0x4402 2140 This
-                                            // register is dedicated to the
-                                            // configuration of the channel.
-#define MCSPI_O_CH1STAT         0x00000144  // 0x4402 1144 0x4402 2144 This
-                                            // register provides status
-                                            // information about transmitter and
-                                            // receiver registers of channel 1
-#define MCSPI_O_CH1CTRL         0x00000148  // 0x4402 1148 0x4402 2148 This
-                                            // register is dedicated to enable
-                                            // the channel 1
-#define MCSPI_O_TX1             0x0000014C  // 0x4402 114C 0x4402 214C This
-                                            // register contains a single SPI
-                                            // word to transmit on the serial
-                                            // link what ever SPI word length
-                                            // is.
-#define MCSPI_O_RX1             0x00000150  // 0x4402 1150 0x4402 2150 This
-                                            // register contains a single SPI
-                                            // word received through the serial
-                                            // link what ever SPI word length
-                                            // is.
-#define MCSPI_O_CH2CONF         0x00000154  // 0x4402 1154 0x4402 2154 This
-                                            // register is dedicated to the
-                                            // configuration of the channel 2
-#define MCSPI_O_CH2STAT         0x00000158  // 0x4402 1158 0x4402 2158 This
-                                            // register provides status
-                                            // information about transmitter and
-                                            // receiver registers of channel 2
-#define MCSPI_O_CH2CTRL         0x0000015C  // 0x4402 115C 0x4402 215C This
-                                            // register is dedicated to enable
-                                            // the channel 2
-#define MCSPI_O_TX2             0x00000160  // 0x4402 1160 0x4402 2160 This
-                                            // register contains a single SPI
-                                            // word to transmit on the serial
-                                            // link what ever SPI word length
-                                            // is.
-#define MCSPI_O_RX2             0x00000164  // 0x4402 1164 0x4402 2164 This
-                                            // register contains a single SPI
-                                            // word received through the serial
-                                            // link what ever SPI word length
-                                            // is.
-#define MCSPI_O_CH3CONF         0x00000168  // 0x4402 1168 0x4402 2168 This
-                                            // register is dedicated to the
-                                            // configuration of the channel 3
-#define MCSPI_O_CH3STAT         0x0000016C  // 0x4402 116C 0x4402 216C This
-                                            // register provides status
-                                            // information about transmitter and
-                                            // receiver registers of channel 3
-#define MCSPI_O_CH3CTRL         0x00000170  // 0x4402 1170 0x4402 2170 This
-                                            // register is dedicated to enable
-                                            // the channel 3
-#define MCSPI_O_TX3             0x00000174  // 0x4402 1174 0x4402 2174 This
-                                            // register contains a single SPI
-                                            // word to transmit on the serial
-                                            // link what ever SPI word length
-                                            // is.
-#define MCSPI_O_RX3             0x00000178  // 0x4402 1178 0x4402 2178 This
-                                            // register contains a single SPI
-                                            // word received through the serial
-                                            // link what ever SPI word length
-                                            // is.
-#define MCSPI_O_XFERLEVEL       0x0000017C  // 0x4402 117C 0x4402 217C This
-                                            // register provides transfer levels
-                                            // needed while using FIFO buffer
-                                            // during transfer.
-#define MCSPI_O_DAFTX           0x00000180  // 0x4402 1180 0x4402 2180 This
-                                            // register contains the SPI words
-                                            // to transmit on the serial link
-                                            // when FIFO used and DMA address is
-                                            // aligned on 256 bit.This register
-                                            // is an image of one of MCSPI_TX(i)
-                                            // register corresponding to the
-                                            // channel which have its FIFO
-                                            // enabled.
-#define MCSPI_O_DAFRX           0x000001A0  // 0x4402 11A0 0x4402 21A0 This
-                                            // register contains the SPI words
-                                            // to received on the serial link
-                                            // when FIFO used and DMA address is
-                                            // aligned on 256 bit.This register
-                                            // is an image of one of MCSPI_RX(i)
-                                            // register corresponding to the
-                                            // channel which have its FIFO
-                                            // enabled.
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_HL_REV register.
-//
-//******************************************************************************
-#define MCSPI_HL_REV_SCHEME_M   0xC0000000
-#define MCSPI_HL_REV_SCHEME_S   30
-#define MCSPI_HL_REV_RSVD_M     0x30000000  // Reserved These bits are
-                                            // initialized to zero and writes to
-                                            // them are ignored.
-#define MCSPI_HL_REV_RSVD_S     28
-#define MCSPI_HL_REV_FUNC_M     0x0FFF0000  // Function indicates a software
-                                            // compatible module family. If
-                                            // there is no level of software
-                                            // compatibility a new Func number
-                                            // (and hence REVISION) should be
-                                            // assigned.
-#define MCSPI_HL_REV_FUNC_S     16
-#define MCSPI_HL_REV_R_RTL_M    0x0000F800  // RTL Version (R) maintained by IP
-                                            // design owner. RTL follows a
-                                            // numbering such as X.Y.R.Z which
-                                            // are explained in this table. R
-                                            // changes ONLY when: (1) PDS
-                                            // uploads occur which may have been
-                                            // due to spec changes (2) Bug fixes
-                                            // occur (3) Resets to '0' when X or
-                                            // Y changes. Design team has an
-                                            // internal 'Z' (customer invisible)
-                                            // number which increments on every
-                                            // drop that happens due to DV and
-                                            // RTL updates. Z resets to 0 when R
-                                            // increments.
-#define MCSPI_HL_REV_R_RTL_S    11
-#define MCSPI_HL_REV_X_MAJOR_M  0x00000700  // Major Revision (X) maintained by
-                                            // IP specification owner. X changes
-                                            // ONLY when: (1) There is a major
-                                            // feature addition. An example
-                                            // would be adding Master Mode to
-                                            // Utopia Level2. The Func field (or
-                                            // Class/Type in old PID format)
-                                            // will remain the same. X does NOT
-                                            // change due to: (1) Bug fixes (2)
-                                            // Change in feature parameters.
-#define MCSPI_HL_REV_X_MAJOR_S  8
-#define MCSPI_HL_REV_CUSTOM_M   0x000000C0
-#define MCSPI_HL_REV_CUSTOM_S   6
-#define MCSPI_HL_REV_Y_MINOR_M  0x0000003F  // Minor Revision (Y) maintained by
-                                            // IP specification owner. Y changes
-                                            // ONLY when: (1) Features are
-                                            // scaled (up or down). Flexibility
-                                            // exists in that this feature
-                                            // scalability may either be
-                                            // represented in the Y change or a
-                                            // specific register in the IP that
-                                            // indicates which features are
-                                            // exactly available. (2) When
-                                            // feature creeps from Is-Not list
-                                            // to Is list. But this may not be
-                                            // the case once it sees silicon; in
-                                            // which case X will change. Y does
-                                            // NOT change due to: (1) Bug fixes
-                                            // (2) Typos or clarifications (3)
-                                            // major functional/feature
-                                            // change/addition/deletion. Instead
-                                            // these changes may be reflected
-                                            // via R S X as applicable. Spec
-                                            // owner maintains a
-                                            // customer-invisible number 'S'
-                                            // which changes due to: (1)
-                                            // Typos/clarifications (2) Bug
-                                            // documentation. Note that this bug
-                                            // is not due to a spec change but
-                                            // due to implementation.
-                                            // Nevertheless the spec tracks the
-                                            // IP bugs. An RTL release (say for
-                                            // silicon PG1.1) that occurs due to
-                                            // bug fix should document the
-                                            // corresponding spec number (X.Y.S)
-                                            // in its release notes.
-#define MCSPI_HL_REV_Y_MINOR_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_HL_HWINFO register.
-//
-//******************************************************************************
-#define MCSPI_HL_HWINFO_RETMODE 0x00000040
-#define MCSPI_HL_HWINFO_FFNBYTE_M \
-                                0x0000003E
-
-#define MCSPI_HL_HWINFO_FFNBYTE_S 1
-#define MCSPI_HL_HWINFO_USEFIFO 0x00000001
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// MCSPI_O_HL_SYSCONFIG register.
-//
-//******************************************************************************
-#define MCSPI_HL_SYSCONFIG_IDLEMODE_M \
-                                0x0000000C  // Configuration of the local
-                                            // target state management mode. By
-                                            // definition target can handle
-                                            // read/write transaction as long as
-                                            // it is out of IDLE state. 0x0
-                                            // Force-idle mode: local target's
-                                            // idle state follows (acknowledges)
-                                            // the system's idle requests
-                                            // unconditionally i.e. regardless
-                                            // of the IP module's internal
-                                            // requirements.Backup mode for
-                                            // debug only. 0x1 No-idle mode:
-                                            // local target never enters idle
-                                            // state.Backup mode for debug only.
-                                            // 0x2 Smart-idle mode: local
-                                            // target's idle state eventually
-                                            // follows (acknowledges) the
-                                            // system's idle requests depending
-                                            // on the IP module's internal
-                                            // requirements.IP module shall not
-                                            // generate (IRQ- or
-                                            // DMA-request-related) wakeup
-                                            // events. 0x3 "Smart-idle
-                                            // wakeup-capable mode: local
-                                            // target's idle state eventually
-                                            // follows (acknowledges) the
-                                            // system's idle requests depending
-                                            // on the IP module's internal
-                                            // requirements.IP module may
-                                            // generate (IRQ- or
-                                            // DMA-request-related) wakeup
-                                            // events when in idle state.Mode is
-                                            // only relevant if the appropriate
-                                            // IP module ""swakeup"" output(s)
-                                            // is (are) implemented."
-
-#define MCSPI_HL_SYSCONFIG_IDLEMODE_S 2
-#define MCSPI_HL_SYSCONFIG_FREEEMU \
-                                0x00000002  // Sensitivity to emulation (debug)
-                                            // suspend input signal. 0 IP module
-                                            // is sensitive to emulation suspend
-                                            // 1 IP module is not sensitive to
-                                            // emulation suspend
-
-#define MCSPI_HL_SYSCONFIG_SOFTRESET \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_REVISION register.
-//
-//******************************************************************************
-#define MCSPI_REVISION_REV_M    0x000000FF  // IP revision [7:4] Major revision
-                                            // [3:0] Minor revision Examples:
-                                            // 0x10 for 1.0 0x21 for 2.1
-#define MCSPI_REVISION_REV_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_SYSCONFIG register.
-//
-//******************************************************************************
-#define MCSPI_SYSCONFIG_CLOCKACTIVITY_M \
-                                0x00000300  // Clocks activity during wake up
-                                            // mode period 0x0 OCP and
-                                            // Functional clocks may be switched
-                                            // off. 0x1 OCP clock is maintained.
-                                            // Functional clock may be
-                                            // switched-off. 0x2 Functional
-                                            // clock is maintained. OCP clock
-                                            // may be switched-off. 0x3 OCP and
-                                            // Functional clocks are maintained.
-
-#define MCSPI_SYSCONFIG_CLOCKACTIVITY_S 8
-#define MCSPI_SYSCONFIG_SIDLEMODE_M \
-                                0x00000018  // Power management 0x0 If an idle
-                                            // request is detected the McSPI
-                                            // acknowledges it unconditionally
-                                            // and goes in Inactive mode.
-                                            // Interrupt DMA requests and wake
-                                            // up lines are unconditionally
-                                            // de-asserted and the module wakeup
-                                            // capability is deactivated even if
-                                            // the bit
-                                            // MCSPI_SYSCONFIG[EnaWakeUp] is
-                                            // set. 0x1 If an idle request is
-                                            // detected the request is ignored
-                                            // and the module does not switch to
-                                            // wake up mode and keeps on
-                                            // behaving normally. 0x2 If an idle
-                                            // request is detected the module
-                                            // will switch to idle mode based on
-                                            // its internal activity. The wake
-                                            // up capability cannot be used. 0x3
-                                            // If an idle request is detected
-                                            // the module will switch to idle
-                                            // mode based on its internal
-                                            // activity and the wake up
-                                            // capability can be used if the bit
-                                            // MCSPI_SYSCONFIG[EnaWakeUp] is
-                                            // set.
-
-#define MCSPI_SYSCONFIG_SIDLEMODE_S 3
-#define MCSPI_SYSCONFIG_ENAWAKEUP \
-                                0x00000004  // WakeUp feature control 0 WakeUp
-                                            // capability is disabled 1 WakeUp
-                                            // capability is enabled
-
-#define MCSPI_SYSCONFIG_SOFTRESET \
-                                0x00000002  // Software reset. During reads it
-                                            // always returns 0. 0 (write)
-                                            // Normal mode 1 (write) Set this
-                                            // bit to 1 to trigger a module
-                                            // reset.The bit is automatically
-                                            // reset by the hardware.
-
-#define MCSPI_SYSCONFIG_AUTOIDLE \
-                                0x00000001  // Internal OCP Clock gating
-                                            // strategy 0 OCP clock is
-                                            // free-running 1 Automatic OCP
-                                            // clock gating strategy is applied
-                                            // based on the OCP interface
-                                            // activity
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_SYSSTATUS register.
-//
-//******************************************************************************
-#define MCSPI_SYSSTATUS_RESETDONE \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_IRQSTATUS register.
-//
-//******************************************************************************
-#define MCSPI_IRQSTATUS_EOW     0x00020000
-#define MCSPI_IRQSTATUS_WKS     0x00010000
-#define MCSPI_IRQSTATUS_RX3_FULL \
-                                0x00004000
-
-#define MCSPI_IRQSTATUS_TX3_UNDERFLOW \
-                                0x00002000
-
-#define MCSPI_IRQSTATUS_TX3_EMPTY \
-                                0x00001000
-
-#define MCSPI_IRQSTATUS_RX2_FULL \
-                                0x00000400
-
-#define MCSPI_IRQSTATUS_TX2_UNDERFLOW \
-                                0x00000200
-
-#define MCSPI_IRQSTATUS_TX2_EMPTY \
-                                0x00000100
-
-#define MCSPI_IRQSTATUS_RX1_FULL \
-                                0x00000040
-
-#define MCSPI_IRQSTATUS_TX1_UNDERFLOW \
-                                0x00000020
-
-#define MCSPI_IRQSTATUS_TX1_EMPTY \
-                                0x00000010
-
-#define MCSPI_IRQSTATUS_RX0_OVERFLOW \
-                                0x00000008
-
-#define MCSPI_IRQSTATUS_RX0_FULL \
-                                0x00000004
-
-#define MCSPI_IRQSTATUS_TX0_UNDERFLOW \
-                                0x00000002
-
-#define MCSPI_IRQSTATUS_TX0_EMPTY \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_IRQENABLE register.
-//
-//******************************************************************************
-#define MCSPI_IRQENABLE_EOW_ENABLE \
-                                0x00020000  // End of Word count Interrupt
-                                            // Enable. 0 Interrupt disabled 1
-                                            // Interrupt enabled
-
-#define MCSPI_IRQENABLE_WKE     0x00010000  // Wake Up event interrupt Enable
-                                            // in slave mode when an active
-                                            // control signal is detected on the
-                                            // SPIEN line programmed in the
-                                            // field MCSPI_CH0CONF[SPIENSLV] 0
-                                            // Interrupt disabled 1 Interrupt
-                                            // enabled
-#define MCSPI_IRQENABLE_RX3_FULL_ENABLE \
-                                0x00004000  // Receiver register Full Interrupt
-                                            // Enable. Ch 3 0 Interrupt disabled
-                                            // 1 Interrupt enabled
-
-#define MCSPI_IRQENABLE_TX3_UNDERFLOW_ENABLE \
-                                0x00002000  // Transmitter register Underflow
-                                            // Interrupt Enable. Ch 3 0
-                                            // Interrupt disabled 1 Interrupt
-                                            // enabled
-
-#define MCSPI_IRQENABLE_TX3_EMPTY_ENABLE \
-                                0x00001000  // Transmitter register Empty
-                                            // Interrupt Enable. Ch3 0 Interrupt
-                                            // disabled 1 Interrupt enabled
-
-#define MCSPI_IRQENABLE_RX2_FULL_ENABLE \
-                                0x00000400  // Receiver register Full Interrupt
-                                            // Enable. Ch 2 0 Interrupt disabled
-                                            // 1 Interrupt enabled
-
-#define MCSPI_IRQENABLE_TX2_UNDERFLOW_ENABLE \
-                                0x00000200  // Transmitter register Underflow
-                                            // Interrupt Enable. Ch 2 0
-                                            // Interrupt disabled 1 Interrupt
-                                            // enabled
-
-#define MCSPI_IRQENABLE_TX2_EMPTY_ENABLE \
-                                0x00000100  // Transmitter register Empty
-                                            // Interrupt Enable. Ch 2 0
-                                            // Interrupt disabled 1 Interrupt
-                                            // enabled
-
-#define MCSPI_IRQENABLE_RX1_FULL_ENABLE \
-                                0x00000040  // Receiver register Full Interrupt
-                                            // Enable. Ch 1 0 Interrupt disabled
-                                            // 1 Interrupt enabled
-
-#define MCSPI_IRQENABLE_TX1_UNDERFLOW_ENABLE \
-                                0x00000020  // Transmitter register Underflow
-                                            // Interrupt Enable. Ch 1 0
-                                            // Interrupt disabled 1 Interrupt
-                                            // enabled
-
-#define MCSPI_IRQENABLE_TX1_EMPTY_ENABLE \
-                                0x00000010  // Transmitter register Empty
-                                            // Interrupt Enable. Ch 1 0
-                                            // Interrupt disabled 1 Interrupt
-                                            // enabled
-
-#define MCSPI_IRQENABLE_RX0_OVERFLOW_ENABLE \
-                                0x00000008  // Receiver register Overflow
-                                            // Interrupt Enable. Ch 0 0
-                                            // Interrupt disabled 1 Interrupt
-                                            // enabled
-
-#define MCSPI_IRQENABLE_RX0_FULL_ENABLE \
-                                0x00000004  // Receiver register Full Interrupt
-                                            // Enable. Ch 0 0 Interrupt disabled
-                                            // 1 Interrupt enabled
-
-#define MCSPI_IRQENABLE_TX0_UNDERFLOW_ENABLE \
-                                0x00000002  // Transmitter register Underflow
-                                            // Interrupt Enable. Ch 0 0
-                                            // Interrupt disabled 1 Interrupt
-                                            // enabled
-
-#define MCSPI_IRQENABLE_TX0_EMPTY_ENABLE \
-                                0x00000001  // Transmitter register Empty
-                                            // Interrupt Enable. Ch 0 0
-                                            // Interrupt disabled 1 Interrupt
-                                            // enabled
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// MCSPI_O_WAKEUPENABLE register.
-//
-//******************************************************************************
-#define MCSPI_WAKEUPENABLE_WKEN 0x00000001  // WakeUp functionality in slave
-                                            // mode when an active control
-                                            // signal is detected on the SPIEN
-                                            // line programmed in the field
-                                            // MCSPI_CH0CONF[SPIENSLV] 0 The
-                                            // event is not allowed to wakeup
-                                            // the system even if the global
-                                            // control bit
-                                            // MCSPI_SYSCONF[EnaWakeUp] is set.
-                                            // 1 The event is allowed to wakeup
-                                            // the system if the global control
-                                            // bit MCSPI_SYSCONF[EnaWakeUp] is
-                                            // set.
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_SYST register.
-//
-//******************************************************************************
-#define MCSPI_SYST_SSB          0x00000800  // Set status bit 0 No action.
-                                            // Writing 0 does not clear already
-                                            // set status bits; This bit must be
-                                            // cleared prior attempting to clear
-                                            // a status bit of the
-                                            // <MCSPI_IRQSTATUS> register. 1
-                                            // Force to 1 all status bits of
-                                            // MCSPI_IRQSTATUS register. Writing
-                                            // 1 into this bit sets to 1 all
-                                            // status bits contained in the
-                                            // <MCSPI_IRQSTATUS> register.
-#define MCSPI_SYST_SPIENDIR     0x00000400  // Set the direction of the
-                                            // SPIEN[3:0] lines and SPICLK line
-                                            // 0 output (as in master mode) 1
-                                            // input (as in slave mode)
-#define MCSPI_SYST_SPIDATDIR1   0x00000200  // Set the direction of the
-                                            // SPIDAT[1] 0 output 1 input
-#define MCSPI_SYST_SPIDATDIR0   0x00000100  // Set the direction of the
-                                            // SPIDAT[0] 0 output 1 input
-#define MCSPI_SYST_WAKD         0x00000080  // SWAKEUP output (signal data
-                                            // value of internal signal to
-                                            // system). The signal is driven
-                                            // high or low according to the
-                                            // value written into this register
-                                            // bit. 0 The pin is driven low. 1
-                                            // The pin is driven high.
-#define MCSPI_SYST_SPICLK       0x00000040  // SPICLK line (signal data value)
-                                            // If MCSPI_SYST[SPIENDIR] = 1
-                                            // (input mode direction) this bit
-                                            // returns the value on the CLKSPI
-                                            // line (high or low) and a write
-                                            // into this bit has no effect. If
-                                            // MCSPI_SYST[SPIENDIR] = 0 (output
-                                            // mode direction) the CLKSPI line
-                                            // is driven high or low according
-                                            // to the value written into this
-                                            // register.
-#define MCSPI_SYST_SPIDAT_1     0x00000020  // SPIDAT[1] line (signal data
-                                            // value) If MCSPI_SYST[SPIDATDIR1]
-                                            // = 0 (output mode direction) the
-                                            // SPIDAT[1] line is driven high or
-                                            // low according to the value
-                                            // written into this register. If
-                                            // MCSPI_SYST[SPIDATDIR1] = 1 (input
-                                            // mode direction) this bit returns
-                                            // the value on the SPIDAT[1] line
-                                            // (high or low) and a write into
-                                            // this bit has no effect.
-#define MCSPI_SYST_SPIDAT_0     0x00000010  // SPIDAT[0] line (signal data
-                                            // value) If MCSPI_SYST[SPIDATDIR0]
-                                            // = 0 (output mode direction) the
-                                            // SPIDAT[0] line is driven high or
-                                            // low according to the value
-                                            // written into this register. If
-                                            // MCSPI_SYST[SPIDATDIR0] = 1 (input
-                                            // mode direction) this bit returns
-                                            // the value on the SPIDAT[0] line
-                                            // (high or low) and a write into
-                                            // this bit has no effect.
-#define MCSPI_SYST_SPIEN_3      0x00000008  // SPIEN[3] line (signal data
-                                            // value) If MCSPI_SYST[SPIENDIR] =
-                                            // 0 (output mode direction) the
-                                            // SPIENT[3] line is driven high or
-                                            // low according to the value
-                                            // written into this register. If
-                                            // MCSPI_SYST[SPIENDIR] = 1 (input
-                                            // mode direction) this bit returns
-                                            // the value on the SPIEN[3] line
-                                            // (high or low) and a write into
-                                            // this bit has no effect.
-#define MCSPI_SYST_SPIEN_2      0x00000004  // SPIEN[2] line (signal data
-                                            // value) If MCSPI_SYST[SPIENDIR] =
-                                            // 0 (output mode direction) the
-                                            // SPIENT[2] line is driven high or
-                                            // low according to the value
-                                            // written into this register. If
-                                            // MCSPI_SYST[SPIENDIR] = 1 (input
-                                            // mode direction) this bit returns
-                                            // the value on the SPIEN[2] line
-                                            // (high or low) and a write into
-                                            // this bit has no effect.
-#define MCSPI_SYST_SPIEN_1      0x00000002  // SPIEN[1] line (signal data
-                                            // value) If MCSPI_SYST[SPIENDIR] =
-                                            // 0 (output mode direction) the
-                                            // SPIENT[1] line is driven high or
-                                            // low according to the value
-                                            // written into this register. If
-                                            // MCSPI_SYST[SPIENDIR] = 1 (input
-                                            // mode direction) this bit returns
-                                            // the value on the SPIEN[1] line
-                                            // (high or low) and a write into
-                                            // this bit has no effect.
-#define MCSPI_SYST_SPIEN_0      0x00000001  // SPIEN[0] line (signal data
-                                            // value) If MCSPI_SYST[SPIENDIR] =
-                                            // 0 (output mode direction) the
-                                            // SPIENT[0] line is driven high or
-                                            // low according to the value
-                                            // written into this register. If
-                                            // MCSPI_SYST[SPIENDIR] = 1 (input
-                                            // mode direction) this bit returns
-                                            // the value on the SPIEN[0] line
-                                            // (high or low) and a write into
-                                            // this bit has no effect.
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_MODULCTRL register.
-//
-//******************************************************************************
-#define MCSPI_MODULCTRL_FDAA    0x00000100  // FIFO DMA Address 256-bit aligned
-                                            // This register is used when a FIFO
-                                            // is managed by the module and DMA
-                                            // connected to the controller
-                                            // provides only 256 bit aligned
-                                            // address. If this bit is set the
-                                            // enabled channel which uses the
-                                            // FIFO has its datas managed
-                                            // through MCSPI_DAFTX and
-                                            // MCSPI_DAFRX registers instead of
-                                            // MCSPI_TX(i) and MCSPI_RX(i)
-                                            // registers. 0 FIFO data managed by
-                                            // MCSPI_TX(i) and MCSPI_RX(i)
-                                            // registers. 1 FIFO data managed by
-                                            // MCSPI_DAFTX and MCSPI_DAFRX
-                                            // registers.
-#define MCSPI_MODULCTRL_MOA     0x00000080  // Multiple word ocp access: This
-                                            // register can only be used when a
-                                            // channel is enabled using a FIFO.
-                                            // It allows the system to perform
-                                            // multiple SPI word access for a
-                                            // single 32-bit OCP word access.
-                                            // This is possible for WL < 16. 0
-                                            // Multiple word access disabled 1
-                                            // Multiple word access enabled with
-                                            // FIFO
-#define MCSPI_MODULCTRL_INITDLY_M \
-                                0x00000070  // Initial spi delay for first
-                                            // transfer: This register is an
-                                            // option only available in SINGLE
-                                            // master mode The controller waits
-                                            // for a delay to transmit the first
-                                            // spi word after channel enabled
-                                            // and corresponding TX register
-                                            // filled. This Delay is based on
-                                            // SPI output frequency clock No
-                                            // clock output provided to the
-                                            // boundary and chip select is not
-                                            // active in 4 pin mode within this
-                                            // period. 0x0 No delay for first
-                                            // spi transfer. 0x1 The controller
-                                            // wait 4 spi bus clock 0x2 The
-                                            // controller wait 8 spi bus clock
-                                            // 0x3 The controller wait 16 spi
-                                            // bus clock 0x4 The controller wait
-                                            // 32 spi bus clock
-
-#define MCSPI_MODULCTRL_INITDLY_S 4
-#define MCSPI_MODULCTRL_SYSTEM_TEST \
-                                0x00000008  // Enables the system test mode 0
-                                            // Functional mode 1 System test
-                                            // mode (SYSTEST)
-
-#define MCSPI_MODULCTRL_MS      0x00000004  // Master/ Slave 0 Master - The
-                                            // module generates the SPICLK and
-                                            // SPIEN[3:0] 1 Slave - The module
-                                            // receives the SPICLK and
-                                            // SPIEN[3:0]
-#define MCSPI_MODULCTRL_PIN34   0x00000002  // Pin mode selection: This
-                                            // register is used to configure the
-                                            // SPI pin mode in master or slave
-                                            // mode. If asserted the controller
-                                            // only use SIMOSOMI and SPICLK
-                                            // clock pin for spi transfers. 0
-                                            // SPIEN is used as a chip select. 1
-                                            // SPIEN is not used.In this mode
-                                            // all related option to chip select
-                                            // have no meaning.
-#define MCSPI_MODULCTRL_SINGLE  0x00000001  // Single channel / Multi Channel
-                                            // (master mode only) 0 More than
-                                            // one channel will be used in
-                                            // master mode. 1 Only one channel
-                                            // will be used in master mode. This
-                                            // bit must be set in Force SPIEN
-                                            // mode.
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_CH0CONF register.
-//
-//******************************************************************************
-#define MCSPI_CH0CONF_CLKG      0x20000000  // Clock divider granularity This
-                                            // register defines the granularity
-                                            // of channel clock divider: power
-                                            // of two or one clock cycle
-                                            // granularity. When this bit is set
-                                            // the register MCSPI_CHCTRL[EXTCLK]
-                                            // must be configured to reach a
-                                            // maximum of 4096 clock divider
-                                            // ratio. Then The clock divider
-                                            // ratio is a concatenation of
-                                            // MCSPI_CHCONF[CLKD] and
-                                            // MCSPI_CHCTRL[EXTCLK] values 0
-                                            // Clock granularity of power of two
-                                            // 1 One clock cycle ganularity
-#define MCSPI_CH0CONF_FFER      0x10000000  // FIFO enabled for receive:Only
-                                            // one channel can have this bit
-                                            // field set. 0 The buffer is not
-                                            // used to receive data. 1 The
-                                            // buffer is used to receive data.
-#define MCSPI_CH0CONF_FFEW      0x08000000  // FIFO enabled for Transmit:Only
-                                            // one channel can have this bit
-                                            // field set. 0 The buffer is not
-                                            // used to transmit data. 1 The
-                                            // buffer is used to transmit data.
-#define MCSPI_CH0CONF_TCS0_M    0x06000000  // Chip Select Time Control This
-                                            // 2-bits field defines the number
-                                            // of interface clock cycles between
-                                            // CS toggling and first or last
-                                            // edge of SPI clock. 0x0 0.5 clock
-                                            // cycle 0x1 1.5 clock cycle 0x2 2.5
-                                            // clock cycle 0x3 3.5 clock cycle
-#define MCSPI_CH0CONF_TCS0_S    25
-#define MCSPI_CH0CONF_SBPOL     0x01000000  // Start bit polarity 0 Start bit
-                                            // polarity is held to 0 during SPI
-                                            // transfer. 1 Start bit polarity is
-                                            // held to 1 during SPI transfer.
-#define MCSPI_CH0CONF_SBE       0x00800000  // Start bit enable for SPI
-                                            // transfer 0 Default SPI transfer
-                                            // length as specified by WL bit
-                                            // field 1 Start bit D/CX added
-                                            // before SPI transfer polarity is
-                                            // defined by MCSPI_CH0CONF[SBPOL]
-#define MCSPI_CH0CONF_SPIENSLV_M \
-                                0x00600000  // Channel 0 only and slave mode
-                                            // only: SPI slave select signal
-                                            // detection. Reserved bits for
-                                            // other cases. 0x0 Detection
-                                            // enabled only on SPIEN[0] 0x1
-                                            // Detection enabled only on
-                                            // SPIEN[1] 0x2 Detection enabled
-                                            // only on SPIEN[2] 0x3 Detection
-                                            // enabled only on SPIEN[3]
-
-#define MCSPI_CH0CONF_SPIENSLV_S 21
-#define MCSPI_CH0CONF_FORCE     0x00100000  // Manual SPIEN assertion to keep
-                                            // SPIEN active between SPI words.
-                                            // (single channel master mode only)
-                                            // 0 Writing 0 into this bit drives
-                                            // low the SPIEN line when
-                                            // MCSPI_CHCONF(i)[EPOL]=0 and
-                                            // drives it high when
-                                            // MCSPI_CHCONF(i)[EPOL]=1. 1
-                                            // Writing 1 into this bit drives
-                                            // high the SPIEN line when
-                                            // MCSPI_CHCONF(i)[EPOL]=0 and
-                                            // drives it low when
-                                            // MCSPI_CHCONF(i)[EPOL]=1
-#define MCSPI_CH0CONF_TURBO     0x00080000  // Turbo mode 0 Turbo is
-                                            // deactivated (recommended for
-                                            // single SPI word transfer) 1 Turbo
-                                            // is activated to maximize the
-                                            // throughput for multi SPI words
-                                            // transfer.
-#define MCSPI_CH0CONF_IS        0x00040000  // Input Select 0 Data Line0
-                                            // (SPIDAT[0]) selected for
-                                            // reception. 1 Data Line1
-                                            // (SPIDAT[1]) selected for
-                                            // reception
-#define MCSPI_CH0CONF_DPE1      0x00020000  // Transmission Enable for data
-                                            // line 1 (SPIDATAGZEN[1]) 0 Data
-                                            // Line1 (SPIDAT[1]) selected for
-                                            // transmission 1 No transmission on
-                                            // Data Line1 (SPIDAT[1])
-#define MCSPI_CH0CONF_DPE0      0x00010000  // Transmission Enable for data
-                                            // line 0 (SPIDATAGZEN[0]) 0 Data
-                                            // Line0 (SPIDAT[0]) selected for
-                                            // transmission 1 No transmission on
-                                            // Data Line0 (SPIDAT[0])
-#define MCSPI_CH0CONF_DMAR      0x00008000  // DMA Read request The DMA Read
-                                            // request line is asserted when the
-                                            // channel is enabled and a new data
-                                            // is available in the receive
-                                            // register of the channel. The DMA
-                                            // Read request line is deasserted
-                                            // on read completion of the receive
-                                            // register of the channel. 0 DMA
-                                            // Read Request disabled 1 DMA Read
-                                            // Request enabled
-#define MCSPI_CH0CONF_DMAW      0x00004000  // DMA Write request. The DMA Write
-                                            // request line is asserted when The
-                                            // channel is enabled and the
-                                            // transmitter register of the
-                                            // channel is empty. The DMA Write
-                                            // request line is deasserted on
-                                            // load completion of the
-                                            // transmitter register of the
-                                            // channel. 0 DMA Write Request
-                                            // disabled 1 DMA Write Request
-                                            // enabled
-#define MCSPI_CH0CONF_TRM_M     0x00003000  // Transmit/Receive modes 0x0
-                                            // Transmit and Receive mode 0x1
-                                            // Receive only mode 0x2 Transmit
-                                            // only mode 0x3 Reserved
-#define MCSPI_CH0CONF_TRM_S     12
-#define MCSPI_CH0CONF_WL_M      0x00000F80  // SPI word length 0x00 Reserved
-                                            // 0x01 Reserved 0x02 Reserved 0x03
-                                            // The SPI word is 4-bits long 0x04
-                                            // The SPI word is 5-bits long 0x05
-                                            // The SPI word is 6-bits long 0x06
-                                            // The SPI word is 7-bits long 0x07
-                                            // The SPI word is 8-bits long 0x08
-                                            // The SPI word is 9-bits long 0x09
-                                            // The SPI word is 10-bits long 0x0A
-                                            // The SPI word is 11-bits long 0x0B
-                                            // The SPI word is 12-bits long 0x0C
-                                            // The SPI word is 13-bits long 0x0D
-                                            // The SPI word is 14-bits long 0x0E
-                                            // The SPI word is 15-bits long 0x0F
-                                            // The SPI word is 16-bits long 0x10
-                                            // The SPI word is 17-bits long 0x11
-                                            // The SPI word is 18-bits long 0x12
-                                            // The SPI word is 19-bits long 0x13
-                                            // The SPI word is 20-bits long 0x14
-                                            // The SPI word is 21-bits long 0x15
-                                            // The SPI word is 22-bits long 0x16
-                                            // The SPI word is 23-bits long 0x17
-                                            // The SPI word is 24-bits long 0x18
-                                            // The SPI word is 25-bits long 0x19
-                                            // The SPI word is 26-bits long 0x1A
-                                            // The SPI word is 27-bits long 0x1B
-                                            // The SPI word is 28-bits long 0x1C
-                                            // The SPI word is 29-bits long 0x1D
-                                            // The SPI word is 30-bits long 0x1E
-                                            // The SPI word is 31-bits long 0x1F
-                                            // The SPI word is 32-bits long
-#define MCSPI_CH0CONF_WL_S      7
-#define MCSPI_CH0CONF_EPOL      0x00000040  // SPIEN polarity 0 SPIEN is held
-                                            // high during the active state. 1
-                                            // SPIEN is held low during the
-                                            // active state.
-#define MCSPI_CH0CONF_CLKD_M    0x0000003C  // Frequency divider for SPICLK.
-                                            // (only when the module is a Master
-                                            // SPI device). A programmable clock
-                                            // divider divides the SPI reference
-                                            // clock (CLKSPIREF) with a 4-bit
-                                            // value and results in a new clock
-                                            // SPICLK available to shift-in and
-                                            // shift-out data. By default the
-                                            // clock divider ratio has a power
-                                            // of two granularity when
-                                            // MCSPI_CHCONF[CLKG] is cleared
-                                            // Otherwise this register is the 4
-                                            // LSB bit of a 12-bit register
-                                            // concatenated with clock divider
-                                            // extension MCSPI_CHCTRL[EXTCLK]
-                                            // register.The value description
-                                            // below defines the clock ratio
-                                            // when MCSPI_CHCONF[CLKG] is set to
-                                            // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16
-                                            // 0x5 32 0x6 64 0x7 128 0x8 256 0x9
-                                            // 512 0xA 1024 0xB 2048 0xC 4096
-                                            // 0xD 8192 0xE 16384 0xF 32768
-#define MCSPI_CH0CONF_CLKD_S    2
-#define MCSPI_CH0CONF_POL       0x00000002  // SPICLK polarity 0 SPICLK is held
-                                            // high during the active state 1
-                                            // SPICLK is held low during the
-                                            // active state
-#define MCSPI_CH0CONF_PHA       0x00000001  // SPICLK phase 0 Data are latched
-                                            // on odd numbered edges of SPICLK.
-                                            // 1 Data are latched on even
-                                            // numbered edges of SPICLK.
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_CH0STAT register.
-//
-//******************************************************************************
-#define MCSPI_CH0STAT_RXFFF     0x00000040
-#define MCSPI_CH0STAT_RXFFE     0x00000020
-#define MCSPI_CH0STAT_TXFFF     0x00000010
-#define MCSPI_CH0STAT_TXFFE     0x00000008
-#define MCSPI_CH0STAT_EOT       0x00000004
-#define MCSPI_CH0STAT_TXS       0x00000002
-#define MCSPI_CH0STAT_RXS       0x00000001
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_CH0CTRL register.
-//
-//******************************************************************************
-#define MCSPI_CH0CTRL_EXTCLK_M  0x0000FF00  // Clock ratio extension: This
-                                            // register is used to concatenate
-                                            // with MCSPI_CHCONF[CLKD] register
-                                            // for clock ratio only when
-                                            // granularity is one clock cycle
-                                            // (MCSPI_CHCONF[CLKG] set to 1).
-                                            // Then the max value reached is
-                                            // 4096 clock divider ratio. 0x00
-                                            // Clock ratio is CLKD + 1 0x01
-                                            // Clock ratio is CLKD + 1 + 16 0xFF
-                                            // Clock ratio is CLKD + 1 + 4080
-#define MCSPI_CH0CTRL_EXTCLK_S  8
-#define MCSPI_CH0CTRL_EN        0x00000001  // Channel Enable 0 "Channel ""i""
-                                            // is not active" 1 "Channel ""i""
-                                            // is active"
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_TX0 register.
-//
-//******************************************************************************
-#define MCSPI_TX0_TDATA_M       0xFFFFFFFF  // Channel 0 Data to transmit
-#define MCSPI_TX0_TDATA_S       0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_RX0 register.
-//
-//******************************************************************************
-#define MCSPI_RX0_RDATA_M       0xFFFFFFFF  // Channel 0 Received Data
-#define MCSPI_RX0_RDATA_S       0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_CH1CONF register.
-//
-//******************************************************************************
-#define MCSPI_CH1CONF_CLKG      0x20000000  // Clock divider granularity This
-                                            // register defines the granularity
-                                            // of channel clock divider: power
-                                            // of two or one clock cycle
-                                            // granularity. When this bit is set
-                                            // the register MCSPI_CHCTRL[EXTCLK]
-                                            // must be configured to reach a
-                                            // maximum of 4096 clock divider
-                                            // ratio. Then The clock divider
-                                            // ratio is a concatenation of
-                                            // MCSPI_CHCONF[CLKD] and
-                                            // MCSPI_CHCTRL[EXTCLK] values 0
-                                            // Clock granularity of power of two
-                                            // 1 One clock cycle ganularity
-#define MCSPI_CH1CONF_FFER      0x10000000  // FIFO enabled for receive:Only
-                                            // one channel can have this bit
-                                            // field set. 0 The buffer is not
-                                            // used to receive data. 1 The
-                                            // buffer is used to receive data.
-#define MCSPI_CH1CONF_FFEW      0x08000000  // FIFO enabled for Transmit:Only
-                                            // one channel can have this bit
-                                            // field set. 0 The buffer is not
-                                            // used to transmit data. 1 The
-                                            // buffer is used to transmit data.
-#define MCSPI_CH1CONF_TCS1_M    0x06000000  // Chip Select Time Control This
-                                            // 2-bits field defines the number
-                                            // of interface clock cycles between
-                                            // CS toggling and first or last
-                                            // edge of SPI clock. 0x0 0.5 clock
-                                            // cycle 0x1 1.5 clock cycle 0x2 2.5
-                                            // clock cycle 0x3 3.5 clock cycle
-#define MCSPI_CH1CONF_TCS1_S    25
-#define MCSPI_CH1CONF_SBPOL     0x01000000  // Start bit polarity 0 Start bit
-                                            // polarity is held to 0 during SPI
-                                            // transfer. 1 Start bit polarity is
-                                            // held to 1 during SPI transfer.
-#define MCSPI_CH1CONF_SBE       0x00800000  // Start bit enable for SPI
-                                            // transfer 0 Default SPI transfer
-                                            // length as specified by WL bit
-                                            // field 1 Start bit D/CX added
-                                            // before SPI transfer polarity is
-                                            // defined by MCSPI_CH1CONF[SBPOL]
-#define MCSPI_CH1CONF_FORCE     0x00100000  // Manual SPIEN assertion to keep
-                                            // SPIEN active between SPI words.
-                                            // (single channel master mode only)
-                                            // 0 Writing 0 into this bit drives
-                                            // low the SPIEN line when
-                                            // MCSPI_CHCONF(i)[EPOL]=0 and
-                                            // drives it high when
-                                            // MCSPI_CHCONF(i)[EPOL]=1. 1
-                                            // Writing 1 into this bit drives
-                                            // high the SPIEN line when
-                                            // MCSPI_CHCONF(i)[EPOL]=0 and
-                                            // drives it low when
-                                            // MCSPI_CHCONF(i)[EPOL]=1
-#define MCSPI_CH1CONF_TURBO     0x00080000  // Turbo mode 0 Turbo is
-                                            // deactivated (recommended for
-                                            // single SPI word transfer) 1 Turbo
-                                            // is activated to maximize the
-                                            // throughput for multi SPI words
-                                            // transfer.
-#define MCSPI_CH1CONF_IS        0x00040000  // Input Select 0 Data Line0
-                                            // (SPIDAT[0]) selected for
-                                            // reception. 1 Data Line1
-                                            // (SPIDAT[1]) selected for
-                                            // reception
-#define MCSPI_CH1CONF_DPE1      0x00020000  // Transmission Enable for data
-                                            // line 1 (SPIDATAGZEN[1]) 0 Data
-                                            // Line1 (SPIDAT[1]) selected for
-                                            // transmission 1 No transmission on
-                                            // Data Line1 (SPIDAT[1])
-#define MCSPI_CH1CONF_DPE0      0x00010000  // Transmission Enable for data
-                                            // line 0 (SPIDATAGZEN[0]) 0 Data
-                                            // Line0 (SPIDAT[0]) selected for
-                                            // transmission 1 No transmission on
-                                            // Data Line0 (SPIDAT[0])
-#define MCSPI_CH1CONF_DMAR      0x00008000  // DMA Read request The DMA Read
-                                            // request line is asserted when the
-                                            // channel is enabled and a new data
-                                            // is available in the receive
-                                            // register of the channel. The DMA
-                                            // Read request line is deasserted
-                                            // on read completion of the receive
-                                            // register of the channel. 0 DMA
-                                            // Read Request disabled 1 DMA Read
-                                            // Request enabled
-#define MCSPI_CH1CONF_DMAW      0x00004000  // DMA Write request. The DMA Write
-                                            // request line is asserted when The
-                                            // channel is enabled and the
-                                            // transmitter register of the
-                                            // channel is empty. The DMA Write
-                                            // request line is deasserted on
-                                            // load completion of the
-                                            // transmitter register of the
-                                            // channel. 0 DMA Write Request
-                                            // disabled 1 DMA Write Request
-                                            // enabled
-#define MCSPI_CH1CONF_TRM_M     0x00003000  // Transmit/Receive modes 0x0
-                                            // Transmit and Receive mode 0x1
-                                            // Receive only mode 0x2 Transmit
-                                            // only mode 0x3 Reserved
-#define MCSPI_CH1CONF_TRM_S     12
-#define MCSPI_CH1CONF_WL_M      0x00000F80  // SPI word length 0x00 Reserved
-                                            // 0x01 Reserved 0x02 Reserved 0x03
-                                            // The SPI word is 4-bits long 0x04
-                                            // The SPI word is 5-bits long 0x05
-                                            // The SPI word is 6-bits long 0x06
-                                            // The SPI word is 7-bits long 0x07
-                                            // The SPI word is 8-bits long 0x08
-                                            // The SPI word is 9-bits long 0x09
-                                            // The SPI word is 10-bits long 0x0A
-                                            // The SPI word is 11-bits long 0x0B
-                                            // The SPI word is 12-bits long 0x0C
-                                            // The SPI word is 13-bits long 0x0D
-                                            // The SPI word is 14-bits long 0x0E
-                                            // The SPI word is 15-bits long 0x0F
-                                            // The SPI word is 16-bits long 0x10
-                                            // The SPI word is 17-bits long 0x11
-                                            // The SPI word is 18-bits long 0x12
-                                            // The SPI word is 19-bits long 0x13
-                                            // The SPI word is 20-bits long 0x14
-                                            // The SPI word is 21-bits long 0x15
-                                            // The SPI word is 22-bits long 0x16
-                                            // The SPI word is 23-bits long 0x17
-                                            // The SPI word is 24-bits long 0x18
-                                            // The SPI word is 25-bits long 0x19
-                                            // The SPI word is 26-bits long 0x1A
-                                            // The SPI word is 27-bits long 0x1B
-                                            // The SPI word is 28-bits long 0x1C
-                                            // The SPI word is 29-bits long 0x1D
-                                            // The SPI word is 30-bits long 0x1E
-                                            // The SPI word is 31-bits long 0x1F
-                                            // The SPI word is 32-bits long
-#define MCSPI_CH1CONF_WL_S      7
-#define MCSPI_CH1CONF_EPOL      0x00000040  // SPIEN polarity 0 SPIEN is held
-                                            // high during the active state. 1
-                                            // SPIEN is held low during the
-                                            // active state.
-#define MCSPI_CH1CONF_CLKD_M    0x0000003C  // Frequency divider for SPICLK.
-                                            // (only when the module is a Master
-                                            // SPI device). A programmable clock
-                                            // divider divides the SPI reference
-                                            // clock (CLKSPIREF) with a 4-bit
-                                            // value and results in a new clock
-                                            // SPICLK available to shift-in and
-                                            // shift-out data. By default the
-                                            // clock divider ratio has a power
-                                            // of two granularity when
-                                            // MCSPI_CHCONF[CLKG] is cleared
-                                            // Otherwise this register is the 4
-                                            // LSB bit of a 12-bit register
-                                            // concatenated with clock divider
-                                            // extension MCSPI_CHCTRL[EXTCLK]
-                                            // register.The value description
-                                            // below defines the clock ratio
-                                            // when MCSPI_CHCONF[CLKG] is set to
-                                            // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16
-                                            // 0x5 32 0x6 64 0x7 128 0x8 256 0x9
-                                            // 512 0xA 1024 0xB 2048 0xC 4096
-                                            // 0xD 8192 0xE 16384 0xF 32768
-#define MCSPI_CH1CONF_CLKD_S    2
-#define MCSPI_CH1CONF_POL       0x00000002  // SPICLK polarity 0 SPICLK is held
-                                            // high during the active state 1
-                                            // SPICLK is held low during the
-                                            // active state
-#define MCSPI_CH1CONF_PHA       0x00000001  // SPICLK phase 0 Data are latched
-                                            // on odd numbered edges of SPICLK.
-                                            // 1 Data are latched on even
-                                            // numbered edges of SPICLK.
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_CH1STAT register.
-//
-//******************************************************************************
-#define MCSPI_CH1STAT_RXFFF     0x00000040
-#define MCSPI_CH1STAT_RXFFE     0x00000020
-#define MCSPI_CH1STAT_TXFFF     0x00000010
-#define MCSPI_CH1STAT_TXFFE     0x00000008
-#define MCSPI_CH1STAT_EOT       0x00000004
-#define MCSPI_CH1STAT_TXS       0x00000002
-#define MCSPI_CH1STAT_RXS       0x00000001
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_CH1CTRL register.
-//
-//******************************************************************************
-#define MCSPI_CH1CTRL_EXTCLK_M  0x0000FF00  // Clock ratio extension: This
-                                            // register is used to concatenate
-                                            // with MCSPI_CHCONF[CLKD] register
-                                            // for clock ratio only when
-                                            // granularity is one clock cycle
-                                            // (MCSPI_CHCONF[CLKG] set to 1).
-                                            // Then the max value reached is
-                                            // 4096 clock divider ratio. 0x00
-                                            // Clock ratio is CLKD + 1 0x01
-                                            // Clock ratio is CLKD + 1 + 16 0xFF
-                                            // Clock ratio is CLKD + 1 + 4080
-#define MCSPI_CH1CTRL_EXTCLK_S  8
-#define MCSPI_CH1CTRL_EN        0x00000001  // Channel Enable 0 "Channel ""i""
-                                            // is not active" 1 "Channel ""i""
-                                            // is active"
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_TX1 register.
-//
-//******************************************************************************
-#define MCSPI_TX1_TDATA_M       0xFFFFFFFF  // Channel 1 Data to transmit
-#define MCSPI_TX1_TDATA_S       0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_RX1 register.
-//
-//******************************************************************************
-#define MCSPI_RX1_RDATA_M       0xFFFFFFFF  // Channel 1 Received Data
-#define MCSPI_RX1_RDATA_S       0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_CH2CONF register.
-//
-//******************************************************************************
-#define MCSPI_CH2CONF_CLKG      0x20000000  // Clock divider granularity This
-                                            // register defines the granularity
-                                            // of channel clock divider: power
-                                            // of two or one clock cycle
-                                            // granularity. When this bit is set
-                                            // the register MCSPI_CHCTRL[EXTCLK]
-                                            // must be configured to reach a
-                                            // maximum of 4096 clock divider
-                                            // ratio. Then The clock divider
-                                            // ratio is a concatenation of
-                                            // MCSPI_CHCONF[CLKD] and
-                                            // MCSPI_CHCTRL[EXTCLK] values 0
-                                            // Clock granularity of power of two
-                                            // 1 One clock cycle ganularity
-#define MCSPI_CH2CONF_FFER      0x10000000  // FIFO enabled for receive:Only
-                                            // one channel can have this bit
-                                            // field set. 0 The buffer is not
-                                            // used to receive data. 1 The
-                                            // buffer is used to receive data.
-#define MCSPI_CH2CONF_FFEW      0x08000000  // FIFO enabled for Transmit:Only
-                                            // one channel can have this bit
-                                            // field set. 0 The buffer is not
-                                            // used to transmit data. 1 The
-                                            // buffer is used to transmit data.
-#define MCSPI_CH2CONF_TCS2_M    0x06000000  // Chip Select Time Control This
-                                            // 2-bits field defines the number
-                                            // of interface clock cycles between
-                                            // CS toggling and first or last
-                                            // edge of SPI clock. 0x0 0.5 clock
-                                            // cycle 0x1 1.5 clock cycle 0x2 2.5
-                                            // clock cycle 0x3 3.5 clock cycle
-#define MCSPI_CH2CONF_TCS2_S    25
-#define MCSPI_CH2CONF_SBPOL     0x01000000  // Start bit polarity 0 Start bit
-                                            // polarity is held to 0 during SPI
-                                            // transfer. 1 Start bit polarity is
-                                            // held to 1 during SPI transfer.
-#define MCSPI_CH2CONF_SBE       0x00800000  // Start bit enable for SPI
-                                            // transfer 0 Default SPI transfer
-                                            // length as specified by WL bit
-                                            // field 1 Start bit D/CX added
-                                            // before SPI transfer polarity is
-                                            // defined by MCSPI_CH2CONF[SBPOL]
-#define MCSPI_CH2CONF_FORCE     0x00100000  // Manual SPIEN assertion to keep
-                                            // SPIEN active between SPI words.
-                                            // (single channel master mode only)
-                                            // 0 Writing 0 into this bit drives
-                                            // low the SPIEN line when
-                                            // MCSPI_CHCONF(i)[EPOL]=0 and
-                                            // drives it high when
-                                            // MCSPI_CHCONF(i)[EPOL]=1. 1
-                                            // Writing 1 into this bit drives
-                                            // high the SPIEN line when
-                                            // MCSPI_CHCONF(i)[EPOL]=0 and
-                                            // drives it low when
-                                            // MCSPI_CHCONF(i)[EPOL]=1
-#define MCSPI_CH2CONF_TURBO     0x00080000  // Turbo mode 0 Turbo is
-                                            // deactivated (recommended for
-                                            // single SPI word transfer) 1 Turbo
-                                            // is activated to maximize the
-                                            // throughput for multi SPI words
-                                            // transfer.
-#define MCSPI_CH2CONF_IS        0x00040000  // Input Select 0 Data Line0
-                                            // (SPIDAT[0]) selected for
-                                            // reception. 1 Data Line1
-                                            // (SPIDAT[1]) selected for
-                                            // reception
-#define MCSPI_CH2CONF_DPE1      0x00020000  // Transmission Enable for data
-                                            // line 1 (SPIDATAGZEN[1]) 0 Data
-                                            // Line1 (SPIDAT[1]) selected for
-                                            // transmission 1 No transmission on
-                                            // Data Line1 (SPIDAT[1])
-#define MCSPI_CH2CONF_DPE0      0x00010000  // Transmission Enable for data
-                                            // line 0 (SPIDATAGZEN[0]) 0 Data
-                                            // Line0 (SPIDAT[0]) selected for
-                                            // transmission 1 No transmission on
-                                            // Data Line0 (SPIDAT[0])
-#define MCSPI_CH2CONF_DMAR      0x00008000  // DMA Read request The DMA Read
-                                            // request line is asserted when the
-                                            // channel is enabled and a new data
-                                            // is available in the receive
-                                            // register of the channel. The DMA
-                                            // Read request line is deasserted
-                                            // on read completion of the receive
-                                            // register of the channel. 0 DMA
-                                            // Read Request disabled 1 DMA Read
-                                            // Request enabled
-#define MCSPI_CH2CONF_DMAW      0x00004000  // DMA Write request. The DMA Write
-                                            // request line is asserted when The
-                                            // channel is enabled and the
-                                            // transmitter register of the
-                                            // channel is empty. The DMA Write
-                                            // request line is deasserted on
-                                            // load completion of the
-                                            // transmitter register of the
-                                            // channel. 0 DMA Write Request
-                                            // disabled 1 DMA Write Request
-                                            // enabled
-#define MCSPI_CH2CONF_TRM_M     0x00003000  // Transmit/Receive modes 0x0
-                                            // Transmit and Receive mode 0x1
-                                            // Receive only mode 0x2 Transmit
-                                            // only mode 0x3 Reserved
-#define MCSPI_CH2CONF_TRM_S     12
-#define MCSPI_CH2CONF_WL_M      0x00000F80  // SPI word length 0x00 Reserved
-                                            // 0x01 Reserved 0x02 Reserved 0x03
-                                            // The SPI word is 4-bits long 0x04
-                                            // The SPI word is 5-bits long 0x05
-                                            // The SPI word is 6-bits long 0x06
-                                            // The SPI word is 7-bits long 0x07
-                                            // The SPI word is 8-bits long 0x08
-                                            // The SPI word is 9-bits long 0x09
-                                            // The SPI word is 10-bits long 0x0A
-                                            // The SPI word is 11-bits long 0x0B
-                                            // The SPI word is 12-bits long 0x0C
-                                            // The SPI word is 13-bits long 0x0D
-                                            // The SPI word is 14-bits long 0x0E
-                                            // The SPI word is 15-bits long 0x0F
-                                            // The SPI word is 16-bits long 0x10
-                                            // The SPI word is 17-bits long 0x11
-                                            // The SPI word is 18-bits long 0x12
-                                            // The SPI word is 19-bits long 0x13
-                                            // The SPI word is 20-bits long 0x14
-                                            // The SPI word is 21-bits long 0x15
-                                            // The SPI word is 22-bits long 0x16
-                                            // The SPI word is 23-bits long 0x17
-                                            // The SPI word is 24-bits long 0x18
-                                            // The SPI word is 25-bits long 0x19
-                                            // The SPI word is 26-bits long 0x1A
-                                            // The SPI word is 27-bits long 0x1B
-                                            // The SPI word is 28-bits long 0x1C
-                                            // The SPI word is 29-bits long 0x1D
-                                            // The SPI word is 30-bits long 0x1E
-                                            // The SPI word is 31-bits long 0x1F
-                                            // The SPI word is 32-bits long
-#define MCSPI_CH2CONF_WL_S      7
-#define MCSPI_CH2CONF_EPOL      0x00000040  // SPIEN polarity 0 SPIEN is held
-                                            // high during the active state. 1
-                                            // SPIEN is held low during the
-                                            // active state.
-#define MCSPI_CH2CONF_CLKD_M    0x0000003C  // Frequency divider for SPICLK.
-                                            // (only when the module is a Master
-                                            // SPI device). A programmable clock
-                                            // divider divides the SPI reference
-                                            // clock (CLKSPIREF) with a 4-bit
-                                            // value and results in a new clock
-                                            // SPICLK available to shift-in and
-                                            // shift-out data. By default the
-                                            // clock divider ratio has a power
-                                            // of two granularity when
-                                            // MCSPI_CHCONF[CLKG] is cleared
-                                            // Otherwise this register is the 4
-                                            // LSB bit of a 12-bit register
-                                            // concatenated with clock divider
-                                            // extension MCSPI_CHCTRL[EXTCLK]
-                                            // register.The value description
-                                            // below defines the clock ratio
-                                            // when MCSPI_CHCONF[CLKG] is set to
-                                            // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16
-                                            // 0x5 32 0x6 64 0x7 128 0x8 256 0x9
-                                            // 512 0xA 1024 0xB 2048 0xC 4096
-                                            // 0xD 8192 0xE 16384 0xF 32768
-#define MCSPI_CH2CONF_CLKD_S    2
-#define MCSPI_CH2CONF_POL       0x00000002  // SPICLK polarity 0 SPICLK is held
-                                            // high during the active state 1
-                                            // SPICLK is held low during the
-                                            // active state
-#define MCSPI_CH2CONF_PHA       0x00000001  // SPICLK phase 0 Data are latched
-                                            // on odd numbered edges of SPICLK.
-                                            // 1 Data are latched on even
-                                            // numbered edges of SPICLK.
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_CH2STAT register.
-//
-//******************************************************************************
-#define MCSPI_CH2STAT_RXFFF     0x00000040
-#define MCSPI_CH2STAT_RXFFE     0x00000020
-#define MCSPI_CH2STAT_TXFFF     0x00000010
-#define MCSPI_CH2STAT_TXFFE     0x00000008
-#define MCSPI_CH2STAT_EOT       0x00000004
-#define MCSPI_CH2STAT_TXS       0x00000002
-#define MCSPI_CH2STAT_RXS       0x00000001
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_CH2CTRL register.
-//
-//******************************************************************************
-#define MCSPI_CH2CTRL_EXTCLK_M  0x0000FF00  // Clock ratio extension: This
-                                            // register is used to concatenate
-                                            // with MCSPI_CHCONF[CLKD] register
-                                            // for clock ratio only when
-                                            // granularity is one clock cycle
-                                            // (MCSPI_CHCONF[CLKG] set to 1).
-                                            // Then the max value reached is
-                                            // 4096 clock divider ratio. 0x00
-                                            // Clock ratio is CLKD + 1 0x01
-                                            // Clock ratio is CLKD + 1 + 16 0xFF
-                                            // Clock ratio is CLKD + 1 + 4080
-#define MCSPI_CH2CTRL_EXTCLK_S  8
-#define MCSPI_CH2CTRL_EN        0x00000001  // Channel Enable 0 "Channel ""i""
-                                            // is not active" 1 "Channel ""i""
-                                            // is active"
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_TX2 register.
-//
-//******************************************************************************
-#define MCSPI_TX2_TDATA_M       0xFFFFFFFF  // Channel 2 Data to transmit
-#define MCSPI_TX2_TDATA_S       0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_RX2 register.
-//
-//******************************************************************************
-#define MCSPI_RX2_RDATA_M       0xFFFFFFFF  // Channel 2 Received Data
-#define MCSPI_RX2_RDATA_S       0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_CH3CONF register.
-//
-//******************************************************************************
-#define MCSPI_CH3CONF_CLKG      0x20000000  // Clock divider granularity This
-                                            // register defines the granularity
-                                            // of channel clock divider: power
-                                            // of two or one clock cycle
-                                            // granularity. When this bit is set
-                                            // the register MCSPI_CHCTRL[EXTCLK]
-                                            // must be configured to reach a
-                                            // maximum of 4096 clock divider
-                                            // ratio. Then The clock divider
-                                            // ratio is a concatenation of
-                                            // MCSPI_CHCONF[CLKD] and
-                                            // MCSPI_CHCTRL[EXTCLK] values 0
-                                            // Clock granularity of power of two
-                                            // 1 One clock cycle ganularity
-#define MCSPI_CH3CONF_FFER      0x10000000  // FIFO enabled for receive:Only
-                                            // one channel can have this bit
-                                            // field set. 0 The buffer is not
-                                            // used to receive data. 1 The
-                                            // buffer is used to receive data.
-#define MCSPI_CH3CONF_FFEW      0x08000000  // FIFO enabled for Transmit:Only
-                                            // one channel can have this bit
-                                            // field set. 0 The buffer is not
-                                            // used to transmit data. 1 The
-                                            // buffer is used to transmit data.
-#define MCSPI_CH3CONF_TCS3_M    0x06000000  // Chip Select Time Control This
-                                            // 2-bits field defines the number
-                                            // of interface clock cycles between
-                                            // CS toggling and first or last
-                                            // edge of SPI clock. 0x0 0.5 clock
-                                            // cycle 0x1 1.5 clock cycle 0x2 2.5
-                                            // clock cycle 0x3 3.5 clock cycle
-#define MCSPI_CH3CONF_TCS3_S    25
-#define MCSPI_CH3CONF_SBPOL     0x01000000  // Start bit polarity 0 Start bit
-                                            // polarity is held to 0 during SPI
-                                            // transfer. 1 Start bit polarity is
-                                            // held to 1 during SPI transfer.
-#define MCSPI_CH3CONF_SBE       0x00800000  // Start bit enable for SPI
-                                            // transfer 0 Default SPI transfer
-                                            // length as specified by WL bit
-                                            // field 1 Start bit D/CX added
-                                            // before SPI transfer polarity is
-                                            // defined by MCSPI_CH3CONF[SBPOL]
-#define MCSPI_CH3CONF_FORCE     0x00100000  // Manual SPIEN assertion to keep
-                                            // SPIEN active between SPI words.
-                                            // (single channel master mode only)
-                                            // 0 Writing 0 into this bit drives
-                                            // low the SPIEN line when
-                                            // MCSPI_CHCONF(i)[EPOL]=0 and
-                                            // drives it high when
-                                            // MCSPI_CHCONF(i)[EPOL]=1. 1
-                                            // Writing 1 into this bit drives
-                                            // high the SPIEN line when
-                                            // MCSPI_CHCONF(i)[EPOL]=0 and
-                                            // drives it low when
-                                            // MCSPI_CHCONF(i)[EPOL]=1
-#define MCSPI_CH3CONF_TURBO     0x00080000  // Turbo mode 0 Turbo is
-                                            // deactivated (recommended for
-                                            // single SPI word transfer) 1 Turbo
-                                            // is activated to maximize the
-                                            // throughput for multi SPI words
-                                            // transfer.
-#define MCSPI_CH3CONF_IS        0x00040000  // Input Select 0 Data Line0
-                                            // (SPIDAT[0]) selected for
-                                            // reception. 1 Data Line1
-                                            // (SPIDAT[1]) selected for
-                                            // reception
-#define MCSPI_CH3CONF_DPE1      0x00020000  // Transmission Enable for data
-                                            // line 1 (SPIDATAGZEN[1]) 0 Data
-                                            // Line1 (SPIDAT[1]) selected for
-                                            // transmission 1 No transmission on
-                                            // Data Line1 (SPIDAT[1])
-#define MCSPI_CH3CONF_DPE0      0x00010000  // Transmission Enable for data
-                                            // line 0 (SPIDATAGZEN[0]) 0 Data
-                                            // Line0 (SPIDAT[0]) selected for
-                                            // transmission 1 No transmission on
-                                            // Data Line0 (SPIDAT[0])
-#define MCSPI_CH3CONF_DMAR      0x00008000  // DMA Read request The DMA Read
-                                            // request line is asserted when the
-                                            // channel is enabled and a new data
-                                            // is available in the receive
-                                            // register of the channel. The DMA
-                                            // Read request line is deasserted
-                                            // on read completion of the receive
-                                            // register of the channel. 0 DMA
-                                            // Read Request disabled 1 DMA Read
-                                            // Request enabled
-#define MCSPI_CH3CONF_DMAW      0x00004000  // DMA Write request. The DMA Write
-                                            // request line is asserted when The
-                                            // channel is enabled and the
-                                            // transmitter register of the
-                                            // channel is empty. The DMA Write
-                                            // request line is deasserted on
-                                            // load completion of the
-                                            // transmitter register of the
-                                            // channel. 0 DMA Write Request
-                                            // disabled 1 DMA Write Request
-                                            // enabled
-#define MCSPI_CH3CONF_TRM_M     0x00003000  // Transmit/Receive modes 0x0
-                                            // Transmit and Receive mode 0x1
-                                            // Receive only mode 0x2 Transmit
-                                            // only mode 0x3 Reserved
-#define MCSPI_CH3CONF_TRM_S     12
-#define MCSPI_CH3CONF_WL_M      0x00000F80  // SPI word length 0x00 Reserved
-                                            // 0x01 Reserved 0x02 Reserved 0x03
-                                            // The SPI word is 4-bits long 0x04
-                                            // The SPI word is 5-bits long 0x05
-                                            // The SPI word is 6-bits long 0x06
-                                            // The SPI word is 7-bits long 0x07
-                                            // The SPI word is 8-bits long 0x08
-                                            // The SPI word is 9-bits long 0x09
-                                            // The SPI word is 10-bits long 0x0A
-                                            // The SPI word is 11-bits long 0x0B
-                                            // The SPI word is 12-bits long 0x0C
-                                            // The SPI word is 13-bits long 0x0D
-                                            // The SPI word is 14-bits long 0x0E
-                                            // The SPI word is 15-bits long 0x0F
-                                            // The SPI word is 16-bits long 0x10
-                                            // The SPI word is 17-bits long 0x11
-                                            // The SPI word is 18-bits long 0x12
-                                            // The SPI word is 19-bits long 0x13
-                                            // The SPI word is 20-bits long 0x14
-                                            // The SPI word is 21-bits long 0x15
-                                            // The SPI word is 22-bits long 0x16
-                                            // The SPI word is 23-bits long 0x17
-                                            // The SPI word is 24-bits long 0x18
-                                            // The SPI word is 25-bits long 0x19
-                                            // The SPI word is 26-bits long 0x1A
-                                            // The SPI word is 27-bits long 0x1B
-                                            // The SPI word is 28-bits long 0x1C
-                                            // The SPI word is 29-bits long 0x1D
-                                            // The SPI word is 30-bits long 0x1E
-                                            // The SPI word is 31-bits long 0x1F
-                                            // The SPI word is 32-bits long
-#define MCSPI_CH3CONF_WL_S      7
-#define MCSPI_CH3CONF_EPOL      0x00000040  // SPIEN polarity 0 SPIEN is held
-                                            // high during the active state. 1
-                                            // SPIEN is held low during the
-                                            // active state.
-#define MCSPI_CH3CONF_CLKD_M    0x0000003C  // Frequency divider for SPICLK.
-                                            // (only when the module is a Master
-                                            // SPI device). A programmable clock
-                                            // divider divides the SPI reference
-                                            // clock (CLKSPIREF) with a 4-bit
-                                            // value and results in a new clock
-                                            // SPICLK available to shift-in and
-                                            // shift-out data. By default the
-                                            // clock divider ratio has a power
-                                            // of two granularity when
-                                            // MCSPI_CHCONF[CLKG] is cleared
-                                            // Otherwise this register is the 4
-                                            // LSB bit of a 12-bit register
-                                            // concatenated with clock divider
-                                            // extension MCSPI_CHCTRL[EXTCLK]
-                                            // register.The value description
-                                            // below defines the clock ratio
-                                            // when MCSPI_CHCONF[CLKG] is set to
-                                            // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16
-                                            // 0x5 32 0x6 64 0x7 128 0x8 256 0x9
-                                            // 512 0xA 1024 0xB 2048 0xC 4096
-                                            // 0xD 8192 0xE 16384 0xF 32768
-#define MCSPI_CH3CONF_CLKD_S    2
-#define MCSPI_CH3CONF_POL       0x00000002  // SPICLK polarity 0 SPICLK is held
-                                            // high during the active state 1
-                                            // SPICLK is held low during the
-                                            // active state
-#define MCSPI_CH3CONF_PHA       0x00000001  // SPICLK phase 0 Data are latched
-                                            // on odd numbered edges of SPICLK.
-                                            // 1 Data are latched on even
-                                            // numbered edges of SPICLK.
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_CH3STAT register.
-//
-//******************************************************************************
-#define MCSPI_CH3STAT_RXFFF     0x00000040
-#define MCSPI_CH3STAT_RXFFE     0x00000020
-#define MCSPI_CH3STAT_TXFFF     0x00000010
-#define MCSPI_CH3STAT_TXFFE     0x00000008
-#define MCSPI_CH3STAT_EOT       0x00000004
-#define MCSPI_CH3STAT_TXS       0x00000002
-#define MCSPI_CH3STAT_RXS       0x00000001
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_CH3CTRL register.
-//
-//******************************************************************************
-#define MCSPI_CH3CTRL_EXTCLK_M  0x0000FF00  // Clock ratio extension: This
-                                            // register is used to concatenate
-                                            // with MCSPI_CHCONF[CLKD] register
-                                            // for clock ratio only when
-                                            // granularity is one clock cycle
-                                            // (MCSPI_CHCONF[CLKG] set to 1).
-                                            // Then the max value reached is
-                                            // 4096 clock divider ratio. 0x00
-                                            // Clock ratio is CLKD + 1 0x01
-                                            // Clock ratio is CLKD + 1 + 16 0xFF
-                                            // Clock ratio is CLKD + 1 + 4080
-#define MCSPI_CH3CTRL_EXTCLK_S  8
-#define MCSPI_CH3CTRL_EN        0x00000001  // Channel Enable 0 "Channel ""i""
-                                            // is not active" 1 "Channel ""i""
-                                            // is active"
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_TX3 register.
-//
-//******************************************************************************
-#define MCSPI_TX3_TDATA_M       0xFFFFFFFF  // Channel 3 Data to transmit
-#define MCSPI_TX3_TDATA_S       0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_RX3 register.
-//
-//******************************************************************************
-#define MCSPI_RX3_RDATA_M       0xFFFFFFFF  // Channel 3 Received Data
-#define MCSPI_RX3_RDATA_S       0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_XFERLEVEL register.
-//
-//******************************************************************************
-#define MCSPI_XFERLEVEL_WCNT_M  0xFFFF0000  // Spi word counterThis register
-                                            // holds the programmable value of
-                                            // number of SPI word to be
-                                            // transferred on channel which is
-                                            // using the FIFO buffer.When
-                                            // transfer had started a read back
-                                            // in this register returns the
-                                            // current SPI word transfer index.
-                                            // 0x0000 Counter not used 0x0001
-                                            // one word 0xFFFE 65534 spi word
-                                            // 0xFFFF 65535 spi word
-#define MCSPI_XFERLEVEL_WCNT_S  16
-#define MCSPI_XFERLEVEL_AFL_M   0x0000FF00  // Buffer Almost Full This register
-                                            // holds the programmable almost
-                                            // full level value used to
-                                            // determine almost full buffer
-                                            // condition. If the user wants an
-                                            // interrupt or a DMA read request
-                                            // to be issued during a receive
-                                            // operation when the data buffer
-                                            // holds at least n bytes then the
-                                            // buffer MCSPI_MODULCTRL[AFL] must
-                                            // be set with n-1.The size of this
-                                            // register is defined by the
-                                            // generic parameter FFNBYTE. 0x00
-                                            // one byte 0x01 2 bytes 0xFE
-                                            // 255bytes 0xFF 256bytes
-#define MCSPI_XFERLEVEL_AFL_S   8
-#define MCSPI_XFERLEVEL_AEL_M   0x000000FF  // Buffer Almost EmptyThis register
-                                            // holds the programmable almost
-                                            // empty level value used to
-                                            // determine almost empty buffer
-                                            // condition. If the user wants an
-                                            // interrupt or a DMA write request
-                                            // to be issued during a transmit
-                                            // operation when the data buffer is
-                                            // able to receive n bytes then the
-                                            // buffer MCSPI_MODULCTRL[AEL] must
-                                            // be set with n-1. 0x00 one byte
-                                            // 0x01 2 bytes 0xFE 255 bytes 0xFF
-                                            // 256bytes
-#define MCSPI_XFERLEVEL_AEL_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_DAFTX register.
-//
-//******************************************************************************
-#define MCSPI_DAFTX_DAFTDATA_M  0xFFFFFFFF  // FIFO Data to transmit with DMA
-                                            // 256 bit aligned address. "This
-                                            // Register is only is used when
-                                            // MCSPI_MODULCTRL[FDAA] is set to
-                                            // ""1"" and only one of the
-                                            // MCSPI_CH(i)CONF[FFEW] of enabled
-                                            // channels is set. If these
-                                            // conditions are not respected any
-                                            // access to this register return a
-                                            // null value."
-#define MCSPI_DAFTX_DAFTDATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MCSPI_O_DAFRX register.
-//
-//******************************************************************************
-#define MCSPI_DAFRX_DAFRDATA_M  0xFFFFFFFF  // FIFO Data to transmit with DMA
-                                            // 256 bit aligned address. "This
-                                            // Register is only is used when
-                                            // MCSPI_MODULCTRL[FDAA] is set to
-                                            // ""1"" and only one of the
-                                            // MCSPI_CH(i)CONF[FFEW] of enabled
-                                            // channels is set. If these
-                                            // conditions are not respected any
-                                            // access to this register return a
-                                            // null value."
-#define MCSPI_DAFRX_DAFRDATA_S  0
-
-
-
-#endif // __HW_MCSPI_H__
diff --git a/cc3200/hal/inc/hw_memmap.h b/cc3200/hal/inc/hw_memmap.h
deleted file mode 100644
index 244905dd2..000000000
--- a/cc3200/hal/inc/hw_memmap.h
+++ /dev/null
@@ -1,84 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_MEMMAP_H__
-#define __HW_MEMMAP_H__
-
-//*****************************************************************************
-//
-// The following are defines for the base address of the memories and
-// peripherals on the slave_1 interface.
-//
-//*****************************************************************************
-#define FLASH_BASE              0x01000000
-#define SRAM_BASE               0x20000000
-#define WDT_BASE                0x40000000
-#define GPIOA0_BASE             0x40004000
-#define GPIOA1_BASE             0x40005000
-#define GPIOA2_BASE             0x40006000
-#define GPIOA3_BASE             0x40007000
-#define GPIOA4_BASE             0x40024000 
-#define UARTA0_BASE             0x4000C000
-#define UARTA1_BASE             0x4000D000
-#define I2CA0_BASE              0x40020000
-#define TIMERA0_BASE            0x40030000
-#define TIMERA1_BASE            0x40031000
-#define TIMERA2_BASE            0x40032000
-#define TIMERA3_BASE            0x40033000
-#define STACKDIE_CTRL_BASE      0x400F5000
-#define COMMON_REG_BASE         0x400F7000
-#define FLASH_CONTROL_BASE      0x400FD000
-#define SYSTEM_CONTROL_BASE     0x400FE000
-#define UDMA_BASE               0x400FF000
-#define SDHOST_BASE             0x44010000
-#define CAMERA_BASE             0x44018000
-#define I2S_BASE                0x4401C000
-#define SSPI_BASE               0x44020000
-#define GSPI_BASE               0x44021000
-#define LSPI_BASE               0x44022000
-#define ARCM_BASE               0x44025000
-#define APPS_CONFIG_BASE        0x44026000
-#define GPRCM_BASE              0x4402D000
-#define OCP_SHARED_BASE         0x4402E000
-#define ADC_BASE                0x4402E800
-#define HIB1P2_BASE             0x4402F000
-#define HIB3P3_BASE             0x4402F800
-#define DTHE_BASE               0x44030000
-#define SHAMD5_BASE             0x44035000
-#define AES_BASE                0x44037000
-#define DES_BASE                0x44039000
-
-
-#endif // __HW_MEMMAP_H__
diff --git a/cc3200/hal/inc/hw_mmchs.h b/cc3200/hal/inc/hw_mmchs.h
deleted file mode 100644
index 3096d13a9..000000000
--- a/cc3200/hal/inc/hw_mmchs.h
+++ /dev/null
@@ -1,1919 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_MMCHS_H__
-#define __HW_MMCHS_H__
-
-//*****************************************************************************
-//
-// The following are defines for the MMCHS register offsets.
-//
-//*****************************************************************************
-#define MMCHS_O_HL_REV          0x00000000  // IP Revision Identifier (X.Y.R)
-                                            // Used by software to track
-                                            // features bugs and compatibility
-#define MMCHS_O_HL_HWINFO       0x00000004  // Information about the IP
-                                            // module's hardware configuration
-                                            // i.e. typically the module's HDL
-                                            // generics (if any). Actual field
-                                            // format and encoding is up to the
-                                            // module's designer to decide.
-#define MMCHS_O_HL_SYSCONFIG    0x00000010  // Clock management configuration
-#define MMCHS_O_SYSCONFIG       0x00000110  // System Configuration Register
-                                            // This register allows controlling
-                                            // various parameters of the OCP
-                                            // interface.
-#define MMCHS_O_SYSSTATUS       0x00000114  // System Status Register This
-                                            // register provides status
-                                            // information about the module
-                                            // excluding the interrupt status
-                                            // information
-#define MMCHS_O_CSRE            0x00000124  // Card status response error This
-                                            // register enables the host
-                                            // controller to detect card status
-                                            // errors of response type R1 R1b
-                                            // for all cards and of R5 R5b and
-                                            // R6 response for cards types SD or
-                                            // SDIO. When a bit MMCHS_CSRE[i] is
-                                            // set to 1 if the corresponding bit
-                                            // at the same position in the
-                                            // response MMCHS_RSP0[i] is set to
-                                            // 1 the host controller indicates a
-                                            // card error (MMCHS_STAT[CERR])
-                                            // interrupt status to avoid the
-                                            // host driver reading the response
-                                            // register (MMCHS_RSP0). Note: No
-                                            // automatic card error detection
-                                            // for autoCMD12 is implemented; the
-                                            // host system has to check
-                                            // autoCMD12 response register
-                                            // (MMCHS_RESP76) for possible card
-                                            // errors.
-#define MMCHS_O_SYSTEST         0x00000128  // System Test register This
-                                            // register is used to control the
-                                            // signals that connect to I/O pins
-                                            // when the module is configured in
-                                            // system test (SYSTEST) mode for
-                                            // boundary connectivity
-                                            // verification. Note: In SYSTEST
-                                            // mode a write into MMCHS_CMD
-                                            // register will not start a
-                                            // transfer. The buffer behaves as a
-                                            // stack accessible only by the
-                                            // local host (push and pop
-                                            // operations). In this mode the
-                                            // Transfer Block Size
-                                            // (MMCHS_BLK[BLEN]) and the Blocks
-                                            // count for current transfer
-                                            // (MMCHS_BLK[NBLK]) are needed to
-                                            // generate a Buffer write ready
-                                            // interrupt (MMCHS_STAT[BWR]) or a
-                                            // Buffer read ready interrupt
-                                            // (MMCHS_STAT[BRR]) and DMA
-                                            // requests if enabled.
-#define MMCHS_O_CON             0x0000012C  // Configuration register This
-                                            // register is used: - to select the
-                                            // functional mode or the SYSTEST
-                                            // mode for any card. - to send an
-                                            // initialization sequence to any
-                                            // card. - to enable the detection
-                                            // on DAT[1] of a card interrupt for
-                                            // SDIO cards only. and also to
-                                            // configure : - specific data and
-                                            // command transfers for MMC cards
-                                            // only. - the parameters related to
-                                            // the card detect and write protect
-                                            // input signals.
-#define MMCHS_O_PWCNT           0x00000130  // Power counter register This
-                                            // register is used to program a mmc
-                                            // counter to delay command
-                                            // transfers after activating the
-                                            // PAD power this value depends on
-                                            // PAD characteristics and voltage.
-#define MMCHS_O_BLK             0x00000204  // Transfer Length Configuration
-                                            // register MMCHS_BLK[BLEN] is the
-                                            // block size register.
-                                            // MMCHS_BLK[NBLK] is the block
-                                            // count register. This register
-                                            // shall be used for any card.
-#define MMCHS_O_ARG             0x00000208  // Command argument Register This
-                                            // register contains command
-                                            // argument specified as bit 39-8 of
-                                            // Command-Format These registers
-                                            // must be initialized prior to
-                                            // sending the command itself to the
-                                            // card (write action into the
-                                            // register MMCHS_CMD register).
-                                            // Only exception is for a command
-                                            // index specifying stuff bits in
-                                            // arguments making a write
-                                            // unnecessary.
-#define MMCHS_O_CMD             0x0000020C  // Command and transfer mode
-                                            // register MMCHS_CMD[31:16] = the
-                                            // command register MMCHS_CMD[15:0]
-                                            // = the transfer mode. This
-                                            // register configures the data and
-                                            // command transfers. A write into
-                                            // the most significant byte send
-                                            // the command. A write into
-                                            // MMCHS_CMD[15:0] registers during
-                                            // data transfer has no effect. This
-                                            // register shall be used for any
-                                            // card. Note: In SYSTEST mode a
-                                            // write into MMCHS_CMD register
-                                            // will not start a transfer.
-#define MMCHS_O_RSP10           0x00000210  // Command response[31:0] Register
-                                            // This 32-bit register holds bits
-                                            // positions [31:0] of command
-                                            // response type
-                                            // R1/R1b/R2/R3/R4/R5/R5b/R6
-#define MMCHS_O_RSP32           0x00000214  // Command response[63:32] Register
-                                            // This 32-bit register holds bits
-                                            // positions [63:32] of command
-                                            // response type R2
-#define MMCHS_O_RSP54           0x00000218  // Command response[95:64] Register
-                                            // This 32-bit register holds bits
-                                            // positions [95:64] of command
-                                            // response type R2
-#define MMCHS_O_RSP76           0x0000021C  // Command response[127:96]
-                                            // Register This 32-bit register
-                                            // holds bits positions [127:96] of
-                                            // command response type R2
-#define MMCHS_O_DATA            0x00000220  // Data Register This register is
-                                            // the 32-bit entry point of the
-                                            // buffer for read or write data
-                                            // transfers. The buffer size is
-                                            // 32bits x256(1024 bytes). Bytes
-                                            // within a word are stored and read
-                                            // in little endian format. This
-                                            // buffer can be used as two 512
-                                            // byte buffers to transfer data
-                                            // efficiently without reducing the
-                                            // throughput. Sequential and
-                                            // contiguous access is necessary to
-                                            // increment the pointer correctly.
-                                            // Random or skipped access is not
-                                            // allowed. In little endian if the
-                                            // local host accesses this register
-                                            // byte-wise or 16bit-wise the least
-                                            // significant byte (bits [7:0])
-                                            // must always be written/read
-                                            // first. The update of the buffer
-                                            // address is done on the most
-                                            // significant byte write for full
-                                            // 32-bit DATA register or on the
-                                            // most significant byte of the last
-                                            // word of block transfer. Example
-                                            // 1: Byte or 16-bit access
-                                            // Mbyteen[3:0]=0001 (1-byte) =>
-                                            // Mbyteen[3:0]=0010 (1-byte) =>
-                                            // Mbyteen[3:0]=1100 (2-bytes) OK
-                                            // Mbyteen[3:0]=0001 (1-byte) =>
-                                            // Mbyteen[3:0]=0010 (1-byte) =>
-                                            // Mbyteen[3:0]=0100 (1-byte) OK
-                                            // Mbyteen[3:0]=0001 (1-byte) =>
-                                            // Mbyteen[3:0]=0010 (1-byte) =>
-                                            // Mbyteen[3:0]=1000 (1-byte) Bad
-#define MMCHS_O_PSTATE          0x00000224  // Present state register The Host
-                                            // can get status of the Host
-                                            // Controller from this 32-bit read
-                                            // only register.
-#define MMCHS_O_HCTL            0x00000228  // Control register This register
-                                            // defines the host controls to set
-                                            // power wakeup and transfer
-                                            // parameters. MMCHS_HCTL[31:24] =
-                                            // Wakeup control MMCHS_HCTL[23:16]
-                                            // = Block gap control
-                                            // MMCHS_HCTL[15:8] = Power control
-                                            // MMCHS_HCTL[7:0] = Host control
-#define MMCHS_O_SYSCTL          0x0000022C  // SD system control register This
-                                            // register defines the system
-                                            // controls to set software resets
-                                            // clock frequency management and
-                                            // data timeout. MMCHS_SYSCTL[31:24]
-                                            // = Software resets
-                                            // MMCHS_SYSCTL[23:16] = Timeout
-                                            // control MMCHS_SYSCTL[15:0] =
-                                            // Clock control
-#define MMCHS_O_STAT            0x00000230  // Interrupt status register The
-                                            // interrupt status regroups all the
-                                            // status of the module internal
-                                            // events that can generate an
-                                            // interrupt. MMCHS_STAT[31:16] =
-                                            // Error Interrupt Status
-                                            // MMCHS_STAT[15:0] = Normal
-                                            // Interrupt Status
-#define MMCHS_O_IE              0x00000234  // Interrupt SD enable register
-                                            // This register allows to
-                                            // enable/disable the module to set
-                                            // status bits on an event-by-event
-                                            // basis. MMCHS_IE[31:16] = Error
-                                            // Interrupt Status Enable
-                                            // MMCHS_IE[15:0] = Normal Interrupt
-                                            // Status Enable
-#define MMCHS_O_ISE             0x00000238  // Interrupt signal enable register
-                                            // This register allows to
-                                            // enable/disable the module
-                                            // internal sources of status on an
-                                            // event-by-event basis.
-                                            // MMCHS_ISE[31:16] = Error
-                                            // Interrupt Signal Enable
-                                            // MMCHS_ISE[15:0] = Normal
-                                            // Interrupt Signal Enable
-#define MMCHS_O_AC12            0x0000023C  // Auto CMD12 Error Status Register
-                                            // The host driver may determine
-                                            // which of the errors cases related
-                                            // to Auto CMD12 has occurred by
-                                            // checking this MMCHS_AC12 register
-                                            // when an Auto CMD12 Error
-                                            // interrupt occurs. This register
-                                            // is valid only when Auto CMD12 is
-                                            // enabled (MMCHS_CMD[ACEN]) and
-                                            // Auto CMD12Error (MMCHS_STAT[ACE])
-                                            // is set to 1. Note: These bits are
-                                            // automatically reset when starting
-                                            // a new adtc command with data.
-#define MMCHS_O_CAPA            0x00000240  // Capabilities register This
-                                            // register lists the capabilities
-                                            // of the MMC/SD/SDIO host
-                                            // controller.
-#define MMCHS_O_CUR_CAPA        0x00000248  // Maximum current capabilities
-                                            // Register This register indicates
-                                            // the maximum current capability
-                                            // for each voltage. The value is
-                                            // meaningful if the voltage support
-                                            // is set in the capabilities
-                                            // register (MMCHS_CAPA).
-                                            // Initialization of this register
-                                            // (via a write access to this
-                                            // register) depends on the system
-                                            // capabilities. The host driver
-                                            // shall not modify this register
-                                            // after the initilaization. This
-                                            // register is only reinitialized by
-                                            // a hard reset (via RESETN signal)
-#define MMCHS_O_FE              0x00000250  // Force Event Register for Error
-                                            // Interrupt status The force Event
-                                            // Register is not a physically
-                                            // implemented register. Rather it
-                                            // is an address at which the Error
-                                            // Interrupt Status register can be
-                                            // written. The effect of a write to
-                                            // this address will be reflected in
-                                            // the Error Interrupt Status
-                                            // Register if corresponding bit of
-                                            // the Error Interrupt Status Enable
-                                            // Register is set.
-#define MMCHS_O_ADMAES          0x00000254  // ADMA Error Status Register When
-                                            // ADMA Error Interrupt is occurred
-                                            // the ADMA Error States field in
-                                            // this register holds the ADMA
-                                            // state and the ADMA System Address
-                                            // Register holds the address around
-                                            // the error descriptor. For
-                                            // recovering the error the Host
-                                            // Driver requires the ADMA state to
-                                            // identify the error descriptor
-                                            // address as follows: ST_STOP:
-                                            // Previous location set in the ADMA
-                                            // System Address register is the
-                                            // error descriptor address ST_FDS:
-                                            // Current location set in the ADMA
-                                            // System Address register is the
-                                            // error descriptor address ST_CADR:
-                                            // This sate is never set because do
-                                            // not generate ADMA error in this
-                                            // state. ST_TFR: Previous location
-                                            // set in the ADMA System Address
-                                            // register is the error descriptor
-                                            // address In case of write
-                                            // operation the Host Driver should
-                                            // use ACMD22 to get the number of
-                                            // written block rather than using
-                                            // this information since unwritten
-                                            // data may exist in the Host
-                                            // Controller. The Host Controller
-                                            // generates the ADMA Error
-                                            // Interrupt when it detects invalid
-                                            // descriptor data (Valid=0) at the
-                                            // ST_FDS state. In this case ADMA
-                                            // Error State indicates that an
-                                            // error occurs at ST_FDS state. The
-                                            // Host Driver may find that the
-                                            // Valid bit is not set in the error
-                                            // descriptor.
-#define MMCHS_O_ADMASAL         0x00000258  // ADMA System address Low bits
-#define MMCHS_O_REV             0x000002FC  // Versions Register This register
-                                            // contains the hard coded RTL
-                                            // vendor revision number the
-                                            // version number of SD
-                                            // specification compliancy and a
-                                            // slot status bit. MMCHS_REV[31:16]
-                                            // = Host controller version
-                                            // MMCHS_REV[15:0] = Slot Interrupt
-                                            // Status
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_HL_REV register.
-//
-//******************************************************************************
-#define MMCHS_HL_REV_SCHEME_M   0xC0000000
-#define MMCHS_HL_REV_SCHEME_S   30
-#define MMCHS_HL_REV_FUNC_M     0x0FFF0000  // Function indicates a software
-                                            // compatible module family. If
-                                            // there is no level of software
-                                            // compatibility a new Func number
-                                            // (and hence REVISION) should be
-                                            // assigned.
-#define MMCHS_HL_REV_FUNC_S     16
-#define MMCHS_HL_REV_R_RTL_M    0x0000F800  // RTL Version (R) maintained by IP
-                                            // design owner. RTL follows a
-                                            // numbering such as X.Y.R.Z which
-                                            // are explained in this table. R
-                                            // changes ONLY when: (1) PDS
-                                            // uploads occur which may have been
-                                            // due to spec changes (2) Bug fixes
-                                            // occur (3) Resets to '0' when X or
-                                            // Y changes. Design team has an
-                                            // internal 'Z' (customer invisible)
-                                            // number which increments on every
-                                            // drop that happens due to DV and
-                                            // RTL updates. Z resets to 0 when R
-                                            // increments.
-#define MMCHS_HL_REV_R_RTL_S    11
-#define MMCHS_HL_REV_X_MAJOR_M  0x00000700  // Major Revision (X) maintained by
-                                            // IP specification owner. X changes
-                                            // ONLY when: (1) There is a major
-                                            // feature addition. An example
-                                            // would be adding Master Mode to
-                                            // Utopia Level2. The Func field (or
-                                            // Class/Type in old PID format)
-                                            // will remain the same. X does NOT
-                                            // change due to: (1) Bug fixes (2)
-                                            // Change in feature parameters.
-#define MMCHS_HL_REV_X_MAJOR_S  8
-#define MMCHS_HL_REV_CUSTOM_M   0x000000C0
-#define MMCHS_HL_REV_CUSTOM_S   6
-#define MMCHS_HL_REV_Y_MINOR_M  0x0000003F  // Minor Revision (Y) maintained by
-                                            // IP specification owner. Y changes
-                                            // ONLY when: (1) Features are
-                                            // scaled (up or down). Flexibility
-                                            // exists in that this feature
-                                            // scalability may either be
-                                            // represented in the Y change or a
-                                            // specific register in the IP that
-                                            // indicates which features are
-                                            // exactly available. (2) When
-                                            // feature creeps from Is-Not list
-                                            // to Is list. But this may not be
-                                            // the case once it sees silicon; in
-                                            // which case X will change. Y does
-                                            // NOT change due to: (1) Bug fixes
-                                            // (2) Typos or clarifications (3)
-                                            // major functional/feature
-                                            // change/addition/deletion. Instead
-                                            // these changes may be reflected
-                                            // via R S X as applicable. Spec
-                                            // owner maintains a
-                                            // customer-invisible number 'S'
-                                            // which changes due to: (1)
-                                            // Typos/clarifications (2) Bug
-                                            // documentation. Note that this bug
-                                            // is not due to a spec change but
-                                            // due to implementation.
-                                            // Nevertheless the spec tracks the
-                                            // IP bugs. An RTL release (say for
-                                            // silicon PG1.1) that occurs due to
-                                            // bug fix should document the
-                                            // corresponding spec number (X.Y.S)
-                                            // in its release notes.
-#define MMCHS_HL_REV_Y_MINOR_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_HL_HWINFO register.
-//
-//******************************************************************************
-#define MMCHS_HL_HWINFO_RETMODE 0x00000040
-#define MMCHS_HL_HWINFO_MEM_SIZE_M \
-                                0x0000003C
-
-#define MMCHS_HL_HWINFO_MEM_SIZE_S 2
-#define MMCHS_HL_HWINFO_MERGE_MEM \
-                                0x00000002
-
-#define MMCHS_HL_HWINFO_MADMA_EN \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// MMCHS_O_HL_SYSCONFIG register.
-//
-//******************************************************************************
-#define MMCHS_HL_SYSCONFIG_STANDBYMODE_M \
-                                0x00000030  // Configuration of the local
-                                            // initiator state management mode.
-                                            // By definition initiator may
-                                            // generate read/write transaction
-                                            // as long as it is out of STANDBY
-                                            // state. 0x0 Force-standby mode:
-                                            // local initiator is
-                                            // unconditionally placed in standby
-                                            // state.Backup mode for debug only.
-                                            // 0x1 No-standby mode: local
-                                            // initiator is unconditionally
-                                            // placed out of standby
-                                            // state.Backup mode for debug only.
-                                            // 0x2 Smart-standby mode: local
-                                            // initiator standby status depends
-                                            // on local conditions i.e. the
-                                            // module's functional requirement
-                                            // from the initiator.IP module
-                                            // shall not generate
-                                            // (initiator-related) wakeup
-                                            // events. 0x3 "Smart-Standby
-                                            // wakeup-capable mode: local
-                                            // initiator standby status depends
-                                            // on local conditions i.e. the
-                                            // module's functional requirement
-                                            // from the initiator. IP module may
-                                            // generate (master-related) wakeup
-                                            // events when in standby state.Mode
-                                            // is only relevant if the
-                                            // appropriate IP module ""mwakeup""
-                                            // output is implemented."
-
-#define MMCHS_HL_SYSCONFIG_STANDBYMODE_S 4
-#define MMCHS_HL_SYSCONFIG_IDLEMODE_M \
-                                0x0000000C  // Configuration of the local
-                                            // target state management mode. By
-                                            // definition target can handle
-                                            // read/write transaction as long as
-                                            // it is out of IDLE state. 0x0
-                                            // Force-idle mode: local target's
-                                            // idle state follows (acknowledges)
-                                            // the system's idle requests
-                                            // unconditionally i.e. regardless
-                                            // of the IP module's internal
-                                            // requirements.Backup mode for
-                                            // debug only. 0x1 No-idle mode:
-                                            // local target never enters idle
-                                            // state.Backup mode for debug only.
-                                            // 0x2 Smart-idle mode: local
-                                            // target's idle state eventually
-                                            // follows (acknowledges) the
-                                            // system's idle requests depending
-                                            // on the IP module's internal
-                                            // requirements.IP module shall not
-                                            // generate (IRQ- or
-                                            // DMA-request-related) wakeup
-                                            // events. 0x3 "Smart-idle
-                                            // wakeup-capable mode: local
-                                            // target's idle state eventually
-                                            // follows (acknowledges) the
-                                            // system's idle requests depending
-                                            // on the IP module's internal
-                                            // requirements.IP module may
-                                            // generate (IRQ- or
-                                            // DMA-request-related) wakeup
-                                            // events when in idle state.Mode is
-                                            // only relevant if the appropriate
-                                            // IP module ""swakeup"" output(s)
-                                            // is (are) implemented."
-
-#define MMCHS_HL_SYSCONFIG_IDLEMODE_S 2
-#define MMCHS_HL_SYSCONFIG_FREEEMU \
-                                0x00000002  // Sensitivity to emulation (debug)
-                                            // suspend input signal.
-                                            // Functionality NOT implemented in
-                                            // MMCHS. 0 IP module is sensitive
-                                            // to emulation suspend 1 IP module
-                                            // is not sensitive to emulation
-                                            // suspend
-
-#define MMCHS_HL_SYSCONFIG_SOFTRESET \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_SYSCONFIG register.
-//
-//******************************************************************************
-#define MMCHS_SYSCONFIG_STANDBYMODE_M \
-                                0x00003000  // Master interface power
-                                            // Management standby/wait control.
-                                            // The bit field is only useful when
-                                            // generic parameter MADMA_EN
-                                            // (Master ADMA enable) is set as
-                                            // active otherwise it is a read
-                                            // only register read a '0'. 0x0
-                                            // Force-standby. Mstandby is forced
-                                            // unconditionnaly. 0x1 No-standby.
-                                            // Mstandby is never asserted. 0x2
-                                            // Smart-standby mode: local
-                                            // initiator standby status depends
-                                            // on local conditions i.e. the
-                                            // module's functional requirement
-                                            // from the initiator.IP module
-                                            // shall not generate
-                                            // (initiator-related) wakeup
-                                            // events. 0x3 Smart-Standby
-                                            // wakeup-capable mode: "local
-                                            // initiator standby status depends
-                                            // on local conditions i.e. the
-                                            // module's functional requirement
-                                            // from the initiator. IP module may
-                                            // generate (master-related) wakeup
-                                            // events when in standby state.Mode
-                                            // is only relevant if the
-                                            // appropriate IP module ""mwakeup""
-                                            // output is implemented."
-
-#define MMCHS_SYSCONFIG_STANDBYMODE_S 12
-#define MMCHS_SYSCONFIG_CLOCKACTIVITY_M \
-                                0x00000300  // Clocks activity during wake up
-                                            // mode period. Bit8: OCP interface
-                                            // clock Bit9: Functional clock 0x0
-                                            // OCP and Functional clock may be
-                                            // switched off. 0x1 OCP clock is
-                                            // maintained. Functional clock may
-                                            // be switched-off. 0x2 Functional
-                                            // clock is maintained. OCP clock
-                                            // may be switched-off. 0x3 OCP and
-                                            // Functional clocks are maintained.
-
-#define MMCHS_SYSCONFIG_CLOCKACTIVITY_S 8
-#define MMCHS_SYSCONFIG_SIDLEMODE_M \
-                                0x00000018  // Power management 0x0 If an idle
-                                            // request is detected the MMCHS
-                                            // acknowledges it unconditionally
-                                            // and goes in Inactive mode.
-                                            // Interrupt and DMA requests are
-                                            // unconditionally de-asserted. 0x1
-                                            // If an idle request is detected
-                                            // the request is ignored and the
-                                            // module keeps on behaving
-                                            // normally. 0x2 Smart-idle mode:
-                                            // local target's idle state
-                                            // eventually follows (acknowledges)
-                                            // the system's idle requests
-                                            // depending on the IP module's
-                                            // internal requirements.IP module
-                                            // shall not generate (IRQ- or
-                                            // DMA-request-related) wakeup
-                                            // events. 0x3 Smart-idle
-                                            // wakeup-capable mode: "local
-                                            // target's idle state eventually
-                                            // follows (acknowledges) the
-                                            // system's idle requests depending
-                                            // on the IP module's internal
-                                            // requirements.IP module may
-                                            // generate (IRQ- or
-                                            // DMA-request-related) wakeup
-                                            // events when in idle state.Mode is
-                                            // only relevant if the appropriate
-                                            // IP module ""swakeup"" output(s)
-                                            // is (are) implemented."
-
-#define MMCHS_SYSCONFIG_SIDLEMODE_S 3
-#define MMCHS_SYSCONFIG_ENAWAKEUP \
-                                0x00000004  // Wakeup feature control 0 Wakeup
-                                            // capability is disabled 1 Wakeup
-                                            // capability is enabled
-
-#define MMCHS_SYSCONFIG_SOFTRESET \
-                                0x00000002
-
-#define MMCHS_SYSCONFIG_AUTOIDLE \
-                                0x00000001  // Internal Clock gating strategy 0
-                                            // Clocks are free-running 1
-                                            // Automatic clock gating strategy
-                                            // is applied based on the OCP and
-                                            // MMC interface activity
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_SYSSTATUS register.
-//
-//******************************************************************************
-#define MMCHS_SYSSTATUS_RESETDONE \
-                                0x00000001
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_CSRE register.
-//
-//******************************************************************************
-#define MMCHS_CSRE_CSRE_M       0xFFFFFFFF  // Card status response error
-#define MMCHS_CSRE_CSRE_S       0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_SYSTEST register.
-//
-//******************************************************************************
-#define MMCHS_SYSTEST_OBI       0x00010000
-#define MMCHS_SYSTEST_SDCD      0x00008000
-#define MMCHS_SYSTEST_SDWP      0x00004000
-#define MMCHS_SYSTEST_WAKD      0x00002000
-#define MMCHS_SYSTEST_SSB       0x00001000
-#define MMCHS_SYSTEST_D7D       0x00000800
-#define MMCHS_SYSTEST_D6D       0x00000400
-#define MMCHS_SYSTEST_D5D       0x00000200
-#define MMCHS_SYSTEST_D4D       0x00000100
-#define MMCHS_SYSTEST_D3D       0x00000080
-#define MMCHS_SYSTEST_D2D       0x00000040
-#define MMCHS_SYSTEST_D1D       0x00000020
-#define MMCHS_SYSTEST_D0D       0x00000010
-#define MMCHS_SYSTEST_DDIR      0x00000008
-#define MMCHS_SYSTEST_CDAT      0x00000004
-#define MMCHS_SYSTEST_CDIR      0x00000002
-#define MMCHS_SYSTEST_MCKD      0x00000001
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_CON register.
-//
-//******************************************************************************
-#define MMCHS_CON_SDMA_LNE      0x00200000  // Slave DMA Level/Edge Request:
-                                            // The waveform of the DMA request
-                                            // can be configured either edge
-                                            // sensitive with early de-assertion
-                                            // on first access to MMCHS_DATA
-                                            // register or late de-assertion
-                                            // request remains active until last
-                                            // allowed data written into
-                                            // MMCHS_DATA. 0 Slave DMA edge
-                                            // sensitive Early DMA de-assertion
-                                            // 1 Slave DMA level sensitive Late
-                                            // DMA de-assertion
-#define MMCHS_CON_DMA_MNS       0x00100000  // DMA Master or Slave selection:
-                                            // When this bit is set and the
-                                            // controller is configured to use
-                                            // the DMA Ocp master interface is
-                                            // used to get datas from system
-                                            // using ADMA2 procedure (direct
-                                            // access to the memory).This option
-                                            // is only available if generic
-                                            // parameter MADMA_EN is asserted to
-                                            // '1'. 0 The controller is slave on
-                                            // data transfers with system. 1 The
-                                            // controller is master on data
-                                            // exchange with system controller
-                                            // must be configured as using DMA.
-#define MMCHS_CON_DDR           0x00080000  // Dual Data Rate mode: When this
-                                            // register is set the controller
-                                            // uses both clock edge to emit or
-                                            // receive data. Odd bytes are
-                                            // transmitted on falling edges and
-                                            // even bytes are transmitted on
-                                            // rise edges. It only applies on
-                                            // Data bytes and CRC Start end bits
-                                            // and CRC status are kept full
-                                            // cycle. This bit field is only
-                                            // meaningful and active for even
-                                            // clock divider ratio of
-                                            // MMCHS_SYSCTL[CLKD] it is
-                                            // insensitive to MMCHS_HCTL[HSPE]
-                                            // setting. 0 Standard mode : data
-                                            // are transmitted on a single edge
-                                            // depending on MMCHS_HCTRL[HSPE]. 1
-                                            // Data Bytes and CRC are
-                                            // transmitted on both edge.
-#define MMCHS_CON_BOOT_CF0      0x00040000
-#define MMCHS_CON_BOOT_ACK      0x00020000  // Book acknowledge received: When
-                                            // this bit is set the controller
-                                            // should receive a boot status on
-                                            // DAT0 line after next command
-                                            // issued. If no status is received
-                                            // a data timeout will be generated.
-                                            // 0 No acknowledge to be received 1
-                                            // A boot status will be received on
-                                            // DAT0 line after issuing a
-                                            // command.
-#define MMCHS_CON_CLKEXTFREE    0x00010000  // External clock free running:
-                                            // This register is used to maintain
-                                            // card clock out of transfer
-                                            // transaction to enable slave
-                                            // module for example to generate a
-                                            // synchronous interrupt on DAT[1].
-                                            // The Clock will be maintain only
-                                            // if MMCHS_SYSCTL[CEN] is set. 0
-                                            // External card clock is cut off
-                                            // outside active transaction
-                                            // period. 1 External card clock is
-                                            // maintain even out of active
-                                            // transaction period only if
-                                            // MMCHS_SYSCTL[CEN] is set.
-#define MMCHS_CON_PADEN         0x00008000  // Control Power for MMC Lines:
-                                            // This register is only useful when
-                                            // MMC PADs contain power saving
-                                            // mechanism to minimize its leakage
-                                            // power. It works as a GPIO that
-                                            // directly control the ACTIVE pin
-                                            // of PADs. Excepted for DAT[1] the
-                                            // signal is also combine outside
-                                            // the module with the dedicated
-                                            // power control MMCHS_CON[CTPL]
-                                            // bit. 0 ADPIDLE module pin is not
-                                            // forced it is automatically
-                                            // generated by the MMC fsms. 1
-                                            // ADPIDLE module pin is forced to
-                                            // active state.
-#define MMCHS_CON_OBIE          0x00004000  // Out-of-Band Interrupt Enable MMC
-                                            // cards only: This bit enables the
-                                            // detection of Out-of-Band
-                                            // Interrupt on MMCOBI input pin.
-                                            // The usage of the Out-of-Band
-                                            // signal (OBI) is optional and
-                                            // depends on the system
-                                            // integration. 0 Out-of-Band
-                                            // interrupt detection disabled 1
-                                            // Out-of-Band interrupt detection
-                                            // enabled
-#define MMCHS_CON_OBIP          0x00002000  // Out-of-Band Interrupt Polarity
-                                            // MMC cards only: This bit selects
-                                            // the active level of the
-                                            // out-of-band interrupt coming from
-                                            // MMC cards. The usage of the
-                                            // Out-of-Band signal (OBI) is
-                                            // optional and depends on the
-                                            // system integration. 0 active high
-                                            // level 1 active low level
-#define MMCHS_CON_CEATA         0x00001000  // CE-ATA control mode MMC cards
-                                            // compliant with CE-ATA:By default
-                                            // this bit is set to 0. It is use
-                                            // to indicate that next commands
-                                            // are considered as specific CE-ATA
-                                            // commands that potentially use
-                                            // 'command completion' features. 0
-                                            // Standard MMC/SD/SDIO mode. 1
-                                            // CE-ATA mode next commands are
-                                            // considered as CE-ATA commands.
-#define MMCHS_CON_CTPL          0x00000800  // Control Power for DAT[1] line
-                                            // MMC and SD cards: By default this
-                                            // bit is set to 0 and the host
-                                            // controller automatically disables
-                                            // all the input buffers outside of
-                                            // a transaction to minimize the
-                                            // leakage current. SDIO cards: When
-                                            // this bit is set to 1 the host
-                                            // controller automatically disables
-                                            // all the input buffers except the
-                                            // buffer of DAT[1] outside of a
-                                            // transaction in order to detect
-                                            // asynchronous card interrupt on
-                                            // DAT[1] line and minimize the
-                                            // leakage current of the buffers. 0
-                                            // Disable all the input buffers
-                                            // outside of a transaction. 1
-                                            // Disable all the input buffers
-                                            // except the buffer of DAT[1]
-                                            // outside of a transaction.
-#define MMCHS_CON_DVAL_M        0x00000600  // Debounce filter value All cards
-                                            // This register is used to define a
-                                            // debounce period to filter the
-                                            // card detect input signal (SDCD).
-                                            // The usage of the card detect
-                                            // input signal (SDCD) is optional
-                                            // and depends on the system
-                                            // integration and the type of the
-                                            // connector housing that
-                                            // accommodates the card. 0x0 33 us
-                                            // debounce period 0x1 231 us
-                                            // debounce period 0x2 1 ms debounce
-                                            // period 0x3 84 ms debounce period
-#define MMCHS_CON_DVAL_S        9
-#define MMCHS_CON_WPP           0x00000100  // Write protect polarity For SD
-                                            // and SDIO cards only This bit
-                                            // selects the active level of the
-                                            // write protect input signal
-                                            // (SDWP). The usage of the write
-                                            // protect input signal (SDWP) is
-                                            // optional and depends on the
-                                            // system integration and the type
-                                            // of the connector housing that
-                                            // accommodates the card. 0 active
-                                            // high level 1 active low level
-#define MMCHS_CON_CDP           0x00000080  // Card detect polarity All cards
-                                            // This bit selects the active level
-                                            // of the card detect input signal
-                                            // (SDCD). The usage of the card
-                                            // detect input signal (SDCD) is
-                                            // optional and depends on the
-                                            // system integration and the type
-                                            // of the connector housing that
-                                            // accommodates the card. 0 active
-                                            // high level 1 active low level
-#define MMCHS_CON_MIT           0x00000040  // MMC interrupt command Only for
-                                            // MMC cards. This bit must be set
-                                            // to 1 when the next write access
-                                            // to the command register
-                                            // (MMCHS_CMD) is for writing a MMC
-                                            // interrupt command (CMD40)
-                                            // requiring the command timeout
-                                            // detection to be disabled for the
-                                            // command response. 0 Command
-                                            // timeout enabled 1 Command timeout
-                                            // disabled
-#define MMCHS_CON_DW8           0x00000020  // 8-bit mode MMC select For
-                                            // SD/SDIO cards this bit must be
-                                            // set to 0. For MMC card this bit
-                                            // must be set following a valid
-                                            // SWITCH command (CMD6) with the
-                                            // correct value and extend CSD
-                                            // index written in the argument.
-                                            // Prior to this command the MMC
-                                            // card configuration register (CSD
-                                            // and EXT_CSD) must be verified for
-                                            // compliancy with MMC standard
-                                            // specification 4.x (see section
-                                            // 3.6). 0 1-bit or 4-bit Data width
-                                            // (DAT[0] used MMC SD cards) 1
-                                            // 8-bit Data width (DAT[7:0] used
-                                            // MMC cards)
-#define MMCHS_CON_MODE          0x00000010  // Mode select All cards These bits
-                                            // select between Functional mode
-                                            // and SYSTEST mode. 0 Functional
-                                            // mode. Transfers to the
-                                            // MMC/SD/SDIO cards follow the card
-                                            // protocol. MMC clock is enabled.
-                                            // MMC/SD transfers are operated
-                                            // under the control of the CMD
-                                            // register. 1 SYSTEST mode The
-                                            // signal pins are configured as
-                                            // general-purpose input/output and
-                                            // the 1024-byte buffer is
-                                            // configured as a stack memory
-                                            // accessible only by the local host
-                                            // or system DMA. The pins retain
-                                            // their default type (input output
-                                            // or in-out). SYSTEST mode is
-                                            // operated under the control of the
-                                            // SYSTEST register.
-#define MMCHS_CON_STR           0x00000008  // Stream command Only for MMC
-                                            // cards. This bit must be set to 1
-                                            // only for the stream data
-                                            // transfers (read or write) of the
-                                            // adtc commands. Stream read is a
-                                            // class 1 command (CMD11:
-                                            // READ_DAT_UNTIL_STOP). Stream
-                                            // write is a class 3 command
-                                            // (CMD20: WRITE_DAT_UNTIL_STOP). 0
-                                            // Block oriented data transfer 1
-                                            // Stream oriented data transfer
-#define MMCHS_CON_HR            0x00000004  // Broadcast host response Only for
-                                            // MMC cards. This register is used
-                                            // to force the host to generate a
-                                            // 48-bit response for bc command
-                                            // type. "It can be used to
-                                            // terminate the interrupt mode by
-                                            // generating a CMD40 response by
-                                            // the core (see section 4.3
-                                            // ""Interrupt Mode"" in the MMC [1]
-                                            // specification). In order to have
-                                            // the host response to be generated
-                                            // in open drain mode the register
-                                            // MMCHS_CON[OD] must be set to 1."
-                                            // When MMCHS_CON[CEATA] is set to 1
-                                            // and MMCHS_ARG set to 0x00000000
-                                            // when writing 0x00000000 into
-                                            // MMCHS_CMD register the host
-                                            // controller performs a 'command
-                                            // completion signal disable' token
-                                            // i.e. CMD line held to '0' during
-                                            // 47 cycles followed by a 1. 0 The
-                                            // host does not generate a 48-bit
-                                            // response instead of a command. 1
-                                            // The host generates a 48-bit
-                                            // response instead of a command or
-                                            // a command completion signal
-                                            // disable token.
-#define MMCHS_CON_INIT          0x00000002  // Send initialization stream All
-                                            // cards. When this bit is set to 1
-                                            // and the card is idle an
-                                            // initialization sequence is sent
-                                            // to the card. "An initialization
-                                            // sequence consists of setting the
-                                            // CMD line to 1 during 80 clock
-                                            // cycles. The initialisation
-                                            // sequence is mandatory - but it is
-                                            // not required to do it through
-                                            // this bit - this bit makes it
-                                            // easier. Clock divider
-                                            // (MMCHS_SYSCTL[CLKD]) should be
-                                            // set to ensure that 80 clock
-                                            // periods are greater than 1ms.
-                                            // (see section 9.3 ""Power-Up"" in
-                                            // the MMC card specification [1] or
-                                            // section 6.4 in the SD card
-                                            // specification [2])." Note: in
-                                            // this mode there is no command
-                                            // sent to the card and no response
-                                            // is expected 0 The host does not
-                                            // send an initialization sequence.
-                                            // 1 The host sends an
-                                            // initialization sequence.
-#define MMCHS_CON_OD            0x00000001  // Card open drain mode. Only for
-                                            // MMC cards. This bit must be set
-                                            // to 1 for MMC card commands 1 2 3
-                                            // and 40 and if the MMC card bus is
-                                            // operating in open-drain mode
-                                            // during the response phase to the
-                                            // command sent. Typically during
-                                            // card identification mode when the
-                                            // card is either in idle ready or
-                                            // ident state. It is also necessary
-                                            // to set this bit to 1 for a
-                                            // broadcast host response (see
-                                            // Broadcast host response register
-                                            // MMCHS_CON[HR]) 0 No Open Drain 1
-                                            // Open Drain or Broadcast host
-                                            // response
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_PWCNT register.
-//
-//******************************************************************************
-#define MMCHS_PWCNT_PWRCNT_M    0x0000FFFF  // Power counter register. This
-                                            // register is used to introduce a
-                                            // delay between the PAD ACTIVE pin
-                                            // assertion and the command issued.
-                                            // 0x0000 No additional delay added
-                                            // 0x0001 TCF delay (card clock
-                                            // period) 0x0002 TCF x 2 delay
-                                            // (card clock period) 0xFFFE TCF x
-                                            // 65534 delay (card clock period)
-                                            // 0xFFFF TCF x 65535 delay (card
-                                            // clock period)
-#define MMCHS_PWCNT_PWRCNT_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_BLK register.
-//
-//******************************************************************************
-#define MMCHS_BLK_NBLK_M        0xFFFF0000  // Blocks count for current
-                                            // transfer This register is enabled
-                                            // when Block count Enable
-                                            // (MMCHS_CMD[BCE]) is set to 1 and
-                                            // is valid only for multiple block
-                                            // transfers. Setting the block
-                                            // count to 0 results no data blocks
-                                            // being transferred. Note: The host
-                                            // controller decrements the block
-                                            // count after each block transfer
-                                            // and stops when the count reaches
-                                            // zero. This register can be
-                                            // accessed only if no transaction
-                                            // is executing (i.e after a
-                                            // transaction has stopped). Read
-                                            // operations during transfers may
-                                            // return an invalid value and write
-                                            // operation will be ignored. In
-                                            // suspend context the number of
-                                            // blocks yet to be transferred can
-                                            // be determined by reading this
-                                            // register. When restoring transfer
-                                            // context prior to issuing a Resume
-                                            // command The local host shall
-                                            // restore the previously saved
-                                            // block count. 0x0000 Stop count
-                                            // 0x0001 1 block 0x0002 2 blocks
-                                            // 0xFFFF 65535 blocks
-#define MMCHS_BLK_NBLK_S        16
-#define MMCHS_BLK_BLEN_M        0x00000FFF  // Transfer Block Size. This
-                                            // register specifies the block size
-                                            // for block data transfers. Read
-                                            // operations during transfers may
-                                            // return an invalid value and write
-                                            // operations are ignored. When a
-                                            // CMD12 command is issued to stop
-                                            // the transfer a read of the BLEN
-                                            // field after transfer completion
-                                            // (MMCHS_STAT[TC] set to 1) will
-                                            // not return the true byte number
-                                            // of data length while the stop
-                                            // occurs but the value written in
-                                            // this register before transfer is
-                                            // launched. 0x000 No data transfer
-                                            // 0x001 1 byte block length 0x002 2
-                                            // bytes block length 0x003 3 bytes
-                                            // block length 0x1FF 511 bytes
-                                            // block length 0x200 512 bytes
-                                            // block length 0x7FF 2047 bytes
-                                            // block length 0x800 2048 bytes
-                                            // block length
-#define MMCHS_BLK_BLEN_S        0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_ARG register.
-//
-//******************************************************************************
-#define MMCHS_ARG_ARG_M         0xFFFFFFFF  // Command argument bits [31:0]
-#define MMCHS_ARG_ARG_S         0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_CMD register.
-//
-//******************************************************************************
-#define MMCHS_CMD_INDX_M        0x3F000000  // Command index Binary encoded
-                                            // value from 0 to 63 specifying the
-                                            // command number send to card 0x00
-                                            // CMD0 or ACMD0 0x01 CMD1 or ACMD1
-                                            // 0x02 CMD2 or ACMD2 0x03 CMD3 or
-                                            // ACMD3 0x04 CMD4 or ACMD4 0x05
-                                            // CMD5 or ACMD5 0x06 CMD6 or ACMD6
-                                            // 0x07 CMD7 or ACMD7 0x08 CMD8 or
-                                            // ACMD8 0x09 CMD9 or ACMD9 0x0A
-                                            // CMD10 or ACMD10 0x0B CMD11 or
-                                            // ACMD11 0x0C CMD12 or ACMD12 0x0D
-                                            // CMD13 or ACMD13 0x0E CMD14 or
-                                            // ACMD14 0x0F CMD15 or ACMD15 0x10
-                                            // CMD16 or ACMD16 0x11 CMD17 or
-                                            // ACMD17 0x12 CMD18 or ACMD18 0x13
-                                            // CMD19 or ACMD19 0x14 CMD20 or
-                                            // ACMD20 0x15 CMD21 or ACMD21 0x16
-                                            // CMD22 or ACMD22 0x17 CMD23 or
-                                            // ACMD23 0x18 CMD24 or ACMD24 0x19
-                                            // CMD25 or ACMD25 0x1A CMD26 or
-                                            // ACMD26 0x1B CMD27 or ACMD27 0x1C
-                                            // CMD28 or ACMD28 0x1D CMD29 or
-                                            // ACMD29 0x1E CMD30 or ACMD30 0x1F
-                                            // CMD31 or ACMD31 0x20 CMD32 or
-                                            // ACMD32 0x21 CMD33 or ACMD33 0x22
-                                            // CMD34 or ACMD34 0x23 CMD35 or
-                                            // ACMD35 0x24 CMD36 or ACMD36 0x25
-                                            // CMD37 or ACMD37 0x26 CMD38 or
-                                            // ACMD38 0x27 CMD39 or ACMD39 0x28
-                                            // CMD40 or ACMD40 0x29 CMD41 or
-                                            // ACMD41 0x2A CMD42 or ACMD42 0x2B
-                                            // CMD43 or ACMD43 0x2C CMD44 or
-                                            // ACMD44 0x2D CMD45 or ACMD45 0x2E
-                                            // CMD46 or ACMD46 0x2F CMD47 or
-                                            // ACMD47 0x30 CMD48 or ACMD48 0x31
-                                            // CMD49 or ACMD49 0x32 CMD50 or
-                                            // ACMD50 0x33 CMD51 or ACMD51 0x34
-                                            // CMD52 or ACMD52 0x35 CMD53 or
-                                            // ACMD53 0x36 CMD54 or ACMD54 0x37
-                                            // CMD55 or ACMD55 0x38 CMD56 or
-                                            // ACMD56 0x39 CMD57 or ACMD57 0x3A
-                                            // CMD58 or ACMD58 0x3B CMD59 or
-                                            // ACMD59 0x3C CMD60 or ACMD60 0x3D
-                                            // CMD61 or ACMD61 0x3E CMD62 or
-                                            // ACMD62 0x3F CMD63 or ACMD63
-#define MMCHS_CMD_INDX_S        24
-#define MMCHS_CMD_CMD_TYPE_M    0x00C00000  // Command type This register
-                                            // specifies three types of special
-                                            // command: Suspend Resume and
-                                            // Abort. These bits shall be set to
-                                            // 00b for all other commands. 0x0
-                                            // Others Commands 0x1 "CMD52 for
-                                            // writing ""Bus Suspend"" in CCCR"
-                                            // 0x2 "CMD52 for writing ""Function
-                                            // Select"" in CCCR" 0x3 "Abort
-                                            // command CMD12 CMD52 for writing
-                                            // "" I/O Abort"" in CCCR"
-#define MMCHS_CMD_CMD_TYPE_S    22
-#define MMCHS_CMD_DP            0x00200000  // Data present select This
-                                            // register indicates that data is
-                                            // present and DAT line shall be
-                                            // used. It must be set to 0 in the
-                                            // following conditions: - command
-                                            // using only CMD line - command
-                                            // with no data transfer but using
-                                            // busy signal on DAT[0] - Resume
-                                            // command 0 Command with no data
-                                            // transfer 1 Command with data
-                                            // transfer
-#define MMCHS_CMD_CICE          0x00100000  // Command Index check enable This
-                                            // bit must be set to 1 to enable
-                                            // index check on command response
-                                            // to compare the index field in the
-                                            // response against the index of the
-                                            // command. If the index is not the
-                                            // same in the response as in the
-                                            // command it is reported as a
-                                            // command index error
-                                            // (MMCHS_STAT[CIE] set to1) Note:
-                                            // The register CICE cannot be
-                                            // configured for an Auto CMD12 then
-                                            // index check is automatically
-                                            // checked when this command is
-                                            // issued. 0 Index check disable 1
-                                            // Index check enable
-#define MMCHS_CMD_CCCE          0x00080000  // Command CRC check enable This
-                                            // bit must be set to 1 to enable
-                                            // CRC7 check on command response to
-                                            // protect the response against
-                                            // transmission errors on the bus.
-                                            // If an error is detected it is
-                                            // reported as a command CRC error
-                                            // (MMCHS_STAT[CCRC] set to 1).
-                                            // Note: The register CCCE cannot be
-                                            // configured for an Auto CMD12 and
-                                            // then CRC check is automatically
-                                            // checked when this command is
-                                            // issued. 0 CRC7 check disable 1
-                                            // CRC7 check enable
-#define MMCHS_CMD_RSP_TYPE_M    0x00030000  // Response type This bits defines
-                                            // the response type of the command
-                                            // 0x0 No response 0x1 Response
-                                            // Length 136 bits 0x2 Response
-                                            // Length 48 bits 0x3 Response
-                                            // Length 48 bits with busy after
-                                            // response
-#define MMCHS_CMD_RSP_TYPE_S    16
-#define MMCHS_CMD_MSBS          0x00000020  // Multi/Single block select This
-                                            // bit must be set to 1 for data
-                                            // transfer in case of multi block
-                                            // command. For any others command
-                                            // this bit shall be set to 0. 0
-                                            // Single block. If this bit is 0 it
-                                            // is not necessary to set the
-                                            // register MMCHS_BLK[NBLK]. 1 Multi
-                                            // block. When Block Count is
-                                            // disabled (MMCHS_CMD[BCE] is set
-                                            // to 0) in Multiple block transfers
-                                            // (MMCHS_CMD[MSBS] is set to 1) the
-                                            // module can perform infinite
-                                            // transfer.
-#define MMCHS_CMD_DDIR          0x00000010  // Data transfer Direction Select
-                                            // This bit defines either data
-                                            // transfer will be a read or a
-                                            // write. 0 Data Write (host to
-                                            // card) 1 Data Read (card to host)
-#define MMCHS_CMD_ACEN          0x00000004  // Auto CMD12 Enable SD card only.
-                                            // When this bit is set to 1 the
-                                            // host controller issues a CMD12
-                                            // automatically after the transfer
-                                            // completion of the last block. The
-                                            // Host Driver shall not set this
-                                            // bit to issue commands that do not
-                                            // require CMD12 to stop data
-                                            // transfer. In particular secure
-                                            // commands do not require CMD12. 0
-                                            // Auto CMD12 disable 1 Auto CMD12
-                                            // enable or CCS detection enabled.
-#define MMCHS_CMD_BCE           0x00000002  // Block Count Enable Multiple
-                                            // block transfers only. This bit is
-                                            // used to enable the block count
-                                            // register (MMCHS_BLK[NBLK]). When
-                                            // Block Count is disabled
-                                            // (MMCHS_CMD[BCE] is set to 0) in
-                                            // Multiple block transfers
-                                            // (MMCHS_CMD[MSBS] is set to 1) the
-                                            // module can perform infinite
-                                            // transfer. 0 Block count disabled
-                                            // for infinite transfer. 1 Block
-                                            // count enabled for multiple block
-                                            // transfer with known number of
-                                            // blocks
-#define MMCHS_CMD_DE            0x00000001  // DMA Enable This bit is used to
-                                            // enable DMA mode for host data
-                                            // access. 0 DMA mode disable 1 DMA
-                                            // mode enable
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_RSP10 register.
-//
-//******************************************************************************
-#define MMCHS_RSP10_RSP1_M      0xFFFF0000  // Command Response [31:16]
-#define MMCHS_RSP10_RSP1_S      16
-#define MMCHS_RSP10_RSP0_M      0x0000FFFF  // Command Response [15:0]
-#define MMCHS_RSP10_RSP0_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_RSP32 register.
-//
-//******************************************************************************
-#define MMCHS_RSP32_RSP3_M      0xFFFF0000  // Command Response [63:48]
-#define MMCHS_RSP32_RSP3_S      16
-#define MMCHS_RSP32_RSP2_M      0x0000FFFF  // Command Response [47:32]
-#define MMCHS_RSP32_RSP2_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_RSP54 register.
-//
-//******************************************************************************
-#define MMCHS_RSP54_RSP5_M      0xFFFF0000  // Command Response [95:80]
-#define MMCHS_RSP54_RSP5_S      16
-#define MMCHS_RSP54_RSP4_M      0x0000FFFF  // Command Response [79:64]
-#define MMCHS_RSP54_RSP4_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_RSP76 register.
-//
-//******************************************************************************
-#define MMCHS_RSP76_RSP7_M      0xFFFF0000  // Command Response [127:112]
-#define MMCHS_RSP76_RSP7_S      16
-#define MMCHS_RSP76_RSP6_M      0x0000FFFF  // Command Response [111:96]
-#define MMCHS_RSP76_RSP6_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_DATA register.
-//
-//******************************************************************************
-#define MMCHS_DATA_DATA_M       0xFFFFFFFF  // Data Register [31:0] In
-                                            // functional mode (MMCHS_CON[MODE]
-                                            // set to the default value 0) A
-                                            // read access to this register is
-                                            // allowed only when the buffer read
-                                            // enable status is set to 1
-                                            // (MMCHS_PSTATE[BRE]) otherwise a
-                                            // bad access (MMCHS_STAT[BADA]) is
-                                            // signaled. A write access to this
-                                            // register is allowed only when the
-                                            // buffer write enable status is set
-                                            // to 1(MMCHS_STATE[BWE]) otherwise
-                                            // a bad access (MMCHS_STAT[BADA])
-                                            // is signaled and the data is not
-                                            // written.
-#define MMCHS_DATA_DATA_S       0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_PSTATE register.
-//
-//******************************************************************************
-#define MMCHS_PSTATE_CLEV       0x01000000
-#define MMCHS_PSTATE_DLEV_M     0x00F00000  // DAT[3:0] line signal level
-                                            // DAT[3] => bit 23 DAT[2] => bit 22
-                                            // DAT[1] => bit 21 DAT[0] => bit 20
-                                            // This status is used to check DAT
-                                            // line level to recover from errors
-                                            // and for debugging. This is
-                                            // especially useful in detecting
-                                            // the busy signal level from
-                                            // DAT[0]. The value of these
-                                            // registers after reset depends on
-                                            // the DAT lines level at that time.
-#define MMCHS_PSTATE_DLEV_S     20
-#define MMCHS_PSTATE_WP         0x00080000
-#define MMCHS_PSTATE_CDPL       0x00040000
-#define MMCHS_PSTATE_CSS        0x00020000
-#define MMCHS_PSTATE_CINS       0x00010000
-#define MMCHS_PSTATE_BRE        0x00000800
-#define MMCHS_PSTATE_BWE        0x00000400
-#define MMCHS_PSTATE_RTA        0x00000200
-#define MMCHS_PSTATE_WTA        0x00000100
-#define MMCHS_PSTATE_DLA        0x00000004
-#define MMCHS_PSTATE_DATI       0x00000002
-#define MMCHS_PSTATE_CMDI       0x00000001
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_HCTL register.
-//
-//******************************************************************************
-#define MMCHS_HCTL_OBWE         0x08000000  // Wakeup event enable for
-                                            // 'Out-of-Band' Interrupt. This bit
-                                            // enables wakeup events for
-                                            // 'Out-of-Band' assertion. Wakeup
-                                            // is generated if the wakeup
-                                            // feature is enabled
-                                            // (MMCHS_SYSCONFIG[ENAWAKEUP]). The
-                                            // write to this register is ignored
-                                            // when MMCHS_CON[OBIE] is not set.
-                                            // 0 Disable wakeup on 'Out-of-Band'
-                                            // Interrupt 1 Enable wakeup on
-                                            // 'Out-of-Band' Interrupt
-#define MMCHS_HCTL_REM          0x04000000  // Wakeup event enable on SD card
-                                            // removal This bit enables wakeup
-                                            // events for card removal
-                                            // assertion. Wakeup is generated if
-                                            // the wakeup feature is enabled
-                                            // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0
-                                            // Disable wakeup on card removal 1
-                                            // Enable wakeup on card removal
-#define MMCHS_HCTL_INS          0x02000000  // Wakeup event enable on SD card
-                                            // insertion This bit enables wakeup
-                                            // events for card insertion
-                                            // assertion. Wakeup is generated if
-                                            // the wakeup feature is enabled
-                                            // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0
-                                            // Disable wakeup on card insertion
-                                            // 1 Enable wakeup on card insertion
-#define MMCHS_HCTL_IWE          0x01000000  // Wakeup event enable on SD card
-                                            // interrupt This bit enables wakeup
-                                            // events for card interrupt
-                                            // assertion. Wakeup is generated if
-                                            // the wakeup feature is enabled
-                                            // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0
-                                            // Disable wakeup on card interrupt
-                                            // 1 Enable wakeup on card interrupt
-#define MMCHS_HCTL_IBG          0x00080000  // Interrupt block at gap This bit
-                                            // is valid only in 4-bit mode of
-                                            // SDIO card to enable interrupt
-                                            // detection in the interrupt cycle
-                                            // at block gap for a multiple block
-                                            // transfer. For MMC cards and for
-                                            // SD card this bit should be set to
-                                            // 0. 0 Disable interrupt detection
-                                            // at the block gap in 4-bit mode 1
-                                            // Enable interrupt detection at the
-                                            // block gap in 4-bit mode
-#define MMCHS_HCTL_RWC          0x00040000  // Read wait control The read wait
-                                            // function is optional only for
-                                            // SDIO cards. If the card supports
-                                            // read wait this bit must be
-                                            // enabled then requesting a stop at
-                                            // block gap (MMCHS_HCTL[SBGR])
-                                            // generates a read wait period
-                                            // after the current end of block.
-                                            // Be careful if read wait is not
-                                            // supported it may cause a conflict
-                                            // on DAT line. 0 Disable Read Wait
-                                            // Control. Suspend/Resume cannot be
-                                            // supported. 1 Enable Read Wait
-                                            // Control
-#define MMCHS_HCTL_CR           0x00020000  // Continue request This bit is
-                                            // used to restart a transaction
-                                            // that was stopped by requesting a
-                                            // stop at block gap
-                                            // (MMCHS_HCTL[SBGR]). Set this bit
-                                            // to 1 restarts the transfer. The
-                                            // bit is automatically set to 0 by
-                                            // the host controller when transfer
-                                            // has restarted i.e DAT line is
-                                            // active (MMCHS_PSTATE[DLA]) or
-                                            // transferring data
-                                            // (MMCHS_PSTATE[WTA]). The Stop at
-                                            // block gap request must be
-                                            // disabled (MMCHS_HCTL[SBGR]=0)
-                                            // before setting this bit. 0 No
-                                            // affect 1 transfer restart
-#define MMCHS_HCTL_SBGR         0x00010000  // Stop at block gap request This
-                                            // bit is used to stop executing a
-                                            // transaction at the next block
-                                            // gap. The transfer can restart
-                                            // with a continue request
-                                            // (MMHS_HCTL[CR]) or during a
-                                            // suspend/resume sequence. In case
-                                            // of read transfer the card must
-                                            // support read wait control. In
-                                            // case of write transfer the host
-                                            // driver shall set this bit after
-                                            // all block data written. Until the
-                                            // transfer completion
-                                            // (MMCHS_STAT[TC] set to 1) the
-                                            // host driver shall leave this bit
-                                            // set to 1. If this bit is set the
-                                            // local host shall not write to the
-                                            // data register (MMCHS_DATA). 0
-                                            // Transfer mode 1 Stop at block gap
-#define MMCHS_HCTL_SDVS_M       0x00000E00  // SD bus voltage select All cards.
-                                            // The host driver should set to
-                                            // these bits to select the voltage
-                                            // level for the card according to
-                                            // the voltage supported by the
-                                            // system (MMCHS_CAPA[VS18VS30VS33])
-                                            // before starting a transfer. 0x5
-                                            // 1.8V (Typical) 0x6 3.0V (Typical)
-                                            // 0x7 3.3V (Typical)
-#define MMCHS_HCTL_SDVS_S       9
-#define MMCHS_HCTL_SDBP         0x00000100  // SD bus power Before setting this
-                                            // bit the host driver shall select
-                                            // the SD bus voltage
-                                            // (MMCHS_HCTL[SDVS]). If the host
-                                            // controller detects the No card
-                                            // state this bit is automatically
-                                            // set to 0. If the module is power
-                                            // off a write in the command
-                                            // register (MMCHS_CMD) will not
-                                            // start the transfer. A write to
-                                            // this bit has no effect if the
-                                            // selected SD bus voltage
-                                            // MMCHS_HCTL[SDVS] is not supported
-                                            // according to capability register
-                                            // (MMCHS_CAPA[VS*]). 0 Power off 1
-                                            // Power on
-#define MMCHS_HCTL_CDSS         0x00000080  // Card Detect Signal Selection
-                                            // This bit selects source for the
-                                            // card detection.When the source
-                                            // for the card detection is
-                                            // switched the interrupt should be
-                                            // disabled during the switching
-                                            // period by clearing the Interrupt
-                                            // Status/Signal Enable register in
-                                            // order to mask unexpected
-                                            // interrupt being caused by the
-                                            // glitch. The Interrupt
-                                            // Status/Signal Enable should be
-                                            // disabled during over the period
-                                            // of debouncing. 0 SDCD# is
-                                            // selected (for normal use) 1 The
-                                            // Card Detect Test Level is
-                                            // selected (for test purpose)
-#define MMCHS_HCTL_CDTL         0x00000040  // Card Detect Test Level: This bit
-                                            // is enabled while the Card Detect
-                                            // Signal Selection is set to 1 and
-                                            // it indicates card inserted or
-                                            // not. 0 No Card 1 Card Inserted
-#define MMCHS_HCTL_DMAS_M       0x00000018  // DMA Select Mode: One of
-                                            // supported DMA modes can be
-                                            // selected. The host driver shall
-                                            // check support of DMA modes by
-                                            // referring the Capabilities
-                                            // register. Use of selected DMA is
-                                            // determined by DMA Enable of the
-                                            // Transfer Mode register. This
-                                            // register is only meaningful when
-                                            // MADMA_EN is set to 1. When
-                                            // MADMA_EN is set to 0 the bit
-                                            // field is read only and returned
-                                            // value is 0. 0x0 Reserved 0x1
-                                            // Reserved 0x2 32-bit Address ADMA2
-                                            // is selected 0x3 Reserved
-#define MMCHS_HCTL_DMAS_S       3
-#define MMCHS_HCTL_HSPE         0x00000004  // High Speed Enable: Before
-                                            // setting this bit the Host Driver
-                                            // shall check the High Speed
-                                            // Support in the Capabilities
-                                            // register. If this bit is set to 0
-                                            // (default) the Host Controller
-                                            // outputs CMD line and DAT lines at
-                                            // the falling edge of the SD Clock.
-                                            // If this bit is set to 1 the Host
-                                            // Controller outputs CMD line and
-                                            // DAT lines at the rising edge of
-                                            // the SD Clock.This bit shall not
-                                            // be set when dual data rate mode
-                                            // is activated in MMCHS_CON[DDR]. 0
-                                            // Normal speed mode 1 High speed
-                                            // mode
-#define MMCHS_HCTL_DTW          0x00000002  // Data transfer width For MMC card
-                                            // this bit must be set following a
-                                            // valid SWITCH command (CMD6) with
-                                            // the correct value and extend CSD
-                                            // index written in the argument.
-                                            // Prior to this command the MMC
-                                            // card configuration register (CSD
-                                            // and EXT_CSD) must be verified for
-                                            // compliance with MMC standard
-                                            // specification 4.x (see section
-                                            // 3.6). This register has no effect
-                                            // when the MMC 8-bit mode is
-                                            // selected (register MMCHS_CON[DW8]
-                                            // set to1 ) For SD/SDIO cards this
-                                            // bit must be set following a valid
-                                            // SET_BUS_WIDTH command (ACMD6)
-                                            // with the value written in bit 1
-                                            // of the argument. Prior to this
-                                            // command the SD card configuration
-                                            // register (SCR) must be verified
-                                            // for the supported bus width by
-                                            // the SD card. 0 1-bit Data width
-                                            // (DAT[0] used) 1 4-bit Data width
-                                            // (DAT[3:0] used)
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_SYSCTL register.
-//
-//******************************************************************************
-#define MMCHS_SYSCTL_SRD        0x04000000  // Software reset for DAT line This
-                                            // bit is set to 1 for reset and
-                                            // released to 0 when completed. DAT
-                                            // finite state machine in both
-                                            // clock domain are also reset. Here
-                                            // below are the registers cleared
-                                            // by MMCHS_SYSCTL[SRD]: #VALUE! -
-                                            // MMCHS_PSTATE: BRE BWE RTA WTA DLA
-                                            // and DATI - MMCHS_HCTL: SBGR and
-                                            // CR - MMCHS_STAT: BRR BWR BGE and
-                                            // TC OCP and MMC buffer data
-                                            // management is reinitialized. 0
-                                            // Reset completed 1 Software reset
-                                            // for DAT line
-#define MMCHS_SYSCTL_SRC        0x02000000  // Software reset for CMD line This
-                                            // bit is set to 1 for reset and
-                                            // released to 0 when completed. CMD
-                                            // finite state machine in both
-                                            // clock domain are also reset. Here
-                                            // below the registers cleared by
-                                            // MMCHS_SYSCTL[SRC]: -
-                                            // MMCHS_PSTATE: CMDI - MMCHS_STAT:
-                                            // CC OCP and MMC command status
-                                            // management is reinitialized. 0
-                                            // Reset completed 1 Software reset
-                                            // for CMD line
-#define MMCHS_SYSCTL_SRA        0x01000000  // Software reset for all This bit
-                                            // is set to 1 for reset and
-                                            // released to 0 when completed.
-                                            // This reset affects the entire
-                                            // host controller except for the
-                                            // card detection circuit and
-                                            // capabilities registers. 0 Reset
-                                            // completed 1 Software reset for
-                                            // all the design
-#define MMCHS_SYSCTL_DTO_M      0x000F0000  // Data timeout counter value and
-                                            // busy timeout. This value
-                                            // determines the interval by which
-                                            // DAT lines timeouts are detected.
-                                            // The host driver needs to set this
-                                            // bitfield based on - the maximum
-                                            // read access time (NAC) (Refer to
-                                            // the SD Specification Part1
-                                            // Physical Layer) - the data read
-                                            // access time values (TAAC and
-                                            // NSAC) in the card specific data
-                                            // register (CSD) of the card - the
-                                            // timeout clock base frequency
-                                            // (MMCHS_CAPA[TCF]). If the card
-                                            // does not respond within the
-                                            // specified number of cycles a data
-                                            // timeout error occurs
-                                            // (MMCHS_STA[DTO]). The
-                                            // MMCHS_SYSCTL[DTO] register is
-                                            // also used to check busy duration
-                                            // to generate busy timeout for
-                                            // commands with busy response or
-                                            // for busy programming during a
-                                            // write command. Timeout on CRC
-                                            // status is generated if no CRC
-                                            // token is present after a block
-                                            // write. 0x0 TCF x 2^13 0x1 TCF x
-                                            // 2^14 0xE TCF x 2^27 0xF Reserved
-#define MMCHS_SYSCTL_DTO_S      16
-#define MMCHS_SYSCTL_CLKD_M     0x0000FFC0  // Clock frequency select These
-                                            // bits define the ratio between a
-                                            // reference clock frequency (system
-                                            // dependant) and the output clock
-                                            // frequency on the CLK pin of
-                                            // either the memory card (MMC SD or
-                                            // SDIO). 0x000 Clock Ref bypass
-                                            // 0x001 Clock Ref bypass 0x002
-                                            // Clock Ref / 2 0x003 Clock Ref / 3
-                                            // 0x3FF Clock Ref / 1023
-#define MMCHS_SYSCTL_CLKD_S     6
-#define MMCHS_SYSCTL_CEN        0x00000004  // Clock enable This bit controls
-                                            // if the clock is provided to the
-                                            // card or not. 0 The clock is not
-                                            // provided to the card . Clock
-                                            // frequency can be changed . 1 The
-                                            // clock is provided to the card and
-                                            // can be automatically gated when
-                                            // MMCHS_SYSCONFIG[AUTOIDLE] is set
-                                            // to 1 (default value) . The host
-                                            // driver shall wait to set this bit
-                                            // to 1 until the Internal clock is
-                                            // stable (MMCHS_SYSCTL[ICS]).
-#define MMCHS_SYSCTL_ICS        0x00000002
-#define MMCHS_SYSCTL_ICE        0x00000001  // Internal clock enable This
-                                            // register controls the internal
-                                            // clock activity. In very low power
-                                            // state the internal clock is
-                                            // stopped. Note: The activity of
-                                            // the debounce clock (used for
-                                            // wakeup events) and the OCP clock
-                                            // (used for reads and writes to the
-                                            // module register map) are not
-                                            // affected by this register. 0 The
-                                            // internal clock is stopped (very
-                                            // low power state). 1 The internal
-                                            // clock oscillates and can be
-                                            // automatically gated when
-                                            // MMCHS_SYSCONFIG[AUTOIDLE] is set
-                                            // to 1 (default value) .
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_STAT register.
-//
-//******************************************************************************
-#define MMCHS_STAT_BADA         0x20000000
-#define MMCHS_STAT_CERR         0x10000000
-#define MMCHS_STAT_ADMAE        0x02000000
-#define MMCHS_STAT_ACE          0x01000000
-#define MMCHS_STAT_DEB          0x00400000
-#define MMCHS_STAT_DCRC         0x00200000
-#define MMCHS_STAT_DTO          0x00100000
-#define MMCHS_STAT_CIE          0x00080000
-#define MMCHS_STAT_CEB          0x00040000
-#define MMCHS_STAT_CCRC         0x00020000
-#define MMCHS_STAT_CTO          0x00010000
-#define MMCHS_STAT_ERRI         0x00008000
-#define MMCHS_STAT_BSR          0x00000400
-#define MMCHS_STAT_OBI          0x00000200
-#define MMCHS_STAT_CIRQ         0x00000100
-#define MMCHS_STAT_CREM         0x00000080
-#define MMCHS_STAT_CINS         0x00000040
-#define MMCHS_STAT_BRR          0x00000020
-#define MMCHS_STAT_BWR          0x00000010
-#define MMCHS_STAT_DMA          0x00000008
-#define MMCHS_STAT_BGE          0x00000004
-#define MMCHS_STAT_TC           0x00000002
-#define MMCHS_STAT_CC           0x00000001
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_IE register.
-//
-//******************************************************************************
-#define MMCHS_IE_BADA_ENABLE    0x20000000  // Bad access to data space
-                                            // Interrupt Enable 0 Masked 1
-                                            // Enabled
-#define MMCHS_IE_CERR_ENABLE    0x10000000  // Card error interrupt Enable 0
-                                            // Masked 1 Enabled
-#define MMCHS_IE_ADMAE_ENABLE   0x02000000  // ADMA error Interrupt Enable 0
-                                            // Masked 1 Enabled
-#define MMCHS_IE_ACE_ENABLE     0x01000000  // Auto CMD12 error Interrupt
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_IE_DEB_ENABLE     0x00400000  // Data end bit error Interrupt
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_IE_DCRC_ENABLE    0x00200000  // Data CRC error Interrupt Enable
-                                            // 0 Masked 1 Enabled
-#define MMCHS_IE_DTO_ENABLE     0x00100000  // Data timeout error Interrupt
-                                            // Enable 0 The data timeout
-                                            // detection is deactivated. The
-                                            // host controller provides the
-                                            // clock to the card until the card
-                                            // sends the data or the transfer is
-                                            // aborted. 1 The data timeout
-                                            // detection is enabled.
-#define MMCHS_IE_CIE_ENABLE     0x00080000  // Command index error Interrupt
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_IE_CEB_ENABLE     0x00040000  // Command end bit error Interrupt
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_IE_CCRC_ENABLE    0x00020000  // Command CRC error Interrupt
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_IE_CTO_ENABLE     0x00010000  // Command timeout error Interrupt
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_IE_NULL           0x00008000  // Fixed to 0 The host driver shall
-                                            // control error interrupts using
-                                            // the Error Interrupt Signal Enable
-                                            // register. Writes to this bit are
-                                            // ignored
-#define MMCHS_IE_BSR_ENABLE     0x00000400  // Boot status interrupt Enable A
-                                            // write to this register when
-                                            // MMCHS_CON[BOOT_ACK] is set to 0x0
-                                            // is ignored. 0 Masked 1 Enabled
-#define MMCHS_IE_OBI_ENABLE     0x00000200  // Out-of-Band interrupt Enable A
-                                            // write to this register when
-                                            // MMCHS_CON[OBIE] is set to '0' is
-                                            // ignored. 0 Masked 1 Enabled
-#define MMCHS_IE_CIRQ_ENABLE    0x00000100  // Card interrupt Enable A clear of
-                                            // this bit also clears the
-                                            // corresponding status bit. During
-                                            // 1-bit mode if the interrupt
-                                            // routine doesn't remove the source
-                                            // of a card interrupt in the SDIO
-                                            // card the status bit is reasserted
-                                            // when this bit is set to 1. 0
-                                            // Masked 1 Enabled
-#define MMCHS_IE_CREM_ENABLE    0x00000080  // Card removal Interrupt Enable 0
-                                            // Masked 1 Enabled
-#define MMCHS_IE_CINS_ENABLE    0x00000040  // Card insertion Interrupt Enable
-                                            // 0 Masked 1 Enabled
-#define MMCHS_IE_BRR_ENABLE     0x00000020  // Buffer Read Ready Interrupt
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_IE_BWR_ENABLE     0x00000010  // Buffer Write Ready Interrupt
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_IE_DMA_ENABLE     0x00000008  // DMA interrupt Enable 0 Masked 1
-                                            // Enabled
-#define MMCHS_IE_BGE_ENABLE     0x00000004  // Block Gap Event Interrupt Enable
-                                            // 0 Masked 1 Enabled
-#define MMCHS_IE_TC_ENABLE      0x00000002  // Transfer completed Interrupt
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_IE_CC_ENABLE      0x00000001  // Command completed Interrupt
-                                            // Enable 0 Masked 1 Enabled
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_ISE register.
-//
-//******************************************************************************
-#define MMCHS_ISE_BADA_SIGEN    0x20000000  // Bad access to data space signal
-                                            // status Enable 0 Masked 1 Enabled
-#define MMCHS_ISE_CERR_SIGEN    0x10000000  // Card error interrupt signal
-                                            // status Enable 0 Masked 1 Enabled
-#define MMCHS_ISE_ADMAE_SIGEN   0x02000000  // ADMA error signal status Enable
-                                            // 0 Masked 1 Enabled
-#define MMCHS_ISE_ACE_SIGEN     0x01000000  // Auto CMD12 error signal status
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_ISE_DEB_SIGEN     0x00400000  // Data end bit error signal status
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_ISE_DCRC_SIGEN    0x00200000  // Data CRC error signal status
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_ISE_DTO_SIGEN     0x00100000  // Data timeout error signal status
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_ISE_CIE_SIGEN     0x00080000  // Command index error signal
-                                            // status Enable 0 Masked 1 Enabled
-#define MMCHS_ISE_CEB_SIGEN     0x00040000  // Command end bit error signal
-                                            // status Enable 0 Masked 1 Enabled
-#define MMCHS_ISE_CCRC_SIGEN    0x00020000  // Command CRC error signal status
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_ISE_CTO_SIGEN     0x00010000  // Command timeout error signal
-                                            // status Enable 0 Masked 1 Enabled
-#define MMCHS_ISE_NULL          0x00008000  // Fixed to 0 The host driver shall
-                                            // control error interrupts using
-                                            // the Error Interrupt Signal Enable
-                                            // register. Writes to this bit are
-                                            // ignored
-#define MMCHS_ISE_BSR_SIGEN     0x00000400  // Boot status signal status
-                                            // EnableA write to this register
-                                            // when MMCHS_CON[BOOT_ACK] is set
-                                            // to 0x0 is ignored. 0 Masked 1
-                                            // Enabled
-#define MMCHS_ISE_OBI_SIGEN     0x00000200  // Out-Of-Band Interrupt signal
-                                            // status Enable A write to this
-                                            // register when MMCHS_CON[OBIE] is
-                                            // set to '0' is ignored. 0 Masked 1
-                                            // Enabled
-#define MMCHS_ISE_CIRQ_SIGEN    0x00000100  // Card interrupt signal status
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_ISE_CREM_SIGEN    0x00000080  // Card removal signal status
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_ISE_CINS_SIGEN    0x00000040  // Card insertion signal status
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_ISE_BRR_SIGEN     0x00000020  // Buffer Read Ready signal status
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_ISE_BWR_SIGEN     0x00000010  // Buffer Write Ready signal status
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_ISE_DMA_SIGEN     0x00000008  // DMA interrupt Signal status
-                                            // enable 0 Masked 1 Enabled
-#define MMCHS_ISE_BGE_SIGEN     0x00000004  // Black Gap Event signal status
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_ISE_TC_SIGEN      0x00000002  // Transfer completed signal status
-                                            // Enable 0 Masked 1 Enabled
-#define MMCHS_ISE_CC_SIGEN      0x00000001  // Command completed signal status
-                                            // Enable 0 Masked 1 Enabled
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_AC12 register.
-//
-//******************************************************************************
-#define MMCHS_AC12_CNI          0x00000080
-#define MMCHS_AC12_ACIE         0x00000010
-#define MMCHS_AC12_ACEB         0x00000008
-#define MMCHS_AC12_ACCE         0x00000004
-#define MMCHS_AC12_ACTO         0x00000002
-#define MMCHS_AC12_ACNE         0x00000001
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_CAPA register.
-//
-//******************************************************************************
-#define MMCHS_CAPA_BIT64        0x10000000
-#define MMCHS_CAPA_VS18         0x04000000
-#define MMCHS_CAPA_VS30         0x02000000
-#define MMCHS_CAPA_VS33         0x01000000
-#define MMCHS_CAPA_SRS          0x00800000
-#define MMCHS_CAPA_DS           0x00400000
-#define MMCHS_CAPA_HSS          0x00200000
-#define MMCHS_CAPA_AD2S         0x00080000
-#define MMCHS_CAPA_MBL_M        0x00030000
-#define MMCHS_CAPA_MBL_S        16
-#define MMCHS_CAPA_BCF_M        0x00003F00
-#define MMCHS_CAPA_BCF_S        8
-#define MMCHS_CAPA_TCU          0x00000080
-#define MMCHS_CAPA_TCF_M        0x0000003F
-#define MMCHS_CAPA_TCF_S        0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_CUR_CAPA register.
-//
-//******************************************************************************
-#define MMCHS_CUR_CAPA_CUR_1V8_M \
-                                0x00FF0000
-
-#define MMCHS_CUR_CAPA_CUR_1V8_S 16
-#define MMCHS_CUR_CAPA_CUR_3V0_M \
-                                0x0000FF00
-
-#define MMCHS_CUR_CAPA_CUR_3V0_S 8
-#define MMCHS_CUR_CAPA_CUR_3V3_M \
-                                0x000000FF
-
-#define MMCHS_CUR_CAPA_CUR_3V3_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_FE register.
-//
-//******************************************************************************
-#define MMCHS_FE_FE_BADA        0x20000000
-#define MMCHS_FE_FE_CERR        0x10000000
-#define MMCHS_FE_FE_ADMAE       0x02000000
-#define MMCHS_FE_FE_ACE         0x01000000
-#define MMCHS_FE_FE_DEB         0x00400000
-#define MMCHS_FE_FE_DCRC        0x00200000
-#define MMCHS_FE_FE_DTO         0x00100000
-#define MMCHS_FE_FE_CIE         0x00080000
-#define MMCHS_FE_FE_CEB         0x00040000
-#define MMCHS_FE_FE_CCRC        0x00020000
-#define MMCHS_FE_FE_CTO         0x00010000
-#define MMCHS_FE_FE_CNI         0x00000080
-#define MMCHS_FE_FE_ACIE        0x00000010
-#define MMCHS_FE_FE_ACEB        0x00000008
-#define MMCHS_FE_FE_ACCE        0x00000004
-#define MMCHS_FE_FE_ACTO        0x00000002
-#define MMCHS_FE_FE_ACNE        0x00000001
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_ADMAES register.
-//
-//******************************************************************************
-#define MMCHS_ADMAES_LME        0x00000004  // ADMA Length Mismatch Error: (1)
-                                            // While Block Count Enable being
-                                            // set the total data length
-                                            // specified by the Descriptor table
-                                            // is different from that specified
-                                            // by the Block Count and Block
-                                            // Length. (2) Total data length can
-                                            // not be divided by the block
-                                            // length. 0 No Error 1 Error
-#define MMCHS_ADMAES_AES_M      0x00000003  // ADMA Error State his field
-                                            // indicates the state of ADMA when
-                                            // error is occurred during ADMA
-                                            // data transfer. "This field never
-                                            // indicates ""10"" because ADMA
-                                            // never stops in this state." 0x0
-                                            // ST_STOP (Stop DMA)Contents of
-                                            // SYS_SDR register 0x1 ST_STOP
-                                            // (Stop DMA)Points the error
-                                            // descriptor 0x2 Never set this
-                                            // state(Not used) 0x3 ST_TFR
-                                            // (Transfer Data)Points the next of
-                                            // the error descriptor
-#define MMCHS_ADMAES_AES_S      0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_ADMASAL register.
-//
-//******************************************************************************
-#define MMCHS_ADMASAL_ADMA_A32B_M \
-                                0xFFFFFFFF  // ADMA System address 32 bits.This
-                                            // register holds byte address of
-                                            // executing command of the
-                                            // Descriptor table. 32-bit Address
-                                            // Descriptor uses lower 32-bit of
-                                            // this register. At the start of
-                                            // ADMA the Host Driver shall set
-                                            // start address of the Descriptor
-                                            // table. The ADMA increments this
-                                            // register address which points to
-                                            // next line when every fetching a
-                                            // Descriptor line. When the ADMA
-                                            // Error Interrupt is generated this
-                                            // register shall hold valid
-                                            // Descriptor address depending on
-                                            // the ADMA state. The Host Driver
-                                            // shall program Descriptor Table on
-                                            // 32-bit boundary and set 32-bit
-                                            // boundary address to this
-                                            // register. ADMA2 ignores lower
-                                            // 2-bit of this register and
-                                            // assumes it to be 00b.
-
-#define MMCHS_ADMASAL_ADMA_A32B_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the MMCHS_O_REV register.
-//
-//******************************************************************************
-#define MMCHS_REV_VREV_M        0xFF000000  // Vendor Version Number: IP
-                                            // revision [7:4] Major revision
-                                            // [3:0] Minor revision Examples:
-                                            // 0x10 for 1.0 0x21 for 2.1
-#define MMCHS_REV_VREV_S        24
-#define MMCHS_REV_SREV_M        0x00FF0000
-#define MMCHS_REV_SREV_S        16
-#define MMCHS_REV_SIS           0x00000001  // Slot Interrupt Status This
-                                            // status bit indicates the inverted
-                                            // state of interrupt signal for the
-                                            // module. By a power on reset or by
-                                            // setting a software reset for all
-                                            // (MMCHS_HCTL[SRA]) the interrupt
-                                            // signal shall be de-asserted and
-                                            // this status shall read 0.
-
-
-
-#endif // __HW_MMCHS_H__
diff --git a/cc3200/hal/inc/hw_nvic.h b/cc3200/hal/inc/hw_nvic.h
deleted file mode 100644
index 1545f2265..000000000
--- a/cc3200/hal/inc/hw_nvic.h
+++ /dev/null
@@ -1,1710 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-// hw_nvic.h - Macros used when accessing the NVIC hardware.
-//
-//*****************************************************************************
-
-#ifndef __HW_NVIC_H__
-#define __HW_NVIC_H__
-
-//*****************************************************************************
-//
-// The following are defines for the NVIC register addresses.
-//
-//*****************************************************************************
-#define NVIC_INT_TYPE           0xE000E004  // Interrupt Controller Type Reg
-#define NVIC_ACTLR              0xE000E008  // Auxiliary Control
-#define NVIC_ST_CTRL            0xE000E010  // SysTick Control and Status
-                                            // Register
-#define NVIC_ST_RELOAD          0xE000E014  // SysTick Reload Value Register
-#define NVIC_ST_CURRENT         0xE000E018  // SysTick Current Value Register
-#define NVIC_ST_CAL             0xE000E01C  // SysTick Calibration Value Reg
-
-#define NVIC_EN0                0xE000E100  // Interrupt 0-31 Set Enable
-#define NVIC_EN1                0xE000E104  // Interrupt 32-54 Set Enable
-#define NVIC_EN2                0xE000E108  // Interrupt 64-95 Set Enable
-#define NVIC_EN3                0xE000E10C  // Interrupt 96-127 Set Enable
-#define NVIC_EN4                0xE000E110  // Interrupt 128-131 Set Enable
-#define NVIC_EN5                0xE000E114  // Interrupt 160-191 Set Enable
-
-#define NVIC_DIS0               0xE000E180  // Interrupt 0-31 Clear Enable
-#define NVIC_DIS1               0xE000E184  // Interrupt 32-54 Clear Enable
-
-#define NVIC_DIS2               0xE000E188  // Interrupt 64-95 Clear Enable
-#define NVIC_DIS3               0xE000E18C  // Interrupt 96-127 Clear Enable
-#define NVIC_DIS4               0xE000E190  // Interrupt 128-131 Clear Enable
-#define NVIC_DIS5               0xE000E194  // Interrupt 160-191 Clear Enable
-
-#define NVIC_PEND0              0xE000E200  // Interrupt 0-31 Set Pending
-#define NVIC_PEND1              0xE000E204  // Interrupt 32-54 Set Pending
-
-#define NVIC_PEND2              0xE000E208  // Interrupt 64-95 Set Pending
-#define NVIC_PEND3              0xE000E20C  // Interrupt 96-127 Set Pending
-#define NVIC_PEND4              0xE000E210  // Interrupt 128-131 Set Pending
-#define NVIC_PEND5              0xE000E214  // Interrupt 160-191 Set Pending
-
-#define NVIC_UNPEND0            0xE000E280  // Interrupt 0-31 Clear Pending
-#define NVIC_UNPEND1            0xE000E284  // Interrupt 32-54 Clear Pending
-
-#define NVIC_UNPEND2            0xE000E288  // Interrupt 64-95 Clear Pending
-#define NVIC_UNPEND3            0xE000E28C  // Interrupt 96-127 Clear Pending
-#define NVIC_UNPEND4            0xE000E290  // Interrupt 128-131 Clear Pending
-#define NVIC_UNPEND5            0xE000E294  // Interrupt 160-191 Clear Pending
-
-#define NVIC_ACTIVE0            0xE000E300  // Interrupt 0-31 Active Bit
-#define NVIC_ACTIVE1            0xE000E304  // Interrupt 32-54 Active Bit
-
-#define NVIC_ACTIVE2            0xE000E308  // Interrupt 64-95 Active Bit
-#define NVIC_ACTIVE3            0xE000E30C  // Interrupt 96-127 Active Bit
-#define NVIC_ACTIVE4            0xE000E310  // Interrupt 128-131 Active Bit
-#define NVIC_ACTIVE5            0xE000E314  // Interrupt 160-191 Active Bit
-
-#define NVIC_PRI0               0xE000E400  // Interrupt 0-3 Priority
-#define NVIC_PRI1               0xE000E404  // Interrupt 4-7 Priority
-#define NVIC_PRI2               0xE000E408  // Interrupt 8-11 Priority
-#define NVIC_PRI3               0xE000E40C  // Interrupt 12-15 Priority
-#define NVIC_PRI4               0xE000E410  // Interrupt 16-19 Priority
-#define NVIC_PRI5               0xE000E414  // Interrupt 20-23 Priority
-#define NVIC_PRI6               0xE000E418  // Interrupt 24-27 Priority
-#define NVIC_PRI7               0xE000E41C  // Interrupt 28-31 Priority
-#define NVIC_PRI8               0xE000E420  // Interrupt 32-35 Priority
-#define NVIC_PRI9               0xE000E424  // Interrupt 36-39 Priority
-#define NVIC_PRI10              0xE000E428  // Interrupt 40-43 Priority
-#define NVIC_PRI11              0xE000E42C  // Interrupt 44-47 Priority
-#define NVIC_PRI12              0xE000E430  // Interrupt 48-51 Priority
-#define NVIC_PRI13              0xE000E434  // Interrupt 52-53 Priority
-
-#define NVIC_PRI14              0xE000E438  // Interrupt 56-59 Priority
-#define NVIC_PRI15              0xE000E43C  // Interrupt 60-63 Priority
-#define NVIC_PRI16              0xE000E440  // Interrupt 64-67 Priority
-#define NVIC_PRI17              0xE000E444  // Interrupt 68-71 Priority
-#define NVIC_PRI18              0xE000E448  // Interrupt 72-75 Priority
-#define NVIC_PRI19              0xE000E44C  // Interrupt 76-79 Priority
-#define NVIC_PRI20              0xE000E450  // Interrupt 80-83 Priority
-#define NVIC_PRI21              0xE000E454  // Interrupt 84-87 Priority
-#define NVIC_PRI22              0xE000E458  // Interrupt 88-91 Priority
-#define NVIC_PRI23              0xE000E45C  // Interrupt 92-95 Priority
-#define NVIC_PRI24              0xE000E460  // Interrupt 96-99 Priority
-#define NVIC_PRI25              0xE000E464  // Interrupt 100-103 Priority
-#define NVIC_PRI26              0xE000E468  // Interrupt 104-107 Priority
-#define NVIC_PRI27              0xE000E46C  // Interrupt 108-111 Priority
-#define NVIC_PRI28              0xE000E470  // Interrupt 112-115 Priority
-#define NVIC_PRI29              0xE000E474  // Interrupt 116-119 Priority
-#define NVIC_PRI30              0xE000E478  // Interrupt 120-123 Priority
-#define NVIC_PRI31              0xE000E47C  // Interrupt 124-127 Priority
-#define NVIC_PRI32              0xE000E480  // Interrupt 128-131 Priority
-#define NVIC_PRI33              0xE000E484  // Interrupt 132-135 Priority
-#define NVIC_PRI34              0xE000E488  // Interrupt 136-139 Priority
-#define NVIC_PRI35              0xE000E48C  // Interrupt 140-143 Priority
-#define NVIC_PRI36              0xE000E490  // Interrupt 144-147 Priority
-#define NVIC_PRI37              0xE000E494  // Interrupt 148-151 Priority
-#define NVIC_PRI38              0xE000E498  // Interrupt 152-155 Priority
-#define NVIC_PRI39              0xE000E49C  // Interrupt 156-159 Priority
-#define NVIC_PRI40              0xE000E4A0  // Interrupt 160-163 Priority
-#define NVIC_PRI41              0xE000E4A4  // Interrupt 164-167 Priority
-#define NVIC_PRI42              0xE000E4A8  // Interrupt 168-171 Priority
-#define NVIC_PRI43              0xE000E4AC  // Interrupt 172-175 Priority
-#define NVIC_PRI44              0xE000E4B0  // Interrupt 176-179 Priority
-#define NVIC_PRI45              0xE000E4B4  // Interrupt 180-183 Priority
-#define NVIC_PRI46              0xE000E4B8  // Interrupt 184-187 Priority
-#define NVIC_PRI47              0xE000E4BC  // Interrupt 188-191 Priority
-#define NVIC_PRI48              0xE000E4C0  // Interrupt 192-195 Priority
-
-
-
-#define NVIC_CPUID              0xE000ED00  // CPU ID Base
-#define NVIC_INT_CTRL           0xE000ED04  // Interrupt Control and State
-#define NVIC_VTABLE             0xE000ED08  // Vector Table Offset
-#define NVIC_APINT              0xE000ED0C  // Application Interrupt and Reset
-                                            // Control
-#define NVIC_SYS_CTRL           0xE000ED10  // System Control
-#define NVIC_CFG_CTRL           0xE000ED14  // Configuration and Control
-#define NVIC_SYS_PRI1           0xE000ED18  // System Handler Priority 1
-#define NVIC_SYS_PRI2           0xE000ED1C  // System Handler Priority 2
-#define NVIC_SYS_PRI3           0xE000ED20  // System Handler Priority 3
-#define NVIC_SYS_HND_CTRL       0xE000ED24  // System Handler Control and State
-#define NVIC_FAULT_STAT         0xE000ED28  // Configurable Fault Status
-#define NVIC_HFAULT_STAT        0xE000ED2C  // Hard Fault Status
-#define NVIC_DEBUG_STAT         0xE000ED30  // Debug Status Register
-#define NVIC_MM_ADDR            0xE000ED34  // Memory Management Fault Address
-#define NVIC_FAULT_ADDR         0xE000ED38  // Bus Fault Address
-#define NVIC_MPU_TYPE           0xE000ED90  // MPU Type
-#define NVIC_MPU_CTRL           0xE000ED94  // MPU Control
-#define NVIC_MPU_NUMBER         0xE000ED98  // MPU Region Number
-#define NVIC_MPU_BASE           0xE000ED9C  // MPU Region Base Address
-#define NVIC_MPU_ATTR           0xE000EDA0  // MPU Region Attribute and Size
-#define NVIC_MPU_BASE1          0xE000EDA4  // MPU Region Base Address Alias 1
-#define NVIC_MPU_ATTR1          0xE000EDA8  // MPU Region Attribute and Size
-                                            // Alias 1
-#define NVIC_MPU_BASE2          0xE000EDAC  // MPU Region Base Address Alias 2
-#define NVIC_MPU_ATTR2          0xE000EDB0  // MPU Region Attribute and Size
-                                            // Alias 2
-#define NVIC_MPU_BASE3          0xE000EDB4  // MPU Region Base Address Alias 3
-#define NVIC_MPU_ATTR3          0xE000EDB8  // MPU Region Attribute and Size
-                                            // Alias 3
-#define NVIC_DBG_CTRL           0xE000EDF0  // Debug Control and Status Reg
-#define NVIC_DBG_XFER           0xE000EDF4  // Debug Core Reg. Transfer Select
-#define NVIC_DBG_DATA           0xE000EDF8  // Debug Core Register Data
-#define NVIC_DBG_INT            0xE000EDFC  // Debug Reset Interrupt Control
-#define NVIC_SW_TRIG            0xE000EF00  // Software Trigger Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_INT_TYPE register.
-//
-//*****************************************************************************
-#define NVIC_INT_TYPE_LINES_M   0x0000001F  // Number of interrupt lines (x32)
-#define NVIC_INT_TYPE_LINES_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ACTLR register.
-//
-//*****************************************************************************
-#define NVIC_ACTLR_DISFOLD      0x00000004  // Disable IT Folding
-#define NVIC_ACTLR_DISWBUF      0x00000002  // Disable Write Buffer
-#define NVIC_ACTLR_DISMCYC      0x00000001  // Disable Interrupts of Multiple
-                                            // Cycle Instructions
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ST_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_ST_CTRL_COUNT      0x00010000  // Count Flag
-#define NVIC_ST_CTRL_CLK_SRC    0x00000004  // Clock Source
-#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt Enable
-#define NVIC_ST_CTRL_ENABLE     0x00000001  // Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
-//
-//*****************************************************************************
-#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Reload Value
-#define NVIC_ST_RELOAD_S        0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ST_CURRENT
-// register.
-//
-//*****************************************************************************
-#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Current Value
-#define NVIC_ST_CURRENT_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ST_CAL register.
-//
-//*****************************************************************************
-#define NVIC_ST_CAL_NOREF       0x80000000  // No reference clock
-#define NVIC_ST_CAL_SKEW        0x40000000  // Clock skew
-#define NVIC_ST_CAL_ONEMS_M     0x00FFFFFF  // 1ms reference value
-#define NVIC_ST_CAL_ONEMS_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_EN0 register.
-//
-//*****************************************************************************
-#define NVIC_EN0_INT_M          0xFFFFFFFF  // Interrupt Enable
-#define NVIC_EN0_INT0           0x00000001  // Interrupt 0 enable
-#define NVIC_EN0_INT1           0x00000002  // Interrupt 1 enable
-#define NVIC_EN0_INT2           0x00000004  // Interrupt 2 enable
-#define NVIC_EN0_INT3           0x00000008  // Interrupt 3 enable
-#define NVIC_EN0_INT4           0x00000010  // Interrupt 4 enable
-#define NVIC_EN0_INT5           0x00000020  // Interrupt 5 enable
-#define NVIC_EN0_INT6           0x00000040  // Interrupt 6 enable
-#define NVIC_EN0_INT7           0x00000080  // Interrupt 7 enable
-#define NVIC_EN0_INT8           0x00000100  // Interrupt 8 enable
-#define NVIC_EN0_INT9           0x00000200  // Interrupt 9 enable
-#define NVIC_EN0_INT10          0x00000400  // Interrupt 10 enable
-#define NVIC_EN0_INT11          0x00000800  // Interrupt 11 enable
-#define NVIC_EN0_INT12          0x00001000  // Interrupt 12 enable
-#define NVIC_EN0_INT13          0x00002000  // Interrupt 13 enable
-#define NVIC_EN0_INT14          0x00004000  // Interrupt 14 enable
-#define NVIC_EN0_INT15          0x00008000  // Interrupt 15 enable
-#define NVIC_EN0_INT16          0x00010000  // Interrupt 16 enable
-#define NVIC_EN0_INT17          0x00020000  // Interrupt 17 enable
-#define NVIC_EN0_INT18          0x00040000  // Interrupt 18 enable
-#define NVIC_EN0_INT19          0x00080000  // Interrupt 19 enable
-#define NVIC_EN0_INT20          0x00100000  // Interrupt 20 enable
-#define NVIC_EN0_INT21          0x00200000  // Interrupt 21 enable
-#define NVIC_EN0_INT22          0x00400000  // Interrupt 22 enable
-#define NVIC_EN0_INT23          0x00800000  // Interrupt 23 enable
-#define NVIC_EN0_INT24          0x01000000  // Interrupt 24 enable
-#define NVIC_EN0_INT25          0x02000000  // Interrupt 25 enable
-#define NVIC_EN0_INT26          0x04000000  // Interrupt 26 enable
-#define NVIC_EN0_INT27          0x08000000  // Interrupt 27 enable
-#define NVIC_EN0_INT28          0x10000000  // Interrupt 28 enable
-#define NVIC_EN0_INT29          0x20000000  // Interrupt 29 enable
-#define NVIC_EN0_INT30          0x40000000  // Interrupt 30 enable
-#define NVIC_EN0_INT31          0x80000000  // Interrupt 31 enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_EN1 register.
-//
-//*****************************************************************************
-#define NVIC_EN1_INT_M          0x007FFFFF  // Interrupt Enable
-
-#undef NVIC_EN1_INT_M
-#define NVIC_EN1_INT_M          0xFFFFFFFF  // Interrupt Enable
-
-#define NVIC_EN1_INT32          0x00000001  // Interrupt 32 enable
-#define NVIC_EN1_INT33          0x00000002  // Interrupt 33 enable
-#define NVIC_EN1_INT34          0x00000004  // Interrupt 34 enable
-#define NVIC_EN1_INT35          0x00000008  // Interrupt 35 enable
-#define NVIC_EN1_INT36          0x00000010  // Interrupt 36 enable
-#define NVIC_EN1_INT37          0x00000020  // Interrupt 37 enable
-#define NVIC_EN1_INT38          0x00000040  // Interrupt 38 enable
-#define NVIC_EN1_INT39          0x00000080  // Interrupt 39 enable
-#define NVIC_EN1_INT40          0x00000100  // Interrupt 40 enable
-#define NVIC_EN1_INT41          0x00000200  // Interrupt 41 enable
-#define NVIC_EN1_INT42          0x00000400  // Interrupt 42 enable
-#define NVIC_EN1_INT43          0x00000800  // Interrupt 43 enable
-#define NVIC_EN1_INT44          0x00001000  // Interrupt 44 enable
-#define NVIC_EN1_INT45          0x00002000  // Interrupt 45 enable
-#define NVIC_EN1_INT46          0x00004000  // Interrupt 46 enable
-#define NVIC_EN1_INT47          0x00008000  // Interrupt 47 enable
-#define NVIC_EN1_INT48          0x00010000  // Interrupt 48 enable
-#define NVIC_EN1_INT49          0x00020000  // Interrupt 49 enable
-#define NVIC_EN1_INT50          0x00040000  // Interrupt 50 enable
-#define NVIC_EN1_INT51          0x00080000  // Interrupt 51 enable
-#define NVIC_EN1_INT52          0x00100000  // Interrupt 52 enable
-#define NVIC_EN1_INT53          0x00200000  // Interrupt 53 enable
-#define NVIC_EN1_INT54          0x00400000  // Interrupt 54 enable
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_EN2 register.
-//
-//*****************************************************************************
-#define NVIC_EN2_INT_M          0xFFFFFFFF  // Interrupt Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_EN3 register.
-//
-//*****************************************************************************
-#define NVIC_EN3_INT_M          0xFFFFFFFF  // Interrupt Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_EN4 register.
-//
-//*****************************************************************************
-#define NVIC_EN4_INT_M          0x0000000F  // Interrupt Enable
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DIS0 register.
-//
-//*****************************************************************************
-#define NVIC_DIS0_INT_M         0xFFFFFFFF  // Interrupt Disable
-#define NVIC_DIS0_INT0          0x00000001  // Interrupt 0 disable
-#define NVIC_DIS0_INT1          0x00000002  // Interrupt 1 disable
-#define NVIC_DIS0_INT2          0x00000004  // Interrupt 2 disable
-#define NVIC_DIS0_INT3          0x00000008  // Interrupt 3 disable
-#define NVIC_DIS0_INT4          0x00000010  // Interrupt 4 disable
-#define NVIC_DIS0_INT5          0x00000020  // Interrupt 5 disable
-#define NVIC_DIS0_INT6          0x00000040  // Interrupt 6 disable
-#define NVIC_DIS0_INT7          0x00000080  // Interrupt 7 disable
-#define NVIC_DIS0_INT8          0x00000100  // Interrupt 8 disable
-#define NVIC_DIS0_INT9          0x00000200  // Interrupt 9 disable
-#define NVIC_DIS0_INT10         0x00000400  // Interrupt 10 disable
-#define NVIC_DIS0_INT11         0x00000800  // Interrupt 11 disable
-#define NVIC_DIS0_INT12         0x00001000  // Interrupt 12 disable
-#define NVIC_DIS0_INT13         0x00002000  // Interrupt 13 disable
-#define NVIC_DIS0_INT14         0x00004000  // Interrupt 14 disable
-#define NVIC_DIS0_INT15         0x00008000  // Interrupt 15 disable
-#define NVIC_DIS0_INT16         0x00010000  // Interrupt 16 disable
-#define NVIC_DIS0_INT17         0x00020000  // Interrupt 17 disable
-#define NVIC_DIS0_INT18         0x00040000  // Interrupt 18 disable
-#define NVIC_DIS0_INT19         0x00080000  // Interrupt 19 disable
-#define NVIC_DIS0_INT20         0x00100000  // Interrupt 20 disable
-#define NVIC_DIS0_INT21         0x00200000  // Interrupt 21 disable
-#define NVIC_DIS0_INT22         0x00400000  // Interrupt 22 disable
-#define NVIC_DIS0_INT23         0x00800000  // Interrupt 23 disable
-#define NVIC_DIS0_INT24         0x01000000  // Interrupt 24 disable
-#define NVIC_DIS0_INT25         0x02000000  // Interrupt 25 disable
-#define NVIC_DIS0_INT26         0x04000000  // Interrupt 26 disable
-#define NVIC_DIS0_INT27         0x08000000  // Interrupt 27 disable
-#define NVIC_DIS0_INT28         0x10000000  // Interrupt 28 disable
-#define NVIC_DIS0_INT29         0x20000000  // Interrupt 29 disable
-#define NVIC_DIS0_INT30         0x40000000  // Interrupt 30 disable
-#define NVIC_DIS0_INT31         0x80000000  // Interrupt 31 disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DIS1 register.
-//
-//*****************************************************************************
-#define NVIC_DIS1_INT_M         0x00FFFFFF  // Interrupt Disable
-
-#undef NVIC_DIS1_INT_M
-#define NVIC_DIS1_INT_M         0xFFFFFFFF  // Interrupt Disable
-
-#define NVIC_DIS1_INT32         0x00000001  // Interrupt 32 disable
-#define NVIC_DIS1_INT33         0x00000002  // Interrupt 33 disable
-#define NVIC_DIS1_INT34         0x00000004  // Interrupt 34 disable
-#define NVIC_DIS1_INT35         0x00000008  // Interrupt 35 disable
-#define NVIC_DIS1_INT36         0x00000010  // Interrupt 36 disable
-#define NVIC_DIS1_INT37         0x00000020  // Interrupt 37 disable
-#define NVIC_DIS1_INT38         0x00000040  // Interrupt 38 disable
-#define NVIC_DIS1_INT39         0x00000080  // Interrupt 39 disable
-#define NVIC_DIS1_INT40         0x00000100  // Interrupt 40 disable
-#define NVIC_DIS1_INT41         0x00000200  // Interrupt 41 disable
-#define NVIC_DIS1_INT42         0x00000400  // Interrupt 42 disable
-#define NVIC_DIS1_INT43         0x00000800  // Interrupt 43 disable
-#define NVIC_DIS1_INT44         0x00001000  // Interrupt 44 disable
-#define NVIC_DIS1_INT45         0x00002000  // Interrupt 45 disable
-#define NVIC_DIS1_INT46         0x00004000  // Interrupt 46 disable
-#define NVIC_DIS1_INT47         0x00008000  // Interrupt 47 disable
-#define NVIC_DIS1_INT48         0x00010000  // Interrupt 48 disable
-#define NVIC_DIS1_INT49         0x00020000  // Interrupt 49 disable
-#define NVIC_DIS1_INT50         0x00040000  // Interrupt 50 disable
-#define NVIC_DIS1_INT51         0x00080000  // Interrupt 51 disable
-#define NVIC_DIS1_INT52         0x00100000  // Interrupt 52 disable
-#define NVIC_DIS1_INT53         0x00200000  // Interrupt 53 disable
-#define NVIC_DIS1_INT54         0x00400000  // Interrupt 54 disable
-#define NVIC_DIS1_INT55         0x00800000  // Interrupt 55 disable
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DIS2 register.
-//
-//*****************************************************************************
-#define NVIC_DIS2_INT_M         0xFFFFFFFF  // Interrupt Disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DIS3 register.
-//
-//*****************************************************************************
-#define NVIC_DIS3_INT_M         0xFFFFFFFF  // Interrupt Disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DIS4 register.
-//
-//*****************************************************************************
-#define NVIC_DIS4_INT_M         0x0000000F  // Interrupt Disable
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PEND0 register.
-//
-//*****************************************************************************
-#define NVIC_PEND0_INT_M        0xFFFFFFFF  // Interrupt Set Pending
-#define NVIC_PEND0_INT0         0x00000001  // Interrupt 0 pend
-#define NVIC_PEND0_INT1         0x00000002  // Interrupt 1 pend
-#define NVIC_PEND0_INT2         0x00000004  // Interrupt 2 pend
-#define NVIC_PEND0_INT3         0x00000008  // Interrupt 3 pend
-#define NVIC_PEND0_INT4         0x00000010  // Interrupt 4 pend
-#define NVIC_PEND0_INT5         0x00000020  // Interrupt 5 pend
-#define NVIC_PEND0_INT6         0x00000040  // Interrupt 6 pend
-#define NVIC_PEND0_INT7         0x00000080  // Interrupt 7 pend
-#define NVIC_PEND0_INT8         0x00000100  // Interrupt 8 pend
-#define NVIC_PEND0_INT9         0x00000200  // Interrupt 9 pend
-#define NVIC_PEND0_INT10        0x00000400  // Interrupt 10 pend
-#define NVIC_PEND0_INT11        0x00000800  // Interrupt 11 pend
-#define NVIC_PEND0_INT12        0x00001000  // Interrupt 12 pend
-#define NVIC_PEND0_INT13        0x00002000  // Interrupt 13 pend
-#define NVIC_PEND0_INT14        0x00004000  // Interrupt 14 pend
-#define NVIC_PEND0_INT15        0x00008000  // Interrupt 15 pend
-#define NVIC_PEND0_INT16        0x00010000  // Interrupt 16 pend
-#define NVIC_PEND0_INT17        0x00020000  // Interrupt 17 pend
-#define NVIC_PEND0_INT18        0x00040000  // Interrupt 18 pend
-#define NVIC_PEND0_INT19        0x00080000  // Interrupt 19 pend
-#define NVIC_PEND0_INT20        0x00100000  // Interrupt 20 pend
-#define NVIC_PEND0_INT21        0x00200000  // Interrupt 21 pend
-#define NVIC_PEND0_INT22        0x00400000  // Interrupt 22 pend
-#define NVIC_PEND0_INT23        0x00800000  // Interrupt 23 pend
-#define NVIC_PEND0_INT24        0x01000000  // Interrupt 24 pend
-#define NVIC_PEND0_INT25        0x02000000  // Interrupt 25 pend
-#define NVIC_PEND0_INT26        0x04000000  // Interrupt 26 pend
-#define NVIC_PEND0_INT27        0x08000000  // Interrupt 27 pend
-#define NVIC_PEND0_INT28        0x10000000  // Interrupt 28 pend
-#define NVIC_PEND0_INT29        0x20000000  // Interrupt 29 pend
-#define NVIC_PEND0_INT30        0x40000000  // Interrupt 30 pend
-#define NVIC_PEND0_INT31        0x80000000  // Interrupt 31 pend
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PEND1 register.
-//
-//*****************************************************************************
-#define NVIC_PEND1_INT_M        0x00FFFFFF  // Interrupt Set Pending
-
-#undef NVIC_PEND1_INT_M
-#define NVIC_PEND1_INT_M        0xFFFFFFFF  // Interrupt Set Pending
-
-#define NVIC_PEND1_INT32        0x00000001  // Interrupt 32 pend
-#define NVIC_PEND1_INT33        0x00000002  // Interrupt 33 pend
-#define NVIC_PEND1_INT34        0x00000004  // Interrupt 34 pend
-#define NVIC_PEND1_INT35        0x00000008  // Interrupt 35 pend
-#define NVIC_PEND1_INT36        0x00000010  // Interrupt 36 pend
-#define NVIC_PEND1_INT37        0x00000020  // Interrupt 37 pend
-#define NVIC_PEND1_INT38        0x00000040  // Interrupt 38 pend
-#define NVIC_PEND1_INT39        0x00000080  // Interrupt 39 pend
-#define NVIC_PEND1_INT40        0x00000100  // Interrupt 40 pend
-#define NVIC_PEND1_INT41        0x00000200  // Interrupt 41 pend
-#define NVIC_PEND1_INT42        0x00000400  // Interrupt 42 pend
-#define NVIC_PEND1_INT43        0x00000800  // Interrupt 43 pend
-#define NVIC_PEND1_INT44        0x00001000  // Interrupt 44 pend
-#define NVIC_PEND1_INT45        0x00002000  // Interrupt 45 pend
-#define NVIC_PEND1_INT46        0x00004000  // Interrupt 46 pend
-#define NVIC_PEND1_INT47        0x00008000  // Interrupt 47 pend
-#define NVIC_PEND1_INT48        0x00010000  // Interrupt 48 pend
-#define NVIC_PEND1_INT49        0x00020000  // Interrupt 49 pend
-#define NVIC_PEND1_INT50        0x00040000  // Interrupt 50 pend
-#define NVIC_PEND1_INT51        0x00080000  // Interrupt 51 pend
-#define NVIC_PEND1_INT52        0x00100000  // Interrupt 52 pend
-#define NVIC_PEND1_INT53        0x00200000  // Interrupt 53 pend
-#define NVIC_PEND1_INT54        0x00400000  // Interrupt 54 pend
-#define NVIC_PEND1_INT55        0x00800000  // Interrupt 55 pend
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PEND2 register.
-//
-//*****************************************************************************
-#define NVIC_PEND2_INT_M        0xFFFFFFFF  // Interrupt Set Pending
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PEND3 register.
-//
-//*****************************************************************************
-#define NVIC_PEND3_INT_M        0xFFFFFFFF  // Interrupt Set Pending
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PEND4 register.
-//
-//*****************************************************************************
-#define NVIC_PEND4_INT_M        0x0000000F  // Interrupt Set Pending
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_UNPEND0 register.
-//
-//*****************************************************************************
-#define NVIC_UNPEND0_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
-#define NVIC_UNPEND0_INT0       0x00000001  // Interrupt 0 unpend
-#define NVIC_UNPEND0_INT1       0x00000002  // Interrupt 1 unpend
-#define NVIC_UNPEND0_INT2       0x00000004  // Interrupt 2 unpend
-#define NVIC_UNPEND0_INT3       0x00000008  // Interrupt 3 unpend
-#define NVIC_UNPEND0_INT4       0x00000010  // Interrupt 4 unpend
-#define NVIC_UNPEND0_INT5       0x00000020  // Interrupt 5 unpend
-#define NVIC_UNPEND0_INT6       0x00000040  // Interrupt 6 unpend
-#define NVIC_UNPEND0_INT7       0x00000080  // Interrupt 7 unpend
-#define NVIC_UNPEND0_INT8       0x00000100  // Interrupt 8 unpend
-#define NVIC_UNPEND0_INT9       0x00000200  // Interrupt 9 unpend
-#define NVIC_UNPEND0_INT10      0x00000400  // Interrupt 10 unpend
-#define NVIC_UNPEND0_INT11      0x00000800  // Interrupt 11 unpend
-#define NVIC_UNPEND0_INT12      0x00001000  // Interrupt 12 unpend
-#define NVIC_UNPEND0_INT13      0x00002000  // Interrupt 13 unpend
-#define NVIC_UNPEND0_INT14      0x00004000  // Interrupt 14 unpend
-#define NVIC_UNPEND0_INT15      0x00008000  // Interrupt 15 unpend
-#define NVIC_UNPEND0_INT16      0x00010000  // Interrupt 16 unpend
-#define NVIC_UNPEND0_INT17      0x00020000  // Interrupt 17 unpend
-#define NVIC_UNPEND0_INT18      0x00040000  // Interrupt 18 unpend
-#define NVIC_UNPEND0_INT19      0x00080000  // Interrupt 19 unpend
-#define NVIC_UNPEND0_INT20      0x00100000  // Interrupt 20 unpend
-#define NVIC_UNPEND0_INT21      0x00200000  // Interrupt 21 unpend
-#define NVIC_UNPEND0_INT22      0x00400000  // Interrupt 22 unpend
-#define NVIC_UNPEND0_INT23      0x00800000  // Interrupt 23 unpend
-#define NVIC_UNPEND0_INT24      0x01000000  // Interrupt 24 unpend
-#define NVIC_UNPEND0_INT25      0x02000000  // Interrupt 25 unpend
-#define NVIC_UNPEND0_INT26      0x04000000  // Interrupt 26 unpend
-#define NVIC_UNPEND0_INT27      0x08000000  // Interrupt 27 unpend
-#define NVIC_UNPEND0_INT28      0x10000000  // Interrupt 28 unpend
-#define NVIC_UNPEND0_INT29      0x20000000  // Interrupt 29 unpend
-#define NVIC_UNPEND0_INT30      0x40000000  // Interrupt 30 unpend
-#define NVIC_UNPEND0_INT31      0x80000000  // Interrupt 31 unpend
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_UNPEND1 register.
-//
-//*****************************************************************************
-#define NVIC_UNPEND1_INT_M      0x00FFFFFF  // Interrupt Clear Pending
-
-#undef NVIC_UNPEND1_INT_M
-#define NVIC_UNPEND1_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
-
-#define NVIC_UNPEND1_INT32      0x00000001  // Interrupt 32 unpend
-#define NVIC_UNPEND1_INT33      0x00000002  // Interrupt 33 unpend
-#define NVIC_UNPEND1_INT34      0x00000004  // Interrupt 34 unpend
-#define NVIC_UNPEND1_INT35      0x00000008  // Interrupt 35 unpend
-#define NVIC_UNPEND1_INT36      0x00000010  // Interrupt 36 unpend
-#define NVIC_UNPEND1_INT37      0x00000020  // Interrupt 37 unpend
-#define NVIC_UNPEND1_INT38      0x00000040  // Interrupt 38 unpend
-#define NVIC_UNPEND1_INT39      0x00000080  // Interrupt 39 unpend
-#define NVIC_UNPEND1_INT40      0x00000100  // Interrupt 40 unpend
-#define NVIC_UNPEND1_INT41      0x00000200  // Interrupt 41 unpend
-#define NVIC_UNPEND1_INT42      0x00000400  // Interrupt 42 unpend
-#define NVIC_UNPEND1_INT43      0x00000800  // Interrupt 43 unpend
-#define NVIC_UNPEND1_INT44      0x00001000  // Interrupt 44 unpend
-#define NVIC_UNPEND1_INT45      0x00002000  // Interrupt 45 unpend
-#define NVIC_UNPEND1_INT46      0x00004000  // Interrupt 46 unpend
-#define NVIC_UNPEND1_INT47      0x00008000  // Interrupt 47 unpend
-#define NVIC_UNPEND1_INT48      0x00010000  // Interrupt 48 unpend
-#define NVIC_UNPEND1_INT49      0x00020000  // Interrupt 49 unpend
-#define NVIC_UNPEND1_INT50      0x00040000  // Interrupt 50 unpend
-#define NVIC_UNPEND1_INT51      0x00080000  // Interrupt 51 unpend
-#define NVIC_UNPEND1_INT52      0x00100000  // Interrupt 52 unpend
-#define NVIC_UNPEND1_INT53      0x00200000  // Interrupt 53 unpend
-#define NVIC_UNPEND1_INT54      0x00400000  // Interrupt 54 unpend
-#define NVIC_UNPEND1_INT55      0x00800000  // Interrupt 55 unpend
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_UNPEND2 register.
-//
-//*****************************************************************************
-#define NVIC_UNPEND2_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_UNPEND3 register.
-//
-//*****************************************************************************
-#define NVIC_UNPEND3_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_UNPEND4 register.
-//
-//*****************************************************************************
-#define NVIC_UNPEND4_INT_M      0x0000000F  // Interrupt Clear Pending
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
-//
-//*****************************************************************************
-#define NVIC_ACTIVE0_INT_M      0xFFFFFFFF  // Interrupt Active
-#define NVIC_ACTIVE0_INT0       0x00000001  // Interrupt 0 active
-#define NVIC_ACTIVE0_INT1       0x00000002  // Interrupt 1 active
-#define NVIC_ACTIVE0_INT2       0x00000004  // Interrupt 2 active
-#define NVIC_ACTIVE0_INT3       0x00000008  // Interrupt 3 active
-#define NVIC_ACTIVE0_INT4       0x00000010  // Interrupt 4 active
-#define NVIC_ACTIVE0_INT5       0x00000020  // Interrupt 5 active
-#define NVIC_ACTIVE0_INT6       0x00000040  // Interrupt 6 active
-#define NVIC_ACTIVE0_INT7       0x00000080  // Interrupt 7 active
-#define NVIC_ACTIVE0_INT8       0x00000100  // Interrupt 8 active
-#define NVIC_ACTIVE0_INT9       0x00000200  // Interrupt 9 active
-#define NVIC_ACTIVE0_INT10      0x00000400  // Interrupt 10 active
-#define NVIC_ACTIVE0_INT11      0x00000800  // Interrupt 11 active
-#define NVIC_ACTIVE0_INT12      0x00001000  // Interrupt 12 active
-#define NVIC_ACTIVE0_INT13      0x00002000  // Interrupt 13 active
-#define NVIC_ACTIVE0_INT14      0x00004000  // Interrupt 14 active
-#define NVIC_ACTIVE0_INT15      0x00008000  // Interrupt 15 active
-#define NVIC_ACTIVE0_INT16      0x00010000  // Interrupt 16 active
-#define NVIC_ACTIVE0_INT17      0x00020000  // Interrupt 17 active
-#define NVIC_ACTIVE0_INT18      0x00040000  // Interrupt 18 active
-#define NVIC_ACTIVE0_INT19      0x00080000  // Interrupt 19 active
-#define NVIC_ACTIVE0_INT20      0x00100000  // Interrupt 20 active
-#define NVIC_ACTIVE0_INT21      0x00200000  // Interrupt 21 active
-#define NVIC_ACTIVE0_INT22      0x00400000  // Interrupt 22 active
-#define NVIC_ACTIVE0_INT23      0x00800000  // Interrupt 23 active
-#define NVIC_ACTIVE0_INT24      0x01000000  // Interrupt 24 active
-#define NVIC_ACTIVE0_INT25      0x02000000  // Interrupt 25 active
-#define NVIC_ACTIVE0_INT26      0x04000000  // Interrupt 26 active
-#define NVIC_ACTIVE0_INT27      0x08000000  // Interrupt 27 active
-#define NVIC_ACTIVE0_INT28      0x10000000  // Interrupt 28 active
-#define NVIC_ACTIVE0_INT29      0x20000000  // Interrupt 29 active
-#define NVIC_ACTIVE0_INT30      0x40000000  // Interrupt 30 active
-#define NVIC_ACTIVE0_INT31      0x80000000  // Interrupt 31 active
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
-//
-//*****************************************************************************
-#define NVIC_ACTIVE1_INT_M      0x00FFFFFF  // Interrupt Active
-
-#undef NVIC_ACTIVE1_INT_M
-#define NVIC_ACTIVE1_INT_M      0xFFFFFFFF  // Interrupt Active
-
-#define NVIC_ACTIVE1_INT32      0x00000001  // Interrupt 32 active
-#define NVIC_ACTIVE1_INT33      0x00000002  // Interrupt 33 active
-#define NVIC_ACTIVE1_INT34      0x00000004  // Interrupt 34 active
-#define NVIC_ACTIVE1_INT35      0x00000008  // Interrupt 35 active
-#define NVIC_ACTIVE1_INT36      0x00000010  // Interrupt 36 active
-#define NVIC_ACTIVE1_INT37      0x00000020  // Interrupt 37 active
-#define NVIC_ACTIVE1_INT38      0x00000040  // Interrupt 38 active
-#define NVIC_ACTIVE1_INT39      0x00000080  // Interrupt 39 active
-#define NVIC_ACTIVE1_INT40      0x00000100  // Interrupt 40 active
-#define NVIC_ACTIVE1_INT41      0x00000200  // Interrupt 41 active
-#define NVIC_ACTIVE1_INT42      0x00000400  // Interrupt 42 active
-#define NVIC_ACTIVE1_INT43      0x00000800  // Interrupt 43 active
-#define NVIC_ACTIVE1_INT44      0x00001000  // Interrupt 44 active
-#define NVIC_ACTIVE1_INT45      0x00002000  // Interrupt 45 active
-#define NVIC_ACTIVE1_INT46      0x00004000  // Interrupt 46 active
-#define NVIC_ACTIVE1_INT47      0x00008000  // Interrupt 47 active
-#define NVIC_ACTIVE1_INT48      0x00010000  // Interrupt 48 active
-#define NVIC_ACTIVE1_INT49      0x00020000  // Interrupt 49 active
-#define NVIC_ACTIVE1_INT50      0x00040000  // Interrupt 50 active
-#define NVIC_ACTIVE1_INT51      0x00080000  // Interrupt 51 active
-#define NVIC_ACTIVE1_INT52      0x00100000  // Interrupt 52 active
-#define NVIC_ACTIVE1_INT53      0x00200000  // Interrupt 53 active
-#define NVIC_ACTIVE1_INT54      0x00400000  // Interrupt 54 active
-#define NVIC_ACTIVE1_INT55      0x00800000  // Interrupt 55 active
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ACTIVE2 register.
-//
-//*****************************************************************************
-#define NVIC_ACTIVE2_INT_M      0xFFFFFFFF  // Interrupt Active
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ACTIVE3 register.
-//
-//*****************************************************************************
-#define NVIC_ACTIVE3_INT_M      0xFFFFFFFF  // Interrupt Active
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ACTIVE4 register.
-//
-//*****************************************************************************
-#define NVIC_ACTIVE4_INT_M      0x0000000F  // Interrupt Active
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI0 register.
-//
-//*****************************************************************************
-#define NVIC_PRI0_INT3_M        0xE0000000  // Interrupt 3 Priority Mask
-#define NVIC_PRI0_INT2_M        0x00E00000  // Interrupt 2 Priority Mask
-#define NVIC_PRI0_INT1_M        0x0000E000  // Interrupt 1 Priority Mask
-#define NVIC_PRI0_INT0_M        0x000000E0  // Interrupt 0 Priority Mask
-#define NVIC_PRI0_INT3_S        29
-#define NVIC_PRI0_INT2_S        21
-#define NVIC_PRI0_INT1_S        13
-#define NVIC_PRI0_INT0_S        5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI1 register.
-//
-//*****************************************************************************
-#define NVIC_PRI1_INT7_M        0xE0000000  // Interrupt 7 Priority Mask
-#define NVIC_PRI1_INT6_M        0x00E00000  // Interrupt 6 Priority Mask
-#define NVIC_PRI1_INT5_M        0x0000E000  // Interrupt 5 Priority Mask
-#define NVIC_PRI1_INT4_M        0x000000E0  // Interrupt 4 Priority Mask
-#define NVIC_PRI1_INT7_S        29
-#define NVIC_PRI1_INT6_S        21
-#define NVIC_PRI1_INT5_S        13
-#define NVIC_PRI1_INT4_S        5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI2 register.
-//
-//*****************************************************************************
-#define NVIC_PRI2_INT11_M       0xE0000000  // Interrupt 11 Priority Mask
-#define NVIC_PRI2_INT10_M       0x00E00000  // Interrupt 10 Priority Mask
-#define NVIC_PRI2_INT9_M        0x0000E000  // Interrupt 9 Priority Mask
-#define NVIC_PRI2_INT8_M        0x000000E0  // Interrupt 8 Priority Mask
-#define NVIC_PRI2_INT11_S       29
-#define NVIC_PRI2_INT10_S       21
-#define NVIC_PRI2_INT9_S        13
-#define NVIC_PRI2_INT8_S        5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI3 register.
-//
-//*****************************************************************************
-#define NVIC_PRI3_INT15_M       0xE0000000  // Interrupt 15 Priority Mask
-#define NVIC_PRI3_INT14_M       0x00E00000  // Interrupt 14 Priority Mask
-#define NVIC_PRI3_INT13_M       0x0000E000  // Interrupt 13 Priority Mask
-#define NVIC_PRI3_INT12_M       0x000000E0  // Interrupt 12 Priority Mask
-#define NVIC_PRI3_INT15_S       29
-#define NVIC_PRI3_INT14_S       21
-#define NVIC_PRI3_INT13_S       13
-#define NVIC_PRI3_INT12_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI4 register.
-//
-//*****************************************************************************
-#define NVIC_PRI4_INT19_M       0xE0000000  // Interrupt 19 Priority Mask
-#define NVIC_PRI4_INT18_M       0x00E00000  // Interrupt 18 Priority Mask
-#define NVIC_PRI4_INT17_M       0x0000E000  // Interrupt 17 Priority Mask
-#define NVIC_PRI4_INT16_M       0x000000E0  // Interrupt 16 Priority Mask
-#define NVIC_PRI4_INT19_S       29
-#define NVIC_PRI4_INT18_S       21
-#define NVIC_PRI4_INT17_S       13
-#define NVIC_PRI4_INT16_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI5 register.
-//
-//*****************************************************************************
-#define NVIC_PRI5_INT23_M       0xE0000000  // Interrupt 23 Priority Mask
-#define NVIC_PRI5_INT22_M       0x00E00000  // Interrupt 22 Priority Mask
-#define NVIC_PRI5_INT21_M       0x0000E000  // Interrupt 21 Priority Mask
-#define NVIC_PRI5_INT20_M       0x000000E0  // Interrupt 20 Priority Mask
-#define NVIC_PRI5_INT23_S       29
-#define NVIC_PRI5_INT22_S       21
-#define NVIC_PRI5_INT21_S       13
-#define NVIC_PRI5_INT20_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI6 register.
-//
-//*****************************************************************************
-#define NVIC_PRI6_INT27_M       0xE0000000  // Interrupt 27 Priority Mask
-#define NVIC_PRI6_INT26_M       0x00E00000  // Interrupt 26 Priority Mask
-#define NVIC_PRI6_INT25_M       0x0000E000  // Interrupt 25 Priority Mask
-#define NVIC_PRI6_INT24_M       0x000000E0  // Interrupt 24 Priority Mask
-#define NVIC_PRI6_INT27_S       29
-#define NVIC_PRI6_INT26_S       21
-#define NVIC_PRI6_INT25_S       13
-#define NVIC_PRI6_INT24_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI7 register.
-//
-//*****************************************************************************
-#define NVIC_PRI7_INT31_M       0xE0000000  // Interrupt 31 Priority Mask
-#define NVIC_PRI7_INT30_M       0x00E00000  // Interrupt 30 Priority Mask
-#define NVIC_PRI7_INT29_M       0x0000E000  // Interrupt 29 Priority Mask
-#define NVIC_PRI7_INT28_M       0x000000E0  // Interrupt 28 Priority Mask
-#define NVIC_PRI7_INT31_S       29
-#define NVIC_PRI7_INT30_S       21
-#define NVIC_PRI7_INT29_S       13
-#define NVIC_PRI7_INT28_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI8 register.
-//
-//*****************************************************************************
-#define NVIC_PRI8_INT35_M       0xE0000000  // Interrupt 35 Priority Mask
-#define NVIC_PRI8_INT34_M       0x00E00000  // Interrupt 34 Priority Mask
-#define NVIC_PRI8_INT33_M       0x0000E000  // Interrupt 33 Priority Mask
-#define NVIC_PRI8_INT32_M       0x000000E0  // Interrupt 32 Priority Mask
-#define NVIC_PRI8_INT35_S       29
-#define NVIC_PRI8_INT34_S       21
-#define NVIC_PRI8_INT33_S       13
-#define NVIC_PRI8_INT32_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI9 register.
-//
-//*****************************************************************************
-#define NVIC_PRI9_INT39_M       0xE0000000  // Interrupt 39 Priority Mask
-#define NVIC_PRI9_INT38_M       0x00E00000  // Interrupt 38 Priority Mask
-#define NVIC_PRI9_INT37_M       0x0000E000  // Interrupt 37 Priority Mask
-#define NVIC_PRI9_INT36_M       0x000000E0  // Interrupt 36 Priority Mask
-#define NVIC_PRI9_INT39_S       29
-#define NVIC_PRI9_INT38_S       21
-#define NVIC_PRI9_INT37_S       13
-#define NVIC_PRI9_INT36_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI10 register.
-//
-//*****************************************************************************
-#define NVIC_PRI10_INT43_M      0xE0000000  // Interrupt 43 Priority Mask
-#define NVIC_PRI10_INT42_M      0x00E00000  // Interrupt 42 Priority Mask
-#define NVIC_PRI10_INT41_M      0x0000E000  // Interrupt 41 Priority Mask
-#define NVIC_PRI10_INT40_M      0x000000E0  // Interrupt 40 Priority Mask
-#define NVIC_PRI10_INT43_S      29
-#define NVIC_PRI10_INT42_S      21
-#define NVIC_PRI10_INT41_S      13
-#define NVIC_PRI10_INT40_S      5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI11 register.
-//
-//*****************************************************************************
-#define NVIC_PRI11_INT47_M      0xE0000000  // Interrupt 47 Priority Mask
-#define NVIC_PRI11_INT46_M      0x00E00000  // Interrupt 46 Priority Mask
-#define NVIC_PRI11_INT45_M      0x0000E000  // Interrupt 45 Priority Mask
-#define NVIC_PRI11_INT44_M      0x000000E0  // Interrupt 44 Priority Mask
-#define NVIC_PRI11_INT47_S      29
-#define NVIC_PRI11_INT46_S      21
-#define NVIC_PRI11_INT45_S      13
-#define NVIC_PRI11_INT44_S      5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI12 register.
-//
-//*****************************************************************************
-#define NVIC_PRI12_INT51_M      0xE0000000  // Interrupt 51 Priority Mask
-#define NVIC_PRI12_INT50_M      0x00E00000  // Interrupt 50 Priority Mask
-#define NVIC_PRI12_INT49_M      0x0000E000  // Interrupt 49 Priority Mask
-#define NVIC_PRI12_INT48_M      0x000000E0  // Interrupt 48 Priority Mask
-#define NVIC_PRI12_INT51_S      29
-#define NVIC_PRI12_INT50_S      21
-#define NVIC_PRI12_INT49_S      13
-#define NVIC_PRI12_INT48_S      5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI13 register.
-//
-//*****************************************************************************
-#define NVIC_PRI13_INT55_M      0xE0000000  // Interrupt 55 Priority Mask
-#define NVIC_PRI13_INT54_M      0x00E00000  // Interrupt 54 Priority Mask
-#define NVIC_PRI13_INT53_M      0x0000E000  // Interrupt 53 Priority Mask
-#define NVIC_PRI13_INT52_M      0x000000E0  // Interrupt 52 Priority Mask
-#define NVIC_PRI13_INT55_S      29
-#define NVIC_PRI13_INT54_S      21
-#define NVIC_PRI13_INT53_S      13
-#define NVIC_PRI13_INT52_S      5
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI14 register.
-//
-//*****************************************************************************
-#define NVIC_PRI14_INTD_M       0xE0000000  // Interrupt 59 Priority Mask
-#define NVIC_PRI14_INTC_M       0x00E00000  // Interrupt 58 Priority Mask
-#define NVIC_PRI14_INTB_M       0x0000E000  // Interrupt 57 Priority Mask
-#define NVIC_PRI14_INTA_M       0x000000E0  // Interrupt 56 Priority Mask
-#define NVIC_PRI14_INTD_S       29
-#define NVIC_PRI14_INTC_S       21
-#define NVIC_PRI14_INTB_S       13
-#define NVIC_PRI14_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI15 register.
-//
-//*****************************************************************************
-#define NVIC_PRI15_INTD_M       0xE0000000  // Interrupt 63 Priority Mask
-#define NVIC_PRI15_INTC_M       0x00E00000  // Interrupt 62 Priority Mask
-#define NVIC_PRI15_INTB_M       0x0000E000  // Interrupt 61 Priority Mask
-#define NVIC_PRI15_INTA_M       0x000000E0  // Interrupt 60 Priority Mask
-#define NVIC_PRI15_INTD_S       29
-#define NVIC_PRI15_INTC_S       21
-#define NVIC_PRI15_INTB_S       13
-#define NVIC_PRI15_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI16 register.
-//
-//*****************************************************************************
-#define NVIC_PRI16_INTD_M       0xE0000000  // Interrupt 67 Priority Mask
-#define NVIC_PRI16_INTC_M       0x00E00000  // Interrupt 66 Priority Mask
-#define NVIC_PRI16_INTB_M       0x0000E000  // Interrupt 65 Priority Mask
-#define NVIC_PRI16_INTA_M       0x000000E0  // Interrupt 64 Priority Mask
-#define NVIC_PRI16_INTD_S       29
-#define NVIC_PRI16_INTC_S       21
-#define NVIC_PRI16_INTB_S       13
-#define NVIC_PRI16_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI17 register.
-//
-//*****************************************************************************
-#define NVIC_PRI17_INTD_M       0xE0000000  // Interrupt 71 Priority Mask
-#define NVIC_PRI17_INTC_M       0x00E00000  // Interrupt 70 Priority Mask
-#define NVIC_PRI17_INTB_M       0x0000E000  // Interrupt 69 Priority Mask
-#define NVIC_PRI17_INTA_M       0x000000E0  // Interrupt 68 Priority Mask
-#define NVIC_PRI17_INTD_S       29
-#define NVIC_PRI17_INTC_S       21
-#define NVIC_PRI17_INTB_S       13
-#define NVIC_PRI17_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI18 register.
-//
-//*****************************************************************************
-#define NVIC_PRI18_INTD_M       0xE0000000  // Interrupt 75 Priority Mask
-#define NVIC_PRI18_INTC_M       0x00E00000  // Interrupt 74 Priority Mask
-#define NVIC_PRI18_INTB_M       0x0000E000  // Interrupt 73 Priority Mask
-#define NVIC_PRI18_INTA_M       0x000000E0  // Interrupt 72 Priority Mask
-#define NVIC_PRI18_INTD_S       29
-#define NVIC_PRI18_INTC_S       21
-#define NVIC_PRI18_INTB_S       13
-#define NVIC_PRI18_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI19 register.
-//
-//*****************************************************************************
-#define NVIC_PRI19_INTD_M       0xE0000000  // Interrupt 79 Priority Mask
-#define NVIC_PRI19_INTC_M       0x00E00000  // Interrupt 78 Priority Mask
-#define NVIC_PRI19_INTB_M       0x0000E000  // Interrupt 77 Priority Mask
-#define NVIC_PRI19_INTA_M       0x000000E0  // Interrupt 76 Priority Mask
-#define NVIC_PRI19_INTD_S       29
-#define NVIC_PRI19_INTC_S       21
-#define NVIC_PRI19_INTB_S       13
-#define NVIC_PRI19_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI20 register.
-//
-//*****************************************************************************
-#define NVIC_PRI20_INTD_M       0xE0000000  // Interrupt 83 Priority Mask
-#define NVIC_PRI20_INTC_M       0x00E00000  // Interrupt 82 Priority Mask
-#define NVIC_PRI20_INTB_M       0x0000E000  // Interrupt 81 Priority Mask
-#define NVIC_PRI20_INTA_M       0x000000E0  // Interrupt 80 Priority Mask
-#define NVIC_PRI20_INTD_S       29
-#define NVIC_PRI20_INTC_S       21
-#define NVIC_PRI20_INTB_S       13
-#define NVIC_PRI20_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI21 register.
-//
-//*****************************************************************************
-#define NVIC_PRI21_INTD_M       0xE0000000  // Interrupt 87 Priority Mask
-#define NVIC_PRI21_INTC_M       0x00E00000  // Interrupt 86 Priority Mask
-#define NVIC_PRI21_INTB_M       0x0000E000  // Interrupt 85 Priority Mask
-#define NVIC_PRI21_INTA_M       0x000000E0  // Interrupt 84 Priority Mask
-#define NVIC_PRI21_INTD_S       29
-#define NVIC_PRI21_INTC_S       21
-#define NVIC_PRI21_INTB_S       13
-#define NVIC_PRI21_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI22 register.
-//
-//*****************************************************************************
-#define NVIC_PRI22_INTD_M       0xE0000000  // Interrupt 91 Priority Mask
-#define NVIC_PRI22_INTC_M       0x00E00000  // Interrupt 90 Priority Mask
-#define NVIC_PRI22_INTB_M       0x0000E000  // Interrupt 89 Priority Mask
-#define NVIC_PRI22_INTA_M       0x000000E0  // Interrupt 88 Priority Mask
-#define NVIC_PRI22_INTD_S       29
-#define NVIC_PRI22_INTC_S       21
-#define NVIC_PRI22_INTB_S       13
-#define NVIC_PRI22_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI23 register.
-//
-//*****************************************************************************
-#define NVIC_PRI23_INTD_M       0xE0000000  // Interrupt 95 Priority Mask
-#define NVIC_PRI23_INTC_M       0x00E00000  // Interrupt 94 Priority Mask
-#define NVIC_PRI23_INTB_M       0x0000E000  // Interrupt 93 Priority Mask
-#define NVIC_PRI23_INTA_M       0x000000E0  // Interrupt 92 Priority Mask
-#define NVIC_PRI23_INTD_S       29
-#define NVIC_PRI23_INTC_S       21
-#define NVIC_PRI23_INTB_S       13
-#define NVIC_PRI23_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI24 register.
-//
-//*****************************************************************************
-#define NVIC_PRI24_INTD_M       0xE0000000  // Interrupt 99 Priority Mask
-#define NVIC_PRI24_INTC_M       0x00E00000  // Interrupt 98 Priority Mask
-#define NVIC_PRI24_INTB_M       0x0000E000  // Interrupt 97 Priority Mask
-#define NVIC_PRI24_INTA_M       0x000000E0  // Interrupt 96 Priority Mask
-#define NVIC_PRI24_INTD_S       29
-#define NVIC_PRI24_INTC_S       21
-#define NVIC_PRI24_INTB_S       13
-#define NVIC_PRI24_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI25 register.
-//
-//*****************************************************************************
-#define NVIC_PRI25_INTD_M       0xE0000000  // Interrupt 103 Priority Mask
-#define NVIC_PRI25_INTC_M       0x00E00000  // Interrupt 102 Priority Mask
-#define NVIC_PRI25_INTB_M       0x0000E000  // Interrupt 101 Priority Mask
-#define NVIC_PRI25_INTA_M       0x000000E0  // Interrupt 100 Priority Mask
-#define NVIC_PRI25_INTD_S       29
-#define NVIC_PRI25_INTC_S       21
-#define NVIC_PRI25_INTB_S       13
-#define NVIC_PRI25_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI26 register.
-//
-//*****************************************************************************
-#define NVIC_PRI26_INTD_M       0xE0000000  // Interrupt 107 Priority Mask
-#define NVIC_PRI26_INTC_M       0x00E00000  // Interrupt 106 Priority Mask
-#define NVIC_PRI26_INTB_M       0x0000E000  // Interrupt 105 Priority Mask
-#define NVIC_PRI26_INTA_M       0x000000E0  // Interrupt 104 Priority Mask
-#define NVIC_PRI26_INTD_S       29
-#define NVIC_PRI26_INTC_S       21
-#define NVIC_PRI26_INTB_S       13
-#define NVIC_PRI26_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI27 register.
-//
-//*****************************************************************************
-#define NVIC_PRI27_INTD_M       0xE0000000  // Interrupt 111 Priority Mask
-#define NVIC_PRI27_INTC_M       0x00E00000  // Interrupt 110 Priority Mask
-#define NVIC_PRI27_INTB_M       0x0000E000  // Interrupt 109 Priority Mask
-#define NVIC_PRI27_INTA_M       0x000000E0  // Interrupt 108 Priority Mask
-#define NVIC_PRI27_INTD_S       29
-#define NVIC_PRI27_INTC_S       21
-#define NVIC_PRI27_INTB_S       13
-#define NVIC_PRI27_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI28 register.
-//
-//*****************************************************************************
-#define NVIC_PRI28_INTD_M       0xE0000000  // Interrupt 115 Priority Mask
-#define NVIC_PRI28_INTC_M       0x00E00000  // Interrupt 114 Priority Mask
-#define NVIC_PRI28_INTB_M       0x0000E000  // Interrupt 113 Priority Mask
-#define NVIC_PRI28_INTA_M       0x000000E0  // Interrupt 112 Priority Mask
-#define NVIC_PRI28_INTD_S       29
-#define NVIC_PRI28_INTC_S       21
-#define NVIC_PRI28_INTB_S       13
-#define NVIC_PRI28_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI29 register.
-//
-//*****************************************************************************
-#define NVIC_PRI29_INTD_M       0xE0000000  // Interrupt 119 Priority Mask
-#define NVIC_PRI29_INTC_M       0x00E00000  // Interrupt 118 Priority Mask
-#define NVIC_PRI29_INTB_M       0x0000E000  // Interrupt 117 Priority Mask
-#define NVIC_PRI29_INTA_M       0x000000E0  // Interrupt 116 Priority Mask
-#define NVIC_PRI29_INTD_S       29
-#define NVIC_PRI29_INTC_S       21
-#define NVIC_PRI29_INTB_S       13
-#define NVIC_PRI29_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI30 register.
-//
-//*****************************************************************************
-#define NVIC_PRI30_INTD_M       0xE0000000  // Interrupt 123 Priority Mask
-#define NVIC_PRI30_INTC_M       0x00E00000  // Interrupt 122 Priority Mask
-#define NVIC_PRI30_INTB_M       0x0000E000  // Interrupt 121 Priority Mask
-#define NVIC_PRI30_INTA_M       0x000000E0  // Interrupt 120 Priority Mask
-#define NVIC_PRI30_INTD_S       29
-#define NVIC_PRI30_INTC_S       21
-#define NVIC_PRI30_INTB_S       13
-#define NVIC_PRI30_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI31 register.
-//
-//*****************************************************************************
-#define NVIC_PRI31_INTD_M       0xE0000000  // Interrupt 127 Priority Mask
-#define NVIC_PRI31_INTC_M       0x00E00000  // Interrupt 126 Priority Mask
-#define NVIC_PRI31_INTB_M       0x0000E000  // Interrupt 125 Priority Mask
-#define NVIC_PRI31_INTA_M       0x000000E0  // Interrupt 124 Priority Mask
-#define NVIC_PRI31_INTD_S       29
-#define NVIC_PRI31_INTC_S       21
-#define NVIC_PRI31_INTB_S       13
-#define NVIC_PRI31_INTA_S       5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI32 register.
-//
-//*****************************************************************************
-#define NVIC_PRI32_INTD_M       0xE0000000  // Interrupt 131 Priority Mask
-#define NVIC_PRI32_INTC_M       0x00E00000  // Interrupt 130 Priority Mask
-#define NVIC_PRI32_INTB_M       0x0000E000  // Interrupt 129 Priority Mask
-#define NVIC_PRI32_INTA_M       0x000000E0  // Interrupt 128 Priority Mask
-#define NVIC_PRI32_INTD_S       29
-#define NVIC_PRI32_INTC_S       21
-#define NVIC_PRI32_INTB_S       13
-#define NVIC_PRI32_INTA_S       5
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_CPUID register.
-//
-//*****************************************************************************
-#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer Code
-#define NVIC_CPUID_IMP_ARM      0x41000000  // ARM
-#define NVIC_CPUID_VAR_M        0x00F00000  // Variant Number
-#define NVIC_CPUID_CON_M        0x000F0000  // Constant
-#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Part Number
-#define NVIC_CPUID_PARTNO_CM3   0x0000C230  // Cortex-M3 processor
-
-#define NVIC_CPUID_PARTNO_CM4   0x0000C240  // Cortex-M4 processor
-
-#define NVIC_CPUID_REV_M        0x0000000F  // Revision Number
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_INT_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_INT_CTRL_NMI_SET   0x80000000  // NMI Set Pending
-#define NVIC_INT_CTRL_PEND_SV   0x10000000  // PendSV Set Pending
-#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // PendSV Clear Pending
-#define NVIC_INT_CTRL_PENDSTSET 0x04000000  // SysTick Set Pending
-#define NVIC_INT_CTRL_PENDSTCLR 0x02000000  // SysTick Clear Pending
-#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug Interrupt Handling
-#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Interrupt Pending
-#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000  // Interrupt Pending Vector Number
-
-#undef NVIC_INT_CTRL_VEC_PEN_M
-#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000  // Interrupt Pending Vector Number
-
-#define NVIC_INT_CTRL_VEC_PEN_NMI \
-                                0x00002000  // NMI
-#define NVIC_INT_CTRL_VEC_PEN_HARD \
-                                0x00003000  // Hard fault
-#define NVIC_INT_CTRL_VEC_PEN_MEM \
-                                0x00004000  // Memory management fault
-#define NVIC_INT_CTRL_VEC_PEN_BUS \
-                                0x00005000  // Bus fault
-#define NVIC_INT_CTRL_VEC_PEN_USG \
-                                0x00006000  // Usage fault
-#define NVIC_INT_CTRL_VEC_PEN_SVC \
-                                0x0000B000  // SVCall
-#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
-                                0x0000E000  // PendSV
-#define NVIC_INT_CTRL_VEC_PEN_TICK \
-                                0x0000F000  // SysTick
-#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to Base
-#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F  // Interrupt Pending Vector Number
-
-#undef NVIC_INT_CTRL_VEC_ACT_M
-#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF  // Interrupt Pending Vector Number
-
-#define NVIC_INT_CTRL_VEC_PEN_S 12
-#define NVIC_INT_CTRL_VEC_ACT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_VTABLE register.
-//
-//*****************************************************************************
-#define NVIC_VTABLE_BASE        0x20000000  // Vector Table Base
-#define NVIC_VTABLE_OFFSET_M    0x1FFFFE00  // Vector Table Offset
-
-#undef NVIC_VTABLE_OFFSET_M
-#define NVIC_VTABLE_OFFSET_M    0x1FFFFC00  // Vector Table Offset
-
-#define NVIC_VTABLE_OFFSET_S    9
-
-#undef NVIC_VTABLE_OFFSET_S
-#define NVIC_VTABLE_OFFSET_S    10
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_APINT register.
-//
-//*****************************************************************************
-#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Register Key
-#define NVIC_APINT_VECTKEY      0x05FA0000  // Vector key
-#define NVIC_APINT_ENDIANESS    0x00008000  // Data Endianess
-#define NVIC_APINT_PRIGROUP_M   0x00000700  // Interrupt Priority Grouping
-#define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
-#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
-#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
-#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
-#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
-#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
-#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
-#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
-#define NVIC_APINT_SYSRESETREQ  0x00000004  // System Reset Request
-#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear Active NMI / Fault
-#define NVIC_APINT_VECT_RESET   0x00000001  // System Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wake Up on Pending
-#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep Sleep Enable
-#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR Exit
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_CFG_CTRL_STKALIGN  0x00000200  // Stack Alignment on Exception
-                                            // Entry
-#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore Bus Fault in NMI and
-                                            // Fault
-#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on Divide by 0
-#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on Unaligned Access
-#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow Main Interrupt Trigger
-#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread State Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
-//
-//*****************************************************************************
-#define NVIC_SYS_PRI1_USAGE_M   0x00E00000  // Usage Fault Priority
-#define NVIC_SYS_PRI1_BUS_M     0x0000E000  // Bus Fault Priority
-#define NVIC_SYS_PRI1_MEM_M     0x000000E0  // Memory Management Fault Priority
-#define NVIC_SYS_PRI1_USAGE_S   21
-#define NVIC_SYS_PRI1_BUS_S     13
-#define NVIC_SYS_PRI1_MEM_S     5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
-//
-//*****************************************************************************
-#define NVIC_SYS_PRI2_SVC_M     0xE0000000  // SVCall Priority
-#define NVIC_SYS_PRI2_SVC_S     29
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
-//
-//*****************************************************************************
-#define NVIC_SYS_PRI3_TICK_M    0xE0000000  // SysTick Exception Priority
-#define NVIC_SYS_PRI3_PENDSV_M  0x00E00000  // PendSV Priority
-#define NVIC_SYS_PRI3_DEBUG_M   0x000000E0  // Debug Priority
-#define NVIC_SYS_PRI3_TICK_S    29
-#define NVIC_SYS_PRI3_PENDSV_S  21
-#define NVIC_SYS_PRI3_DEBUG_S   5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
-// register.
-//
-//*****************************************************************************
-#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage Fault Enable
-#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus Fault Enable
-#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Memory Management Fault Enable
-#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVC Call Pending
-#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus Fault Pending
-#define NVIC_SYS_HND_CTRL_MEMP  0x00002000  // Memory Management Fault Pending
-#define NVIC_SYS_HND_CTRL_USAGEP \
-                                0x00001000  // Usage Fault Pending
-#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // SysTick Exception Active
-#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV Exception Active
-#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Debug Monitor Active
-#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVC Call Active
-#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage Fault Active
-#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus Fault Active
-#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Memory Management Fault Active
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_FAULT_STAT
-// register.
-//
-//*****************************************************************************
-#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide-by-Zero Usage Fault
-#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned Access Usage Fault
-#define NVIC_FAULT_STAT_NOCP    0x00080000  // No Coprocessor Usage Fault
-#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC Load Usage Fault
-#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid State Usage Fault
-#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined Instruction Usage
-                                            // Fault
-#define NVIC_FAULT_STAT_BFARV   0x00008000  // Bus Fault Address Register Valid
-
-#define NVIC_FAULT_STAT_BLSPERR 0x00002000  // Bus Fault on Floating-Point Lazy
-                                            // State Preservation
-
-#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack Bus Fault
-#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack Bus Fault
-#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise Data Bus Error
-#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise Data Bus Error
-#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction Bus Error
-#define NVIC_FAULT_STAT_MMARV   0x00000080  // Memory Management Fault Address
-                                            // Register Valid
-
-#define NVIC_FAULT_STAT_MLSPERR 0x00000020  // Memory Management Fault on
-                                            // Floating-Point Lazy State
-                                            // Preservation
-
-#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack Access Violation
-#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack Access Violation
-#define NVIC_FAULT_STAT_DERR    0x00000002  // Data Access Violation
-#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction Access Violation
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_HFAULT_STAT
-// register.
-//
-//*****************************************************************************
-#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug Event
-#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Forced Hard Fault
-#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector Table Read Fault
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DEBUG_STAT
-// register.
-//
-//*****************************************************************************
-#define NVIC_DEBUG_STAT_EXTRNL  0x00000010  // EDBGRQ asserted
-#define NVIC_DEBUG_STAT_VCATCH  0x00000008  // Vector catch
-#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004  // DWT match
-#define NVIC_DEBUG_STAT_BKPT    0x00000002  // Breakpoint instruction
-#define NVIC_DEBUG_STAT_HALTED  0x00000001  // Halt request
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MM_ADDR register.
-//
-//*****************************************************************************
-#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Fault Address
-#define NVIC_MM_ADDR_S          0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_FAULT_ADDR
-// register.
-//
-//*****************************************************************************
-#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Fault Address
-#define NVIC_FAULT_ADDR_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
-//
-//*****************************************************************************
-#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I Regions
-#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D Regions
-#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or Unified MPU
-#define NVIC_MPU_TYPE_IREGION_S 16
-#define NVIC_MPU_TYPE_DREGION_S 8
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU Default Region
-#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU Enabled During Faults
-#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_NUMBER
-// register.
-//
-//*****************************************************************************
-#define NVIC_MPU_NUMBER_M       0x00000007  // MPU Region to Access
-#define NVIC_MPU_NUMBER_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_BASE register.
-//
-//*****************************************************************************
-#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base Address Mask
-#define NVIC_MPU_BASE_VALID     0x00000010  // Region Number Valid
-#define NVIC_MPU_BASE_REGION_M  0x00000007  // Region Number
-#define NVIC_MPU_BASE_ADDR_S    5
-#define NVIC_MPU_BASE_REGION_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
-//
-//*****************************************************************************
-#define NVIC_MPU_ATTR_M         0xFFFF0000  // Attributes
-#define NVIC_MPU_ATTR_XN        0x10000000  // Instruction Access Disable
-#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access Privilege
-#define NVIC_MPU_ATTR_AP_NO_NO  0x00000000  // prv: no access, usr: no access
-#define NVIC_MPU_ATTR_AP_RW_NO  0x01000000  // prv: rw, usr: none
-#define NVIC_MPU_ATTR_AP_RW_RO  0x02000000  // prv: rw, usr: read-only
-#define NVIC_MPU_ATTR_AP_RW_RW  0x03000000  // prv: rw, usr: rw
-#define NVIC_MPU_ATTR_AP_RO_NO  0x05000000  // prv: ro, usr: none
-#define NVIC_MPU_ATTR_AP_RO_RO  0x06000000  // prv: ro, usr: ro
-#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type Extension Mask
-#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
-#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
-#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
-#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Subregion Disable Bits
-#define NVIC_MPU_ATTR_SRD_0     0x00000100  // Sub-region 0 disable
-#define NVIC_MPU_ATTR_SRD_1     0x00000200  // Sub-region 1 disable
-#define NVIC_MPU_ATTR_SRD_2     0x00000400  // Sub-region 2 disable
-#define NVIC_MPU_ATTR_SRD_3     0x00000800  // Sub-region 3 disable
-#define NVIC_MPU_ATTR_SRD_4     0x00001000  // Sub-region 4 disable
-#define NVIC_MPU_ATTR_SRD_5     0x00002000  // Sub-region 5 disable
-#define NVIC_MPU_ATTR_SRD_6     0x00004000  // Sub-region 6 disable
-#define NVIC_MPU_ATTR_SRD_7     0x00008000  // Sub-region 7 disable
-#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region Size Mask
-#define NVIC_MPU_ATTR_SIZE_32B  0x00000008  // Region size 32 bytes
-#define NVIC_MPU_ATTR_SIZE_64B  0x0000000A  // Region size 64 bytes
-#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C  // Region size 128 bytes
-#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E  // Region size 256 bytes
-#define NVIC_MPU_ATTR_SIZE_512B 0x00000010  // Region size 512 bytes
-#define NVIC_MPU_ATTR_SIZE_1K   0x00000012  // Region size 1 Kbytes
-#define NVIC_MPU_ATTR_SIZE_2K   0x00000014  // Region size 2 Kbytes
-#define NVIC_MPU_ATTR_SIZE_4K   0x00000016  // Region size 4 Kbytes
-#define NVIC_MPU_ATTR_SIZE_8K   0x00000018  // Region size 8 Kbytes
-#define NVIC_MPU_ATTR_SIZE_16K  0x0000001A  // Region size 16 Kbytes
-#define NVIC_MPU_ATTR_SIZE_32K  0x0000001C  // Region size 32 Kbytes
-#define NVIC_MPU_ATTR_SIZE_64K  0x0000001E  // Region size 64 Kbytes
-#define NVIC_MPU_ATTR_SIZE_128K 0x00000020  // Region size 128 Kbytes
-#define NVIC_MPU_ATTR_SIZE_256K 0x00000022  // Region size 256 Kbytes
-#define NVIC_MPU_ATTR_SIZE_512K 0x00000024  // Region size 512 Kbytes
-#define NVIC_MPU_ATTR_SIZE_1M   0x00000026  // Region size 1 Mbytes
-#define NVIC_MPU_ATTR_SIZE_2M   0x00000028  // Region size 2 Mbytes
-#define NVIC_MPU_ATTR_SIZE_4M   0x0000002A  // Region size 4 Mbytes
-#define NVIC_MPU_ATTR_SIZE_8M   0x0000002C  // Region size 8 Mbytes
-#define NVIC_MPU_ATTR_SIZE_16M  0x0000002E  // Region size 16 Mbytes
-#define NVIC_MPU_ATTR_SIZE_32M  0x00000030  // Region size 32 Mbytes
-#define NVIC_MPU_ATTR_SIZE_64M  0x00000032  // Region size 64 Mbytes
-#define NVIC_MPU_ATTR_SIZE_128M 0x00000034  // Region size 128 Mbytes
-#define NVIC_MPU_ATTR_SIZE_256M 0x00000036  // Region size 256 Mbytes
-#define NVIC_MPU_ATTR_SIZE_512M 0x00000038  // Region size 512 Mbytes
-#define NVIC_MPU_ATTR_SIZE_1G   0x0000003A  // Region size 1 Gbytes
-#define NVIC_MPU_ATTR_SIZE_2G   0x0000003C  // Region size 2 Gbytes
-#define NVIC_MPU_ATTR_SIZE_4G   0x0000003E  // Region size 4 Gbytes
-#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
-//
-//*****************************************************************************
-#define NVIC_MPU_BASE1_ADDR_M   0xFFFFFFE0  // Base Address Mask
-#define NVIC_MPU_BASE1_VALID    0x00000010  // Region Number Valid
-#define NVIC_MPU_BASE1_REGION_M 0x00000007  // Region Number
-#define NVIC_MPU_BASE1_ADDR_S   5
-#define NVIC_MPU_BASE1_REGION_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
-//
-//*****************************************************************************
-#define NVIC_MPU_ATTR1_XN       0x10000000  // Instruction Access Disable
-#define NVIC_MPU_ATTR1_AP_M     0x07000000  // Access Privilege
-#define NVIC_MPU_ATTR1_TEX_M    0x00380000  // Type Extension Mask
-#define NVIC_MPU_ATTR1_SHAREABLE \
-                                0x00040000  // Shareable
-#define NVIC_MPU_ATTR1_CACHEABLE \
-                                0x00020000  // Cacheable
-#define NVIC_MPU_ATTR1_BUFFRABLE \
-                                0x00010000  // Bufferable
-#define NVIC_MPU_ATTR1_SRD_M    0x0000FF00  // Subregion Disable Bits
-#define NVIC_MPU_ATTR1_SIZE_M   0x0000003E  // Region Size Mask
-#define NVIC_MPU_ATTR1_ENABLE   0x00000001  // Region Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
-//
-//*****************************************************************************
-#define NVIC_MPU_BASE2_ADDR_M   0xFFFFFFE0  // Base Address Mask
-#define NVIC_MPU_BASE2_VALID    0x00000010  // Region Number Valid
-#define NVIC_MPU_BASE2_REGION_M 0x00000007  // Region Number
-#define NVIC_MPU_BASE2_ADDR_S   5
-#define NVIC_MPU_BASE2_REGION_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
-//
-//*****************************************************************************
-#define NVIC_MPU_ATTR2_XN       0x10000000  // Instruction Access Disable
-#define NVIC_MPU_ATTR2_AP_M     0x07000000  // Access Privilege
-#define NVIC_MPU_ATTR2_TEX_M    0x00380000  // Type Extension Mask
-#define NVIC_MPU_ATTR2_SHAREABLE \
-                                0x00040000  // Shareable
-#define NVIC_MPU_ATTR2_CACHEABLE \
-                                0x00020000  // Cacheable
-#define NVIC_MPU_ATTR2_BUFFRABLE \
-                                0x00010000  // Bufferable
-#define NVIC_MPU_ATTR2_SRD_M    0x0000FF00  // Subregion Disable Bits
-#define NVIC_MPU_ATTR2_SIZE_M   0x0000003E  // Region Size Mask
-#define NVIC_MPU_ATTR2_ENABLE   0x00000001  // Region Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
-//
-//*****************************************************************************
-#define NVIC_MPU_BASE3_ADDR_M   0xFFFFFFE0  // Base Address Mask
-#define NVIC_MPU_BASE3_VALID    0x00000010  // Region Number Valid
-#define NVIC_MPU_BASE3_REGION_M 0x00000007  // Region Number
-#define NVIC_MPU_BASE3_ADDR_S   5
-#define NVIC_MPU_BASE3_REGION_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
-//
-//*****************************************************************************
-#define NVIC_MPU_ATTR3_XN       0x10000000  // Instruction Access Disable
-#define NVIC_MPU_ATTR3_AP_M     0x07000000  // Access Privilege
-#define NVIC_MPU_ATTR3_TEX_M    0x00380000  // Type Extension Mask
-#define NVIC_MPU_ATTR3_SHAREABLE \
-                                0x00040000  // Shareable
-#define NVIC_MPU_ATTR3_CACHEABLE \
-                                0x00020000  // Cacheable
-#define NVIC_MPU_ATTR3_BUFFRABLE \
-                                0x00010000  // Bufferable
-#define NVIC_MPU_ATTR3_SRD_M    0x0000FF00  // Subregion Disable Bits
-#define NVIC_MPU_ATTR3_SIZE_M   0x0000003E  // Region Size Mask
-#define NVIC_MPU_ATTR3_ENABLE   0x00000001  // Region Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_DBG_CTRL_DBGKEY_M  0xFFFF0000  // Debug key mask
-#define NVIC_DBG_CTRL_DBGKEY    0xA05F0000  // Debug key
-#define NVIC_DBG_CTRL_S_RESET_ST \
-                                0x02000000  // Core has reset since last read
-#define NVIC_DBG_CTRL_S_RETIRE_ST \
-                                0x01000000  // Core has executed insruction
-                                            // since last read
-#define NVIC_DBG_CTRL_S_LOCKUP  0x00080000  // Core is locked up
-#define NVIC_DBG_CTRL_S_SLEEP   0x00040000  // Core is sleeping
-#define NVIC_DBG_CTRL_S_HALT    0x00020000  // Core status on halt
-#define NVIC_DBG_CTRL_S_REGRDY  0x00010000  // Register read/write available
-#define NVIC_DBG_CTRL_C_SNAPSTALL \
-                                0x00000020  // Breaks a stalled load/store
-#define NVIC_DBG_CTRL_C_MASKINT 0x00000008  // Mask interrupts when stepping
-#define NVIC_DBG_CTRL_C_STEP    0x00000004  // Step the core
-#define NVIC_DBG_CTRL_C_HALT    0x00000002  // Halt the core
-#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001  // Enable debug
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DBG_XFER register.
-//
-//*****************************************************************************
-#define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read
-#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register
-#define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0
-#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
-#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
-#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
-#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
-#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
-#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
-#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
-#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
-#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
-#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
-#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
-#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
-#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
-#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
-#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
-#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
-#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
-#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
-#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
-#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DBG_DATA register.
-//
-//*****************************************************************************
-#define NVIC_DBG_DATA_M         0xFFFFFFFF  // Data temporary cache
-#define NVIC_DBG_DATA_S         0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DBG_INT register.
-//
-//*****************************************************************************
-#define NVIC_DBG_INT_HARDERR    0x00000400  // Debug trap on hard fault
-#define NVIC_DBG_INT_INTERR     0x00000200  // Debug trap on interrupt errors
-#define NVIC_DBG_INT_BUSERR     0x00000100  // Debug trap on bus error
-#define NVIC_DBG_INT_STATERR    0x00000080  // Debug trap on usage fault state
-#define NVIC_DBG_INT_CHKERR     0x00000040  // Debug trap on usage fault check
-#define NVIC_DBG_INT_NOCPERR    0x00000020  // Debug trap on coprocessor error
-#define NVIC_DBG_INT_MMERR      0x00000010  // Debug trap on mem manage fault
-#define NVIC_DBG_INT_RESET      0x00000008  // Core reset status
-#define NVIC_DBG_INT_RSTPENDCLR 0x00000004  // Clear pending core reset
-#define NVIC_DBG_INT_RSTPENDING 0x00000002  // Core reset is pending
-#define NVIC_DBG_INT_RSTVCATCH  0x00000001  // Reset vector catch
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SW_TRIG register.
-//
-//*****************************************************************************
-#define NVIC_SW_TRIG_INTID_M    0x0000003F  // Interrupt ID
-
-#undef NVIC_SW_TRIG_INTID_M
-#define NVIC_SW_TRIG_INTID_M    0x000000FF  // Interrupt ID
-
-#define NVIC_SW_TRIG_INTID_S    0
-
-#endif // __HW_NVIC_H__
diff --git a/cc3200/hal/inc/hw_ocp_shared.h b/cc3200/hal/inc/hw_ocp_shared.h
deleted file mode 100644
index a52f6901b..000000000
--- a/cc3200/hal/inc/hw_ocp_shared.h
+++ /dev/null
@@ -1,3445 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_OCP_SHARED_H__
-#define __HW_OCP_SHARED_H__
-
-//*****************************************************************************
-//
-// The following are defines for the OCP_SHARED register offsets.
-//
-//*****************************************************************************
-#define OCP_SHARED_O_SEMAPHORE1 0x00000000
-#define OCP_SHARED_O_SEMAPHORE2 0x00000004
-#define OCP_SHARED_O_SEMAPHORE3 0x00000008
-#define OCP_SHARED_O_SEMAPHORE4 0x0000000C
-#define OCP_SHARED_O_SEMAPHORE5 0x00000010
-#define OCP_SHARED_O_SEMAPHORE6 0x00000014
-#define OCP_SHARED_O_SEMAPHORE7 0x00000018
-#define OCP_SHARED_O_SEMAPHORE8 0x0000001C
-#define OCP_SHARED_O_SEMAPHORE9 0x00000020
-#define OCP_SHARED_O_SEMAPHORE10 \
-                                0x00000024
-
-#define OCP_SHARED_O_SEMAPHORE11 \
-                                0x00000028
-
-#define OCP_SHARED_O_SEMAPHORE12 \
-                                0x0000002C
-
-#define OCP_SHARED_O_IC_LOCKER_ID \
-                                0x00000030
-
-#define OCP_SHARED_O_MCU_SEMAPHORE_PEND \
-                                0x00000034
-
-#define OCP_SHARED_O_WL_SEMAPHORE_PEND \
-                                0x00000038
-
-#define OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY \
-                                0x0000003C
-
-#define OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY \
-                                0x00000040
-
-#define OCP_SHARED_O_CC3XX_CONFIG_CTRL \
-                                0x00000044
-
-#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB \
-                                0x00000048
-
-#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB \
-                                0x0000004C
-
-#define OCP_SHARED_O_WLAN_ELP_WAKE_EN \
-                                0x00000050
-
-#define OCP_SHARED_O_DEVINIT_ROM_START_ADDR \
-                                0x00000054
-
-#define OCP_SHARED_O_DEVINIT_ROM_END_ADDR \
-                                0x00000058
-
-#define OCP_SHARED_O_SSBD_SEED  0x0000005C
-#define OCP_SHARED_O_SSBD_CHK   0x00000060
-#define OCP_SHARED_O_SSBD_POLY_SEL \
-                                0x00000064
-
-#define OCP_SHARED_O_SPARE_REG_0 \
-                                0x00000068
-
-#define OCP_SHARED_O_SPARE_REG_1 \
-                                0x0000006C
-
-#define OCP_SHARED_O_SPARE_REG_2 \
-                                0x00000070
-
-#define OCP_SHARED_O_SPARE_REG_3 \
-                                0x00000074
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_0 \
-                                0x000000A0
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_1 \
-                                0x000000A4
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_2 \
-                                0x000000A8
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_3 \
-                                0x000000AC
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_4 \
-                                0x000000B0
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_5 \
-                                0x000000B4
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_6 \
-                                0x000000B8
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_7 \
-                                0x000000BC
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_8 \
-                                0x000000C0
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_9 \
-                                0x000000C4
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_10 \
-                                0x000000C8
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_11 \
-                                0x000000CC
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_12 \
-                                0x000000D0
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_13 \
-                                0x000000D4
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_14 \
-                                0x000000D8
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_15 \
-                                0x000000DC
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_16 \
-                                0x000000E0
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_17 \
-                                0x000000E4
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_18 \
-                                0x000000E8
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_19 \
-                                0x000000EC
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_20 \
-                                0x000000F0
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_21 \
-                                0x000000F4
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_22 \
-                                0x000000F8
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_23 \
-                                0x000000FC
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_24 \
-                                0x00000100
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_25 \
-                                0x00000104
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_26 \
-                                0x00000108
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_27 \
-                                0x0000010C
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_28 \
-                                0x00000110
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_29 \
-                                0x00000114
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_30 \
-                                0x00000118
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_31 \
-                                0x0000011C
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_32 \
-                                0x00000120
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_33 \
-                                0x00000124
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_34 \
-                                0x00000128
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_35 \
-                                0x0000012C
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_36 \
-                                0x00000130
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_37 \
-                                0x00000134
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_38 \
-                                0x00000138
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_39 \
-                                0x0000013C
-
-#define OCP_SHARED_O_GPIO_PAD_CONFIG_40 \
-                                0x00000140
-
-#define OCP_SHARED_O_GPIO_PAD_CMN_CONFIG \
-                                0x00000144  // This register provide control to
-                                            // GPIO_CC3XXV1 IO PAD. Common
-                                            // control signals to all bottom Die
-                                            // IO's are controlled via this.
-
-#define OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG \
-                                0x00000148
-
-#define OCP_SHARED_O_D2D_TOSTACK_PAD_CONF \
-                                0x0000014C
-
-#define OCP_SHARED_O_D2D_MISC_PAD_CONF \
-                                0x00000150
-
-#define OCP_SHARED_O_SOP_CONF_OVERRIDE \
-                                0x00000154
-
-#define OCP_SHARED_O_CC3XX_DEBUGSS_STATUS \
-                                0x00000158
-
-#define OCP_SHARED_O_CC3XX_DEBUGMUX_SEL \
-                                0x0000015C
-
-#define OCP_SHARED_O_ALT_PC_VAL_NW \
-                                0x00000160
-
-#define OCP_SHARED_O_ALT_PC_VAL_APPS \
-                                0x00000164
-
-#define OCP_SHARED_O_SPARE_REG_4 \
-                                0x00000168
-
-#define OCP_SHARED_O_SPARE_REG_5 \
-                                0x0000016C
-
-#define OCP_SHARED_O_SH_SPI_CS_MASK \
-                                0x00000170
-
-#define OCP_SHARED_O_CC3XX_DEVICE_TYPE \
-                                0x00000174
-
-#define OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE \
-                                0x00000178
-
-#define OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT \
-                                0x0000017C
-
-#define OCP_SHARED_O_AUTONMS_SPICLK_SEL \
-                                0x00000180
-
-#define OCP_SHARED_O_CC3XX_DEV_PADCONF \
-                                0x00000184
-
-#define OCP_SHARED_O_SPARE_REG_8 \
-                                0x00000188
-
-#define OCP_SHARED_O_SPARE_REG_6 \
-                                0x0000018C
-
-#define OCP_SHARED_O_SPARE_REG_7 \
-                                0x00000190
-
-#define OCP_SHARED_O_APPS_WLAN_ORBIT \
-                                0x00000194
-
-#define OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD \
-                                0x00000198
-
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SEMAPHORE1 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_M \
-                                0x00000003  // General Purpose Semaphore for SW
-                                            // Usage. If any of the 2 bits of a
-                                            // given register is set to 1, it
-                                            // means that the semaphore is
-                                            // locked by one of the masters.
-                                            // Each bit represents a master IP
-                                            // as follows: {WLAN,NWP}. The JTAG
-                                            // cannot capture the semaphore but
-                                            // it can release it. As a master IP
-                                            // reads the semaphore, it will be
-                                            // caputed and the masters
-                                            // correlating bit will be set to 1
-                                            // (set upon read). As any IP writes
-                                            // to this address (independent of
-                                            // the written data) the semaphore
-                                            // will be set to 2'b00.
-
-#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SEMAPHORE2 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_M \
-                                0x00000003  // General Purpose Semaphore for SW
-                                            // Usage. If any of the 2 bits of a
-                                            // given register is set to 1, it
-                                            // means that the semaphore is
-                                            // locked by one of the masters.
-                                            // Each bit represents a master IP
-                                            // as follows: {WLAN,NWP}. The JTAG
-                                            // cannot capture the semaphore but
-                                            // it can release it. As a master IP
-                                            // reads the semaphore, it will be
-                                            // caputed and the masters
-                                            // correlating bit will be set to 1
-                                            // (set upon read). As any IP writes
-                                            // to this address (independent of
-                                            // the written data) the semaphore
-                                            // will be set to 2'b00.
-
-#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SEMAPHORE3 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_M \
-                                0x00000003  // General Purpose Semaphore for SW
-                                            // Usage. If any of the 2 bits of a
-                                            // given register is set to 1, it
-                                            // means that the semaphore is
-                                            // locked by one of the masters.
-                                            // Each bit represents a master IP
-                                            // as follows: {WLAN,NWP}. The JTAG
-                                            // cannot capture the semaphore but
-                                            // it can release it. As a master IP
-                                            // reads the semaphore, it will be
-                                            // caputed and the masters
-                                            // correlating bit will be set to 1
-                                            // (set upon read). As any IP writes
-                                            // to this address (independent of
-                                            // the written data) the semaphore
-                                            // will be set to 2'b00.
-
-#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SEMAPHORE4 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_M \
-                                0x00000003  // General Purpose Semaphore for SW
-                                            // Usage. If any of the 2 bits of a
-                                            // given register is set to 1, it
-                                            // means that the semaphore is
-                                            // locked by one of the masters.
-                                            // Each bit represents a master IP
-                                            // as follows: {WLAN,NWP}. The JTAG
-                                            // cannot capture the semaphore but
-                                            // it can release it. As a master IP
-                                            // reads the semaphore, it will be
-                                            // caputed and the masters
-                                            // correlating bit will be set to 1
-                                            // (set upon read). As any IP writes
-                                            // to this address (independent of
-                                            // the written data) the semaphore
-                                            // will be set to 2'b00.
-
-#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SEMAPHORE5 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_M \
-                                0x00000003  // General Purpose Semaphore for SW
-                                            // Usage. If any of the 2 bits of a
-                                            // given register is set to 1, it
-                                            // means that the semaphore is
-                                            // locked by one of the masters.
-                                            // Each bit represents a master IP
-                                            // as follows: {WLAN,NWP}. The JTAG
-                                            // cannot capture the semaphore but
-                                            // it can release it. As a master IP
-                                            // reads the semaphore, it will be
-                                            // caputed and the masters
-                                            // correlating bit will be set to 1
-                                            // (set upon read). As any IP writes
-                                            // to this address (independent of
-                                            // the written data) the semaphore
-                                            // will be set to 2'b00.
-
-#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SEMAPHORE6 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_M \
-                                0x00000003  // General Purpose Semaphore for SW
-                                            // Usage. If any of the 2 bits of a
-                                            // given register is set to 1, it
-                                            // means that the semaphore is
-                                            // locked by one of the masters.
-                                            // Each bit represents a master IP
-                                            // as follows: {WLAN,NWP}. The JTAG
-                                            // cannot capture the semaphore but
-                                            // it can release it. As a master IP
-                                            // reads the semaphore, it will be
-                                            // caputed and the masters
-                                            // correlating bit will be set to 1
-                                            // (set upon read). As any IP writes
-                                            // to this address (independent of
-                                            // the written data) the semaphore
-                                            // will be set to 2'b00.
-
-#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SEMAPHORE7 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_M \
-                                0x00000003  // General Purpose Semaphore for SW
-                                            // Usage. If any of the 2 bits of a
-                                            // given register is set to 1, it
-                                            // means that the semaphore is
-                                            // locked by one of the masters.
-                                            // Each bit represents a master IP
-                                            // as follows: {WLAN,NWP}. The JTAG
-                                            // cannot capture the semaphore but
-                                            // it can release it. As a master IP
-                                            // reads the semaphore, it will be
-                                            // caputed and the masters
-                                            // correlating bit will be set to 1
-                                            // (set upon read). As any IP writes
-                                            // to this address (independent of
-                                            // the written data) the semaphore
-                                            // will be set to 2'b00.
-
-#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SEMAPHORE8 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_M \
-                                0x00000003  // General Purpose Semaphore for SW
-                                            // Usage. If any of the 2 bits of a
-                                            // given register is set to 1, it
-                                            // means that the semaphore is
-                                            // locked by one of the masters.
-                                            // Each bit represents a master IP
-                                            // as follows: {WLAN,NWP}. The JTAG
-                                            // cannot capture the semaphore but
-                                            // it can release it. As a master IP
-                                            // reads the semaphore, it will be
-                                            // caputed and the masters
-                                            // correlating bit will be set to 1
-                                            // (set upon read). As any IP writes
-                                            // to this address (independent of
-                                            // the written data) the semaphore
-                                            // will be set to 2'b00.
-
-#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SEMAPHORE9 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_M \
-                                0x00000003  // General Purpose Semaphore for SW
-                                            // Usage. If any of the 2 bits of a
-                                            // given register is set to 1, it
-                                            // means that the semaphore is
-                                            // locked by one of the masters.
-                                            // Each bit represents a master IP
-                                            // as follows: {WLAN,NWP}. The JTAG
-                                            // cannot capture the semaphore but
-                                            // it can release it. As a master IP
-                                            // reads the semaphore, it will be
-                                            // caputed and the masters
-                                            // correlating bit will be set to 1
-                                            // (set upon read). As any IP writes
-                                            // to this address (independent of
-                                            // the written data) the semaphore
-                                            // will be set to 2'b00.
-
-#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SEMAPHORE10 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_M \
-                                0x00000003  // General Purpose Semaphore for SW
-                                            // Usage. If any of the 2 bits of a
-                                            // given register is set to 1, it
-                                            // means that the semaphore is
-                                            // locked by one of the masters.
-                                            // Each bit represents a master IP
-                                            // as follows: {WLAN,NWP}. The JTAG
-                                            // cannot capture the semaphore but
-                                            // it can release it. As a master IP
-                                            // reads the semaphore, it will be
-                                            // caputed and the masters
-                                            // correlating bit will be set to 1
-                                            // (set upon read). As any IP writes
-                                            // to this address (independent of
-                                            // the written data) the semaphore
-                                            // will be set to 2'b00.
-
-#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SEMAPHORE11 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_M \
-                                0x00000003  // General Purpose Semaphore for SW
-                                            // Usage. If any of the 2 bits of a
-                                            // given register is set to 1, it
-                                            // means that the semaphore is
-                                            // locked by one of the masters.
-                                            // Each bit represents a master IP
-                                            // as follows: {WLAN,NWP}. The JTAG
-                                            // cannot capture the semaphore but
-                                            // it can release it. As a master IP
-                                            // reads the semaphore, it will be
-                                            // caputed and the masters
-                                            // correlating bit will be set to 1
-                                            // (set upon read). As any IP writes
-                                            // to this address (independent of
-                                            // the written data) the semaphore
-                                            // will be set to 2'b00.
-
-#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SEMAPHORE12 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_M \
-                                0x00000003  // General Purpose Semaphore for SW
-                                            // Usage. If any of the 2 bits of a
-                                            // given register is set to 1, it
-                                            // means that the semaphore is
-                                            // locked by one of the masters.
-                                            // Each bit represents a master IP
-                                            // as follows: {WLAN,NWP}. The JTAG
-                                            // cannot capture the semaphore but
-                                            // it can release it. As a master IP
-                                            // reads the semaphore, it will be
-                                            // caputed and the masters
-                                            // correlating bit will be set to 1
-                                            // (set upon read). As any IP writes
-                                            // to this address (independent of
-                                            // the written data) the semaphore
-                                            // will be set to 2'b00.
-
-#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_IC_LOCKER_ID register.
-//
-//******************************************************************************
-#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_M \
-                                0x00000007  // This register is used for
-                                            // allowing only one master OCP to
-                                            // perform write transactions to the
-                                            // OCP slaves. Each bit represents
-                                            // an IP in the following format: {
-                                            // JTAG,WLAN, NWP mcu}. As any of
-                                            // the bits is set to one, the
-                                            // correlating IP is preventing the
-                                            // other IP's from performing write
-                                            // transactions to the slaves. As
-                                            // the Inter Connect is locked, the
-                                            // only the locking IP can write to
-                                            // the register and by that
-                                            // releasing the lock. 3'b000 => IC
-                                            // is not locked. 3'b001 => IC is
-                                            // locked by NWP mcu. 3'b010 => IC
-                                            // is locked by WLAN. 3'b100 => IC
-                                            // is locked by JTAG.
-
-#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_MCU_SEMAPHORE_PEND register.
-//
-//******************************************************************************
-#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_M \
-                                0x0000FFFF  // This register specifies the
-                                            // semaphore for which the NWP mcu
-                                            // is waiting to be released. It is
-                                            // set to the serial number of a
-                                            // given locked semaphore after it
-                                            // was read by the NWP mcu. Only
-                                            // [11:0] is used.
-
-#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_WL_SEMAPHORE_PEND register.
-//
-//******************************************************************************
-#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_M \
-                                0x0000FFFF  // This register specifies the
-                                            // semaphore for which the WLAN is
-                                            // waiting to be released. It is set
-                                            // to the serial number of a given
-                                            // locked semaphore after it was
-                                            // read by the WLAN. Only [11:0] is
-                                            // used.
-
-#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY register.
-//
-//******************************************************************************
-#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_M \
-                                0x0000FFFF  // This information serves the IPs
-                                            // for knowing in which platform are
-                                            // they integrated at: 0 = CC31XX.
-
-#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY register.
-//
-//******************************************************************************
-#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_M \
-                                0x00000FFF  // Captured/released semaphores
-                                            // status for the 12 semaphores.
-                                            // Each bit of the 12 bits
-                                            // represents a semaphore. 0 =>
-                                            // Semaphore Free. 1 => Semaphore
-                                            // Captured.
-
-#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_CC3XX_CONFIG_CTRL register.
-//
-//******************************************************************************
-#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_IC_TO_EN \
-                                0x00000010  // This bit is used to enable
-                                            // timeout mechanism for top_ocp_ic
-                                            // (for debug puropse). When 1 value
-                                            // , in case any ocp slave doesn't
-                                            // give sresponse within 16 cylcles
-                                            // top_ic will give error response
-                                            // itself to avoid bus hange.
-
-#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_APPS \
-                                0x00000008  // 1 bit should be accessible only
-                                            // in devinit. This will enable 0x4
-                                            // hack for apps processor
-
-#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_NW \
-                                0x00000004  // 1 bit, should be accessible only
-                                            // in devinit. This will enable 0x4
-                                            // hack for nw processor
-
-#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_EXTEND_NW_ROM \
-                                0x00000002  // When set NW can take over apps
-                                            // rom and flash via IDCODE bus.
-                                            // Apps will able to access this
-                                            // register only during devinit and
-                                            // reset value should be 0.
-
-#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_WLAN_HOST_INTF_SEL \
-                                0x00000001  // When this bit is set to 0 WPSI
-                                            // host interface wil be selected,
-                                            // when this bit is set to 1 , WLAN
-                                            // host async bridge will be
-                                            // selected.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB register.
-//
-//******************************************************************************
-#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_M \
-                                0x3FFFFFFF  // This register provides memss RAM
-                                            // column configuration for column 0
-                                            // to 9. 3 bits are allocated per
-                                            // column. This register is required
-                                            // to be configured before starting
-                                            // RAM access. Changing register
-                                            // setting while code is running
-                                            // will result into unpredictable
-                                            // memory behaviour. Register is
-                                            // supported to configured ones
-                                            // after core is booted up. 3 bit
-                                            // encoding per column is as
-                                            // follows: when 000 : WLAN, 001:
-                                            // NWP, 010: APPS, 011: PHY, 100:
-                                            // OCLA column 0 select: bit [2:0]
-                                            // :when 000 -> WLAN,001 -> NWP,010
-                                            // -> APPS, 011 -> PHY, 100 -> OCLA
-                                            // column 1 select: bit [5:3]
-                                            // :column 2 select: bit [8 : 6]:
-                                            // column 3 select : bit [11: 9]
-                                            // column 4 select : bit [14:12]
-                                            // column 5 select : bit [17:15]
-                                            // column 6 select : bit [20:18]
-                                            // column 7 select : bit [23:21]
-                                            // column 8 select : bit [26:24]
-                                            // column 9 select : bit [29:27]
-                                            // column 10 select
-
-#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB register.
-//
-//******************************************************************************
-#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_M \
-                                0x00000FFF  // This register provides memss RAM
-                                            // column configuration for column
-                                            // 10 to 15. 3 bits are allocated
-                                            // per column. This register is
-                                            // required to be configured before
-                                            // starting RAM access. Changing
-                                            // register setting while code is
-                                            // running will result into
-                                            // unpredictable memory behaviour.
-                                            // Register is supported to
-                                            // configured ones after core is
-                                            // booted up. 3 bit encoding per
-                                            // column is as follows: when 000 :
-                                            // WLAN, 001: NWP, 010: APPS, 011:
-                                            // PHY, 100: OCLA column 11 select :
-                                            // bit [2:0] column 12 select : bit
-                                            // [5:3] column 13 select : bit [8 :
-                                            // 6] column 14 select :
-
-#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_WLAN_ELP_WAKE_EN register.
-//
-//******************************************************************************
-#define OCP_SHARED_WLAN_ELP_WAKE_EN_MEM_WLAN_ELP_WAKE_EN \
-                                0x00000001  // when '1' : signal will enabled
-                                            // ELP power doamin when '0': ELP is
-                                            // not powered up.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_DEVINIT_ROM_START_ADDR register.
-//
-//******************************************************************************
-#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_M \
-                                0xFFFFFFFF  // 32 bit, Writable only during
-                                            // devinit, and whole 32 bit should
-                                            // be output of the config register
-                                            // module. This register is not used
-                                            // , similar register availble in
-                                            // GPRCM space.
-
-#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_DEVINIT_ROM_END_ADDR register.
-//
-//******************************************************************************
-#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_M \
-                                0xFFFFFFFF  // 32 bit, Writable only during
-                                            // devinit, and whole 32 bit should
-                                            // be output of the config register
-                                            // module.
-
-#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SSBD_SEED register.
-//
-//******************************************************************************
-#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_M \
-                                0xFFFFFFFF  // 32 bit, Writable only during
-                                            // devinit, and whole 32 bit should
-                                            // be output of the config register
-                                            // module.
-
-#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SSBD_CHK register.
-//
-//******************************************************************************
-#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_M \
-                                0xFFFFFFFF  // 32 bit, Writable only during
-                                            // devinit, and whole 32 bit should
-                                            // be output of the config register
-                                            // module.
-
-#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SSBD_POLY_SEL register.
-//
-//******************************************************************************
-#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_M \
-                                0x00000003  // 2 bit, Writable only during
-                                            // devinit, and whole 2 bit should
-                                            // be output of the config register
-                                            // module.
-
-#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SPARE_REG_0 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_M \
-                                0xFFFFFFFF  // Devinit code should look for
-                                            // whether corresponding fuse is
-                                            // blown and if blown write to the
-                                            // 11th bit of this register to
-                                            // disable flshtst interface
-
-#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SPARE_REG_1 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_M \
-                                0xFFFFFFFF  // NWP Software register
-
-#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SPARE_REG_2 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_M \
-                                0xFFFFFFFF  // NWP Software register
-
-#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SPARE_REG_3 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_M \
-                                0xFFFFFFFF  // APPS Software register
-
-#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_0 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." "For example in
-                                            // case of I2C Value gets latched at
-                                            // rising edge of RET33.""" """ 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_1 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_2 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_3 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_4 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_5 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_6 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_7 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_8 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_9 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_10 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_11 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_12 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_13 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_14 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_15 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_16 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_17 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_18 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_19 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_20 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_21 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_22 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_23 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_24 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_25 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_26 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_27 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_28 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_29 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_30 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_31 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_32 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_M \
-                                0x00000FFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." it can be used
-                                            // for I2C type of peripherals. 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_33 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_M \
-                                0x0000003F  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 5 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'. IODEN and I8MAEN
-                                            // is diesabled for all development
-                                            // IO's. These signals are tied to
-                                            // logic level '0'. common control
-                                            // is implemented for I2MAEN,
-                                            // I4MAEN, WKPU, WKPD control .
-                                            // refer dev_pad_cmn_config register
-                                            // bits.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_34 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_M \
-                                0x0000003F  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 5 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'. IODEN and I8MAEN
-                                            // is diesabled for all development
-                                            // IO's. These signals are tied to
-                                            // logic level '0'. common control
-                                            // is implemented for I2MAEN,
-                                            // I4MAEN, WKPU, WKPD control .
-                                            // refer dev_pad_cmn_config register
-                                            // bits.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_35 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_M \
-                                0x0000003F  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 5 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'. IODEN and I8MAEN
-                                            // is diesabled for all development
-                                            // IO's. These signals are tied to
-                                            // logic level '0'. common control
-                                            // is implemented for I2MAEN,
-                                            // I4MAEN, WKPU, WKPD control .
-                                            // refer dev_pad_cmn_config register
-                                            // bits.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_36 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_M \
-                                0x0000003F  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 5 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'. IODEN and I8MAEN
-                                            // is diesabled for all development
-                                            // IO's. These signals are tied to
-                                            // logic level '0'. common control
-                                            // is implemented for I2MAEN,
-                                            // I4MAEN, WKPU, WKPD control .
-                                            // refer dev_pad_cmn_config register
-                                            // bits.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_37 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_M \
-                                0x0000003F  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 5 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'. IODEN and I8MAEN
-                                            // is diesabled for all development
-                                            // IO's. These signals are tied to
-                                            // logic level '0'. common control
-                                            // is implemented for I2MAEN,
-                                            // I4MAEN, WKPU, WKPD control .
-                                            // refer dev_pad_cmn_config register
-                                            // bits.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_38 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_M \
-                                0x0000003F  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 5 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'. IODEN and I8MAEN
-                                            // is diesabled for all development
-                                            // IO's. These signals are tied to
-                                            // logic level '0'. common control
-                                            // is implemented for I2MAEN,
-                                            // I4MAEN, WKPU, WKPD control .
-                                            // refer dev_pad_cmn_config register
-                                            // bits.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_39 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_M \
-                                0x0000003F  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 5 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'. IODEN and I8MAEN
-                                            // is diesabled for all development
-                                            // IO's. These signals are tied to
-                                            // logic level '0'. common control
-                                            // is implemented for I2MAEN,
-                                            // I4MAEN, WKPU, WKPD control .
-                                            // refer dev_pad_cmn_config register
-                                            // bits.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CONFIG_40 register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_M \
-                                0x0007FFFF  // GPIO 0 register: "Bit 0 - 3 is
-                                            // used for PAD IO mode selection.
-                                            // io_register={ "" 0 =>
-                                            // """"CONFMODE[0]"""""" "" 1 =>
-                                            // """"CONFMODE[1]"""""" "" 2 =>
-                                            // """"CONFMODE[2]"""""" "" 3 =>
-                                            // """"CONFMODE[3]"""" 4 =>
-                                            // """"IODEN"""" --> When level ‘1’
-                                            // this disables the PMOS xtors of
-                                            // the output stages making them
-                                            // open-drain type." "For example in
-                                            // case of I2C Value gets latched at
-                                            // rising edge of RET33.""" """ 5 =>
-                                            // """"I2MAEN"""" --> Level ‘1’
-                                            // enables the approx 2mA output
-                                            // stage""" """ 6 => """"I4MAEN""""
-                                            // --> Level ‘1’ enables the approx
-                                            // 4mA output stage""" """ 7 =>
-                                            // """"I8MAEN"""" --> Level ‘1’
-                                            // enables the approx 8mA output
-                                            // stage. Note: any drive strength
-                                            // between 2mA and 14mA can be
-                                            // obtained with combination of 2mA
-                                            // 4mA and 8mA.""" """ 8 =>
-                                            // """"IWKPUEN"""" --> 10uA pull up
-                                            // (weak strength)""" """ 9 =>
-                                            // """"IWKPDEN"""" --> 10uA pull
-                                            // down (weak strength)""" """ 10 =>
-                                            // """"IOE_N"""" --> output enable
-                                            // value. level ‘0’ enables the IDO
-                                            // to PAD path. Else PAD is
-                                            // tristated (except for the PU/PD
-                                            // which are independent)." "Value
-                                            // gets latched at rising edge of
-                                            // RET33""" """ 11 =>""""
-                                            // IOE_N_OV"""" --> output enable
-                                            // overirde. when bit is set to
-                                            // logic '1' IOE_N (bit 4) value
-                                            // will control IO IOE_N signal else
-                                            // IOE_N is control via selected HW
-                                            // logic. strong PULL UP and PULL
-                                            // Down control is disabled for all
-                                            // IO's. both controls are tied to
-                                            // logic level '0'.
-
-#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_GPIO_PAD_CMN_CONFIG register.
-//
-//******************************************************************************
-#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_A_EN \
-                                0x00000080  // when '1' enable ISO A control to
-                                            // D2D Pads else ISO is disabled.
-                                            // For these PADS to be functional
-                                            // this signals should be set 0.
-
-#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_Y_EN \
-                                0x00000040  // when '1' enable ISO Y control to
-                                            // D2D Pads else ISO is disabled.
-                                            // For these PADS to be functional
-                                            // this signals should be set 0.
-
-#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_JTAG_IDIEN \
-                                0x00000020  // If level ‘1’ enables the PAD to
-                                            // ODI path for JTAG PADS [PAD 23,
-                                            // 24, 28, 29]. Else ODI is pulled
-                                            // ‘Low’ regardless of PAD level."
-                                            // "Value gets latched at rising
-                                            // edge of RET33.""" """
-
-#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_M \
-                                0x00000018  // 00’: hysteriris = 10% of VDDS
-                                            // (difference between upper and
-                                            // lower threshold of the schmit
-                                            // trigger) ‘01’: hysteriris = 20%
-                                            // of VDDS (difference between upper
-                                            // and lower threshold of the schmit
-                                            // trigger) ‘10’: hysteriris = 30%
-                                            // of VDDS (difference between upper
-                                            // and lower threshold of the schmit
-                                            // trigger) ‘11’: hysteriris = 40%
-                                            // of VDDS (difference between upper
-                                            // and lower threshold of the schmit
-                                            // trigger)" """
-
-#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_S 3
-#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTEN \
-                                0x00000004  // If logic ‘0’ there is no
-                                            // hysteresis. Set to ‘1’ to enable
-                                            // hysteresis. Leave the choice to
-                                            // customers"""
-
-#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IBIASEN \
-                                0x00000002  // Normal functional operation set
-                                            // this to logic ‘1’ to increase the
-                                            // speed of the o/p buffer at the
-                                            // cost of 0.2uA static current
-                                            // consumption per IO. During IDDQ
-                                            // test and during Hibernate this
-                                            // would be forced to logic ‘0’.
-                                            // Value is not latched at rising
-                                            // edge of RET33.""
-
-#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IDIEN \
-                                0x00000001  // If level ‘1’ enables the PAD to
-                                            // ODI path. Else ODI is pulled
-                                            // ‘Low’ regardless of PAD level."
-                                            // "Value gets latched at rising
-                                            // edge of RET33.""" """
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG register.
-//
-//******************************************************************************
-#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_M \
-                                0x0000003F  // this register implements common
-                                            // IO control to all devement mode
-                                            // PADs; these PADs are DEV_PAD33 to
-                                            // DEV_PAD39. Bit [1:0] : Drive
-                                            // strength control. These 2 bits
-                                            // are connected to DEV PAD drive
-                                            // strength control. possible drive
-                                            // stregnths are 2MA, 4MA and 6 MA
-                                            // for the these IO's. bit 0: when
-                                            // set to logic value '1' enable 2MA
-                                            // drive strength for DEVPAD01 to 07
-                                            // bit 1: when set to logic value
-                                            // '1' enable 4MA drive strength for
-                                            // DEVPAD01 to 07. bit[3:2] : WK
-                                            // PULL UP and PULL down control.
-                                            // These 2 bits provide IWKPUEN and
-                                            // IWKPDEN control for all DEV IO's.
-                                            // bit 2: when set to logic value
-                                            // '1' enable WKPU to DEVPAD01 to 07
-                                            // bit 3: when set to logic value
-                                            // '1' enable WKPD to DEVPAD01 to
-                                            // 07. bit 4: WK PULL control for
-                                            // DEV_PKG_DETECT pin. when '1'
-                                            // pullup enabled else it is
-                                            // disable. bit 5: when set to logic
-                                            // value '1' enable 8MA drive
-                                            // strength for DEVPAD01 to 07.
-
-#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_D2D_TOSTACK_PAD_CONF register.
-//
-//******************************************************************************
-#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_M \
-                                0x1FFFFFFF  // OEN/OEN2X control. When 0 : Act
-                                            // as input buffer else output
-                                            // buffer with drive strength 2.
-                                            // this register control OEN2X pin
-                                            // of D2D TOSTACK PAD: OEN1X and
-                                            // OEN2X decoding is as follows:
-                                            // "when ""00"" :" "when ""01"" :
-                                            // dirve strength is '1' and output
-                                            // buffer enabled." "when ""10"" :
-                                            // drive strength is 2 and output
-                                            // buffer is disabled." "when ""11""
-                                            // : dirve strength is '3' and
-                                            // output buffer enabled."
-
-#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_D2D_MISC_PAD_CONF register.
-//
-//******************************************************************************
-#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_POR_RESET_N \
-                                0x00000200  // This register provide OEN2X
-                                            // control to D2D PADS OEN/OEN2X
-                                            // control. When 0 : Act as input
-                                            // buffer else output buffer with
-                                            // drive strength 2.
-
-#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_RESET_N \
-                                0x00000100  // OEN/OEN2X control. When 0 : Act
-                                            // as input buffer else output
-                                            // buffer with drive strength 2.
-
-#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_HCLK \
-                                0x00000080  // OEN/OEN2X control. When 0 : Act
-                                            // as input buffer else output
-                                            // buffer with drive strength 2.
-
-#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TCK \
-                                0x00000040  // OEN/OEN2X control. When 0 : Act
-                                            // as input buffer else output
-                                            // buffer with drive strength 2.
-
-#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TMS \
-                                0x00000020  // OEN/OEN2X control. When 0 : Act
-                                            // as input buffer else output
-                                            // buffer with drive strength 2.
-
-#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TDI \
-                                0x00000010  // OEN/OEN2X control. When 0 : Act
-                                            // as input buffer else output
-                                            // buffer with drive strength 2.
-
-#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_PIOSC \
-                                0x00000008  // OEN/OEN2X control. When 0 : Act
-                                            // as input buffer else output
-                                            // buffer with drive strength 2.
-
-#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_M \
-                                0x00000007  // D2D SPARE PAD OEN/OEN2X control.
-                                            // When 0: Act as input buffer else
-                                            // output buffer with drive strength
-                                            // 2.
-
-#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SOP_CONF_OVERRIDE register.
-//
-//******************************************************************************
-#define OCP_SHARED_SOP_CONF_OVERRIDE_MEM_SOP_CONF_OVERRIDE \
-                                0x00000001  // when '1' : signal will ovberride
-                                            // SoP setting of JTAG PADS. when
-                                            // '0': SoP setting will control
-                                            // JTAG PADs [ TDI, TDO, TMS, TCK]
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_CC3XX_DEBUGSS_STATUS register.
-//
-//******************************************************************************
-#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_MCU_JTAGNSW \
-                                0x00000020  // This register contains debug
-                                            // subsystem status bits From APPS
-                                            // MCU status bit to indicates
-                                            // whether serial wire or 4 pins
-                                            // jtag select.
-
-#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_CJTAG_BYPASS_STATUS \
-                                0x00000010  // cjtag bypass bit select
-
-#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SW_INTERFACE_SEL_STATUS \
-                                0x00000008  // serial wire interface bit select
-
-#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_TAP_ENABLE_STATUS \
-                                0x00000004  // apps tap enable status
-
-#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_TAPS_ENABLE_STATUS \
-                                0x00000002  // tap enable status
-
-#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SSBD_UNLOCK \
-                                0x00000001  // ssbd unlock status
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_CC3XX_DEBUGMUX_SEL register.
-//
-//******************************************************************************
-#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_M \
-                                0x0000FFFF  // debug mux select register. Upper
-                                            // 8 bits are used for debug module
-                                            // selection. Lower 8 bit [7:0] used
-                                            // inside debug module for selecting
-                                            // module specific signals.
-                                            // Bits[15:8: when set x"00" : GPRCM
-                                            // debug bus. When "o1" : SDIO debug
-                                            // debug bus when x"02" :
-                                            // autonoumous SPI when x"03" :
-                                            // TOPIC when x"04": memss when
-                                            // x"25": mcu debug bus : APPS debug
-                                            // when x"45": mcu debug bus : NWP
-                                            // debug when x"65": mcu debug bus :
-                                            // AHB2VBUS debug when x"85": mcu
-                                            // debug bus : VBUS2HAB debug when
-                                            // x"95": mcu debug bus : RCM debug
-                                            // when x"A5": mcu debug bus :
-                                            // crypto debug when x"06": WLAN
-                                            // debug bus when x"07": debugss bus
-                                            // when x"08": ADC debug when x"09":
-                                            // SDIO PHY debug bus then "others"
-                                            // : no debug is selected
-
-#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_ALT_PC_VAL_NW register.
-//
-//******************************************************************************
-#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_M \
-                                0xFFFFFFFF  // 32 bit. Program counter value
-                                            // for 0x4 address when Alt_pc_en_nw
-                                            // is set.
-
-#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_ALT_PC_VAL_APPS register.
-//
-//******************************************************************************
-#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_M \
-                                0xFFFFFFFF  // 32 bit. Program counter value
-                                            // for 0x4 address when
-                                            // Alt_pc_en_apps is set
-
-#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SPARE_REG_4 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_M \
-                                0xFFFFFFFE  // HW register
-
-#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_S 1
-#define OCP_SHARED_SPARE_REG_4_INVERT_D2D_INTERFACE \
-                                0x00000001  // Data to the top die launched at
-                                            // negative edge instead of positive
-                                            // edge.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SPARE_REG_5 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_M \
-                                0xFFFFFFFF  // HW register
-
-#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SH_SPI_CS_MASK register.
-//
-//******************************************************************************
-#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_M \
-                                0x0000000F  // ( chip select 0 is unmasked
-                                            // after reset. When ‘1’ : CS is
-                                            // unmasked or else masked. Valid
-                                            // configurations are 1000, 0100,
-                                            // 0010 or 0001. Any other setting
-                                            // can lead to unpredictable
-                                            // behavior.
-
-#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_CC3XX_DEVICE_TYPE register.
-//
-//******************************************************************************
-#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_M \
-                                0x00000060  // reserved bits tied off "00".
-
-#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_S 5
-#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_M \
-                                0x0000001F  // CC3XX Device type information.
-
-#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE register.
-//
-//******************************************************************************
-#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_M \
-                                0x000000F0  // [4] 1: switch between
-                                            // WLAN_I2C_SCL and
-                                            // TOP_GPIO_PORT4_I2C closes 0:
-                                            // switch opens [5] 1: switch
-                                            // between WLAN_I2C_SCL and
-                                            // TOP_VSENSE_PORT closes 0: switch
-                                            // opens [6] 1: switch between
-                                            // WLAN_I2C_SCL and WLAN_ANA_TP4
-                                            // closes 0: switch opens [7]
-                                            // Reserved
-
-#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_S 4
-#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_M \
-                                0x0000000F  // [0] 1: switch between
-                                            // WLAN_I2C_SDA and
-                                            // TOP_GPIO_PORT3_I2C closes 0:
-                                            // switch opens [1] 1: switch
-                                            // between WLAN_I2C_SDA and
-                                            // TOP_IFORCE_PORT closes 0: switch
-                                            // opens [2] 1: switch between
-                                            // WLAN_I2C_SDA and WLAN_ANA_TP3
-                                            // closes 0: switch opens [3]
-                                            // Reserved
-
-#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT register.
-//
-//******************************************************************************
-#define OCP_SHARED_CC3XX_DEV_PACKAGE_DETECT_DEV_PKG_DETECT \
-                                0x00000001  // when '0' indicates package type
-                                            // is development.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_AUTONMS_SPICLK_SEL register.
-//
-//******************************************************************************
-#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONOMOUS_BYPASS \
-                                0x00000002  // This bit is used to bypass MCPSI
-                                            // autonomous mode .if this bit is 1
-                                            // autonomous MCSPI logic will be
-                                            // bypassed and it will act as link
-                                            // SPI
-
-#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONMS_SPICLK_SEL \
-                                0x00000001  // This bit is used in SPI
-                                            // Autonomous mode to switch clock
-                                            // from system clock to SPI clk that
-                                            // is coming from PAD. When value 1
-                                            // PAD SPI clk is used as system
-                                            // clock in LPDS mode by SPI as well
-                                            // as autonomous wrapper logic.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_CC3XX_DEV_PADCONF register.
-//
-//******************************************************************************
-#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_M \
-                                0x0000FFFF
-
-#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_IDMEM_TIM_UPDATE register.
-//
-//******************************************************************************
-#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_M \
-                                0xFFFFFFFF
-
-#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SPARE_REG_6 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_M \
-                                0xFFFFFFFF  // NWP Software register
-
-#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_SPARE_REG_7 register.
-//
-//******************************************************************************
-#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_M \
-                                0xFFFFFFFF  // NWP Software register
-
-#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_APPS_WLAN_ORBIT register.
-//
-//******************************************************************************
-#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_M \
-                                0xFFFFFC00  // Spare bit
-
-#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_S 10
-#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_status \
-                                0x00000200  // A rising edge on this bit
-                                            // indicates that the test case
-                                            // passes. This bit would be brought
-                                            // out on the pin interface during
-                                            // ORBIT.
-
-#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_exec \
-                                0x00000100  // This register bit is writable by
-                                            // the FW and when set to 1 it
-                                            // indicates the start of a test
-                                            // execution. A failing edge on this
-                                            // bit indicates that the test
-                                            // execution is complete. This bit
-                                            // would be brought out on the pin
-                                            // interface during ORBIT.
-
-#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_M \
-                                0x000000FC  // Implies the test case ID that
-                                            // needs to run.
-
-#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_S 2
-#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_halt_proc \
-                                0x00000002  // This bit is used to trigger the
-                                            // execution of test cases within
-                                            // the (ROM based) IP.
-
-#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_mode \
-                                0x00000001  // When this bit is 1 it implies
-                                            // ORBIT mode of operation and the
-                                            // (ROM based) IP start the
-                                            // execution from a test case
-                                            // perspective
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD register.
-//
-//******************************************************************************
-#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_M \
-                                0xFFFFFFFF  // scratch pad register.
-
-#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_S 0
-
-
-
-#endif // __HW_OCP_SHARED_H__
diff --git a/cc3200/hal/inc/hw_shamd5.h b/cc3200/hal/inc/hw_shamd5.h
deleted file mode 100644
index cf6254f5d..000000000
--- a/cc3200/hal/inc/hw_shamd5.h
+++ /dev/null
@@ -1,1242 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_SHAMD5_H__
-#define __HW_SHAMD5_H__
-
-//*****************************************************************************
-//
-// The following are defines for the SHAMD5_P register offsets.
-//
-//*****************************************************************************
-#define SHAMD5_O_ODIGEST_A       0x00000000  // WRITE: Outer Digest [127:96] for
-                                            // MD5 [159:128] for SHA-1 [255:224]
-                                            // for SHA-2 / HMAC Key [31:0] for
-                                            // HMAC key proc READ: Outer Digest
-                                            // [127:96] for MD5 [159:128] for
-                                            // SHA-1 [255:224] for SHA-2
-#define SHAMD5_O_ODIGEST_B       0x00000004  // WRITE: Outer Digest [95:64] for
-                                            // MD5 [127:96] for SHA-1 [223:192]
-                                            // for SHA-2 / HMAC Key [63:32] for
-                                            // HMAC key proc READ: Outer Digest
-                                            // [95:64] for MD5 [127:96] for
-                                            // SHA-1 [223:192] for SHA-2
-#define SHAMD5_O_ODIGEST_C       0x00000008  // WRITE: Outer Digest [63:32] for
-                                            // MD5 [95:64] for SHA-1 [191:160]
-                                            // for SHA-2 / HMAC Key [95:64] for
-                                            // HMAC key proc READ: Outer Digest
-                                            // [63:32] for MD5 [95:64] for SHA-1
-                                            // [191:160] for SHA-2
-#define SHAMD5_O_ODIGEST_D       0x0000000C  // WRITE: Outer Digest [31:0] for
-                                            // MD5 [63:31] for SHA-1 [159:128]
-                                            // for SHA-2 / HMAC Key [127:96] for
-                                            // HMAC key proc READ: Outer Digest
-                                            // [31:0] for MD5 [63:32] for SHA-1
-                                            // [159:128] for SHA-2
-#define SHAMD5_O_ODIGEST_E       0x00000010  // WRITE: Outer Digest [31:0] for
-                                            // SHA-1 [127:96] for SHA-2 / HMAC
-                                            // Key [159:128] for HMAC key proc
-                                            // READ: Outer Digest [31:0] for
-                                            // SHA-1 [127:96] for SHA-2
-#define SHAMD5_O_ODIGEST_F       0x00000014  // WRITE: Outer Digest [95:64] for
-                                            // SHA-2 / HMAC Key [191:160] for
-                                            // HMAC key proc READ: Outer Digest
-                                            // [95:64] for SHA-2
-#define SHAMD5_O_ODIGEST_G       0x00000018  // WRITE: Outer Digest [63:32] for
-                                            // SHA-2 / HMAC Key [223:192] for
-                                            // HMAC key proc READ: Outer Digest
-                                            // [63:32] for SHA-2
-#define SHAMD5_O_ODIGEST_H       0x0000001C  // WRITE: Outer Digest [31:0] for
-                                            // SHA-2 / HMAC Key [255:224] for
-                                            // HMAC key proc READ: Outer Digest
-                                            // [31:0] for SHA-2
-#define SHAMD5_O_IDIGEST_A       0x00000020  // WRITE: Inner / Initial Digest
-                                            // [127:96] for MD5 [159:128] for
-                                            // SHA-1 [255:224] for SHA-2 / HMAC
-                                            // Key [287:256] for HMAC key proc
-                                            // READ: Intermediate / Inner Digest
-                                            // [127:96] for MD5 [159:128] for
-                                            // SHA-1 [255:224] for SHA-2 /
-                                            // Result Digest/MAC [127:96] for
-                                            // MD5 [159:128] for SHA-1 [223:192]
-                                            // for SHA-2 224 [255:224] for SHA-2
-                                            // 256
-#define SHAMD5_O_IDIGEST_B       0x00000024  // WRITE: Inner / Initial Digest
-                                            // [95:64] for MD5 [127:96] for
-                                            // SHA-1 [223:192] for SHA-2 / HMAC
-                                            // Key [319:288] for HMAC key proc
-                                            // READ: Intermediate / Inner Digest
-                                            // [95:64] for MD5 [127:96] for
-                                            // SHA-1 [223:192] for SHA-2 /
-                                            // Result Digest/MAC [95:64] for MD5
-                                            // [127:96] for SHA-1 [191:160] for
-                                            // SHA-2 224 [223:192] for SHA-2 256
-#define SHAMD5_O_IDIGEST_C       0x00000028  // WRITE: Inner / Initial Digest
-                                            // [63:32] for MD5 [95:64] for SHA-1
-                                            // [191:160] for SHA- 2 / HMAC Key
-                                            // [351:320] for HMAC key proc READ:
-                                            // Intermediate / Inner Digest
-                                            // [63:32] for MD5 [95:64] for SHA-1
-                                            // [191:160] for SHA-2 / Result
-                                            // Digest/MAC [63:32] for MD5
-                                            // [95:64] for SHA-1 [159:128] for
-                                            // SHA-2 224 [191:160] for SHA-2 256
-#define SHAMD5_O_IDIGEST_D       0x0000002C  // WRITE: Inner / Initial Digest
-                                            // [31:0] for MD5 [63:32] for SHA-1
-                                            // [159:128] for SHA-2 / HMAC Key
-                                            // [383:352] for HMAC key proc READ:
-                                            // Intermediate / Inner Digest
-                                            // [31:0] for MD5 [63:32] for SHA-1
-                                            // [159:128] for SHA-2 / Result
-                                            // Digest/MAC [31:0] for MD5 [63:32]
-                                            // for SHA-1 [127:96] for SHA-2 224
-                                            // [159:128] for SHA-2 256
-#define SHAMD5_O_IDIGEST_E       0x00000030  // WRITE: Inner / Initial Digest
-                                            // [31:0] for SHA-1 [127:96] for
-                                            // SHA-2 / HMAC Key [415:384] for
-                                            // HMAC key proc READ: Intermediate
-                                            // / Inner Digest [31:0] for SHA-1
-                                            // [127:96] for SHA-2 / Result
-                                            // Digest/MAC [31:0] for SHA-1
-                                            // [95:64] for SHA-2 224 [127:96]
-                                            // for SHA-2 256
-#define SHAMD5_O_IDIGEST_F       0x00000034  // WRITE: Inner / Initial Digest
-                                            // [95:64] for SHA-2 / HMAC Key
-                                            // [447:416] for HMAC key proc READ:
-                                            // Intermediate / Inner Digest
-                                            // [95:64] for SHA-2 / Result
-                                            // Digest/MAC [63:32] for SHA-2 224
-                                            // [95:64] for SHA-2 256
-#define SHAMD5_O_IDIGEST_G       0x00000038  // WRITE: Inner / Initial Digest
-                                            // [63:32] for SHA-2 / HMAC Key
-                                            // [479:448] for HMAC key proc READ:
-                                            // Intermediate / Inner Digest
-                                            // [63:32] for SHA-2 / Result
-                                            // Digest/MAC [31:0] for SHA-2 224
-                                            // [63:32] for SHA-2 256
-#define SHAMD5_O_IDIGEST_H       0x0000003C  // WRITE: Inner / Initial Digest
-                                            // [31:0] for SHA-2 / HMAC Key
-                                            // [511:480] for HMAC key proc READ:
-                                            // Intermediate / Inner Digest
-                                            // [31:0] for SHA-2 / Result
-                                            // Digest/MAC [31:0] for SHA-2 256
-#define SHAMD5_O_DIGEST_COUNT    0x00000040  // WRITE: Initial Digest Count
-                                            // ([31:6] only [5:0] assumed 0)
-                                            // READ: Result / IntermediateDigest
-                                            // Count The initial digest byte
-                                            // count for hash/HMAC continue
-                                            // operations (HMAC Key Processing =
-                                            // 0 and Use Algorithm Constants =
-                                            // 0) on the Secure World must be
-                                            // written to this register prior to
-                                            // starting the operation by writing
-                                            // to S_HASH_MODE. When either HMAC
-                                            // Key Processing is 1 or Use
-                                            // Algorithm Constants is 1 this
-                                            // register does not need to be
-                                            // written it will be overwritten
-                                            // with 64 (1 hash block of key XOR
-                                            // ipad) or 0 respectively
-                                            // automatically. When starting a
-                                            // HMAC operation from pre-computes
-                                            // (HMAC Key Processing is 0) then
-                                            // the value 64 must be written here
-                                            // to compensate for the appended
-                                            // key XOR ipad block. Note that the
-                                            // value written should always be a
-                                            // 64 byte multiple the lower 6 bits
-                                            // written are ignored. The updated
-                                            // digest byte count (initial digest
-                                            // byte count + bytes processed) can
-                                            // be read from this register when
-                                            // the status register indicates
-                                            // that the operation is done or
-                                            // suspended due to a context switch
-                                            // request or when a Secure World
-                                            // context out DMA is requested. In
-                                            // Advanced DMA mode when not
-                                            // suspended with a partial result
-                                            // reading the SHAMD5_DIGEST_COUNT
-                                            // register triggers the Hash/HMAC
-                                            // Engine to start the next context
-                                            // input DMA. Therefore reading the
-                                            // SHAMD5_DIGEST_COUNT register
-                                            // should always be the last
-                                            // context-read action if not
-                                            // suspended with a partial result
-                                            // (i.e. PartHashReady interrupt not
-                                            // pending).
-#define SHAMD5_O_MODE            0x00000044  // Register SHAMD5_MODE
-#define SHAMD5_O_LENGTH          0x00000048  // WRITE: Block Length / Remaining
-                                            // Byte Count (bytes) READ:
-                                            // Remaining Byte Count. The value
-                                            // programmed MUST be a 64-byte
-                                            // multiple if Close Hash is set to
-                                            // 0. This register is also the
-                                            // trigger to start processing: once
-                                            // this register is written the core
-                                            // will commence requesting input
-                                            // data via DMA or IRQ (if
-                                            // programmed length > 0) and start
-                                            // processing. The remaining byte
-                                            // count for the active operation
-                                            // can be read from this register
-                                            // when the interrupt status
-                                            // register indicates that the
-                                            // operation is suspended due to a
-                                            // context switch request.
-#define SHAMD5_O_DATA0_IN        0x00000080  // Data input message 0
-#define SHAMD5_O_DATA1_IN        0x00000084  // Data input message 1
-#define SHAMD5_O_DATA2_IN        0x00000088  // Data input message 2
-#define SHAMD5_O_DATA3_IN        0x0000008C  // Data input message 3
-#define SHAMD5_O_DATA4_IN        0x00000090  // Data input message 4
-#define SHAMD5_O_DATA5_IN        0x00000094  // Data input message 5
-#define SHAMD5_O_DATA6_IN        0x00000098  // Data input message 6
-#define SHAMD5_O_DATA7_IN        0x0000009C  // Data input message 7
-#define SHAMD5_O_DATA8_IN        0x000000A0  // Data input message 8
-#define SHAMD5_O_DATA9_IN        0x000000A4  // Data input message 9
-#define SHAMD5_O_DATA10_IN       0x000000A8  // Data input message 10
-#define SHAMD5_O_DATA11_IN       0x000000AC  // Data input message 11
-#define SHAMD5_O_DATA12_IN       0x000000B0  // Data input message 12
-#define SHAMD5_O_DATA13_IN       0x000000B4  // Data input message 13
-#define SHAMD5_O_DATA14_IN       0x000000B8  // Data input message 14
-#define SHAMD5_O_DATA15_IN       0x000000BC  // Data input message 15
-#define SHAMD5_O_REVISION        0x00000100  // Register SHAMD5_REV
-#define SHAMD5_O_SYSCONFIG       0x00000110  // Register SHAMD5_SYSCONFIG
-#define SHAMD5_O_SYSSTATUS       0x00000114  // Register SHAMD5_SYSSTATUS
-#define SHAMD5_O_IRQSTATUS       0x00000118  // Register SHAMD5_IRQSTATUS
-#define SHAMD5_O_IRQENABLE       0x0000011C  // Register SHAMD5_IRQENABLE. The
-                                            // SHAMD5_IRQENABLE register contains
-                                            // an enable bit for each unique
-                                            // interrupt for the public side. An
-                                            // interrupt is enabled when both
-                                            // the global enable in
-                                            // SHAMD5_SYSCONFIG (PIT_en) and the
-                                            // bit in this register are both set
-                                            // to 1. An interrupt that is
-                                            // enabled is propagated to the
-                                            // SINTREQUEST_P output. Please note
-                                            // that the dedicated partial hash
-                                            // output (SINTREQUEST_PART_P) is
-                                            // not affected by this register it
-                                            // is only affected by the global
-                                            // enable SHAMD5_SYSCONFIG (PIT_en).
-#define SHAMD5_O_HASH512_ODIGEST_A \
-                                0x00000200
-
-#define SHAMD5_O_HASH512_ODIGEST_B \
-                                0x00000204
-
-#define SHAMD5_O_HASH512_ODIGEST_C \
-                                0x00000208
-
-#define SHAMD5_O_HASH512_ODIGEST_D \
-                                0x0000020C
-
-#define SHAMD5_O_HASH512_ODIGEST_E \
-                                0x00000210
-
-#define SHAMD5_O_HASH512_ODIGEST_F \
-                                0x00000214
-
-#define SHAMD5_O_HASH512_ODIGEST_G \
-                                0x00000218
-
-#define SHAMD5_O_HASH512_ODIGEST_H \
-                                0x0000021C
-
-#define SHAMD5_O_HASH512_ODIGEST_I \
-                                0x00000220
-
-#define SHAMD5_O_HASH512_ODIGEST_J \
-                                0x00000224
-
-#define SHAMD5_O_HASH512_ODIGEST_K \
-                                0x00000228
-
-#define SHAMD5_O_HASH512_ODIGEST_L \
-                                0x0000022C
-
-#define SHAMD5_O_HASH512_ODIGEST_M \
-                                0x00000230
-
-#define SHAMD5_O_HASH512_ODIGEST_N \
-                                0x00000234
-
-#define SHAMD5_O_HASH512_ODIGEST_O \
-                                0x00000238
-
-#define SHAMD5_O_HASH512_ODIGEST_P \
-                                0x0000023C
-
-#define SHAMD5_O_HASH512_IDIGEST_A \
-                                0x00000240
-
-#define SHAMD5_O_HASH512_IDIGEST_B \
-                                0x00000244
-
-#define SHAMD5_O_HASH512_IDIGEST_C \
-                                0x00000248
-
-#define SHAMD5_O_HASH512_IDIGEST_D \
-                                0x0000024C
-
-#define SHAMD5_O_HASH512_IDIGEST_E \
-                                0x00000250
-
-#define SHAMD5_O_HASH512_IDIGEST_F \
-                                0x00000254
-
-#define SHAMD5_O_HASH512_IDIGEST_G \
-                                0x00000258
-
-#define SHAMD5_O_HASH512_IDIGEST_H \
-                                0x0000025C
-
-#define SHAMD5_O_HASH512_IDIGEST_I \
-                                0x00000260
-
-#define SHAMD5_O_HASH512_IDIGEST_J \
-                                0x00000264
-
-#define SHAMD5_O_HASH512_IDIGEST_K \
-                                0x00000268
-
-#define SHAMD5_O_HASH512_IDIGEST_L \
-                                0x0000026C
-
-#define SHAMD5_O_HASH512_IDIGEST_M \
-                                0x00000270
-
-#define SHAMD5_O_HASH512_IDIGEST_N \
-                                0x00000274
-
-#define SHAMD5_O_HASH512_IDIGEST_O \
-                                0x00000278
-
-#define SHAMD5_O_HASH512_IDIGEST_P \
-                                0x0000027C
-
-#define SHAMD5_O_HASH512_DIGEST_COUNT \
-                                0x00000280
-
-#define SHAMD5_O_HASH512_MODE    0x00000284
-#define SHAMD5_O_HASH512_LENGTH  0x00000288
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A register.
-//
-//******************************************************************************
-#define SHAMD5_ODIGEST_A_DATA_M  0xFFFFFFFF  // data
-#define SHAMD5_ODIGEST_A_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B register.
-//
-//******************************************************************************
-#define SHAMD5_ODIGEST_B_DATA_M  0xFFFFFFFF  // data
-#define SHAMD5_ODIGEST_B_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C register.
-//
-//******************************************************************************
-#define SHAMD5_ODIGEST_C_DATA_M  0xFFFFFFFF  // data
-#define SHAMD5_ODIGEST_C_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D register.
-//
-//******************************************************************************
-#define SHAMD5_ODIGEST_D_DATA_M  0xFFFFFFFF  // data
-#define SHAMD5_ODIGEST_D_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E register.
-//
-//******************************************************************************
-#define SHAMD5_ODIGEST_E_DATA_M  0xFFFFFFFF  // data
-#define SHAMD5_ODIGEST_E_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F register.
-//
-//******************************************************************************
-#define SHAMD5_ODIGEST_F_DATA_M  0xFFFFFFFF  // data
-#define SHAMD5_ODIGEST_F_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G register.
-//
-//******************************************************************************
-#define SHAMD5_ODIGEST_G_DATA_M  0xFFFFFFFF  // data
-#define SHAMD5_ODIGEST_G_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H register.
-//
-//******************************************************************************
-#define SHAMD5_ODIGEST_H_DATA_M  0xFFFFFFFF  // data
-#define SHAMD5_ODIGEST_H_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A register.
-//
-//******************************************************************************
-#define SHAMD5_IDIGEST_A_DATA_M  0xFFFFFFFF  // data
-#define SHAMD5_IDIGEST_A_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B register.
-//
-//******************************************************************************
-#define SHAMD5_IDIGEST_B_DATA_M  0xFFFFFFFF  // data
-#define SHAMD5_IDIGEST_B_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C register.
-//
-//******************************************************************************
-#define SHAMD5_IDIGEST_C_DATA_M  0xFFFFFFFF  // data
-#define SHAMD5_IDIGEST_C_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D register.
-//
-//******************************************************************************
-#define SHAMD5_IDIGEST_D_DATA_M  0xFFFFFFFF  // data
-#define SHAMD5_IDIGEST_D_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E register.
-//
-//******************************************************************************
-#define SHAMD5_IDIGEST_E_DATA_M  0xFFFFFFFF  // data
-#define SHAMD5_IDIGEST_E_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F register.
-//
-//******************************************************************************
-#define SHAMD5_IDIGEST_F_DATA_M  0xFFFFFFFF  // data
-#define SHAMD5_IDIGEST_F_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G register.
-//
-//******************************************************************************
-#define SHAMD5_IDIGEST_G_DATA_M  0xFFFFFFFF  // data
-#define SHAMD5_IDIGEST_G_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H register.
-//
-//******************************************************************************
-#define SHAMD5_IDIGEST_H_DATA_M  0xFFFFFFFF  // data
-#define SHAMD5_IDIGEST_H_DATA_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_DIGEST_COUNT register.
-//
-//******************************************************************************
-#define SHAMD5_DIGEST_COUNT_DATA_M \
-                                0xFFFFFFFF  // data
-
-#define SHAMD5_DIGEST_COUNT_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_MODE register.
-//
-//******************************************************************************
-#define SHAMD5_MODE_HMAC_OUTER_HASH \
-                                0x00000080  // The HMAC Outer Hash is performed
-                                            // on the hash digest when the inner
-                                            // hash hash finished (block length
-                                            // exhausted and final hash
-                                            // performed if close_hash is 1).
-                                            // This bit should normally be set
-                                            // together with close_hash to
-                                            // finish the inner hash first or
-                                            // Block Length should be zero (HMAC
-                                            // continue with the just outer hash
-                                            // to be done). Auto cleared
-                                            // internally when outer hash
-                                            // performed. 0 No operation 1 hmac
-                                            // processing
-
-#define SHAMD5_MODE_HMAC_KEY_PROC \
-                                0x00000020  // Performs HMAC key processing on
-                                            // the 512 bit HMAC key loaded into
-                                            // the SHAMD5_IDIGEST_{A to H} and
-                                            // SHAMD5_ODIGEST_{A to H} register
-                                            // block. Once HMAC key processing
-                                            // is finished this bit is
-                                            // automatically cleared and the
-                                            // resulting Inner and Outer digest
-                                            // is available from
-                                            // SHAMD5_IDIGEST_{A to H} and
-                                            // SHAMD5_ODIGEST_{A to H}
-                                            // respectively after which regular
-                                            // hash processing (using
-                                            // SHAMD5_IDIGEST_{A to H} as initial
-                                            // digest) will commence until the
-                                            // Block Length is exhausted. 0 No
-                                            // operation. 1 Hmac processing.
-
-#define SHAMD5_MODE_CLOSE_HASH   0x00000010  // Performs the padding the
-                                            // hash/HMAC will be 'closed' at the
-                                            // end of the block as per
-                                            // MD5/SHA-1/SHA-2 specification
-                                            // (i.e. appropriate padding is
-                                            // added) or no padding is done
-                                            // allowing the hash to be continued
-                                            // later. However if the hash/HMAC
-                                            // is not closed then the Block
-                                            // Length MUST be a multiple of 64
-                                            // bytes to ensure correct
-                                            // operation. Auto cleared
-                                            // internally when hash closed. 0 No
-                                            // padding hash computation can be
-                                            // contimued. 1 Last packet will be
-                                            // padded.
-#define SHAMD5_MODE_ALGO_CONSTANT \
-                                0x00000008  // The initial digest register will
-                                            // be overwritten with the algorithm
-                                            // constants for the selected
-                                            // algorithm when hashing and the
-                                            // initial digest count register
-                                            // will be reset to 0. This will
-                                            // start a normal hash operation.
-                                            // When continuing an existing hash
-                                            // or when performing an HMAC
-                                            // operation this register must be
-                                            // set to 0 and the
-                                            // intermediate/inner digest or HMAC
-                                            // key and digest count need to be
-                                            // written to the context input
-                                            // registers prior to writing
-                                            // SHAMD5_MODE. Auto cleared
-                                            // internally after first block
-                                            // processed. 0 Use pre-calculated
-                                            // digest (from an other operation)
-                                            // 1 Use constants of the selected
-                                            // algo.
-
-#define SHAMD5_MODE_ALGO_M       0x00000006  // These bits select the hash
-                                            // algorithm to be used for
-                                            // processing: 0x0 md5_128 algorithm
-                                            // 0x1 sha1_160 algorithm 0x2
-                                            // sha2_224 algorithm 0x3 sha2_256
-                                            // algorithm
-#define SHAMD5_MODE_ALGO_S       1
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_LENGTH register.
-//
-//******************************************************************************
-#define SHAMD5_LENGTH_DATA_M     0xFFFFFFFF  // data
-#define SHAMD5_LENGTH_DATA_S     0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_DATA0_IN register.
-//
-//******************************************************************************
-#define SHAMD5_DATA0_IN_DATA0_IN_M \
-                                0xFFFFFFFF  // data
-
-#define SHAMD5_DATA0_IN_DATA0_IN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_DATA1_IN register.
-//
-//******************************************************************************
-#define SHAMD5_DATA1_IN_DATA1_IN_M \
-                                0xFFFFFFFF  // data
-
-#define SHAMD5_DATA1_IN_DATA1_IN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_DATA2_IN register.
-//
-//******************************************************************************
-#define SHAMD5_DATA2_IN_DATA2_IN_M \
-                                0xFFFFFFFF  // data
-
-#define SHAMD5_DATA2_IN_DATA2_IN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_DATA3_IN register.
-//
-//******************************************************************************
-#define SHAMD5_DATA3_IN_DATA3_IN_M \
-                                0xFFFFFFFF  // data
-
-#define SHAMD5_DATA3_IN_DATA3_IN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_DATA4_IN register.
-//
-//******************************************************************************
-#define SHAMD5_DATA4_IN_DATA4_IN_M \
-                                0xFFFFFFFF  // data
-
-#define SHAMD5_DATA4_IN_DATA4_IN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_DATA5_IN register.
-//
-//******************************************************************************
-#define SHAMD5_DATA5_IN_DATA5_IN_M \
-                                0xFFFFFFFF  // data
-
-#define SHAMD5_DATA5_IN_DATA5_IN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_DATA6_IN register.
-//
-//******************************************************************************
-#define SHAMD5_DATA6_IN_DATA6_IN_M \
-                                0xFFFFFFFF  // data
-
-#define SHAMD5_DATA6_IN_DATA6_IN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_DATA7_IN register.
-//
-//******************************************************************************
-#define SHAMD5_DATA7_IN_DATA7_IN_M \
-                                0xFFFFFFFF  // data
-
-#define SHAMD5_DATA7_IN_DATA7_IN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_DATA8_IN register.
-//
-//******************************************************************************
-#define SHAMD5_DATA8_IN_DATA8_IN_M \
-                                0xFFFFFFFF  // data
-
-#define SHAMD5_DATA8_IN_DATA8_IN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_DATA9_IN register.
-//
-//******************************************************************************
-#define SHAMD5_DATA9_IN_DATA9_IN_M \
-                                0xFFFFFFFF  // data
-
-#define SHAMD5_DATA9_IN_DATA9_IN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_DATA10_IN register.
-//
-//******************************************************************************
-#define SHAMD5_DATA10_IN_DATA10_IN_M \
-                                0xFFFFFFFF  // data
-
-#define SHAMD5_DATA10_IN_DATA10_IN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_DATA11_IN register.
-//
-//******************************************************************************
-#define SHAMD5_DATA11_IN_DATA11_IN_M \
-                                0xFFFFFFFF  // data
-
-#define SHAMD5_DATA11_IN_DATA11_IN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_DATA12_IN register.
-//
-//******************************************************************************
-#define SHAMD5_DATA12_IN_DATA12_IN_M \
-                                0xFFFFFFFF  // data
-
-#define SHAMD5_DATA12_IN_DATA12_IN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_DATA13_IN register.
-//
-//******************************************************************************
-#define SHAMD5_DATA13_IN_DATA13_IN_M \
-                                0xFFFFFFFF  // data
-
-#define SHAMD5_DATA13_IN_DATA13_IN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_DATA14_IN register.
-//
-//******************************************************************************
-#define SHAMD5_DATA14_IN_DATA14_IN_M \
-                                0xFFFFFFFF  // data
-
-#define SHAMD5_DATA14_IN_DATA14_IN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_DATA15_IN register.
-//
-//******************************************************************************
-#define SHAMD5_DATA15_IN_DATA15_IN_M \
-                                0xFFFFFFFF  // data
-
-#define SHAMD5_DATA15_IN_DATA15_IN_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_REVISION register.
-//
-//******************************************************************************
-#define SHAMD5_REVISION_SCHEME_M 0xC0000000
-#define SHAMD5_REVISION_SCHEME_S 30
-#define SHAMD5_REVISION_FUNC_M   0x0FFF0000  // Function indicates a software
-                                            // compatible module family. If
-                                            // there is no level of software
-                                            // compatibility a new Func number
-                                            // (and hence REVISION) should be
-                                            // assigned.
-#define SHAMD5_REVISION_FUNC_S   16
-#define SHAMD5_REVISION_R_RTL_M  0x0000F800  // RTL Version (R) maintained by IP
-                                            // design owner. RTL follows a
-                                            // numbering such as X.Y.R.Z which
-                                            // are explained in this table. R
-                                            // changes ONLY when: (1) PDS
-                                            // uploads occur which may have been
-                                            // due to spec changes (2) Bug fixes
-                                            // occur (3) Resets to '0' when X or
-                                            // Y changes. Design team has an
-                                            // internal 'Z' (customer invisible)
-                                            // number which increments on every
-                                            // drop that happens due to DV and
-                                            // RTL updates. Z resets to 0 when R
-                                            // increments.
-#define SHAMD5_REVISION_R_RTL_S  11
-#define SHAMD5_REVISION_X_MAJOR_M \
-                                0x00000700  // Major Revision (X) maintained by
-                                            // IP specification owner. X changes
-                                            // ONLY when: (1) There is a major
-                                            // feature addition. An example
-                                            // would be adding Master Mode to
-                                            // Utopia Level2. The Func field (or
-                                            // Class/Type in old PID format)
-                                            // will remain the same. X does NOT
-                                            // change due to: (1) Bug fixes (2)
-                                            // Change in feature parameters.
-
-#define SHAMD5_REVISION_X_MAJOR_S 8
-#define SHAMD5_REVISION_CUSTOM_M 0x000000C0
-#define SHAMD5_REVISION_CUSTOM_S 6
-#define SHAMD5_REVISION_Y_MINOR_M \
-                                0x0000003F  // Minor Revision (Y) maintained by
-                                            // IP specification owner. Y changes
-                                            // ONLY when: (1) Features are
-                                            // scaled (up or down). Flexibility
-                                            // exists in that this feature
-                                            // scalability may either be
-                                            // represented in the Y change or a
-                                            // specific register in the IP that
-                                            // indicates which features are
-                                            // exactly available. (2) When
-                                            // feature creeps from Is-Not list
-                                            // to Is list. But this may not be
-                                            // the case once it sees silicon; in
-                                            // which case X will change. Y does
-                                            // NOT change due to: (1) Bug fixes
-                                            // (2) Typos or clarifications (3)
-                                            // major functional/feature
-                                            // change/addition/deletion. Instead
-                                            // these changes may be reflected
-                                            // via R S X as applicable. Spec
-                                            // owner maintains a
-                                            // customer-invisible number 'S'
-                                            // which changes due to: (1)
-                                            // Typos/clarifications (2) Bug
-                                            // documentation. Note that this bug
-                                            // is not due to a spec change but
-                                            // due to implementation.
-                                            // Nevertheless the spec tracks the
-                                            // IP bugs. An RTL release (say for
-                                            // silicon PG1.1) that occurs due to
-                                            // bug fix should document the
-                                            // corresponding spec number (X.Y.S)
-                                            // in its release notes.
-
-#define SHAMD5_REVISION_Y_MINOR_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG register.
-//
-//******************************************************************************
-#define SHAMD5_SYSCONFIG_PADVANCED \
-                                0x00000080  // If set to 1 Advanced mode is
-                                            // enabled for the Secure World. If
-                                            // set to 0 Legacy mode is enabled
-                                            // for the Secure World.
-
-#define SHAMD5_SYSCONFIG_PCONT_SWT \
-                                0x00000040  // Finish all pending data and
-                                            // context DMA input requests (but
-                                            // will not assert any new requests)
-                                            // finish processing all data in the
-                                            // module and provide a saved
-                                            // context (partial hash result
-                                            // updated digest count remaining
-                                            // length updated mode information
-                                            // where applicable) for the last
-                                            // operation that was interrupted so
-                                            // that it can be resumed later.
-
-#define SHAMD5_SYSCONFIG_PDMA_EN 0x00000008
-#define SHAMD5_SYSCONFIG_PIT_EN  0x00000004
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS register.
-//
-//******************************************************************************
-#define SHAMD5_SYSSTATUS_RESETDONE \
-                                0x00000001  // data
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS register.
-//
-//******************************************************************************
-#define SHAMD5_IRQSTATUS_CONTEXT_READY \
-                                0x00000008  // indicates that the secure side
-                                            // context input registers are
-                                            // available for a new context for
-                                            // the next packet to be processed.
-
-#define SHAMD5_IRQSTATUS_PARTHASH_READY \
-                                0x00000004  // After a secure side context
-                                            // switch request this bit will read
-                                            // as 1 indicating that the saved
-                                            // context is available from the
-                                            // secure side context output
-                                            // registers. Note that if the
-                                            // context switch request coincides
-                                            // with a final hash (when hashing)
-                                            // or an outer hash (when doing
-                                            // HMAC) that PartHashReady will not
-                                            // become active but a regular
-                                            // Output Ready will occur instead
-                                            // (indicating that the result is
-                                            // final and therefore no
-                                            // continuation is required).
-
-#define SHAMD5_IRQSTATUS_INPUT_READY \
-                                0x00000002  // indicates that the secure side
-                                            // data FIFO is ready to receive the
-                                            // next 64 byte data block.
-
-#define SHAMD5_IRQSTATUS_OUTPUT_READY \
-                                0x00000001  // Indicates that a (partial)
-                                            // result or saved context is
-                                            // available from the secure side
-                                            // context output registers.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE register.
-//
-//******************************************************************************
-#define SHAMD5_IRQENABLE_M_CONTEXT_READY \
-                                0x00000008  // mask for context ready
-
-#define SHAMD5_IRQENABLE_M_PARTHASH_READY \
-                                0x00000004  // mask for partial hash
-
-#define SHAMD5_IRQENABLE_M_INPUT_READY \
-                                0x00000002  // mask for input_ready
-
-#define SHAMD5_IRQENABLE_M_OUTPUT_READY \
-                                0x00000001  // mask for output_ready
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_ODIGEST_A register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_ODIGEST_A_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_ODIGEST_A_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_ODIGEST_B register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_ODIGEST_B_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_ODIGEST_B_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_ODIGEST_C register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_ODIGEST_C_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_ODIGEST_C_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_ODIGEST_D register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_ODIGEST_D_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_ODIGEST_D_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_ODIGEST_E register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_ODIGEST_E_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_ODIGEST_E_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_ODIGEST_F register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_ODIGEST_F_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_ODIGEST_F_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_ODIGEST_G register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_ODIGEST_G_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_ODIGEST_G_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_ODIGEST_H register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_ODIGEST_H_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_ODIGEST_H_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_ODIGEST_I register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_ODIGEST_I_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_ODIGEST_I_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_ODIGEST_J register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_ODIGEST_J_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_ODIGEST_J_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_ODIGEST_K register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_ODIGEST_K_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_ODIGEST_K_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_ODIGEST_L register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_ODIGEST_L_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_ODIGEST_L_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_ODIGEST_M register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_ODIGEST_M_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_ODIGEST_M_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_ODIGEST_N register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_ODIGEST_N_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_ODIGEST_N_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_ODIGEST_O register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_ODIGEST_O_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_ODIGEST_O_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_ODIGEST_P register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_ODIGEST_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_ODIGEST_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_IDIGEST_A register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_IDIGEST_A_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_IDIGEST_A_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_IDIGEST_B register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_IDIGEST_B_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_IDIGEST_B_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_IDIGEST_C register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_IDIGEST_C_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_IDIGEST_C_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_IDIGEST_D register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_IDIGEST_D_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_IDIGEST_D_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_IDIGEST_E register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_IDIGEST_E_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_IDIGEST_E_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_IDIGEST_F register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_IDIGEST_F_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_IDIGEST_F_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_IDIGEST_G register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_IDIGEST_G_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_IDIGEST_G_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_IDIGEST_H register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_IDIGEST_H_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_IDIGEST_H_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_IDIGEST_I register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_IDIGEST_I_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_IDIGEST_I_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_IDIGEST_J register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_IDIGEST_J_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_IDIGEST_J_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_IDIGEST_K register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_IDIGEST_K_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_IDIGEST_K_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_IDIGEST_L register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_IDIGEST_L_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_IDIGEST_L_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_IDIGEST_M register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_IDIGEST_M_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_IDIGEST_M_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_IDIGEST_N register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_IDIGEST_N_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_IDIGEST_N_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_IDIGEST_O register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_IDIGEST_O_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_IDIGEST_O_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_IDIGEST_P register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_IDIGEST_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_IDIGEST_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_DIGEST_COUNT register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_DIGEST_COUNT_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_DIGEST_COUNT_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_MODE register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_MODE_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_MODE_DATA_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// SHAMD5_O_HASH512_LENGTH register.
-//
-//******************************************************************************
-#define SHAMD5_HASH512_LENGTH_DATA_M \
-                                0xFFFFFFFF
-
-#define SHAMD5_HASH512_LENGTH_DATA_S 0
-
-
-
-#endif // __HW_SHAMD5_H__
diff --git a/cc3200/hal/inc/hw_stack_die_ctrl.h b/cc3200/hal/inc/hw_stack_die_ctrl.h
deleted file mode 100644
index eba31e4f0..000000000
--- a/cc3200/hal/inc/hw_stack_die_ctrl.h
+++ /dev/null
@@ -1,764 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-
-#ifndef __HW_STACK_DIE_CTRL_H__
-#define __HW_STACK_DIE_CTRL_H__
-
-//*****************************************************************************
-//
-// The following are defines for the STACK_DIE_CTRL register offsets.
-//
-//*****************************************************************************
-#define STACK_DIE_CTRL_O_STK_UP_RESET \
-                                0x00000000  // Can be written only by Base
-                                            // Processor. Writing to this
-                                            // register will reset the stack
-                                            // processor reset will be
-                                            // de-asserted upon clearing this
-                                            // register.
-
-#define STACK_DIE_CTRL_O_SR_MASTER_PRIORITY \
-                                0x00000004  // This register defines who among
-                                            // base processor and stack
-                                            // processor have highest priority
-                                            // for Sram Access. Can be written
-                                            // only by Base Processor.
-
-#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 \
-                                0x00000008  // In Spinlock mode this Register
-                                            // defines who among base processor
-                                            // and stack processor have access
-                                            // to Sram Bank2 right now. In
-                                            // Handshake mode this Register
-                                            // defines who among base processor
-                                            // and stack processor have access
-                                            // to Sram Bank2 and Bank3 right
-                                            // now. Its Clear only register and
-                                            // is set by hardware. Lower bit can
-                                            // be cleared only by Base Processor
-                                            // and Upper bit Cleared only by the
-                                            // Stack processor.
-
-#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 \
-                                0x0000000C  // In Spinlock mode whenever Base
-                                            // processor wants the access to
-                                            // Sram Bank2 it should request for
-                                            // it by writing into this register.
-                                            // It'll get interrupt whenever it
-                                            // is granted. In Handshake mode
-                                            // this bit will be set by Stack
-                                            // processor. Its a set only bit and
-                                            // is cleared by HW when the request
-                                            // is granted.
-
-#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 \
-                                0x00000010  // In Spinlock mode Whenever Stack
-                                            // processor wants the access to
-                                            // Sram Bank2 it should request for
-                                            // it by writing into this register.
-                                            // It'll get interrupt whenever it
-                                            // is granted. In Handshake mode
-                                            // this bit will be set by the Base
-                                            // processor. Its a set only bit and
-                                            // is cleared by HW when the request
-                                            // is granted.
-
-#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 \
-                                0x00000014  // Register defines who among base
-                                            // processor and stack processor
-                                            // have access to Sram Bank3 right
-                                            // now. Its Clear only register and
-                                            // is set by hardware. Lower bit can
-                                            // be cleared only by Base Processor
-                                            // and Upper bit Cleared only by the
-                                            // Stack processor.
-
-#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 \
-                                0x00000018  // In Spinlock mode whenever Base
-                                            // processor wants the access to
-                                            // Sram Bank3 it should request for
-                                            // it by writing into this register.
-                                            // It'll get interrupt whenever it
-                                            // is granted. In Handshake mode
-                                            // this bit will be set by Stack
-                                            // processor. Its a set only bit and
-                                            // is cleared by HW when the request
-                                            // is granted.
-
-#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 \
-                                0x0000001C  // In Spinlock mode Whenever Stack
-                                            // processor wants the access to
-                                            // Sram Bank3 it should request for
-                                            // it by writing into this register.
-                                            // It'll get interrupt whenever it
-                                            // is granted. In Handshake mode
-                                            // this bit will be set by the Base
-                                            // processor. Its a set only bit and
-                                            // is cleared by HW when the request
-                                            // is granted.
-
-#define STACK_DIE_CTRL_O_RDSM_CFG_CPU \
-                                0x00000020  // Read State Machine timing
-                                            // configuration register. Generally
-                                            // Bit 4 and 3 will be identical.
-                                            // For stacked die always 43 are 0
-                                            // and 6:5 == 1 for 120Mhz.
-
-#define STACK_DIE_CTRL_O_RDSM_CFG_EE \
-                                0x00000024  // Read State Machine timing
-                                            // configuration register. Generally
-                                            // Bit 4 and 3 will be identical.
-                                            // For stacked die always 43 are 0
-                                            // and 6:5 == 1 for 120Mhz.
-
-#define STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG \
-                                0x00000028  // Reading this register Base
-                                            // procesor will able to know the
-                                            // reason for the interrupt. This is
-                                            // clear only register - set by HW
-                                            // upon an interrupt to Base
-                                            // processor and can be cleared only
-                                            // by BASE processor.
-
-#define STACK_DIE_CTRL_O_STK_UP_IRQ_LOG \
-                                0x0000002C  // Reading this register Stack
-                                            // procesor will able to know the
-                                            // reason for the interrupt. This is
-                                            // clear only register - set by HW
-                                            // upon an interrupt to Stack
-                                            // processor and can be cleared only
-                                            // by Stack processor.
-
-#define STACK_DIE_CTRL_O_STK_CLK_EN \
-                                0x00000030  // Can be written only by base
-                                            // processor. Controls the enable
-                                            // pin of the cgcs for the clocks
-                                            // going to CM3 dft ctrl block and
-                                            // Sram.
-
-#define STACK_DIE_CTRL_O_SPIN_LOCK_MODE \
-                                0x00000034  // Can be written only by the base
-                                            // processor. Decides the ram
-                                            // sharing mode :: handshake or
-                                            // Spinlock mode.
-
-#define STACK_DIE_CTRL_O_BUS_FAULT_ADDR \
-                                0x00000038  // Stores the last bus fault
-                                            // address.
-
-#define STACK_DIE_CTRL_O_BUS_FAULT_CLR \
-                                0x0000003C  // write only registers on read
-                                            // returns 0.W Write 1 to clear the
-                                            // bust fault to store the new bus
-                                            // fault address
-
-#define STACK_DIE_CTRL_O_RESET_CAUSE \
-                                0x00000040  // Reset cause value captured from
-                                            // the ICR_CLKRST block.
-
-#define STACK_DIE_CTRL_O_WDOG_TIMER_EVENT \
-                                0x00000044  // Watchdog timer event value
-                                            // captured from the ICR_CLKRST
-                                            // block
-
-#define STACK_DIE_CTRL_O_DMA_REQ \
-                                0x00000048  // To send Dma Request to bottom
-                                            // die.
-
-#define STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR \
-                                0x0000004C  // Address offset within SRAM to
-                                            // which CM3 should jump after
-                                            // reset.
-
-#define STACK_DIE_CTRL_O_SW_REG1 \
-                                0x00000050  // These are sw registers for
-                                            // topdie processor and bottom die
-                                            // processor to communicate. Both
-                                            // can set and read these registers.
-                                            // In case of write clash bottom
-                                            // die's processor wins and top die
-                                            // processor access is ignored.
-
-#define STACK_DIE_CTRL_O_SW_REG2 \
-                                0x00000054  // These are sw registers for
-                                            // topdie processor and bottom die
-                                            // processor to communicate. Both
-                                            // can set and read these registers.
-                                            // In case of write clash bottom
-                                            // die's processor wins and top die
-                                            // processor access is ignored.
-
-#define STACK_DIE_CTRL_O_FMC_SLEEP_CTL \
-                                0x00000058  // By posting the request Flash can
-                                            // be put into low-power mode
-                                            // (Sleep) without powering down the
-                                            // Flash. Earlier (in Garnet) this
-                                            // was fully h/w controlled and the
-                                            // control for this was coming from
-                                            // SysCtl while entering into Cortex
-                                            // Deep-sleep mode. But for our
-                                            // device the D2D i/f doesnt support
-                                            // this. The Firmware has to program
-                                            // the register in the top-die for
-                                            // entering into this mode and wait
-                                            // for an interrupt.
-
-#define STACK_DIE_CTRL_O_MISC_CTL \
-                                0x0000005C  // Miscellanious control register.
-
-#define STACK_DIE_CTRL_O_SW_DFT_CTL \
-                                0x000000FC  // DFT control and status bits
-
-#define STACK_DIE_CTRL_O_PADN_CTL_0 \
-                                0x00000100  // Mainly for For controlling the
-                                            // pads OEN pins. There are total 60
-                                            // pads and hence 60 control registe
-                                            // i.e n value varies from 0 to 59.
-                                            // Here is the mapping for the
-                                            // pad_ctl register number and the
-                                            // functionality : 0 D2DPAD_DMAREQ1
-                                            // 1 D2DPAD_DMAREQ0 2
-                                            // D2DPAD_INT2BASE 3 D2DPAD_PIOSC 4
-                                            // D2DPAD_RST_N 5 D2DPAD_POR_RST_N 6
-                                            // D2DPAD_HCLK 7 D2DPAD_JTAG_TDO 8
-                                            // D2DPAD_JTAG_TCK 9 D2DPAD_JTAG_TMS
-                                            // 10 D2DPAD_JTAG_TDI 11-27
-                                            // D2DPAD_FROMSTACK[D2D_FROMSTACK_SIZE
-                                            // -1:0] 28-56 D2DPAD_TOSTACK
-                                            // [D2D_TOSTACK_SIZE -1:0] 57-59
-                                            // D2DPAD_SPARE [D2D_SPARE_PAD_SIZE
-                                            // -1:0] 0:00
-
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_STK_UP_RESET register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_STK_UP_RESET_UP_RESET \
-                                0x00000001  // 1 :Assert Reset 0 : Deassert the
-                                            // Reset
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_SR_MASTER_PRIORITY register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_M \
-                                0x00000003  // 00 : Equal Priority 01 : Stack
-                                            // Processor have priority 10 : Base
-                                            // Processor have priority 11 :
-                                            // Unused
-
-#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_STK_UP_ACCSS \
-                                0x00000002  // Stack Processor should clear it
-                                            // when it is done with the sram
-                                            // bank usage. Set by HW It is set
-                                            // when Stack Processor is granted
-                                            // the access to this bank
-
-#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_BASE_UP_ACCSS \
-                                0x00000001  // Base Processor should clear it
-                                            // when it is done wth the sram
-                                            // usage. Set by HW It is set when
-                                            // Base Processor is granted the
-                                            // access to this bank
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK2_ACCSS_REQ \
-                                0x00000001  // Base Processor will set when
-                                            // Sram access is needed in Spin
-                                            // Lock mode. In Handshake mode
-                                            // Stack Processor will set to
-                                            // inform Base Processor that it is
-                                            // done with the processing of data
-                                            // in SRAM and is now ready to use
-                                            // by the base processor.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK2_ACCSS_REQ \
-                                0x00000001  // Stack Processor will set when
-                                            // Sram access is needed in Spin
-                                            // Lock mode. In Handshake mode Base
-                                            // Processor will set to inform
-                                            // Stack Processor to start
-                                            // processing the data in the Ram.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_STK_UP_ACCSS \
-                                0x00000002  // Stack Processor should clear it
-                                            // when it is done with the sram
-                                            // bank usage. Set by HW It is set
-                                            // when Stack Processor is granted
-                                            // the access to this bank.
-
-#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_BASE_UP_ACCSS \
-                                0x00000001  // Base Processor should clear it
-                                            // when it is done wth the sram
-                                            // usage. Set by HW it is set when
-                                            // Base Processor is granted the
-                                            // access to this bank.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK3_ACCSS_REQ \
-                                0x00000001  // Base Processor will set when
-                                            // Sram access is needed in Spin
-                                            // Lock mode. Not used in handshake
-                                            // mode.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK3_ACCSS_REQ \
-                                0x00000001  // Stack Processor will set when
-                                            // Sram access is needed in Spin
-                                            // Lock mode.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_RDSM_CFG_CPU register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_M \
-                                0x000000C0  // Bank Clock Hi Time 00 : HCLK
-                                            // pulse 01 : 1 cycle of HCLK 10 :
-                                            // 1.5 cycles of HCLK 11 : 2 cycles
-                                            // of HCLK
-
-#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_S 6
-#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_SENSE \
-                                0x00000020  // FLCLK 0 : indicates flash clock
-                                            // rise aligns on HCLK rise 1 :
-                                            // indicates flash clock rise aligns
-                                            // on HCLK fall
-
-#define STACK_DIE_CTRL_RDSM_CFG_CPU_PIPELINE_FLDATA \
-                                0x00000010  // 0 : Always register flash rdata
-                                            // before sending to CPU 1 : Drive
-                                            // Flash rdata directly out on MISS
-                                            // (Both ICODE / DCODE)
-
-#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_M \
-                                0x0000000F  // Number of wait states inserted
-
-#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_RDSM_CFG_EE register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_M \
-                                0x000000C0  // Bank Clock Hi Time 00 : HCLK
-                                            // pulse 01 : 1 cycle of HCLK 10 :
-                                            // 1.5 cycles of HCLK 11 : 2 cycles
-                                            // of HCLK
-
-#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_S 6
-#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_SENSE \
-                                0x00000020  // FLCLK 0 : indicates flash clock
-                                            // rise aligns on HCLK rise 1 :
-                                            // indicates flash clock rise aligns
-                                            // on HCLK fall
-
-#define STACK_DIE_CTRL_RDSM_CFG_EE_PIPELINE_FLDATA \
-                                0x00000010  // 0 : Always register flash rdata
-                                            // before sending to CPU 1 : Drive
-                                            // Flash rdata directly out on MISS
-                                            // (Both ICODE / DCODE)
-
-#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_M \
-                                0x0000000F  // Number of wait states inserted
-
-#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_REL \
-                                0x00000010  // Set when Relinquish Interrupt
-                                            // sent to Base processor for Bank3.
-
-#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_RELEASE \
-                                0x00000008  // Set when Relinquish Interrupt
-                                            // sent to Base processor for Bank2.
-
-#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_GRANT \
-                                0x00000004  // Set when Bank3 is granted to
-                                            // Base processor.
-
-#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_GRANT \
-                                0x00000002  // Set when Bank2 is granted to
-                                            // BAse processor.
-
-#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_INVAL_ACCSS \
-                                0x00000001  // Set when there Base processor do
-                                            // an Invalid access to Sram. Ex :
-                                            // Accessing the bank which is not
-                                            // granted for BAse processor.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_STK_UP_IRQ_LOG register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_REL \
-                                0x00000008  // Set when Relinquish Interrupt
-                                            // sent to Stack processor for
-                                            // Bank3.
-
-#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_REL \
-                                0x00000004  // Set when Relinquish Interrupt
-                                            // sent to Stack processor for
-                                            // Bank2.
-
-#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_GRANT \
-                                0x00000002  // Set when Bank3 is granted to
-                                            // Stack processor.
-
-#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_GRANT \
-                                0x00000001  // Set when Bank2 is granted to
-                                            // Stack processor.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_STK_CLK_EN register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_STK_CLK_EN_SR_CLK \
-                                0x00000004  // Enable the clock going to sram.
-
-#define STACK_DIE_CTRL_STK_CLK_EN_DFT_CTRL_CLK \
-                                0x00000002  // Enable the clock going to dft
-                                            // control block
-
-#define STACK_DIE_CTRL_STK_CLK_EN_STK_UP_CLK \
-                                0x00000001  // Enable the clock going to Cm3
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_SPIN_LOCK_MODE register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_SPIN_LOCK_MODE_MODE \
-                                0x00000001  // 0 : Handshake Mode 1 : Spinlock
-                                            // mode.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_BUS_FAULT_ADDR register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_M \
-                                0xFFFFFFFF  // Fault Address
-
-#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_BUS_FAULT_CLR register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_BUS_FAULT_CLR_CLEAR \
-                                0x00000001  // When set it'll clear the bust
-                                            // fault address register to store
-                                            // the new bus fault address
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_RESET_CAUSE register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_M \
-                                0xFFFFFFFF
-
-#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_WDOG_TIMER_EVENT register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_M \
-                                0xFFFFFFFF
-
-#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_DMA_REQ register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_DMA_REQ_DMAREQ1 \
-                                0x00000002  // Generate DMAREQ1 on setting this
-                                            // bit.
-
-#define STACK_DIE_CTRL_DMA_REQ_DMAREQ0 \
-                                0x00000001  // Generate DMAREQ0 on setting this
-                                            // bit.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_M \
-                                0xFFFFFFFF
-
-#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_SW_REG1 register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_M \
-                                0xFFFFFFFF
-
-#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_SW_REG2 register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_M \
-                                0xFFFFFFFF
-
-#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_FMC_SLEEP_CTL register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_ACK \
-                                0x00000002  // captures the status of of
-                                            // fmc_lpm_ack
-
-#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_REQ \
-                                0x00000001  // When set assert
-                                            // iflpe2fmc_lpm_req to FMC.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_MISC_CTL register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_MISC_CTL_WDOG_RESET \
-                                0x00000080  // 1 : will reset the async wdog
-                                            // timer runing on piosc clock
-
-#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ2 \
-                                0x00000020  // Setting this Will send to
-                                            // interttupt to CM3
-
-#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ1 \
-                                0x00000010  // Setting this Will send to
-                                            // interttupt to CM3
-
-#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ0 \
-                                0x00000008  // Setting this Will send to
-                                            // interttupt to CM3
-
-#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK3 \
-                                0x00000004  // While testing Flash Setting this
-                                            // bit will Control the
-                                            // CE/STR/AIN/CLKIN going to flash
-                                            // banks 12 and 3. 0 : Control
-                                            // signals coming from FMC for Bank
-                                            // 3 goes to Bank3 1 : Control
-                                            // signals coming from FMC for Bank
-                                            // 0 goes to Bank2
-
-#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK2 \
-                                0x00000002  // While testing Flash Setting this
-                                            // bit will Control the
-                                            // CE/STR/AIN/CLKIN going to flash
-                                            // banks 12 and 3. 0 : Control
-                                            // signals coming from FMC for Bank
-                                            // 2 goes to Bank2 1 : Control
-                                            // signals coming from FMC for Bank
-                                            // 0 goes to Bank2
-
-#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK1 \
-                                0x00000001  // While testing Flash Setting this
-                                            // bit will Control the
-                                            // CE/STR/AIN/CLKIN going to flash
-                                            // banks 12 and 3. 0 : Control
-                                            // signals coming from FMC for Bank
-                                            // 1 goes to Bank1 1 : Control
-                                            // signals coming from FMC for Bank
-                                            // 0 goes to Bank1
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_SW_DFT_CTL register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_SW_DFT_CTL_FL_CTRL_OWNS \
-                                0x20000000  // when set to '1' all flash
-                                            // control signals switch over to
-                                            // CM3 control when '0' it is under
-                                            // the D2D interface control
-
-#define STACK_DIE_CTRL_SW_DFT_CTL_SWIF_CPU_READ \
-                                0x10000000  // 1 indicates in SWIF mode the
-                                            // control signals to flash are from
-                                            // FMC CPU read controls the clock
-                                            // and address. that is one can give
-                                            // address via FMC and read through
-                                            // IDMEM.
-
-#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_DONE \
-                                0x00800000  // 'CPU Done' bit for PBIST. Write
-                                            // '1' to indicate test done.
-
-#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_FAIL \
-                                0x00400000  // 'CPU Fail' bit for PBIST. Write
-                                            // '1' to indicate test failed.
-
-#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK4_OWNS \
-                                0x00001000  // when set to '1' flash bank 4
-                                            // (EEPROM) is owned by the CM3for
-                                            // reads over DCODE bus. When '0'
-                                            // access control given to D2D
-                                            // interface.
-
-#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK3_OWNS \
-                                0x00000800  // when set to '1' flash bank 3 is
-                                            // owned by the CM3for reads over
-                                            // DCODE bus. When '0' access
-                                            // control given to D2D interface.
-
-#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK2_OWNS \
-                                0x00000400  // when set to '1' flash bank 2 is
-                                            // owned by the CM3for reads over
-                                            // DCODE bus. When '0' access
-                                            // control given to D2D interface.
-
-#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK1_OWNS \
-                                0x00000200  // when set to '1' flash bank 1 is
-                                            // owned by the CM3for reads over
-                                            // DCODE bus. When '0' access
-                                            // control given to D2D interface.
-
-#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK0_OWNS \
-                                0x00000100  // when set to '1' flash bank 0 is
-                                            // owned by the CM3 for reads over
-                                            // DCODE bus. When '0' access
-                                            // control given to D2D interface.
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// STACK_DIE_CTRL_O_PADN_CTL_0 register.
-//
-//******************************************************************************
-#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DOUT \
-                                0x00000008  // This bit is valid for only the
-                                            // spare pads ie for n=57 to 59.
-                                            // value to drive at the output of
-                                            // the pad
-
-#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DIN \
-                                0x00000004  // This bit is valid for only the
-                                            // spare pads ie for n=57 to 59.
-                                            // captures the 'Y' pin of the pad
-                                            // which is the data being driven
-                                            // into the die
-
-#define STACK_DIE_CTRL_PADN_CTL_0_OEN2X \
-                                0x00000002  // OEN2X control when '1' enables
-                                            // the output with 1x. Total drive
-                                            // strength is decided bu oen1x
-                                            // setting + oen2x setting.
-
-#define STACK_DIE_CTRL_PADN_CTL_0_OEN1X \
-                                0x00000001  // OEN1X control when '1' enables
-                                            // the output with 1x . Total drive
-                                            // strength is decided bu oen1x
-                                            // setting + oen2x setting.
-
-
-
-
-#endif // __HW_STACK_DIE_CTRL_H__
diff --git a/cc3200/hal/inc/hw_timer.h b/cc3200/hal/inc/hw_timer.h
deleted file mode 100644
index b6844ec67..000000000
--- a/cc3200/hal/inc/hw_timer.h
+++ /dev/null
@@ -1,778 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-// hw_timer.h - Defines and macros used when accessing the timer.
-//
-//*****************************************************************************
-
-//##### INTERNAL BEGIN #####
-//
-// This is an auto-generated file.  Do not edit by hand.
-// Created by version 6779 of DriverLib.
-//
-//##### INTERNAL END #####
-
-#ifndef __HW_TIMER_H__
-#define __HW_TIMER_H__
-
-//*****************************************************************************
-//
-// The following are defines for the Timer register offsets.
-//
-//*****************************************************************************
-#define TIMER_O_CFG             0x00000000  // GPTM Configuration
-#define TIMER_O_TAMR            0x00000004  // GPTM Timer A Mode
-#define TIMER_O_TBMR            0x00000008  // GPTM Timer B Mode
-#define TIMER_O_CTL             0x0000000C  // GPTM Control
-//##### GARNET BEGIN #####
-#define TIMER_O_SYNC            0x00000010  // GPTM Synchronize
-//##### GARNET END #####
-#define TIMER_O_IMR             0x00000018  // GPTM Interrupt Mask
-#define TIMER_O_RIS             0x0000001C  // GPTM Raw Interrupt Status
-#define TIMER_O_MIS             0x00000020  // GPTM Masked Interrupt Status
-#define TIMER_O_ICR             0x00000024  // GPTM Interrupt Clear
-#define TIMER_O_TAILR           0x00000028  // GPTM Timer A Interval Load
-#define TIMER_O_TBILR           0x0000002C  // GPTM Timer B Interval Load
-#define TIMER_O_TAMATCHR        0x00000030  // GPTM Timer A Match
-#define TIMER_O_TBMATCHR        0x00000034  // GPTM Timer B Match
-#define TIMER_O_TAPR            0x00000038  // GPTM Timer A Prescale
-#define TIMER_O_TBPR            0x0000003C  // GPTM Timer B Prescale
-#define TIMER_O_TAPMR           0x00000040  // GPTM TimerA Prescale Match
-#define TIMER_O_TBPMR           0x00000044  // GPTM TimerB Prescale Match
-#define TIMER_O_TAR             0x00000048  // GPTM Timer A
-#define TIMER_O_TBR             0x0000004C  // GPTM Timer B
-#define TIMER_O_TAV             0x00000050  // GPTM Timer A Value
-#define TIMER_O_TBV             0x00000054  // GPTM Timer B Value
-#define TIMER_O_RTCPD           0x00000058  // GPTM RTC Predivide
-#define TIMER_O_TAPS            0x0000005C  // GPTM Timer A Prescale Snapshot
-#define TIMER_O_TBPS            0x00000060  // GPTM Timer B Prescale Snapshot
-#define TIMER_O_TAPV            0x00000064  // GPTM Timer A Prescale Value
-#define TIMER_O_TBPV            0x00000068  // GPTM Timer B Prescale Value
-#define TIMER_O_DMAEV           0x0000006C  // GPTM DMA Event
-#define TIMER_O_PP              0x00000FC0  // GPTM Peripheral Properties
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_CFG register.
-//
-//*****************************************************************************
-#define TIMER_CFG_M             0x00000007  // GPTM Configuration
-#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32-bit timer configuration
-#define TIMER_CFG_32_BIT_RTC    0x00000001  // 32-bit real-time clock (RTC)
-                                            // counter configuration
-#define TIMER_CFG_16_BIT        0x00000004  // 16-bit timer configuration. The
-                                            // function is controlled by bits
-                                            // 1:0 of GPTMTAMR and GPTMTBMR
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAMR register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_TAMR_TAPLO        0x00000800  // GPTM Timer A PWM Legacy
-                                            // Operation
-#define TIMER_TAMR_TAMRSU       0x00000400  // GPTM Timer A Match Register
-                                            // Update
-#define TIMER_TAMR_TAPWMIE      0x00000200  // GPTM Timer A PWM Interrupt
-                                            // Enable
-#define TIMER_TAMR_TAILD        0x00000100  // GPTM Timer A Interval Load Write
-//##### GARNET END #####
-#define TIMER_TAMR_TASNAPS      0x00000080  // GPTM Timer A Snap-Shot Mode
-#define TIMER_TAMR_TAWOT        0x00000040  // GPTM Timer A Wait-on-Trigger
-#define TIMER_TAMR_TAMIE        0x00000020  // GPTM Timer A Match Interrupt
-                                            // Enable
-#define TIMER_TAMR_TACDIR       0x00000010  // GPTM Timer A Count Direction
-#define TIMER_TAMR_TAAMS        0x00000008  // GPTM Timer A Alternate Mode
-                                            // Select
-#define TIMER_TAMR_TACMR        0x00000004  // GPTM Timer A Capture Mode
-#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM Timer A Mode
-#define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode
-#define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode
-#define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBMR register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_TBMR_TBPLO        0x00000800  // GPTM Timer B PWM Legacy
-                                            // Operation
-#define TIMER_TBMR_TBMRSU       0x00000400  // GPTM Timer B Match Register
-                                            // Update
-#define TIMER_TBMR_TBPWMIE      0x00000200  // GPTM Timer B PWM Interrupt
-                                            // Enable
-#define TIMER_TBMR_TBILD        0x00000100  // GPTM Timer B Interval Load Write
-//##### GARNET END #####
-#define TIMER_TBMR_TBSNAPS      0x00000080  // GPTM Timer B Snap-Shot Mode
-#define TIMER_TBMR_TBWOT        0x00000040  // GPTM Timer B Wait-on-Trigger
-#define TIMER_TBMR_TBMIE        0x00000020  // GPTM Timer B Match Interrupt
-                                            // Enable
-#define TIMER_TBMR_TBCDIR       0x00000010  // GPTM Timer B Count Direction
-#define TIMER_TBMR_TBAMS        0x00000008  // GPTM Timer B Alternate Mode
-                                            // Select
-#define TIMER_TBMR_TBCMR        0x00000004  // GPTM Timer B Capture Mode
-#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM Timer B Mode
-#define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode
-#define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode
-#define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_CTL register.
-//
-//*****************************************************************************
-#define TIMER_CTL_TBPWML        0x00004000  // GPTM Timer B PWM Output Level
-#define TIMER_CTL_TBOTE         0x00002000  // GPTM Timer B Output Trigger
-                                            // Enable
-#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM Timer B Event Mode
-#define TIMER_CTL_TBEVENT_POS   0x00000000  // Positive edge
-#define TIMER_CTL_TBEVENT_NEG   0x00000400  // Negative edge
-#define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // Both edges
-#define TIMER_CTL_TBSTALL       0x00000200  // GPTM Timer B Stall Enable
-#define TIMER_CTL_TBEN          0x00000100  // GPTM Timer B Enable
-#define TIMER_CTL_TAPWML        0x00000040  // GPTM Timer A PWM Output Level
-#define TIMER_CTL_TAOTE         0x00000020  // GPTM Timer A Output Trigger
-                                            // Enable
-#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Enable
-#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM Timer A Event Mode
-#define TIMER_CTL_TAEVENT_POS   0x00000000  // Positive edge
-#define TIMER_CTL_TAEVENT_NEG   0x00000004  // Negative edge
-#define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // Both edges
-#define TIMER_CTL_TASTALL       0x00000002  // GPTM Timer A Stall Enable
-#define TIMER_CTL_TAEN          0x00000001  // GPTM Timer A Enable
-//##### GARNET BEGIN #####
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_SYNC register.
-//
-//*****************************************************************************
-#define TIMER_SYNC_SYNC11_M     0x00C00000  // Synchronize GPTM Timer 11
-#define TIMER_SYNC_SYNC11_TA    0x00400000  // A timeout event for Timer A of
-                                            // GPTM11 is triggered
-#define TIMER_SYNC_SYNC11_TB    0x00800000  // A timeout event for Timer B of
-                                            // GPTM11 is triggered
-#define TIMER_SYNC_SYNC11_TATB  0x00C00000  // A timeout event for both Timer A
-                                            // and Timer B of GPTM11 is
-                                            // triggered
-#define TIMER_SYNC_SYNC10_M     0x00300000  // Synchronize GPTM Timer 10
-#define TIMER_SYNC_SYNC10_TA    0x00100000  // A timeout event for Timer A of
-                                            // GPTM10 is triggered
-#define TIMER_SYNC_SYNC10_TB    0x00200000  // A timeout event for Timer B of
-                                            // GPTM10 is triggered
-#define TIMER_SYNC_SYNC10_TATB  0x00300000  // A timeout event for both Timer A
-                                            // and Timer B of GPTM10 is
-                                            // triggered
-#define TIMER_SYNC_SYNC9_M      0x000C0000  // Synchronize GPTM Timer 9
-#define TIMER_SYNC_SYNC9_TA     0x00040000  // A timeout event for Timer A of
-                                            // GPTM9 is triggered
-#define TIMER_SYNC_SYNC9_TB     0x00080000  // A timeout event for Timer B of
-                                            // GPTM9 is triggered
-#define TIMER_SYNC_SYNC9_TATB   0x000C0000  // A timeout event for both Timer A
-                                            // and Timer B of GPTM9 is
-                                            // triggered
-#define TIMER_SYNC_SYNC8_M      0x00030000  // Synchronize GPTM Timer 8
-#define TIMER_SYNC_SYNC8_TA     0x00010000  // A timeout event for Timer A of
-                                            // GPTM8 is triggered
-#define TIMER_SYNC_SYNC8_TB     0x00020000  // A timeout event for Timer B of
-                                            // GPTM8 is triggered
-#define TIMER_SYNC_SYNC8_TATB   0x00030000  // A timeout event for both Timer A
-                                            // and Timer B of GPTM8 is
-                                            // triggered
-#define TIMER_SYNC_SYNC7_M      0x0000C000  // Synchronize GPTM Timer 7
-#define TIMER_SYNC_SYNC7_TA     0x00004000  // A timeout event for Timer A of
-                                            // GPTM7 is triggered
-#define TIMER_SYNC_SYNC7_TB     0x00008000  // A timeout event for Timer B of
-                                            // GPTM7 is triggered
-#define TIMER_SYNC_SYNC7_TATB   0x0000C000  // A timeout event for both Timer A
-                                            // and Timer B of GPTM7 is
-                                            // triggered
-#define TIMER_SYNC_SYNC6_M      0x00003000  // Synchronize GPTM Timer 6
-#define TIMER_SYNC_SYNC6_TA     0x00001000  // A timeout event for Timer A of
-                                            // GPTM6 is triggered
-#define TIMER_SYNC_SYNC6_TB     0x00002000  // A timeout event for Timer B of
-                                            // GPTM6 is triggered
-#define TIMER_SYNC_SYNC6_TATB   0x00003000  // A timeout event for both Timer A
-                                            // and Timer B of GPTM6 is
-                                            // triggered
-#define TIMER_SYNC_SYNC5_M      0x00000C00  // Synchronize GPTM Timer 5
-#define TIMER_SYNC_SYNC5_TA     0x00000400  // A timeout event for Timer A of
-                                            // GPTM5 is triggered
-#define TIMER_SYNC_SYNC5_TB     0x00000800  // A timeout event for Timer B of
-                                            // GPTM5 is triggered
-#define TIMER_SYNC_SYNC5_TATB   0x00000C00  // A timeout event for both Timer A
-                                            // and Timer B of GPTM5 is
-                                            // triggered
-#define TIMER_SYNC_SYNC4_M      0x00000300  // Synchronize GPTM Timer 4
-#define TIMER_SYNC_SYNC4_TA     0x00000100  // A timeout event for Timer A of
-                                            // GPTM4 is triggered
-#define TIMER_SYNC_SYNC4_TB     0x00000200  // A timeout event for Timer B of
-                                            // GPTM4 is triggered
-#define TIMER_SYNC_SYNC4_TATB   0x00000300  // A timeout event for both Timer A
-                                            // and Timer B of GPTM4 is
-                                            // triggered
-#define TIMER_SYNC_SYNC3_M      0x000000C0  // Synchronize GPTM Timer 3
-#define TIMER_SYNC_SYNC3_TA     0x00000040  // A timeout event for Timer A of
-                                            // GPTM3 is triggered
-#define TIMER_SYNC_SYNC3_TB     0x00000080  // A timeout event for Timer B of
-                                            // GPTM3 is triggered
-#define TIMER_SYNC_SYNC3_TATB   0x000000C0  // A timeout event for both Timer A
-                                            // and Timer B of GPTM3 is
-                                            // triggered
-#define TIMER_SYNC_SYNC2_M      0x00000030  // Synchronize GPTM Timer 2
-#define TIMER_SYNC_SYNC2_TA     0x00000010  // A timeout event for Timer A of
-                                            // GPTM2 is triggered
-#define TIMER_SYNC_SYNC2_TB     0x00000020  // A timeout event for Timer B of
-                                            // GPTM2 is triggered
-#define TIMER_SYNC_SYNC2_TATB   0x00000030  // A timeout event for both Timer A
-                                            // and Timer B of GPTM2 is
-                                            // triggered
-#define TIMER_SYNC_SYNC1_M      0x0000000C  // Synchronize GPTM Timer 1
-#define TIMER_SYNC_SYNC1_TA     0x00000004  // A timeout event for Timer A of
-                                            // GPTM1 is triggered
-#define TIMER_SYNC_SYNC1_TB     0x00000008  // A timeout event for Timer B of
-                                            // GPTM1 is triggered
-#define TIMER_SYNC_SYNC1_TATB   0x0000000C  // A timeout event for both Timer A
-                                            // and Timer B of GPTM1 is
-                                            // triggered
-#define TIMER_SYNC_SYNC0_M      0x00000003  // Synchronize GPTM Timer 0
-#define TIMER_SYNC_SYNC0_TA     0x00000001  // A timeout event for Timer A of
-                                            // GPTM0 is triggered
-#define TIMER_SYNC_SYNC0_TB     0x00000002  // A timeout event for Timer B of
-                                            // GPTM0 is triggered
-#define TIMER_SYNC_SYNC0_TATB   0x00000003  // A timeout event for both Timer A
-                                            // and Timer B of GPTM0 is
-                                            // triggered
-//##### GARNET END #####
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_IMR register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_IMR_WUEIM         0x00010000  // 32/64-Bit GPTM Write Update
-                                            // Error Interrupt Mask
-//##### GARNET END #####
-#define TIMER_IMR_TBMIM         0x00000800  // GPTM Timer B Mode Match
-                                            // Interrupt Mask
-#define TIMER_IMR_CBEIM         0x00000400  // GPTM Capture B Event Interrupt
-                                            // Mask
-#define TIMER_IMR_CBMIM         0x00000200  // GPTM Capture B Match Interrupt
-                                            // Mask
-#define TIMER_IMR_TBTOIM        0x00000100  // GPTM Timer B Time-Out Interrupt
-                                            // Mask
-#define TIMER_IMR_TAMIM         0x00000010  // GPTM Timer A Mode Match
-                                            // Interrupt Mask
-#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask
-#define TIMER_IMR_CAEIM         0x00000004  // GPTM Capture A Event Interrupt
-                                            // Mask
-#define TIMER_IMR_CAMIM         0x00000002  // GPTM Capture A Match Interrupt
-                                            // Mask
-#define TIMER_IMR_TATOIM        0x00000001  // GPTM Timer A Time-Out Interrupt
-                                            // Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_RIS register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_RIS_WUERIS        0x00010000  // 32/64-Bit GPTM Write Update
-                                            // Error Raw Interrupt Status
-//##### GARNET END #####
-#define TIMER_RIS_TBMRIS        0x00000800  // GPTM Timer B Mode Match Raw
-                                            // Interrupt
-#define TIMER_RIS_CBERIS        0x00000400  // GPTM Capture B Event Raw
-                                            // Interrupt
-#define TIMER_RIS_CBMRIS        0x00000200  // GPTM Capture B Match Raw
-                                            // Interrupt
-#define TIMER_RIS_TBTORIS       0x00000100  // GPTM Timer B Time-Out Raw
-                                            // Interrupt
-#define TIMER_RIS_TAMRIS        0x00000010  // GPTM Timer A Mode Match Raw
-                                            // Interrupt
-#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt
-#define TIMER_RIS_CAERIS        0x00000004  // GPTM Capture A Event Raw
-                                            // Interrupt
-#define TIMER_RIS_CAMRIS        0x00000002  // GPTM Capture A Match Raw
-                                            // Interrupt
-#define TIMER_RIS_TATORIS       0x00000001  // GPTM Timer A Time-Out Raw
-                                            // Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_MIS register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_MIS_WUEMIS        0x00010000  // 32/64-Bit GPTM Write Update
-                                            // Error Masked Interrupt Status
-//##### GARNET END #####
-#define TIMER_MIS_TBMMIS        0x00000800  // GPTM Timer B Mode Match Masked
-                                            // Interrupt
-#define TIMER_MIS_CBEMIS        0x00000400  // GPTM Capture B Event Masked
-                                            // Interrupt
-#define TIMER_MIS_CBMMIS        0x00000200  // GPTM Capture B Match Masked
-                                            // Interrupt
-#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM Timer B Time-Out Masked
-                                            // Interrupt
-#define TIMER_MIS_TAMMIS        0x00000010  // GPTM Timer A Mode Match Masked
-                                            // Interrupt
-#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt
-#define TIMER_MIS_CAEMIS        0x00000004  // GPTM Capture A Event Masked
-                                            // Interrupt
-#define TIMER_MIS_CAMMIS        0x00000002  // GPTM Capture A Match Masked
-                                            // Interrupt
-#define TIMER_MIS_TATOMIS       0x00000001  // GPTM Timer A Time-Out Masked
-                                            // Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_ICR register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_ICR_WUECINT       0x00010000  // 32/64-Bit GPTM Write Update
-                                            // Error Interrupt Clear
-//##### GARNET END #####
-#define TIMER_ICR_TBMCINT       0x00000800  // GPTM Timer B Mode Match
-                                            // Interrupt Clear
-#define TIMER_ICR_CBECINT       0x00000400  // GPTM Capture B Event Interrupt
-                                            // Clear
-#define TIMER_ICR_CBMCINT       0x00000200  // GPTM Capture B Match Interrupt
-                                            // Clear
-#define TIMER_ICR_TBTOCINT      0x00000100  // GPTM Timer B Time-Out Interrupt
-                                            // Clear
-#define TIMER_ICR_TAMCINT       0x00000010  // GPTM Timer A Mode Match
-                                            // Interrupt Clear
-#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear
-#define TIMER_ICR_CAECINT       0x00000004  // GPTM Capture A Event Interrupt
-                                            // Clear
-#define TIMER_ICR_CAMCINT       0x00000002  // GPTM Capture A Match Interrupt
-                                            // Clear
-#define TIMER_ICR_TATOCINT      0x00000001  // GPTM Timer A Time-Out Raw
-                                            // Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAILR register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_TAILR_M           0xFFFFFFFF  // GPTM Timer A Interval Load
-                                            // Register
-//##### GARNET END #####
-#define TIMER_TAILR_TAILRH_M    0xFFFF0000  // GPTM Timer A Interval Load
-                                            // Register High
-#define TIMER_TAILR_TAILRL_M    0x0000FFFF  // GPTM Timer A Interval Load
-                                            // Register Low
-#define TIMER_TAILR_TAILRH_S    16
-#define TIMER_TAILR_TAILRL_S    0
-//##### GARNET BEGIN #####
-#define TIMER_TAILR_S           0
-//##### GARNET END #####
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBILR register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_TBILR_M           0xFFFFFFFF  // GPTM Timer B Interval Load
-                                            // Register
-//##### GARNET END #####
-#define TIMER_TBILR_TBILRL_M    0x0000FFFF  // GPTM Timer B Interval Load
-                                            // Register
-#define TIMER_TBILR_TBILRL_S    0
-//##### GARNET BEGIN #####
-#define TIMER_TBILR_S           0
-//##### GARNET END #####
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAMATCHR
-// register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_TAMATCHR_TAMR_M   0xFFFFFFFF  // GPTM Timer A Match Register
-//##### GARNET END #####
-#define TIMER_TAMATCHR_TAMRH_M  0xFFFF0000  // GPTM Timer A Match Register High
-#define TIMER_TAMATCHR_TAMRL_M  0x0000FFFF  // GPTM Timer A Match Register Low
-#define TIMER_TAMATCHR_TAMRH_S  16
-#define TIMER_TAMATCHR_TAMRL_S  0
-//##### GARNET BEGIN #####
-#define TIMER_TAMATCHR_TAMR_S   0
-//##### GARNET END #####
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBMATCHR
-// register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_TBMATCHR_TBMR_M   0xFFFFFFFF  // GPTM Timer B Match Register
-//##### GARNET END #####
-#define TIMER_TBMATCHR_TBMRL_M  0x0000FFFF  // GPTM Timer B Match Register Low
-//##### GARNET BEGIN #####
-#define TIMER_TBMATCHR_TBMR_S   0
-//##### GARNET END #####
-#define TIMER_TBMATCHR_TBMRL_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAPR register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_TAPR_TAPSRH_M     0x0000FF00  // GPTM Timer A Prescale High Byte
-//##### GARNET END #####
-#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM Timer A Prescale
-//##### GARNET BEGIN #####
-#define TIMER_TAPR_TAPSRH_S     8
-//##### GARNET END #####
-#define TIMER_TAPR_TAPSR_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBPR register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_TBPR_TBPSRH_M     0x0000FF00  // GPTM Timer B Prescale High Byte
-//##### GARNET END #####
-#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM Timer B Prescale
-//##### GARNET BEGIN #####
-#define TIMER_TBPR_TBPSRH_S     8
-//##### GARNET END #####
-#define TIMER_TBPR_TBPSR_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAPMR register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_TAPMR_TAPSMRH_M   0x0000FF00  // GPTM Timer A Prescale Match High
-                                            // Byte
-//##### GARNET END #####
-#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match
-//##### GARNET BEGIN #####
-#define TIMER_TAPMR_TAPSMRH_S   8
-//##### GARNET END #####
-#define TIMER_TAPMR_TAPSMR_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBPMR register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_TBPMR_TBPSMRH_M   0x0000FF00  // GPTM Timer B Prescale Match High
-                                            // Byte
-//##### GARNET END #####
-#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match
-//##### GARNET BEGIN #####
-#define TIMER_TBPMR_TBPSMRH_S   8
-//##### GARNET END #####
-#define TIMER_TBPMR_TBPSMR_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAR register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_TAR_M             0xFFFFFFFF  // GPTM Timer A Register
-//##### GARNET END #####
-#define TIMER_TAR_TARH_M        0xFFFF0000  // GPTM Timer A Register High
-#define TIMER_TAR_TARL_M        0x0000FFFF  // GPTM Timer A Register Low
-#define TIMER_TAR_TARH_S        16
-#define TIMER_TAR_TARL_S        0
-//##### GARNET BEGIN #####
-#define TIMER_TAR_S             0
-//##### GARNET END #####
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBR register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_TBR_M             0xFFFFFFFF  // GPTM Timer B Register
-//##### GARNET END #####
-#define TIMER_TBR_TBRL_M        0x00FFFFFF  // GPTM Timer B
-#define TIMER_TBR_TBRL_S        0
-//##### GARNET BEGIN #####
-#define TIMER_TBR_S             0
-//##### GARNET END #####
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAV register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_TAV_M             0xFFFFFFFF  // GPTM Timer A Value
-//##### GARNET END #####
-#define TIMER_TAV_TAVH_M        0xFFFF0000  // GPTM Timer A Value High
-#define TIMER_TAV_TAVL_M        0x0000FFFF  // GPTM Timer A Register Low
-#define TIMER_TAV_TAVH_S        16
-#define TIMER_TAV_TAVL_S        0
-//##### GARNET BEGIN #####
-#define TIMER_TAV_S             0
-//##### GARNET END #####
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBV register.
-//
-//*****************************************************************************
-//##### GARNET BEGIN #####
-#define TIMER_TBV_M             0xFFFFFFFF  // GPTM Timer B Value
-//##### GARNET END #####
-#define TIMER_TBV_TBVL_M        0x0000FFFF  // GPTM Timer B Register
-#define TIMER_TBV_TBVL_S        0
-//##### GARNET BEGIN #####
-#define TIMER_TBV_S             0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_RTCPD register.
-//
-//*****************************************************************************
-#define TIMER_RTCPD_RTCPD_M     0x0000FFFF  // RTC Predivide Counter Value
-#define TIMER_RTCPD_RTCPD_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAPS register.
-//
-//*****************************************************************************
-#define TIMER_TAPS_PSS_M        0x0000FFFF  // GPTM Timer A Prescaler Snapshot
-#define TIMER_TAPS_PSS_S        0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBPS register.
-//
-//*****************************************************************************
-#define TIMER_TBPS_PSS_M        0x0000FFFF  // GPTM Timer A Prescaler Value
-#define TIMER_TBPS_PSS_S        0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAPV register.
-//
-//*****************************************************************************
-#define TIMER_TAPV_PSV_M        0x0000FFFF  // GPTM Timer A Prescaler Value
-#define TIMER_TAPV_PSV_S        0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBPV register.
-//
-//*****************************************************************************
-#define TIMER_TBPV_PSV_M        0x0000FFFF  // GPTM Timer B Prescaler Value
-#define TIMER_TBPV_PSV_S        0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_PP register.
-//
-//*****************************************************************************
-#define TIMER_PP_SYNCCNT        0x00000020  // Synchronize Start
-#define TIMER_PP_CHAIN          0x00000010  // Chain with Other Timers
-#define TIMER_PP_SIZE_M         0x0000000F  // Count Size
-#define TIMER_PP_SIZE__0        0x00000000  // Timer A and Timer B counters are
-                                            // 16 bits each with an 8-bit
-                                            // prescale counter
-#define TIMER_PP_SIZE__1        0x00000001  // Timer A and Timer B counters are
-                                            // 32 bits each with an 16-bit
-                                            // prescale counter
-//##### GARNET END #####
-
-//*****************************************************************************
-//
-// The following definitions are deprecated.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_O_CFG
-// register.
-//
-//*****************************************************************************
-#define TIMER_CFG_CFG_MSK       0x00000007  // Configuration options mask
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_O_CTL
-// register.
-//
-//*****************************************************************************
-#define TIMER_CTL_TBEVENT_MSK   0x00000C00  // TimerB event mode mask
-#define TIMER_CTL_TAEVENT_MSK   0x0000000C  // TimerA event mode mask
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_O_RIS
-// register.
-//
-//*****************************************************************************
-#define TIMER_RIS_CBEMIS        0x00000400  // CaptureB event masked int status
-#define TIMER_RIS_CBMMIS        0x00000200  // CaptureB match masked int status
-#define TIMER_RIS_TBTOMIS       0x00000100  // TimerB time out masked int stat
-#define TIMER_RIS_RTCMIS        0x00000008  // RTC masked int status
-#define TIMER_RIS_CAEMIS        0x00000004  // CaptureA event masked int status
-#define TIMER_RIS_CAMMIS        0x00000002  // CaptureA match masked int status
-#define TIMER_RIS_TATOMIS       0x00000001  // TimerA time out masked int stat
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_O_TAILR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TAILR_TAILRH      0xFFFF0000  // TimerB load val in 32 bit mode
-#define TIMER_TAILR_TAILRL      0x0000FFFF  // TimerA interval load value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_O_TBILR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TBILR_TBILRL      0x0000FFFF  // TimerB interval load value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the
-// TIMER_O_TAMATCHR register.
-//
-//*****************************************************************************
-#define TIMER_TAMATCHR_TAMRH    0xFFFF0000  // TimerB match val in 32 bit mode
-#define TIMER_TAMATCHR_TAMRL    0x0000FFFF  // TimerA match value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the
-// TIMER_O_TBMATCHR register.
-//
-//*****************************************************************************
-#define TIMER_TBMATCHR_TBMRL    0x0000FFFF  // TimerB match load value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_O_TAR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TAR_TARH          0xFFFF0000  // TimerB val in 32 bit mode
-#define TIMER_TAR_TARL          0x0000FFFF  // TimerA value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_O_TBR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TBR_TBRL          0x0000FFFF  // TimerB value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the reset values of the timer
-// registers.
-//
-//*****************************************************************************
-#define TIMER_RV_TAILR          0xFFFFFFFF  // TimerA interval load reg RV
-#define TIMER_RV_TAR            0xFFFFFFFF  // TimerA register RV
-#define TIMER_RV_TAMATCHR       0xFFFFFFFF  // TimerA match register RV
-#define TIMER_RV_TBILR          0x0000FFFF  // TimerB interval load reg RV
-#define TIMER_RV_TBMATCHR       0x0000FFFF  // TimerB match register RV
-#define TIMER_RV_TBR            0x0000FFFF  // TimerB register RV
-#define TIMER_RV_TAPR           0x00000000  // TimerA prescale register RV
-#define TIMER_RV_CFG            0x00000000  // Configuration register RV
-#define TIMER_RV_TBPMR          0x00000000  // TimerB prescale match regi RV
-#define TIMER_RV_TAPMR          0x00000000  // TimerA prescale match reg RV
-#define TIMER_RV_CTL            0x00000000  // Control register RV
-#define TIMER_RV_ICR            0x00000000  // Interrupt clear register RV
-#define TIMER_RV_TBMR           0x00000000  // TimerB mode register RV
-#define TIMER_RV_MIS            0x00000000  // Masked interrupt status reg RV
-#define TIMER_RV_RIS            0x00000000  // Interrupt status register RV
-#define TIMER_RV_TBPR           0x00000000  // TimerB prescale register RV
-#define TIMER_RV_IMR            0x00000000  // Interrupt mask register RV
-#define TIMER_RV_TAMR           0x00000000  // TimerA mode register RV
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_TnMR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TNMR_TNAMS        0x00000008  // Alternate mode select
-#define TIMER_TNMR_TNCMR        0x00000004  // Capture mode - count or time
-#define TIMER_TNMR_TNTMR_MSK    0x00000003  // Timer mode mask
-#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001  // Mode - one shot
-#define TIMER_TNMR_TNTMR_PERIOD 0x00000002  // Mode - periodic
-#define TIMER_TNMR_TNTMR_CAP    0x00000003  // Mode - capture
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_TnPR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TNPR_TNPSR        0x000000FF  // TimerN prescale value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_TnPMR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TNPMR_TNPSMR      0x000000FF  // TimerN prescale match value
-
-#endif
-
-#endif // __HW_TIMER_H__
diff --git a/cc3200/hal/inc/hw_types.h b/cc3200/hal/inc/hw_types.h
deleted file mode 100644
index d7a6ab4fe..000000000
--- a/cc3200/hal/inc/hw_types.h
+++ /dev/null
@@ -1,76 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_TYPES_H__
-#define __HW_TYPES_H__
-
-//*****************************************************************************
-//
-// Define a boolean type, and values for true and false.
-//
-//*****************************************************************************
-typedef unsigned char tBoolean;
-
-#ifndef true
-#define true 1
-#endif
-
-#ifndef false
-#define false 0
-#endif
-
-//*****************************************************************************
-//
-// Macros for hardware access, both direct and via the bit-band region.
-//
-//*****************************************************************************
-#define HWREG(x)                                                              \
-        (*((volatile unsigned long *)(x)))
-#define HWREGH(x)                                                             \
-        (*((volatile unsigned short *)(x)))
-#define HWREGB(x)                                                             \
-        (*((volatile unsigned char *)(x)))
-#define HWREGBITW(x, b)                                                       \
-        HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 |                \
-              (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
-#define HWREGBITH(x, b)                                                       \
-        HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 |               \
-               (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
-#define HWREGBITB(x, b)                                                       \
-        HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 |               \
-               (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
-
-
-#endif // __HW_TYPES_H__
diff --git a/cc3200/hal/inc/hw_uart.h b/cc3200/hal/inc/hw_uart.h
deleted file mode 100644
index ae50ac381..000000000
--- a/cc3200/hal/inc/hw_uart.h
+++ /dev/null
@@ -1,417 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_UART_H__
-#define __HW_UART_H__
-
-//*****************************************************************************
-//
-// The following are defines for the UART register offsets.
-//
-//*****************************************************************************
-#define UART_O_DR               0x00000000
-#define UART_O_RSR              0x00000004
-#define UART_O_ECR              0x00000004
-#define UART_O_FR               0x00000018
-#define UART_O_ILPR             0x00000020
-#define UART_O_IBRD             0x00000024
-#define UART_O_FBRD             0x00000028
-#define UART_O_LCRH             0x0000002C
-#define UART_O_CTL              0x00000030
-#define UART_O_IFLS             0x00000034
-#define UART_O_IM               0x00000038
-#define UART_O_RIS              0x0000003C
-#define UART_O_MIS              0x00000040
-#define UART_O_ICR              0x00000044
-#define UART_O_DMACTL           0x00000048
-#define UART_O_LCTL             0x00000090
-#define UART_O_LSS              0x00000094
-#define UART_O_LTIM             0x00000098
-#define UART_O_9BITADDR      0x000000A4
-#define UART_O_9BITAMASK     0x000000A8
-#define UART_O_PP               0x00000FC0
-#define UART_O_CC               0x00000FC8
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_DR register.
-//
-//******************************************************************************
-#define UART_DR_OE              0x00000800  // UART Overrun Error
-#define UART_DR_BE              0x00000400  // UART Break Error
-#define UART_DR_PE              0x00000200  // UART Parity Error
-#define UART_DR_FE              0x00000100  // UART Framing Error
-#define UART_DR_DATA_M        0x000000FF  // Data Transmitted or Received
-#define UART_DR_DATA_S        0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_RSR register.
-//
-//******************************************************************************
-#define UART_RSR_OE             0x00000008  // UART Overrun Error
-#define UART_RSR_BE             0x00000004  // UART Break Error
-#define UART_RSR_PE             0x00000002  // UART Parity Error
-#define UART_RSR_FE             0x00000001  // UART Framing Error
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_ECR register.
-//
-//******************************************************************************
-#define UART_ECR_DATA_M       0x000000FF  // Error Clear
-#define UART_ECR_DATA_S       0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_FR register.
-//
-//******************************************************************************
-#define UART_FR_RI              0x00000100  // Ring Indicator
-#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty
-#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full
-#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full
-#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty
-#define UART_FR_BUSY            0x00000008  // UART Busy
-#define UART_FR_DCD             0x00000004  // Data Carrier Detect
-#define UART_FR_DSR             0x00000002  // Data Set Ready
-#define UART_FR_CTS             0x00000001  // Clear To Send
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_ILPR register.
-//
-//******************************************************************************
-#define UART_ILPR_ILPDVSR_M   0x000000FF  // IrDA Low-Power Divisor
-#define UART_ILPR_ILPDVSR_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_IBRD register.
-//
-//******************************************************************************
-#define UART_IBRD_DIVINT_M    0x0000FFFF  // Integer Baud-Rate Divisor
-#define UART_IBRD_DIVINT_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_FBRD register.
-//
-//******************************************************************************
-#define UART_FBRD_DIVFRAC_M   0x0000003F  // Fractional Baud-Rate Divisor
-#define UART_FBRD_DIVFRAC_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_LCRH register.
-//
-//******************************************************************************
-#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select
-#define UART_LCRH_WLEN_M      0x00000060  // UART Word Length 0x00000000 :
-                                            // UART_LCRH_WLEN_5 : 5 bits
-                                            // (default) 0x00000020 :
-                                            // UART_LCRH_WLEN_6 : 6 bits
-                                            // 0x00000040 : UART_LCRH_WLEN_7 : 7
-                                            // bits 0x00000060 :
-                                            // UART_LCRH_WLEN_8 : 8 bits
-#define UART_LCRH_WLEN_S      5
-#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs
-#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select
-#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select
-#define UART_LCRH_PEN           0x00000002  // UART Parity Enable
-#define UART_LCRH_BRK           0x00000001  // UART Send Break
-#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length
-#define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
-#define UART_LCRH_WLEN_6        0x00000020  // 6 bits
-#define UART_LCRH_WLEN_7        0x00000040  // 7 bits
-#define UART_LCRH_WLEN_8        0x00000060  // 8 bits
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_CTL register.
-//
-//******************************************************************************
-#define UART_CTL_CTSEN          0x00008000  // Enable Clear To Send
-#define UART_CTL_RTSEN          0x00004000  // Enable Request to Send
-#define UART_CTL_RI             0x00002000  // Ring Indicator
-#define UART_CTL_DCD            0x00001000  // Data Carrier Detect
-#define UART_CTL_RTS            0x00000800  // Request to Send
-#define UART_CTL_DTR            0x00000400  // Data Terminal Ready
-#define UART_CTL_RXE            0x00000200  // UART Receive Enable
-#define UART_CTL_TXE            0x00000100  // UART Transmit Enable
-#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable
-#define UART_CTL_LIN            0x00000040  // LIN Mode Enable
-#define UART_CTL_HSE            0x00000020  // High-Speed Enable
-#define UART_CTL_EOT            0x00000010  // End of Transmission
-#define UART_CTL_SMART          0x00000008  // ISO 7816 Smart Card Support
-#define UART_CTL_SIRLP          0x00000004  // UART SIR Low-Power Mode
-#define UART_CTL_SIREN          0x00000002  // UART SIR Enable
-#define UART_CTL_UARTEN         0x00000001  // UART Enable
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_IFLS register.
-//
-//******************************************************************************
-#define UART_IFLS_RX_M        0x00000038  // UART Receive Interrupt FIFO
-                                            // Level Select
-#define UART_IFLS_RX_S        3
-#define UART_IFLS_TX_M        0x00000007  // UART Transmit Interrupt FIFO
-                                            // Level Select
-#define UART_IFLS_TX_S        0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_IM register.
-//
-//******************************************************************************
-#define UART_IM_DMATXIM         0x00020000  // Transmit DMA Interrupt Mask
-#define UART_IM_DMARXIM         0x00010000  // Receive DMA Interrupt Mask
-#define UART_IM_LME5IM          0x00008000  // LIN Mode Edge 5 Interrupt Mask
-#define UART_IM_LME1IM          0x00004000  // LIN Mode Edge 1 Interrupt Mask
-#define UART_IM_LMSBIM          0x00002000  // LIN Mode Sync Break Interrupt
-                                            // Mask
-#define UART_IM_9BITIM       0x00001000  // 9-Bit Mode Interrupt Mask
-#define UART_IM_EOTIM           0x00000800  // End of Transmission Interrupt
-                                            // Mask
-#define UART_IM_OEIM            0x00000400  // UART Overrun Error Interrupt
-                                            // Mask
-#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask
-#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt Mask
-#define UART_IM_FEIM            0x00000080  // UART Framing Error Interrupt
-                                            // Mask
-#define UART_IM_RTIM            0x00000040  // UART Receive Time-Out Interrupt
-                                            // Mask
-#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask
-#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask
-#define UART_IM_DSRMIM          0x00000008  // UART Data Set Ready Modem
-                                            // Interrupt Mask
-#define UART_IM_DCDMIM          0x00000004  // UART Data Carrier Detect Modem
-                                            // Interrupt Mask
-#define UART_IM_CTSMIM          0x00000002  // UART Clear to Send Modem
-                                            // Interrupt Mask
-#define UART_IM_RIMIM           0x00000001  // UART Ring Indicator Modem
-                                            // Interrupt Mask
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_RIS register.
-//
-//******************************************************************************
-#define UART_RIS_DMATXRIS       0x00020000  // Transmit DMA Raw Interrupt
-                                            // Status
-#define UART_RIS_DMARXRIS       0x00010000  // Receive DMA Raw Interrupt Status
-#define UART_RIS_LME5RIS        0x00008000  // LIN Mode Edge 5 Raw Interrupt
-                                            // Status
-#define UART_RIS_LME1RIS        0x00004000  // LIN Mode Edge 1 Raw Interrupt
-                                            // Status
-#define UART_RIS_LMSBRIS        0x00002000  // LIN Mode Sync Break Raw
-                                            // Interrupt Status
-#define UART_RIS_9BITRIS     0x00001000  // 9-Bit Mode Raw Interrupt Status
-#define UART_RIS_EOTRIS         0x00000800  // End of Transmission Raw
-                                            // Interrupt Status
-#define UART_RIS_OERIS          0x00000400  // UART Overrun Error Raw Interrupt
-                                            // Status
-#define UART_RIS_BERIS          0x00000200  // UART Break Error Raw Interrupt
-                                            // Status
-#define UART_RIS_PERIS          0x00000100  // UART Parity Error Raw Interrupt
-                                            // Status
-#define UART_RIS_FERIS          0x00000080  // UART Framing Error Raw Interrupt
-                                            // Status
-#define UART_RIS_RTRIS          0x00000040  // UART Receive Time-Out Raw
-                                            // Interrupt Status
-#define UART_RIS_TXRIS          0x00000020  // UART Transmit Raw Interrupt
-                                            // Status
-#define UART_RIS_RXRIS          0x00000010  // UART Receive Raw Interrupt
-                                            // Status
-#define UART_RIS_DSRRIS         0x00000008  // UART Data Set Ready Modem Raw
-                                            // Interrupt Status
-#define UART_RIS_DCDRIS         0x00000004  // UART Data Carrier Detect Modem
-                                            // Raw Interrupt Status
-#define UART_RIS_CTSRIS         0x00000002  // UART Clear to Send Modem Raw
-                                            // Interrupt Status
-#define UART_RIS_RIRIS          0x00000001  // UART Ring Indicator Modem Raw
-                                            // Interrupt Status
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_MIS register.
-//
-//******************************************************************************
-#define UART_MIS_DMATXMIS       0x00020000  // Transmit DMA Masked Interrupt
-                                            // Status
-#define UART_MIS_DMARXMIS       0x00010000  // Receive DMA Masked Interrupt
-                                            // Status
-#define UART_MIS_LME5MIS        0x00008000  // LIN Mode Edge 5 Masked Interrupt
-                                            // Status
-#define UART_MIS_LME1MIS        0x00004000  // LIN Mode Edge 1 Masked Interrupt
-                                            // Status
-#define UART_MIS_LMSBMIS        0x00002000  // LIN Mode Sync Break Masked
-                                            // Interrupt Status
-#define UART_MIS_9BITMIS     0x00001000  // 9-Bit Mode Masked Interrupt
-                                            // Status
-#define UART_MIS_EOTMIS         0x00000800  // End of Transmission Masked
-                                            // Interrupt Status
-#define UART_MIS_OEMIS          0x00000400  // UART Overrun Error Masked
-                                            // Interrupt Status
-#define UART_MIS_BEMIS          0x00000200  // UART Break Error Masked
-                                            // Interrupt Status
-#define UART_MIS_PEMIS          0x00000100  // UART Parity Error Masked
-                                            // Interrupt Status
-#define UART_MIS_FEMIS          0x00000080  // UART Framing Error Masked
-                                            // Interrupt Status
-#define UART_MIS_RTMIS          0x00000040  // UART Receive Time-Out Masked
-                                            // Interrupt Status
-#define UART_MIS_TXMIS          0x00000020  // UART Transmit Masked Interrupt
-                                            // Status
-#define UART_MIS_RXMIS          0x00000010  // UART Receive Masked Interrupt
-                                            // Status
-#define UART_MIS_DSRMIS         0x00000008  // UART Data Set Ready Modem Masked
-                                            // Interrupt Status
-#define UART_MIS_DCDMIS         0x00000004  // UART Data Carrier Detect Modem
-                                            // Masked Interrupt Status
-#define UART_MIS_CTSMIS         0x00000002  // UART Clear to Send Modem Masked
-                                            // Interrupt Status
-#define UART_MIS_RIMIS          0x00000001  // UART Ring Indicator Modem Masked
-                                            // Interrupt Status
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_ICR register.
-//
-//******************************************************************************
-#define UART_ICR_DMATXIC        0x00020000  // Transmit DMA Interrupt Clear
-#define UART_ICR_DMARXIC        0x00010000  // Receive DMA Interrupt Clear
-#define UART_ICR_LME5MIC        0x00008000  // LIN Mode Edge 5 Interrupt Clear
-#define UART_ICR_LME1MIC        0x00004000  // LIN Mode Edge 1 Interrupt Clear
-#define UART_ICR_LMSBMIC        0x00002000  // LIN Mode Sync Break Interrupt
-                                            // Clear
-#define UART_ICR_9BITIC      0x00001000  // 9-Bit Mode Interrupt Clear
-#define UART_ICR_EOTIC          0x00000800  // End of Transmission Interrupt
-                                            // Clear
-#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear
-#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear
-#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear
-#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear
-#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt Clear
-#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear
-#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear
-#define UART_ICR_DSRMIC         0x00000008  // UART Data Set Ready Modem
-                                            // Interrupt Clear
-#define UART_ICR_DCDMIC         0x00000004  // UART Data Carrier Detect Modem
-                                            // Interrupt Clear
-#define UART_ICR_CTSMIC         0x00000002  // UART Clear to Send Modem
-                                            // Interrupt Clear
-#define UART_ICR_RIMIC          0x00000001  // UART Ring Indicator Modem
-                                            // Interrupt Clear
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_DMACTL register.
-//
-//******************************************************************************
-#define UART_DMACTL_DMAERR      0x00000004  // DMA on Error
-#define UART_DMACTL_TXDMAE      0x00000002  // Transmit DMA Enable
-#define UART_DMACTL_RXDMAE      0x00000001  // Receive DMA Enable
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_LCTL register.
-//
-//******************************************************************************
-#define UART_LCTL_BLEN_M      0x00000030  // Sync Break Length 0x00000000 :
-                                            // UART_LCTL_BLEN_13T : Sync break
-                                            // length is 13T bits (default)
-                                            // 0x00000010 : UART_LCTL_BLEN_14T :
-                                            // Sync break length is 14T bits
-                                            // 0x00000020 : UART_LCTL_BLEN_15T :
-                                            // Sync break length is 15T bits
-                                            // 0x00000030 : UART_LCTL_BLEN_16T :
-                                            // Sync break length is 16T bits
-#define UART_LCTL_BLEN_S      4
-#define UART_LCTL_MASTER        0x00000001  // LIN Master Enable
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_LSS register.
-//
-//******************************************************************************
-#define UART_LSS_TSS_M        0x0000FFFF  // Timer Snap Shot
-#define UART_LSS_TSS_S        0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_LTIM register.
-//
-//******************************************************************************
-#define UART_LTIM_TIMER_M     0x0000FFFF  // Timer Value
-#define UART_LTIM_TIMER_S     0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// UART_O_9BITADDR register.
-//
-//******************************************************************************
-#define UART_9BITADDR_9BITEN \
-                                0x00008000  // Enable 9-Bit Mode
-
-#define UART_9BITADDR_ADDR_M \
-                                0x000000FF  // Self Address for 9-Bit Mode
-
-#define UART_9BITADDR_ADDR_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// UART_O_9BITAMASK register.
-//
-//******************************************************************************
-#define UART_9BITAMASK_RANGE_M \
-                                0x0000FF00  // Self Address Range for 9-Bit
-                                            // Mode
-
-#define UART_9BITAMASK_RANGE_S 8
-#define UART_9BITAMASK_MASK_M \
-                                0x000000FF  // Self Address Mask for 9-Bit Mode
-
-#define UART_9BITAMASK_MASK_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_PP register.
-//
-//******************************************************************************
-#define UART_PP_MSE             0x00000008  // Modem Support Extended
-#define UART_PP_MS              0x00000004  // Modem Support
-#define UART_PP_NB              0x00000002  // 9-Bit Support
-#define UART_PP_SC              0x00000001  // Smart Card Support
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_CC register.
-//
-//******************************************************************************
-#define UART_CC_CS_M          0x0000000F  // UART Baud Clock Source
-                                            // 0x00000005 : UART_CC_CS_PIOSC :
-                                            // PIOSC 0x00000000 :
-                                            // UART_CC_CS_SYSCLK : The system
-                                            // clock (default)
-#define UART_CC_CS_S          0
-
-
-
-#endif // __HW_UART_H__
diff --git a/cc3200/hal/inc/hw_udma.h b/cc3200/hal/inc/hw_udma.h
deleted file mode 100644
index 9a495baea..000000000
--- a/cc3200/hal/inc/hw_udma.h
+++ /dev/null
@@ -1,336 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_UDMA_H__
-#define __HW_UDMA_H__
-
-//*****************************************************************************
-//
-// The following are defines for the UDMA register offsets.
-//
-//*****************************************************************************
-#define UDMA_O_STAT             0x00000000
-#define UDMA_O_CFG              0x00000004
-#define UDMA_O_CTLBASE          0x00000008
-#define UDMA_O_ALTBASE          0x0000000C
-#define UDMA_O_WAITSTAT         0x00000010
-#define UDMA_O_SWREQ            0x00000014
-#define UDMA_O_USEBURSTSET      0x00000018
-#define UDMA_O_USEBURSTCLR      0x0000001C
-#define UDMA_O_REQMASKSET       0x00000020
-#define UDMA_O_REQMASKCLR       0x00000024
-#define UDMA_O_ENASET           0x00000028
-#define UDMA_O_ENACLR           0x0000002C
-#define UDMA_O_ALTSET           0x00000030
-#define UDMA_O_ALTCLR           0x00000034
-#define UDMA_O_PRIOSET          0x00000038
-#define UDMA_O_PRIOCLR          0x0000003C
-#define UDMA_O_ERRCLR           0x0000004C
-#define UDMA_O_CHASGN           0x00000500
-#define UDMA_O_CHIS             0x00000504
-#define UDMA_O_CHMAP0           0x00000510
-#define UDMA_O_CHMAP1           0x00000514
-#define UDMA_O_CHMAP2           0x00000518
-#define UDMA_O_CHMAP3           0x0000051C
-#define UDMA_O_PV               0x00000FB0
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_STAT register.
-//
-//******************************************************************************
-#define UDMA_STAT_DMACHANS_M  0x001F0000  // Available uDMA Channels Minus 1
-#define UDMA_STAT_DMACHANS_S  16
-#define UDMA_STAT_STATE_M     0x000000F0  // Control State Machine Status
-                                            // 0x00000090 : UDMA_STAT_STATE_DONE
-                                            // : Done 0x00000000 :
-                                            // UDMA_STAT_STATE_IDLE : Idle
-                                            // 0x00000010 :
-                                            // UDMA_STAT_STATE_RD_CTRL : Reading
-                                            // channel controller data
-                                            // 0x00000030 :
-                                            // UDMA_STAT_STATE_RD_DSTENDP :
-                                            // Reading destination end pointer
-                                            // 0x00000040 :
-                                            // UDMA_STAT_STATE_RD_SRCDAT :
-                                            // Reading source data 0x00000020 :
-                                            // UDMA_STAT_STATE_RD_SRCENDP :
-                                            // Reading source end pointer
-                                            // 0x00000080 :
-                                            // UDMA_STAT_STATE_STALL : Stalled
-                                            // 0x000000A0 :
-                                            // UDMA_STAT_STATE_UNDEF : Undefined
-                                            // 0x00000060 : UDMA_STAT_STATE_WAIT
-                                            // : Waiting for uDMA request to
-                                            // clear 0x00000070 :
-                                            // UDMA_STAT_STATE_WR_CTRL : Writing
-                                            // channel controller data
-                                            // 0x00000050 :
-                                            // UDMA_STAT_STATE_WR_DSTDAT :
-                                            // Writing destination data
-#define UDMA_STAT_STATE_S     4
-#define UDMA_STAT_MASTEN        0x00000001  // Master Enable Status
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_CFG register.
-//
-//******************************************************************************
-#define UDMA_CFG_MASTEN         0x00000001  // Controller Master Enable
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_CTLBASE register.
-//
-//******************************************************************************
-#define UDMA_CTLBASE_ADDR_M   0xFFFFFC00  // Channel Control Base Address
-#define UDMA_CTLBASE_ADDR_S   10
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_ALTBASE register.
-//
-//******************************************************************************
-#define UDMA_ALTBASE_ADDR_M   0xFFFFFFFF  // Alternate Channel Address
-                                            // Pointer
-#define UDMA_ALTBASE_ADDR_S   0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_WAITSTAT register.
-//
-//******************************************************************************
-#define UDMA_WAITSTAT_WAITREQ_M \
-                                0xFFFFFFFF  // Channel [n] Wait Status
-
-#define UDMA_WAITSTAT_WAITREQ_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_SWREQ register.
-//
-//******************************************************************************
-#define UDMA_SWREQ_M          0xFFFFFFFF  // Channel [n] Software Request
-#define UDMA_SWREQ_S          0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// UDMA_O_USEBURSTSET register.
-//
-//******************************************************************************
-#define UDMA_USEBURSTSET_SET_M \
-                                0xFFFFFFFF  // Channel [n] Useburst Set
-
-#define UDMA_USEBURSTSET_SET_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the
-// UDMA_O_USEBURSTCLR register.
-//
-//******************************************************************************
-#define UDMA_USEBURSTCLR_CLR_M \
-                                0xFFFFFFFF  // Channel [n] Useburst Clear
-
-#define UDMA_USEBURSTCLR_CLR_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_REQMASKSET register.
-//
-//******************************************************************************
-#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF  // Channel [n] Request Mask Set
-#define UDMA_REQMASKSET_SET_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_REQMASKCLR register.
-//
-//******************************************************************************
-#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF  // Channel [n] Request Mask Clear
-#define UDMA_REQMASKCLR_CLR_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_ENASET register.
-//
-//******************************************************************************
-#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF  // Channel [n] Enable Set
-#define UDMA_ENASET_CHENSET_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_ENACLR register.
-//
-//******************************************************************************
-#define UDMA_ENACLR_CLR_M     0xFFFFFFFF  // Clear Channel [n] Enable Clear
-#define UDMA_ENACLR_CLR_S     0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_ALTSET register.
-//
-//******************************************************************************
-#define UDMA_ALTSET_SET_M     0xFFFFFFFF  // Channel [n] Alternate Set
-#define UDMA_ALTSET_SET_S     0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_ALTCLR register.
-//
-//******************************************************************************
-#define UDMA_ALTCLR_CLR_M     0xFFFFFFFF  // Channel [n] Alternate Clear
-#define UDMA_ALTCLR_CLR_S     0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_PRIOSET register.
-//
-//******************************************************************************
-#define UDMA_PRIOSET_SET_M    0xFFFFFFFF  // Channel [n] Priority Set
-#define UDMA_PRIOSET_SET_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_PRIOCLR register.
-//
-//******************************************************************************
-#define UDMA_PRIOCLR_CLR_M    0xFFFFFFFF  // Channel [n] Priority Clear
-#define UDMA_PRIOCLR_CLR_S    0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_ERRCLR register.
-//
-//******************************************************************************
-#define UDMA_ERRCLR_ERRCLR      0x00000001  // uDMA Bus Error Status
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_CHASGN register.
-//
-//******************************************************************************
-#define UDMA_CHASGN_M         0xFFFFFFFF  // Channel [n] Assignment Select
-#define UDMA_CHASGN_S         0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_CHIS register.
-//
-//******************************************************************************
-#define UDMA_CHIS_M           0xFFFFFFFF  // Channel [n] Interrupt Status
-#define UDMA_CHIS_S           0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_CHMAP0 register.
-//
-//******************************************************************************
-#define UDMA_CHMAP0_CH7SEL_M  0xF0000000  // uDMA Channel 7 Source Select
-#define UDMA_CHMAP0_CH7SEL_S  28
-#define UDMA_CHMAP0_CH6SEL_M  0x0F000000  // uDMA Channel 6 Source Select
-#define UDMA_CHMAP0_CH6SEL_S  24
-#define UDMA_CHMAP0_CH5SEL_M  0x00F00000  // uDMA Channel 5 Source Select
-#define UDMA_CHMAP0_CH5SEL_S  20
-#define UDMA_CHMAP0_CH4SEL_M  0x000F0000  // uDMA Channel 4 Source Select
-#define UDMA_CHMAP0_CH4SEL_S  16
-#define UDMA_CHMAP0_CH3SEL_M  0x0000F000  // uDMA Channel 3 Source Select
-#define UDMA_CHMAP0_CH3SEL_S  12
-#define UDMA_CHMAP0_CH2SEL_M  0x00000F00  // uDMA Channel 2 Source Select
-#define UDMA_CHMAP0_CH2SEL_S  8
-#define UDMA_CHMAP0_CH1SEL_M  0x000000F0  // uDMA Channel 1 Source Select
-#define UDMA_CHMAP0_CH1SEL_S  4
-#define UDMA_CHMAP0_CH0SEL_M  0x0000000F  // uDMA Channel 0 Source Select
-#define UDMA_CHMAP0_CH0SEL_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_CHMAP1 register.
-//
-//******************************************************************************
-#define UDMA_CHMAP1_CH15SEL_M 0xF0000000  // uDMA Channel 15 Source Select
-#define UDMA_CHMAP1_CH15SEL_S 28
-#define UDMA_CHMAP1_CH14SEL_M 0x0F000000  // uDMA Channel 14 Source Select
-#define UDMA_CHMAP1_CH14SEL_S 24
-#define UDMA_CHMAP1_CH13SEL_M 0x00F00000  // uDMA Channel 13 Source Select
-#define UDMA_CHMAP1_CH13SEL_S 20
-#define UDMA_CHMAP1_CH12SEL_M 0x000F0000  // uDMA Channel 12 Source Select
-#define UDMA_CHMAP1_CH12SEL_S 16
-#define UDMA_CHMAP1_CH11SEL_M 0x0000F000  // uDMA Channel 11 Source Select
-#define UDMA_CHMAP1_CH11SEL_S 12
-#define UDMA_CHMAP1_CH10SEL_M 0x00000F00  // uDMA Channel 10 Source Select
-#define UDMA_CHMAP1_CH10SEL_S 8
-#define UDMA_CHMAP1_CH9SEL_M  0x000000F0  // uDMA Channel 9 Source Select
-#define UDMA_CHMAP1_CH9SEL_S  4
-#define UDMA_CHMAP1_CH8SEL_M  0x0000000F  // uDMA Channel 8 Source Select
-#define UDMA_CHMAP1_CH8SEL_S  0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_CHMAP2 register.
-//
-//******************************************************************************
-#define UDMA_CHMAP2_CH23SEL_M 0xF0000000  // uDMA Channel 23 Source Select
-#define UDMA_CHMAP2_CH23SEL_S 28
-#define UDMA_CHMAP2_CH22SEL_M 0x0F000000  // uDMA Channel 22 Source Select
-#define UDMA_CHMAP2_CH22SEL_S 24
-#define UDMA_CHMAP2_CH21SEL_M 0x00F00000  // uDMA Channel 21 Source Select
-#define UDMA_CHMAP2_CH21SEL_S 20
-#define UDMA_CHMAP2_CH20SEL_M 0x000F0000  // uDMA Channel 20 Source Select
-#define UDMA_CHMAP2_CH20SEL_S 16
-#define UDMA_CHMAP2_CH19SEL_M 0x0000F000  // uDMA Channel 19 Source Select
-#define UDMA_CHMAP2_CH19SEL_S 12
-#define UDMA_CHMAP2_CH18SEL_M 0x00000F00  // uDMA Channel 18 Source Select
-#define UDMA_CHMAP2_CH18SEL_S 8
-#define UDMA_CHMAP2_CH17SEL_M 0x000000F0  // uDMA Channel 17 Source Select
-#define UDMA_CHMAP2_CH17SEL_S 4
-#define UDMA_CHMAP2_CH16SEL_M 0x0000000F  // uDMA Channel 16 Source Select
-#define UDMA_CHMAP2_CH16SEL_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_CHMAP3 register.
-//
-//******************************************************************************
-#define UDMA_CHMAP3_CH31SEL_M 0xF0000000  // uDMA Channel 31 Source Select
-#define UDMA_CHMAP3_CH31SEL_S 28
-#define UDMA_CHMAP3_CH30SEL_M 0x0F000000  // uDMA Channel 30 Source Select
-#define UDMA_CHMAP3_CH30SEL_S 24
-#define UDMA_CHMAP3_CH29SEL_M 0x00F00000  // uDMA Channel 29 Source Select
-#define UDMA_CHMAP3_CH29SEL_S 20
-#define UDMA_CHMAP3_CH28SEL_M 0x000F0000  // uDMA Channel 28 Source Select
-#define UDMA_CHMAP3_CH28SEL_S 16
-#define UDMA_CHMAP3_CH27SEL_M 0x0000F000  // uDMA Channel 27 Source Select
-#define UDMA_CHMAP3_CH27SEL_S 12
-#define UDMA_CHMAP3_CH26SEL_M 0x00000F00  // uDMA Channel 26 Source Select
-#define UDMA_CHMAP3_CH26SEL_S 8
-#define UDMA_CHMAP3_CH25SEL_M 0x000000F0  // uDMA Channel 25 Source Select
-#define UDMA_CHMAP3_CH25SEL_S 4
-#define UDMA_CHMAP3_CH24SEL_M 0x0000000F  // uDMA Channel 24 Source Select
-#define UDMA_CHMAP3_CH24SEL_S 0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_PV register.
-//
-//******************************************************************************
-#define UDMA_PV_MAJOR_M       0x0000FF00  // Major Revision
-#define UDMA_PV_MAJOR_S       8
-#define UDMA_PV_MINOR_M       0x000000FF  // Minor Revision
-#define UDMA_PV_MINOR_S       0
-
-
-
-#endif // __HW_UDMA_H__
diff --git a/cc3200/hal/inc/hw_wdt.h b/cc3200/hal/inc/hw_wdt.h
deleted file mode 100644
index 00b14acbe..000000000
--- a/cc3200/hal/inc/hw_wdt.h
+++ /dev/null
@@ -1,131 +0,0 @@
-//*****************************************************************************
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __HW_WDT_H__
-#define __HW_WDT_H__
-
-//*****************************************************************************
-//
-// The following are defines for the WDT register offsets.
-//
-//*****************************************************************************
-#define WDT_O_LOAD              0x00000000
-#define WDT_O_VALUE             0x00000004
-#define WDT_O_CTL               0x00000008
-#define WDT_O_ICR               0x0000000C
-#define WDT_O_RIS               0x00000010
-#define WDT_O_MIS               0x00000014
-#define WDT_O_TEST              0x00000418
-#define WDT_O_LOCK              0x00000C00
-
-
-
-//******************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_LOAD register.
-//
-//******************************************************************************
-#define WDT_LOAD_M            0xFFFFFFFF  // Watchdog Load Value
-#define WDT_LOAD_S            0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_VALUE register.
-//
-//******************************************************************************
-#define WDT_VALUE_M           0xFFFFFFFF  // Watchdog Value
-#define WDT_VALUE_S           0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_CTL register.
-//
-//******************************************************************************
-#define WDT_CTL_WRC             0x80000000  // Write Complete
-#define WDT_CTL_INTTYPE         0x00000004  // Watchdog Interrupt Type
-#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable. This bit
-                                            // is not used in cc3xx, WDOG shall
-                                            // always generate RESET to system
-                                            // irrespective of this bit setting.
-#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable
-//******************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_ICR register.
-//
-//******************************************************************************
-#define WDT_ICR_M             0xFFFFFFFF  // Watchdog Interrupt Clear
-#define WDT_ICR_S             0
-//******************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_RIS register.
-//
-//******************************************************************************
-#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status
-//******************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_MIS register.
-//
-//******************************************************************************
-#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt Status
-//******************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_TEST register.
-//
-//******************************************************************************
-#define WDT_TEST_STALL_EN_M     0x00000C00  // Watchdog stall enable
-#define WDT_TEST_STALL_EN_S     10
-#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable
-//******************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_LOCK register.
-//
-//******************************************************************************
-#define WDT_LOCK_M            0xFFFFFFFF  // Watchdog Lock
-#define WDT_LOCK_S            0
-#define WDT_LOCK_UNLOCKED     0x00000000  // Unlocked
-#define WDT_LOCK_LOCKED       0x00000001  // Locked
-#define WDT_LOCK_UNLOCK       0x1ACCE551  // Unlocks the watchdog timer
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
-// WDT_MIS registers.
-//
-//*****************************************************************************
-#define WDT_INT_TIMEOUT         0x00000001  // Watchdog timer expired
-
-
-
-
-
-#endif // __HW_WDT_H__
diff --git a/cc3200/hal/interrupt.c b/cc3200/hal/interrupt.c
deleted file mode 100644
index 897ad966a..000000000
--- a/cc3200/hal/interrupt.c
+++ /dev/null
@@ -1,769 +0,0 @@
-//*****************************************************************************
-//
-//  interrupt.c
-//
-//  Driver for the NVIC Interrupt Controller.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup interrupt_api
-//! @{
-//
-//*****************************************************************************
-
-#include "inc/hw_ints.h"
-#include "inc/hw_nvic.h"
-#include "inc/hw_types.h"
-#include "cpu.h"
-#include "debug.h"
-#include "interrupt.h"
-
-//*****************************************************************************
-//
-// This is a mapping between priority grouping encodings and the number of
-// preemption priority bits.
-//
-//*****************************************************************************
-static const unsigned long g_pulPriority[] =
-{
-    NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
-    NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
-    NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
-};
-
-//*****************************************************************************
-//
-// This is a mapping between interrupt number and the register that contains
-// the priority encoding for that interrupt.
-//
-//*****************************************************************************
-static const unsigned long g_pulRegs[] =
-{
-    0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
-    NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
-    NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13,
-    NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19,
-    NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25,
-    NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31,
-    NVIC_PRI32, NVIC_PRI33, NVIC_PRI34, NVIC_PRI35, NVIC_PRI36, NVIC_PRI37,
-    NVIC_PRI38, NVIC_PRI39, NVIC_PRI40, NVIC_PRI41, NVIC_PRI42, NVIC_PRI43,
-    NVIC_PRI44, NVIC_PRI45, NVIC_PRI46, NVIC_PRI47, NVIC_PRI48
-
-};
-
-
-//*****************************************************************************
-//
-// This is a mapping between interrupt number (for the peripheral interrupts
-// only) and the register that contains the interrupt enable for that
-// interrupt.
-//
-//*****************************************************************************
-static const unsigned long g_pulEnRegs[] =
-{
-    NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4, NVIC_EN5
-};
-
-//*****************************************************************************
-//
-// This is a mapping between interrupt number (for the peripheral interrupts
-// only) and the register that contains the interrupt disable for that
-// interrupt.
-//
-//*****************************************************************************
-static const unsigned long g_pulDisRegs[] =
-{
-    NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4, NVIC_DIS5
-};
-
-//*****************************************************************************
-//
-// This is a mapping between interrupt number (for the peripheral interrupts
-// only) and the register that contains the interrupt pend for that interrupt.
-//
-//*****************************************************************************
-static const unsigned long g_pulPendRegs[] =
-{
-    NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4, NVIC_PEND5
-};
-
-//*****************************************************************************
-//
-// This is a mapping between interrupt number (for the peripheral interrupts
-// only) and the register that contains the interrupt unpend for that
-// interrupt.
-//
-//*****************************************************************************
-static const unsigned long g_pulUnpendRegs[] =
-{
-    NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4,
-    NVIC_UNPEND5
-};
-
-
-//*****************************************************************************
-//
-//! \internal
-//! The default interrupt handler.
-//!
-//! This is the default interrupt handler for all interrupts.  It simply loops
-//! forever so that the system state is preserved for observation by a
-//! debugger.  Since interrupts should be disabled before unregistering the
-//! corresponding handler, this should never be called.
-//!
-//! \return None.
-//
-//*****************************************************************************
-static void
-IntDefaultHandler(void)
-{
-    //
-    // Go into an infinite loop.
-    //
-    while(1)
-    {
-    }
-}
-
-//*****************************************************************************
-//
-//! Enables the processor interrupt.
-//!
-//! Allows the processor to respond to interrupts.  This does not affect the
-//! set of interrupts enabled in the interrupt controller; it just gates the
-//! single interrupt from the controller to the processor.
-//!
-//! \note Previously, this function had no return value.  As such, it was
-//! possible to include <tt>interrupt.h</tt> and call this function without
-//! having included <tt>hw_types.h</tt>.  Now that the return is a
-//! <tt>tBoolean</tt>, a compiler error will occur in this case.  The solution
-//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
-//!
-//! \return Returns \b true if interrupts were disabled when the function was
-//! called or \b false if they were initially enabled.
-//
-//*****************************************************************************
-tBoolean
-IntMasterEnable(void)
-{
-    //
-    // Enable processor interrupts.
-    //
-    return(CPUcpsie());
-}
-
-//*****************************************************************************
-//
-//! Disables the processor interrupt.
-//!
-//! Prevents the processor from receiving interrupts.  This does not affect the
-//! set of interrupts enabled in the interrupt controller; it just gates the
-//! single interrupt from the controller to the processor.
-//!
-//! \note Previously, this function had no return value.  As such, it was
-//! possible to include <tt>interrupt.h</tt> and call this function without
-//! having included <tt>hw_types.h</tt>.  Now that the return is a
-//! <tt>tBoolean</tt>, a compiler error will occur in this case.  The solution
-//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
-//!
-//! \return Returns \b true if interrupts were already disabled when the
-//! function was called or \b false if they were initially enabled.
-//
-//*****************************************************************************
-tBoolean
-IntMasterDisable(void)
-{
-    //
-    // Disable processor interrupts.
-    //
-    return(CPUcpsid());
-}
-//*****************************************************************************
-//
-//! Sets the NVIC VTable base.
-//!
-//! \param ulVtableBase specifies the new base address of VTable
-//!
-//! This function is used to specify a new base address for the VTable.
-//! This function must be called before using IntRegister() for registering
-//! any interrupt handler.
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntVTableBaseSet(unsigned long ulVtableBase)
-{
-    HWREG(NVIC_VTABLE) = ulVtableBase;
-}
-
-//*****************************************************************************
-//
-//! Registers a function to be called when an interrupt occurs.
-//!
-//! \param ulInterrupt specifies the interrupt in question.
-//! \param pfnHandler is a pointer to the function to be called.
-//!
-//! This function is used to specify the handler function to be called when the
-//! given interrupt is asserted to the processor.  When the interrupt occurs,
-//! if it is enabled (via IntEnable()), the handler function will be called in
-//! interrupt context.  Since the handler function can preempt other code, care
-//! must be taken to protect memory or peripherals that are accessed by the
-//! handler and other non-handler code.
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
-{
-    unsigned long *ulNvicTbl;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(ulInterrupt < NUM_INTERRUPTS);
-
-    ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE);
-    ulNvicTbl[ulInterrupt]= (unsigned long)pfnHandler;
-}
-
-//*****************************************************************************
-//
-//! Unregisters the function to be called when an interrupt occurs.
-//!
-//! \param ulInterrupt specifies the interrupt in question.
-//!
-//! This function is used to indicate that no handler should be called when the
-//! given interrupt is asserted to the processor.  The interrupt source will be
-//! automatically disabled (via IntDisable()) if necessary.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntUnregister(unsigned long ulInterrupt)
-{
-  unsigned long *ulNvicTbl;
-
-  //
-  // Check the arguments.
-  //
-  ASSERT(ulInterrupt < NUM_INTERRUPTS);
-
-  ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE);
-  ulNvicTbl[ulInterrupt]= (unsigned long)IntDefaultHandler;
-}
-
-//*****************************************************************************
-//
-//! Sets the priority grouping of the interrupt controller.
-//!
-//! \param ulBits specifies the number of bits of preemptable priority.
-//!
-//! This function specifies the split between preemptable priority levels and
-//! subpriority levels in the interrupt priority specification.  The range of
-//! the grouping values are dependent upon the hardware implementation; on
-//! the CC3200 , three bits are available for hardware interrupt
-//! prioritization and therefore priority grouping values of three through
-//! seven have the same effect.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntPriorityGroupingSet(unsigned long ulBits)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ulBits < NUM_PRIORITY);
-
-    //
-    // Set the priority grouping.
-    //
-    HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits];
-}
-
-//*****************************************************************************
-//
-//! Gets the priority grouping of the interrupt controller.
-//!
-//! This function returns the split between preemptable priority levels and
-//! subpriority levels in the interrupt priority specification.
-//!
-//! \return The number of bits of preemptable priority.
-//
-//*****************************************************************************
-unsigned long
-IntPriorityGroupingGet(void)
-{
-    unsigned long ulLoop, ulValue;
-
-    //
-    // Read the priority grouping.
-    //
-    ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
-
-    //
-    // Loop through the priority grouping values.
-    //
-    for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++)
-    {
-        //
-        // Stop looping if this value matches.
-        //
-        if(ulValue == g_pulPriority[ulLoop])
-        {
-            break;
-        }
-    }
-
-    //
-    // Return the number of priority bits.
-    //
-    return(ulLoop);
-}
-
-//*****************************************************************************
-//
-//! Sets the priority of an interrupt.
-//!
-//! \param ulInterrupt specifies the interrupt in question.
-//! \param ucPriority specifies the priority of the interrupt.
-//!
-//! This function is used to set the priority of an interrupt.  When multiple
-//! interrupts are asserted simultaneously, the ones with the highest priority
-//! are processed before the lower priority interrupts.  Smaller numbers
-//! correspond to higher interrupt priorities; priority 0 is the highest
-//! interrupt priority.
-//!
-//! The hardware priority mechanism will only look at the upper N bits of the
-//! priority level (where N is 3), so any prioritization must be performed in
-//! those bits.  The remaining bits can be used to sub-prioritize the interrupt
-//! sources, and may be used by the hardware priority mechanism on a future
-//! part.  This arrangement allows priorities to migrate to different NVIC
-//! implementations without changing the gross prioritization of the
-//! interrupts.
-//!
-//! The parameter \e ucPriority can be any one of the following
-//! -\b INT_PRIORITY_LVL_0
-//! -\b INT_PRIORITY_LVL_1
-//! -\b INT_PRIORITY_LVL_2
-//! -\b INT_PRIORITY_LVL_3
-//! -\b INT_PRIORITY_LVL_4
-//! -\b INT_PRIORITY_LVL_5
-//! -\b INT_PRIORITY_LVL_6
-//! -\b INT_PRIORITY_LVL_7
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
-{
-    unsigned long ulTemp;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
-
-    //
-    // Set the interrupt priority.
-    //
-    ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]);
-    ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3)));
-    ulTemp |= ucPriority << (8 * (ulInterrupt & 3));
-    HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp;
-}
-
-//*****************************************************************************
-//
-//! Gets the priority of an interrupt.
-//!
-//! \param ulInterrupt specifies the interrupt in question.
-//!
-//! This function gets the priority of an interrupt.  See IntPrioritySet() for
-//! a definition of the priority value.
-//!
-//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
-//! specified.
-//
-//*****************************************************************************
-long
-IntPriorityGet(unsigned long ulInterrupt)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
-
-    //
-    // Return the interrupt priority.
-    //
-    return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) &
-           0xFF);
-}
-
-//*****************************************************************************
-//
-//! Enables an interrupt.
-//!
-//! \param ulInterrupt specifies the interrupt to be enabled.
-//!
-//! The specified interrupt is enabled in the interrupt controller.  Other
-//! enables for the interrupt (such as at the peripheral level) are unaffected
-//! by this function.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntEnable(unsigned long ulInterrupt)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ulInterrupt < NUM_INTERRUPTS);
-
-    //
-    // Determine the interrupt to enable.
-    //
-    if(ulInterrupt == FAULT_MPU)
-    {
-        //
-        // Enable the MemManage interrupt.
-        //
-        HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
-        __asm(" dsb     ");
-        __asm(" isb     ");
-    }
-    else if(ulInterrupt == FAULT_BUS)
-    {
-        //
-        // Enable the bus fault interrupt.
-        //
-        HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
-        __asm(" dsb     ");
-        __asm(" isb     ");
-    }
-    else if(ulInterrupt == FAULT_USAGE)
-    {
-        //
-        // Enable the usage fault interrupt.
-        //
-        HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
-        __asm(" dsb     ");
-        __asm(" isb     ");
-    }
-    else if(ulInterrupt == FAULT_SYSTICK)
-    {
-        //
-        // Enable the System Tick interrupt.
-        //
-        HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
-        __asm(" dsb     ");
-        __asm(" isb     ");
-    }
-    else if(ulInterrupt >= 16)
-    {
-        //
-        // Enable the general interrupt.
-        //
-        HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) =
-            1 << ((ulInterrupt - 16) & 31);
-        __asm(" dsb     ");
-        __asm(" isb     ");
-    }
-}
-
-//*****************************************************************************
-//
-//! Disables an interrupt.
-//!
-//! \param ulInterrupt specifies the interrupt to be disabled.
-//!
-//! The specified interrupt is disabled in the interrupt controller.  Other
-//! enables for the interrupt (such as at the peripheral level) are unaffected
-//! by this function.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntDisable(unsigned long ulInterrupt)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ulInterrupt < NUM_INTERRUPTS);
-
-    //
-    // Determine the interrupt to disable.
-    //
-    if(ulInterrupt == FAULT_MPU)
-    {
-        //
-        // Disable the MemManage interrupt.
-        //
-        HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
-        __asm(" dsb     ");
-        __asm(" isb     ");
-    }
-    else if(ulInterrupt == FAULT_BUS)
-    {
-        //
-        // Disable the bus fault interrupt.
-        //
-        HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
-        __asm(" dsb     ");
-        __asm(" isb     ");
-    }
-    else if(ulInterrupt == FAULT_USAGE)
-    {
-        //
-        // Disable the usage fault interrupt.
-        //
-        HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
-        __asm(" dsb     ");
-        __asm(" isb     ");
-    }
-    else if(ulInterrupt == FAULT_SYSTICK)
-    {
-        //
-        // Disable the System Tick interrupt.
-        //
-        HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
-        __asm(" dsb     ");
-        __asm(" isb     ");
-    }
-    else if(ulInterrupt >= 16)
-    {
-        //
-        // Disable the general interrupt.
-        //
-        HWREG(g_pulDisRegs[(ulInterrupt - 16) / 32]) =
-            1 << ((ulInterrupt - 16) & 31);
-        __asm(" dsb     ");
-        __asm(" isb     ");
-    }
-
-}
-
-//*****************************************************************************
-//
-//! Pends an interrupt.
-//!
-//! \param ulInterrupt specifies the interrupt to be pended.
-//!
-//! The specified interrupt is pended in the interrupt controller.  This will
-//! cause the interrupt controller to execute the corresponding interrupt
-//! handler at the next available time, based on the current interrupt state
-//! priorities.  For example, if called by a higher priority interrupt handler,
-//! the specified interrupt handler will not be called until after the current
-//! interrupt handler has completed execution.  The interrupt must have been
-//! enabled for it to be called.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntPendSet(unsigned long ulInterrupt)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ulInterrupt < NUM_INTERRUPTS);
-
-    //
-    // Determine the interrupt to pend.
-    //
-    if(ulInterrupt == FAULT_NMI)
-    {
-        //
-        // Pend the NMI interrupt.
-        //
-        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET;
-        __asm(" dsb     ");
-        __asm(" isb     ");
-    }
-    else if(ulInterrupt == FAULT_PENDSV)
-    {
-        //
-        // Pend the PendSV interrupt.
-        //
-        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV;
-        __asm(" dsb     ");
-        __asm(" isb     ");
-    }
-    else if(ulInterrupt == FAULT_SYSTICK)
-    {
-        //
-        // Pend the SysTick interrupt.
-        //
-        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
-        __asm(" dsb     ");
-        __asm(" isb     ");
-    }
-    else if(ulInterrupt >= 16)
-    {
-        //
-        // Pend the general interrupt.
-        //
-        HWREG(g_pulPendRegs[(ulInterrupt - 16) / 32]) =
-            1 << ((ulInterrupt - 16) & 31);
-        __asm(" dsb     ");
-        __asm(" isb     ");
-    }
-
-}
-
-//*****************************************************************************
-//
-//! Unpends an interrupt.
-//!
-//! \param ulInterrupt specifies the interrupt to be unpended.
-//!
-//! The specified interrupt is unpended in the interrupt controller.  This will
-//! cause any previously generated interrupts that have not been handled yet
-//! (due to higher priority interrupts or the interrupt no having been enabled
-//! yet) to be discarded.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntPendClear(unsigned long ulInterrupt)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ulInterrupt < NUM_INTERRUPTS);
-
-    //
-    // Determine the interrupt to unpend.
-    //
-    if(ulInterrupt == FAULT_PENDSV)
-    {
-        //
-        // Unpend the PendSV interrupt.
-        //
-        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV;
-    }
-    else if(ulInterrupt == FAULT_SYSTICK)
-    {
-        //
-        // Unpend the SysTick interrupt.
-        //
-        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
-    }
-    else if(ulInterrupt >= 16)
-    {
-        //
-        // Unpend the general interrupt.
-        //
-        HWREG(g_pulUnpendRegs[(ulInterrupt - 16) / 32]) =
-            1 << ((ulInterrupt - 16) & 31);
-    }
-}
-
-//*****************************************************************************
-//
-//! Sets the priority masking level
-//!
-//! \param ulPriorityMask is the priority level that will be masked.
-//!
-//! This function sets the interrupt priority masking level so that all
-//! interrupts at the specified or lesser priority level is masked.  This
-//! can be used to globally disable a set of interrupts with priority below
-//! a predetermined threshold.  A value of 0 disables priority
-//! masking.
-//!
-//! Smaller numbers correspond to higher interrupt priorities.  So for example
-//! a priority level mask of 4 will allow interrupts of priority level 0-3,
-//! and interrupts with a numerical priority of 4 and greater will be blocked.
-//!
-//! The hardware priority mechanism will only look at the upper N bits of the
-//! priority level (where N is 3), so any
-//! prioritization must be performed in those bits.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-IntPriorityMaskSet(unsigned long ulPriorityMask)
-{
-    CPUbasepriSet(ulPriorityMask);
-}
-
-//*****************************************************************************
-//
-//! Gets the priority masking level
-//!
-//! This function gets the current setting of the interrupt priority masking
-//! level.  The value returned is the priority level such that all interrupts
-//! of that and lesser priority are masked.  A value of 0 means that priority
-//! masking is disabled.
-//!
-//! Smaller numbers correspond to higher interrupt priorities.  So for example
-//! a priority level mask of 4 will allow interrupts of priority level 0-3,
-//! and interrupts with a numerical priority of 4 and greater will be blocked.
-//!
-//! The hardware priority mechanism will only look at the upper N bits of the
-//! priority level (where N is 3), so any
-//! prioritization must be performed in those bits.
-//!
-//! \return Returns the value of the interrupt priority level mask.
-//
-//*****************************************************************************
-unsigned long
-IntPriorityMaskGet(void)
-{
-    return(CPUbasepriGet());
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
diff --git a/cc3200/hal/interrupt.h b/cc3200/hal/interrupt.h
deleted file mode 100644
index 941a60f5f..000000000
--- a/cc3200/hal/interrupt.h
+++ /dev/null
@@ -1,120 +0,0 @@
-//*****************************************************************************
-//
-//  interrupt.h
-//
-//  Prototypes for the NVIC Interrupt Controller Driver.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __INTERRUPT_H__
-#define __INTERRUPT_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// A union that describes the entries of the vector table.  The union is needed
-// since the first entry is the stack pointer and the remainder are function
-// pointers.
-//
-//*****************************************************************************
-typedef union
-{
-    void (*pfnHandler)(void);
-    unsigned long ulPtr;
-}
-uVectorEntry;
-
-
-//*****************************************************************************
-//
-// Macro to generate an interrupt priority mask based on the number of bits
-// of priority supported by the hardware.
-//
-//*****************************************************************************
-#define INT_PRIORITY_MASK       ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
-
-//*****************************************************************************
-// Interrupt priority levels
-//*****************************************************************************
-#define INT_PRIORITY_LVL_0      0x00
-#define INT_PRIORITY_LVL_1      0x20
-#define INT_PRIORITY_LVL_2      0x40
-#define INT_PRIORITY_LVL_3      0x60
-#define INT_PRIORITY_LVL_4      0x80
-#define INT_PRIORITY_LVL_5      0xA0
-#define INT_PRIORITY_LVL_6      0xC0
-#define INT_PRIORITY_LVL_7      0xE0
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-extern tBoolean IntMasterEnable(void);
-extern tBoolean IntMasterDisable(void);
-extern void IntVTableBaseSet(unsigned long ulVtableBase);
-extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
-extern void IntUnregister(unsigned long ulInterrupt);
-extern void IntPriorityGroupingSet(unsigned long ulBits);
-extern unsigned long IntPriorityGroupingGet(void);
-extern void IntPrioritySet(unsigned long ulInterrupt,
-                           unsigned char ucPriority);
-extern long IntPriorityGet(unsigned long ulInterrupt);
-extern void IntEnable(unsigned long ulInterrupt);
-extern void IntDisable(unsigned long ulInterrupt);
-extern void IntPendSet(unsigned long ulInterrupt);
-extern void IntPendClear(unsigned long ulInterrupt);
-extern void IntPriorityMaskSet(unsigned long ulPriorityMask);
-extern unsigned long IntPriorityMaskGet(void);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __INTERRUPT_H__
diff --git a/cc3200/hal/pin.c b/cc3200/hal/pin.c
deleted file mode 100644
index 4130a43f0..000000000
--- a/cc3200/hal/pin.c
+++ /dev/null
@@ -1,658 +0,0 @@
-//*****************************************************************************
-//
-//  pin.c
-//
-//  Mapping of peripherals to pins.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup pin_api
-//! @{
-//
-//*****************************************************************************
-
-#include "inc/hw_types.h"
-#include "inc/hw_memmap.h"
-#include "inc/hw_ocp_shared.h"
-#include "pin.h"
-
-//*****************************************************************************
-// PIN to PAD matrix
-//*****************************************************************************
-static const unsigned long g_ulPinToPadMap[64] =
-{
-	10,11,12,13,14,15,16,17,255,255,18,
-	19,20,21,22,23,24,40,28,29,25,255,
-	255,255,255,255,255,255,255,255,255,255,255,
-	255,255,255,255,255,255,255,255,255,255,255,
-	31,255,255,255,255,0,255,32,30,255,1,
-	255,2,3,4,5,6,7,8,9
-};
-
-
-//*****************************************************************************
-//
-//! Configures pin mux for the specified pin.
-//!
-//! \param ulPin is a valid pin.
-//! \param ulPinMode is one of the valid mode
-//!
-//! This function configures the pin mux that selects the peripheral function
-//! associated with a particular SOC pin. Only one peripheral function at a
-//! time can be associated with a pin, and each peripheral function should
-//! only be associated with a single pin at a time.
-//!
-//! \return none
-//
-//*****************************************************************************
-void PinModeSet(unsigned long ulPin,unsigned long ulPinMode)
-{
-
-  unsigned long ulPad;
-
-  //
-  // Get the corresponding Pad
-  //
-  ulPad = g_ulPinToPadMap[ulPin & 0x3F];
-
-  //
-  // Calculate the register address
-  //
-  ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
-
-  //
-  // Set the mode.
-  //
-  HWREG(ulPad) = (((HWREG(ulPad) & ~PAD_MODE_MASK) |  ulPinMode) & ~(3<<10));
-
-}
-
-//*****************************************************************************
-//
-//! Gets current pin mux configuration of specified pin.
-//!
-//! \param ulPin is a valid pin.
-//!
-//! This function get the current configuration of the pin mux.
-//!
-//! \return Returns current pin mode if \e ulPin is valid, 0xFF otherwise.
-//
-//*****************************************************************************
-unsigned long PinModeGet(unsigned long ulPin)
-{
-
-  unsigned long ulPad;
-
-
-  //
-  // Get the corresponding Pad
-  //
-  ulPad = g_ulPinToPadMap[ulPin & 0x3F];
-
-
-  //
-  // Calculate the register address
-  //
-  ulPad = ((ulPad << 2) + PAD_CONFIG_BASE) ;
-
-  //
-  // return the mode.
-  //
-  return (HWREG(ulPad) & PAD_MODE_MASK);
-
-}
-
-//*****************************************************************************
-//
-//! Sets the direction of the specified pin(s).
-//!
-//! \param ulPin is one of the valid pin.
-//! \param ulPinIO is the pin direction and/or mode.
-//!
-//! This function configures the specified pin(s) as either input only or
-//! output only or it configures the pin to be under hardware control.
-//!
-//! The parameter \e ulPinIO is an enumerated data type that can be one of
-//! the following values:
-//!
-//! - \b PIN_DIR_MODE_IN
-//! - \b PIN_DIR_MODE_OUT
-//! - \b PIN_DIR_MODE_HW
-//!
-//! where \b PIN_DIR_MODE_IN specifies that the pin is programmed as a
-//! input only, \b PIN_DIR_MODE_OUT specifies that the pin is
-//! programmed output only, and \b PIN_DIR_MODE_HW specifies that the pin is
-//! placed under hardware control.
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO)
-{
-  unsigned long ulPad;
-
-  //
-  // Get the corresponding Pad
-  //
-  ulPad = g_ulPinToPadMap[ulPin & 0x3F];
-
-  //
-  // Calculate the register address
-  //
-  ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
-
-  //
-  // Set the direction
-  //
-  HWREG(ulPad) = ((HWREG(ulPad) & ~0xC00) | ulPinIO);
-}
-
-//*****************************************************************************
-//
-//! Gets the direction of a pin.
-//!
-//! \param ulPin is one of the valid pin.
-//!
-//! This function gets the direction and control mode for a specified pin on
-//! the selected GPIO port.  The pin can be configured as either an input only
-//! or output only, or it can be under hardware control.  The type of control
-//! and direction are returned as an enumerated data type.
-//!
-//! \return Returns one of the enumerated data types described for
-//! GPIODirModeSet().
-//
-//*****************************************************************************
-unsigned long PinDirModeGet(unsigned long ulPin)
-{
-  unsigned long ulPad;
-
-  //
-  // Get the corresponding Pad
-  //
-  ulPad = g_ulPinToPadMap[ulPin & 0x3F];
-
-  //
-  // Calculate the register address
-  //
-  ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
-
-  //
-  // Return the direction
-  //
-  return ((HWREG(ulPad) & 0xC00));
-}
-
-//*****************************************************************************
-//
-//! Gets Pin output drive strength and Type
-//!
-//! \param ulPin is one of the valid pin
-//! \param pulPinStrength is pointer to storage for output drive strength
-//! \param pulPinType is pinter to storage for pin type
-//!
-//! This function gets the pin type and output drive strength for the pin
-//! specified by \e ulPin parameter. Parameters \e pulPinStrength and
-//! \e pulPinType corresponds to the values used in PinConfigSet().
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PinConfigGet(unsigned long ulPin,unsigned long  *pulPinStrength,
-	       					unsigned long *pulPinType)
-{
-
-  unsigned long ulPad;
-
-
-  //
-  // Get the corresponding Pad
-  //
-  ulPad = g_ulPinToPadMap[ulPin & 0x3F];
-
-
-  //
-  // Calculate the register address
-  //
-  ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
-
-
-  //
-  // Get the type
-  //
-  *pulPinType = (HWREG(ulPad) & PAD_TYPE_MASK);
-
-  //
-  // Get the output drive strength
-  //
-  *pulPinStrength = (HWREG(ulPad) & PAD_STRENGTH_MASK);
-
-}
-
-//*****************************************************************************
-//
-//! Configure Pin output drive strength and Type
-//!
-//! \param ulPin is one of the valid pin
-//! \param ulPinStrength is logical OR of valid output drive strengths.
-//! \param ulPinType is one of the valid pin type.
-//!
-//!  This function sets the pin type and strength for the pin specified by
-//! \e ulPin parameter.
-//!
-//! The parameter \e ulPinStrength should be one of the following
-//! - \b PIN_STRENGTH_2MA
-//! - \b PIN_STRENGTH_4MA
-//! - \b PIN_STRENGTH_6MA
-//!
-//!
-//! The parameter \e ulPinType should be one of the following
-//! For standard type
-//!
-//! - \b PIN_TYPE_STD
-//! - \b PIN_TYPE_STD_PU
-//! - \b PIN_TYPE_STD_PD
-//!
-//! And for Open drain type
-//!
-//! - \b PIN_TYPE_OD
-//! - \b PIN_TYPE_OD_PU
-//! - \b PIN_TYPE_OD_PD
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PinConfigSet(unsigned long ulPin,unsigned long  ulPinStrength,
-						unsigned long ulPinType)
-{
-
-  unsigned long ulPad;
-
-  //
-  // Get the corresponding Pad
-  //
-  ulPad = g_ulPinToPadMap[ulPin & 0x3F];
-
-  //
-  // Write the register
-  //
-  if(ulPinType == PIN_TYPE_ANALOG)
-  {
-    //
-    // Isolate the input
-    //
-    HWREG(0x4402E144) |= ((0x80 << ulPad) & (0x1E << 8));
-
-    //
-    // Calculate the register address
-    //
-    ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
-
-    //
-    // Isolate the output
-    //
-    HWREG(ulPad) = 0xC00;
-
-  }
-  else
-  {
-    //
-    // Enable the input
-    //
-    HWREG(0x4402E144) &= ~((0x80 << ulPad) & (0x1E << 8));
-
-    //
-    // Calculate the register address
-    //
-    ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
-
-    //
-    // Write the configuration
-    //
-    HWREG(ulPad) = ((HWREG(ulPad) & ~(PAD_STRENGTH_MASK | PAD_TYPE_MASK)) |
-		  		(ulPinStrength | ulPinType ));
-  }
-
-
-}
-
-//*****************************************************************************
-//
-//! Sets the pin mode and configures the pin for use by UART peripheral
-//!
-//! \param ulPin is one of the valid pin.
-//! \param ulPinMode is one of the valid pin mode.
-//!
-//! The UART pins must be properly configured for the peripheral to
-//! function correctly.  This function provides a typical configuration for
-//! those pin(s); other configurations may work as well depending upon the
-//! board setup (for example, using the on-chip pull-ups).
-//!
-//!
-//! \note This function cannot be used to turn any pin into a UART pin; it
-//! only sets the pin mode and configures it for proper UART operation.
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode)
-{
-    //
-    // Set the pin to specified mode
-    //
-    PinModeSet(ulPin,ulPinMode);
-
-    //
-    // Set the pin for standard operation
-    //
-    PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_STD);
-}
-
-
-//*****************************************************************************
-//
-//! Sets the pin mode and configures the pin for use by I2C peripheral
-//!
-//! \param ulPin is one of the valid pin.
-//! \param ulPinMode is one of the valid pin mode.
-//!
-//! The I2C pins must be properly configured for the peripheral to
-//! function correctly.  This function provides a typical configuration for
-//! the pin.
-//!
-//!
-//! \note This function cannot be used to turn any pin into a I2C pin; it
-//! only sets the pin mode and configures it for proper I2C operation.
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PinTypeI2C(unsigned long ulPin,unsigned long ulPinMode)
-{
-    //
-    // Set the pin to specified mode
-    //
-    PinModeSet(ulPin,ulPinMode);
-
-    //
-    // Set the pin for open-drain operation with a weak pull-up.
-    //
-    PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_OD_PU);
-}
-
-
-//*****************************************************************************
-//
-//! Sets the pin mode and configures the pin for use by SPI peripheral
-//!
-//! \param ulPin is one of the valid pin.
-//! \param ulPinMode is one of the valid pin mode.
-//!
-//! The SPI pins must be properly configured for the peripheral to
-//! function correctly.  This function provides a typical configuration for
-//! those pin.
-//!
-//!
-//! \note This function cannot be used to turn any pin into a SPI pin; it
-//! only sets the pin mode and configures it for proper SPI operation.
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PinTypeSPI(unsigned long ulPin,unsigned long ulPinMode)
-{
-
-    //
-    // Set the pin to specified mode
-    //
-    PinModeSet(ulPin,ulPinMode);
-
-    //
-    // Set the pin for standard operation
-    //
-    PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD);
-
-}
-
-
-//*****************************************************************************
-//
-//! Sets the pin mode and configures the pin for use by I2S peripheral
-//!
-//! \param ulPin is one of the valid pin.
-//! \param ulPinMode is one of the valid pin mode.
-//!
-//! The I2S pins must be properly configured for the peripheral to
-//! function correctly.  This function provides a typical configuration for
-//! those pin.
-//!
-//!
-//! \note This function cannot be used to turn any pin into a I2S pin; it
-//! only sets the pin mode and configures it for proper I2S operation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PinTypeI2S(unsigned long ulPin,unsigned long ulPinMode)
-{
-
-    //
-    // Set the pin to specified mode
-    //
-    PinModeSet(ulPin,ulPinMode);
-
-    //
-    // Set the pin for standard operation
-    //
-    PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD);
-
-}
-
-
-//*****************************************************************************
-//
-//! Sets the pin mode and configures the pin for use by Timer peripheral
-//!
-//! \param ulPin is one of the valid pin.
-//! \param ulPinMode is one of the valid pin mode.
-//!
-//! The timer PWM pins must be properly configured for the Timer peripheral to
-//! function correctly.  This function provides a typical configuration for
-//! those pin; other configurations may work as well depending upon the
-//! board setup (for example, using the on-chip pull-ups).
-//!
-//!
-//! \note This function cannot be used to turn any pin into a timer PWM pin; it
-//! only sets the pin mode and configures it for proper timer PWM operation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PinTypeTimer(unsigned long ulPin,unsigned long ulPinMode)
-{
-
-    //
-    // Set the pin to specified mode
-    //
-    PinModeSet(ulPin,ulPinMode);
-
-    //
-    // Set the pin for standard operation
-    //
-    PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD);
-}
-
-
-//*****************************************************************************
-//
-//! Sets the pin mode and configures the pin for use by Camera peripheral
-//!
-//! \param ulPin is one of the valid pin.
-//! \param ulPinMode is one of the valid pin mode.
-//!
-//! The Camera pins must be properly configured for the peripheral to
-//! function correctly.  This function provides a typical configuration for
-//! those pin.
-//!
-//!
-//! \note This function cannot be used to turn any pin into a Camera pin; it
-//! only sets the pin mode and configures it for proper Camera operation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PinTypeCamera(unsigned long ulPin,unsigned long ulPinMode)
-{
-
-    //
-    // Set the pin to specified mode
-    //
-    PinModeSet(ulPin,ulPinMode);
-
-    //
-    // Set the pin for standard operation
-    //
-    PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD);
-
-}
-
-
-//*****************************************************************************
-//
-//! Sets the pin mode and configures the pin for use by GPIO peripheral
-//!
-//! \param ulPin is one of the valid pin.
-//! \param ulPinMode is one of the valid pin mode.
-//! \param bOpenDrain is one to decide either OpenDrain or STD
-//!
-//! The GPIO pins must be properly configured for the peripheral to
-//! function correctly.  This function provides a typical configuration for
-//! those pin.
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PinTypeGPIO(unsigned long ulPin,unsigned long ulPinMode,tBoolean bOpenDrain)
-{
-
-    //
-    // Set the pin for standard push-pull operation.
-    //
-    if(bOpenDrain)
-    {
-            PinConfigSet(ulPin, PIN_STRENGTH_2MA, PIN_TYPE_OD);
-    }
-    else
-    {
-            PinConfigSet(ulPin, PIN_STRENGTH_2MA, PIN_TYPE_STD);
-    }
-
-    //
-    // Set the pin to specified mode
-    //
-    PinModeSet(ulPin, ulPinMode);
-
-}
-
-//*****************************************************************************
-//
-//! Sets the pin mode and configures the pin for use by ADC
-//!
-//! \param ulPin is one of the valid pin.
-//! \param ulPinMode is one of the valid pin mode.
-//!
-//! The ADC pins must be properly configured for the peripheral to
-//! function correctly.  This function provides a typical configuration for
-//! those pin.
-//!
-//!
-//! \note This function cannot be used to turn any pin into a ADC pin; it
-//! only sets the pin mode and configures it for proper ADC operation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PinTypeADC(unsigned long ulPin,unsigned long ulPinMode)
-{
-  //
-  // Configure the Pin
-  //
-  PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_ANALOG);
-}
-
-//*****************************************************************************
-//
-//! Sets the pin mode and configures the pin for use by SD Host peripheral
-//!
-//! \param ulPin is one of the valid pin.
-//! \param ulPinMode is one of the valid pin mode.
-//!
-//! The MMC pins must be properly configured for the peripheral to
-//! function correctly.  This function provides a typical configuration for
-//! those pin.
-//!
-//!
-//! \note This function cannot be used to turn any pin into a SD Host pin; it
-//! only sets the pin mode and configures it for proper SD Host operation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PinTypeSDHost(unsigned long ulPin,unsigned long ulPinMode)
-{
-  //
-  // Set pin mode
-  //
-  PinModeSet(ulPin,ulPinMode);
-
-  //
-  // Configure the Pin
-  //
-  PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_STD);
-
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
diff --git a/cc3200/hal/pin.h b/cc3200/hal/pin.h
deleted file mode 100644
index 784e9f463..000000000
--- a/cc3200/hal/pin.h
+++ /dev/null
@@ -1,183 +0,0 @@
-//*****************************************************************************
-//
-//  pin.h
-//
-//  Defines and Macros for the pin mux module
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __PIN_H__
-#define __PIN_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-// Macros Defining Pins
-//*****************************************************************************
-
-#define PIN_01 	 0x00000000
-#define PIN_02 	 0x00000001
-#define PIN_03   0x00000002
-#define PIN_04 	 0x00000003
-#define PIN_05   0x00000004
-#define PIN_06   0x00000005
-#define PIN_07   0x00000006
-#define PIN_08   0x00000007
-#define PIN_11   0x0000000A
-#define PIN_12   0x0000000B
-#define PIN_13   0x0000000C
-#define PIN_14   0x0000000D
-#define PIN_15   0x0000000E
-#define PIN_16   0x0000000F
-#define PIN_17   0x00000010
-#define PIN_18   0x00000011
-#define PIN_19 	 0x00000012
-#define PIN_20   0x00000013
-#define PIN_21   0x00000014
-#define PIN_45   0x0000002C
-#define PIN_46   0x0000002D
-#define PIN_47   0x0000002E
-#define PIN_48   0x0000002F
-#define PIN_49   0x00000030
-#define PIN_50   0x00000031
-#define PIN_52   0x00000033
-#define PIN_53   0x00000034
-#define PIN_55   0x00000036
-#define PIN_56   0x00000037
-#define PIN_57   0x00000038
-#define PIN_58   0x00000039
-#define PIN_59   0x0000003A
-#define PIN_60   0x0000003B
-#define PIN_61	 0x0000003C
-#define PIN_62	 0x0000003D
-#define PIN_63	 0x0000003E
-#define PIN_64	 0x0000003F
-
-
-
-//*****************************************************************************
-// Macros that can be used with PinConfigSet(), PinTypeGet(), PinStrengthGet()
-//*****************************************************************************
-
-#define PIN_MODE_0	 0x00000000
-#define PIN_MODE_1	 0x00000001
-#define PIN_MODE_2	 0x00000002
-#define PIN_MODE_3	 0x00000003
-#define PIN_MODE_4	 0x00000004
-#define PIN_MODE_5	 0x00000005
-#define PIN_MODE_6	 0x00000006
-#define PIN_MODE_7	 0x00000007
-#define PIN_MODE_8	 0x00000008
-#define PIN_MODE_9	 0x00000009
-#define PIN_MODE_10	 0x0000000A
-#define PIN_MODE_11	 0x0000000B
-#define PIN_MODE_12	 0x0000000C
-#define PIN_MODE_13	 0x0000000D
-#define PIN_MODE_14	 0x0000000E
-#define PIN_MODE_15	 0x0000000F
-// Note : PIN_MODE_255 is a dummy define for pinmux utility code generation
-// PIN_MODE_255 should never be used in any user code.  
-#define PIN_MODE_255 0x000000FF  
-
-//*****************************************************************************
-// Macros that can be used with PinDirModeSet() and returned from
-// PinDirModeGet().
-//*****************************************************************************
-#define PIN_DIR_MODE_IN  0x00000C00 // Pin is input
-#define PIN_DIR_MODE_OUT 0x00000800 // Pin is output
-#define PIN_DIR_MODE_HW  0x00000000 // Pin is peripheral function
-
-//*****************************************************************************
-// Macros that can be used with PinConfigSet()
-//*****************************************************************************
-#define PIN_STRENGTH_2MA  0x00000020
-#define PIN_STRENGTH_4MA  0x00000040
-#define PIN_STRENGTH_6MA  0x00000060
-
-#define PIN_TYPE_STD      0x00000000
-#define PIN_TYPE_STD_PU   0x00000100
-#define PIN_TYPE_STD_PD   0x00000200
-
-#define PIN_TYPE_OD       0x00000010
-#define PIN_TYPE_OD_PU    0x00000110
-#define PIN_TYPE_OD_PD    0x00000210
-#define PIN_TYPE_ANALOG   0x10000000
-
-//*****************************************************************************
-// Macros for mode and type
-//*****************************************************************************
-#define PAD_MODE_MASK       0x0000000F
-#define PAD_STRENGTH_MASK   0x000000E0
-#define PAD_TYPE_MASK       0x00000310
-#define PAD_CONFIG_BASE     ((OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0))
-
-//*****************************************************************************
-//
-// API Function prototypes
-//
-//*****************************************************************************
-extern void PinModeSet(unsigned long ulPin, unsigned long ulPinMode);
-extern void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO);
-extern unsigned long PinDirModeGet(unsigned long ulPin);
-extern unsigned long PinModeGet(unsigned long ulPin);
-extern void PinConfigGet(unsigned long ulPin,unsigned long  *pulPinStrength,
-	       					unsigned long *pulPinType);
-extern void PinConfigSet(unsigned long ulPin,unsigned long  ulPinStrength,
-						unsigned long ulPinType);
-extern void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode);
-extern void PinTypeI2C(unsigned long ulPin,unsigned long ulPinMode);
-extern void PinTypeSPI(unsigned long ulPin,unsigned long ulPinMode);
-extern void PinTypeI2S(unsigned long ulPin,unsigned long ulPinMode);
-extern void PinTypeTimer(unsigned long ulPin,unsigned long ulPinMode);
-extern void PinTypeCamera(unsigned long ulPin,unsigned long ulPinMode);
-extern void PinTypeGPIO(unsigned long ulPin,unsigned long ulPinMode,
-                        tBoolean bOpenDrain);
-extern void PinTypeADC(unsigned long ulPin,unsigned long ulPinMode);
-extern void PinTypeSDHost(unsigned long ulPin,unsigned long ulPinMode);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__PIN_H__
diff --git a/cc3200/hal/prcm.c b/cc3200/hal/prcm.c
deleted file mode 100644
index 4b66c0ff1..000000000
--- a/cc3200/hal/prcm.c
+++ /dev/null
@@ -1,1953 +0,0 @@
-//*****************************************************************************
-//
-//  prcm.c
-//
-//  Driver for the Power, Reset and Clock Module (PRCM)
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup PRCM_Power_Reset_Clock_Module_api
-//! @{
-//
-//*****************************************************************************
-
-#include "inc/hw_types.h"
-#include "inc/hw_ints.h"
-#include "inc/hw_memmap.h"
-#include "inc/hw_apps_rcm.h"
-#include "inc/hw_gprcm.h"
-#include "inc/hw_hib1p2.h"
-#include "inc/hw_hib3p3.h"
-#include "prcm.h"
-#include "interrupt.h"
-#include "cpu.h"
-#include "utils.h"
-#include "rom_map.h"
-
-
-//*****************************************************************************
-// Macro definition
-//*****************************************************************************
-#define PRCM_SOFT_RESET           0x00000001
-#define PRCM_ENABLE_STATUS        0x00000002
-#define SYS_CLK                   80000000
-#define XTAL_CLK                  40000000
-
-
-//*****************************************************************************
-//    CC3200 does not have a true RTC capability. However, API(s) in this file
-//    provide an effective mechanism to support RTC feature in the device.
-//
-//    The implementation to support RTC has been kept very simple. A set of
-//    HIB Memory Registers in conjunction with Slow Clock Counter are used
-//    to render RTC information to users. Core principle of design involves
-//    two steps (a) establish an association between user provided wall-clock
-//    and slow clock counter. (b) store reference value of this associattion
-//    in HIB Registers. This reference value and SCC value are then combined
-//    to create real-world calendar time.
-//
-//    Across HIB cycles, value stored in HIB Registers is retained and slow
-//    clock counter continues to tick, thereby, this arragement is relevant
-//    and valid as long as device has a (tickle) battery power.
-//
-//    Further, provision also has been made to set an alarm. When it RTC value
-//    matches that of set for alarm, an interrupt is generated.
-//
-//    HIB MEM REG0 and REG1 are reserved for TI.
-//
-//    If RTC feature is not used, then HIB REG2 & REG3 are available to user.
-//
-//    Lower half of REG0 is used for TI HW ECO.
-//*****************************************************************************
-#define RTC_U64MSEC_MK(u32Secs, u16Msec) (((unsigned long long)u32Secs << 10)|\
-                                          (u16Msec & 0x3FF))
-
-#define RTC_SECS_IN_U64MSEC(u64Msec)     ((unsigned long)(u64Msec  >>   10))
-#define RTC_MSEC_IN_U64MSEC(u64Msec)     ((unsigned short)(u64Msec & 0x3FF))
-
-#define RTC_MSEC_U32_REG_ADDR            (HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2)
-#define RTC_SECS_U32_REG_ADDR            (HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG3)
-
-//*****************************************************************************
-// Register Access and Updates
-//
-// Tick of SCC has a resolution of 32768Hz, meaning 1 sec is equal to 32768
-// clock ticks. Ideal way of getting time in millisecond will involve floating
-// point arithmetic (division by 32.768). To avoid this, we simply divide it by
-// 32, which will give a range from 0 -1023(instead of 0-999). To use this
-// output correctly we have to take care of this inaccuracy externally.
-// following wrapper can be used to convert the value from cycles to
-// millisecond:
-//
-// CYCLES_U16MS(cycles) ((cycles * 1000) / 1024),
-//
-// Similarly, before setting the value, it must be first converted (from ms to
-// cycles).
-//
-// U16MS_CYCLES(msec)   ((msec * 1024) / 1000)
-//
-// Note: There is a precision loss of 1 ms with the above scheme.
-//
-//
-#define SCC_U64MSEC_GET()                (RTCFastDomainCounterGet() >> 5)
-#define SCC_U64MSEC_MATCH_SET(u64Msec)   (MAP_PRCMSlowClkCtrMatchSet(u64Msec << 5))
-#define SCC_U64MSEC_MATCH_GET()          (MAP_PRCMSlowClkCtrMatchGet() >> 5)
-
-//*****************************************************************************
-//
-// Bit:  31 is used to indicate use of RTC. If set as '1', RTC feature is used.
-// Bit:  30 is used to indicate that a safe boot should be performed.
-// bit:  29 is used to indicate that the last reset was caused by the WDT.
-// bit:  28 is used to indicate that the board is booting for the first time after being programmed in factory.
-// Bits: 27 and 26 are unused.
-// Bits: 25 to 16 are used to save millisecond part of RTC reference.
-// Bits: 15 to 0 are being used for HW Changes / ECO.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-// Set RTC USE Bit
-//*****************************************************************************
-static void RTCUseSet(void)
-{
-  unsigned int uiRegValue;
-
-  uiRegValue = MAP_PRCMHIBRegRead(RTC_MSEC_U32_REG_ADDR) | (1 << 31);
-
-  PRCMHIBRegWrite(RTC_MSEC_U32_REG_ADDR, uiRegValue);
-}
-
-//*****************************************************************************
-// Clear RTC USE Bit
-//*****************************************************************************
-static void RTCUseClear(void)
-{
-  unsigned int uiRegValue;
-
-  uiRegValue = MAP_PRCMHIBRegRead(RTC_MSEC_U32_REG_ADDR) & (~(1 << 31));
-
-  PRCMHIBRegWrite(RTC_MSEC_U32_REG_ADDR, uiRegValue);
-}
-
-//*****************************************************************************
-// Checks if RTC-USE bit is set
-//*****************************************************************************
-static tBoolean IsRTCUsed(void)
-{
-  return (MAP_PRCMHIBRegRead(RTC_MSEC_U32_REG_ADDR) & (1 << 31)) ? true : false;
-}
-
-//*****************************************************************************
-// Read 16-bit mSecs
-//*****************************************************************************
-static unsigned short RTCU32MSecRegRead(void)
-{
-  return ((MAP_PRCMHIBRegRead(RTC_MSEC_U32_REG_ADDR) >> 16) & 0x03FF);
-}
-
-//*****************************************************************************
-// Write 16-bit mSecs
-//*****************************************************************************
-static void RTCU32MSecRegWrite(unsigned int u32Msec)
-{
-   unsigned int uiRegValue;
-
-   // read the whole register and clear the msec bits
-   uiRegValue = MAP_PRCMHIBRegRead(RTC_MSEC_U32_REG_ADDR) & (~(0x03FF << 16));
-
-   // write the msec bits only
-   MAP_PRCMHIBRegWrite(RTC_MSEC_U32_REG_ADDR, uiRegValue | ((u32Msec & 0x03FF) << 16));
-}
-
-//*****************************************************************************
-// Read 32-bit Secs
-//*****************************************************************************
-static unsigned long RTCU32SecRegRead(void)
-{
-  return (MAP_PRCMHIBRegRead(RTC_SECS_U32_REG_ADDR));
-}
-
-//*****************************************************************************
-// Write 32-bit Secs
-//*****************************************************************************
-static void RTCU32SecRegWrite(unsigned long u32Msec)
-{
-  MAP_PRCMHIBRegWrite(RTC_SECS_U32_REG_ADDR, u32Msec);
-}
-
-//*****************************************************************************
-// Fast function to get the most accurate RTC counter value
-//*****************************************************************************
-static unsigned long long RTCFastDomainCounterGet (void) {
-
-    #define BRK_IF_RTC_CTRS_ALIGN(c2, c1)       if (c2 - c1 <= 1) {     \
-                                                    itr++;              \
-                                                    break;              \
-                                                }
-
-    unsigned long long rtc_count1, rtc_count2, rtc_count3;
-    unsigned int itr;
-
-    do {
-        rtc_count1 = PRCMSlowClkCtrFastGet();
-        rtc_count2 = PRCMSlowClkCtrFastGet();
-        rtc_count3 = PRCMSlowClkCtrFastGet();
-        itr = 0;
-
-        BRK_IF_RTC_CTRS_ALIGN(rtc_count2, rtc_count1);
-        BRK_IF_RTC_CTRS_ALIGN(rtc_count3, rtc_count2);
-        BRK_IF_RTC_CTRS_ALIGN(rtc_count3, rtc_count1);
-
-        // Consistent values in two consecutive reads implies a correct
-        // value of the counter. Do note, the counter does not give the
-        // calendar time but a hardware that ticks upwards continuously.
-        // The 48-bit counter operates at 32,768 HZ.
-
-    } while (true);
-
-    return (1 == itr) ? rtc_count2 : rtc_count3;
-}
-
-//*****************************************************************************
-// Macros
-//*****************************************************************************
-#define IS_RTC_USED()                   IsRTCUsed()
-#define RTC_USE_SET()                   RTCUseSet()
-#define RTC_USE_CLR()                   RTCUseClear()
-
-#define RTC_U32MSEC_REG_RD()            RTCU32MSecRegRead()
-#define RTC_U32MSEC_REG_WR(u32Msec)     RTCU32MSecRegWrite(u32Msec)
-
-#define RTC_U32SECS_REG_RD()            RTCU32SecRegRead()
-#define RTC_U32SECS_REG_WR(u32Secs)     RTCU32SecRegWrite(u32Secs)
-
-#define SELECT_SCC_U42BITS(u64Msec)     (u64Msec & 0x3ffffffffff)
-
-//*****************************************************************************
-// Global Peripheral clock and rest Registers
-//*****************************************************************************
-static const PRCM_PeriphRegs_t PRCM_PeriphRegsList[] =
-{
-
-	{APPS_RCM_O_CAMERA_CLK_GATING,   APPS_RCM_O_CAMERA_SOFT_RESET   },
-	{APPS_RCM_O_MCASP_CLK_GATING,    APPS_RCM_O_MCASP_SOFT_RESET    },
-	{APPS_RCM_O_MMCHS_CLK_GATING,    APPS_RCM_O_MMCHS_SOFT_RESET    },
-	{APPS_RCM_O_MCSPI_A1_CLK_GATING, APPS_RCM_O_MCSPI_A1_SOFT_RESET },
-	{APPS_RCM_O_MCSPI_A2_CLK_GATING, APPS_RCM_O_MCSPI_A2_SOFT_RESET },
-	{APPS_RCM_O_UDMA_A_CLK_GATING,   APPS_RCM_O_UDMA_A_SOFT_RESET   },
-	{APPS_RCM_O_GPIO_A_CLK_GATING,   APPS_RCM_O_GPIO_A_SOFT_RESET   },
-	{APPS_RCM_O_GPIO_B_CLK_GATING,   APPS_RCM_O_GPIO_B_SOFT_RESET   },
-	{APPS_RCM_O_GPIO_C_CLK_GATING,   APPS_RCM_O_GPIO_C_SOFT_RESET   },
-	{APPS_RCM_O_GPIO_D_CLK_GATING,   APPS_RCM_O_GPIO_D_SOFT_RESET   },
-	{APPS_RCM_O_GPIO_E_CLK_GATING,   APPS_RCM_O_GPIO_E_SOFT_RESET   },
-	{APPS_RCM_O_WDOG_A_CLK_GATING,   APPS_RCM_O_WDOG_A_SOFT_RESET   },
-	{APPS_RCM_O_UART_A0_CLK_GATING,  APPS_RCM_O_UART_A0_SOFT_RESET  },
-	{APPS_RCM_O_UART_A1_CLK_GATING,  APPS_RCM_O_UART_A1_SOFT_RESET  },
-	{APPS_RCM_O_GPT_A0_CLK_GATING ,  APPS_RCM_O_GPT_A0_SOFT_RESET   },
-	{APPS_RCM_O_GPT_A1_CLK_GATING,   APPS_RCM_O_GPT_A1_SOFT_RESET   },
-	{APPS_RCM_O_GPT_A2_CLK_GATING,   APPS_RCM_O_GPT_A2_SOFT_RESET   },
-	{APPS_RCM_O_GPT_A3_CLK_GATING,   APPS_RCM_O_GPT_A3_SOFT_RESET   },
-	{APPS_RCM_O_CRYPTO_CLK_GATING,   APPS_RCM_O_CRYPTO_SOFT_RESET   },
-	{APPS_RCM_O_MCSPI_S0_CLK_GATING, APPS_RCM_O_MCSPI_S0_SOFT_RESET },
-	{APPS_RCM_O_I2C_CLK_GATING,      APPS_RCM_O_I2C_SOFT_RESET      }
-
-};
-
-//*****************************************************************************
-//
-//! Set a special bit
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMSetSpecialBit(unsigned char bit)
-{
-    unsigned int uiRegValue;
-
-    uiRegValue = MAP_PRCMHIBRegRead(RTC_MSEC_U32_REG_ADDR) | (1 << bit);
-
-    PRCMHIBRegWrite(RTC_MSEC_U32_REG_ADDR, uiRegValue);
-}
-
-//*****************************************************************************
-//
-//! Clear a special bit
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMClearSpecialBit(unsigned char bit)
-{
-    unsigned int uiRegValue;
-
-    uiRegValue = MAP_PRCMHIBRegRead(RTC_MSEC_U32_REG_ADDR) & (~(1 << bit));
-
-    PRCMHIBRegWrite(RTC_MSEC_U32_REG_ADDR, uiRegValue);
-}
-
-//*****************************************************************************
-//
-//! Read a special bit
-//!
-//! \return Value of the bit
-//
-//*****************************************************************************
-tBoolean PRCMGetSpecialBit(unsigned char bit)
-{
-    tBoolean value = (MAP_PRCMHIBRegRead(RTC_MSEC_U32_REG_ADDR) & (1 << bit)) ? true : false;
-    // special bits must be cleared immediatelly after reading
-    PRCMClearSpecialBit(bit);
-    return value;
-}
-
-//*****************************************************************************
-//
-//! Performs a software reset of a SOC
-//!
-//! This function performs a software reset of a SOC
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMSOCReset(void)
-{
-  //
-  // Reset MCU
-  //
-  HWREG(GPRCM_BASE+ GPRCM_O_MCU_GLOBAL_SOFT_RESET) |= 0x1;
-
-}
-
-//*****************************************************************************
-//
-//! Performs a software reset of a MCU and associated peripherals
-//!
-//! \param bIncludeSubsystem is \b true to reset associated peripherals.
-//!
-//! This function performs a software reset of a MCU and associated peripherals.
-//! To reset the associated peripheral, the parameter \e bIncludeSubsystem
-//! should be set to \b true.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMMCUReset(tBoolean bIncludeSubsystem)
-{
-  if(bIncludeSubsystem)
-  {
-    //
-    // Reset Apps processor and associated peripheral
-    //
-    HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x2;
-  }
-  else
-  {
-    //
-    // Reset Apps processor only
-    //
-    HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x1;
-  }
-}
-
-//*****************************************************************************
-//
-//! Gets the reason for a reset.
-//!
-//! This function returns the reason(s) for a reset. The reset reason are:-
-//! -\b PRCM_POWER_ON  - Device is powering up.
-//! -\b PRCM_LPDS_EXIT - Device is exiting from LPDS.
-//! -\b PRCM_CORE_RESET - Device is exiting soft core only reset
-//! -\b PRCM_MCU_RESET - Device is exiting soft subsystem reset.
-//! -\b PRCM_WDT_RESET - Device was reset by watchdog.
-//! -\b PRCM_SOC_RESET - Device is exting SOC reset.
-//! -\b PRCM_HIB_EXIT - Device is exiting hibernate.
-//!
-//! \return Returns one of the cause defined above.
-//
-//*****************************************************************************
-unsigned long PRCMSysResetCauseGet(void)
-{
-  unsigned long ulWakeupStatus;
-
-  //
-  // Read the Reset status
-  //
-  ulWakeupStatus = (HWREG(GPRCM_BASE+ GPRCM_O_APPS_RESET_CAUSE) & 0xFF);
-
-  //
-  // For hibernate do additional chaeck.
-  //
-  if(ulWakeupStatus == PRCM_POWER_ON)
-  {
-    if(MAP_PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_WAKE_STATUS) & 0x1)
-    {
-      ulWakeupStatus = PRCM_HIB_EXIT;
-    }
-  }
-
-  //
-  // Return status.
-  //
-  return ulWakeupStatus;
-}
-
-//*****************************************************************************
-//
-//! Enable clock(s) to peripheral.
-//!
-//! \param ulPeripheral is one of the valid peripherals
-//! \param ulClkFlags are bitmask of clock(s) to be enabled.
-//!
-//! This function enables the clock for the specified peripheral. Peripherals
-//! are by default clock gated (disabled) and generates a bus fault if
-//! accessed.
-//!
-//! The parameter \e ulClkFlags can be logical OR of the following:
-//! -\b PRCM_RUN_MODE_CLK - Ungates clock to the peripheral
-//! -\b PRCM_SLP_MODE_CLK - Keeps the clocks ungated in sleep.
-//! -\b PRCM_DSLP_MODE_CLK - Keeps the clock ungated in deepsleep.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMPeripheralClkEnable(unsigned long ulPeripheral, unsigned long ulClkFlags)
-{
-  //
-  // Enable the specified peripheral clocks, Nothing to be done for PRCM_ADC
-  // as it is a dummy define for pinmux utility code generation
-  //
-  if(ulPeripheral != PRCM_ADC)
-  {
-    HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) |= ulClkFlags;
-  }
-  //
-  // Set the default clock for camera
-  //
-  if(ulPeripheral == PRCM_CAMERA)
-  {
-    HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) = 0x0404;
-  }
-}
-
-//*****************************************************************************
-//
-//! Disables clock(s) to peripheral.
-//!
-//! \param ulPeripheral is one of the valid peripherals
-//! \param ulClkFlags are bitmask of clock(s) to be enabled.
-//!
-//! This function disable the clock for the specified peripheral. Peripherals
-//! are by default clock gated (disabled) and generated a bus fault if
-//! accessed.
-//!
-//! The parameter \e ulClkFlags can be logical OR bit fields as defined in
-//! PRCMEnablePeripheral().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMPeripheralClkDisable(unsigned long ulPeripheral, unsigned long ulClkFlags)
-{
-  //
-  // Disable the specified peripheral clocks
-  //
-  HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) &= ~ulClkFlags;
-}
-
-//*****************************************************************************
-//
-//! Gets the input clock for the specified peripheral.
-//!
-//! \param ulPeripheral is one of the valid peripherals.
-//!
-//! This function gets the input clock for the specified peripheral.
-//!
-//! The parameter \e ulPeripheral has the same definition as that in
-//! PRCMPeripheralClkEnable();
-//!
-//! \return Returns input clock frequency for specified peripheral.
-//
-//*****************************************************************************
-unsigned long PRCMPeripheralClockGet(unsigned long ulPeripheral)
-{
-  unsigned long ulClockFreq;
-  unsigned long ulHiPulseDiv;
-  unsigned long ulLoPulseDiv;
-
-  //
-  // Get the clock based on specified peripheral.
-  //
-  if(((ulPeripheral == PRCM_SSPI) | (ulPeripheral == PRCM_LSPI)
-            | (ulPeripheral == PRCM_GSPI)))
-  {
-    return XTAL_CLK;
-  }
-  else if(ulPeripheral == PRCM_CAMERA)
-  {
-    ulHiPulseDiv = ((HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) >> 8) & 0x07);
-    ulLoPulseDiv = (HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN)& 0xFF);
-  }
-  else if(ulPeripheral == PRCM_SDHOST)
-  {
-    ulHiPulseDiv = ((HWREG(ARCM_BASE + APPS_RCM_O_MMCHS_CLK_GEN) >> 8) & 0x07);
-    ulLoPulseDiv = (HWREG(ARCM_BASE + APPS_RCM_O_MMCHS_CLK_GEN)& 0xFF);
-  }
-  else
-  {
-    return SYS_CLK;
-  }
-
-  //
-  // Compute the clock freq. from the divider value
-  //
-  ulClockFreq = (240000000/((ulHiPulseDiv + 1) + (ulLoPulseDiv + 1)));
-
-  //
-  // Return the clock rate.
-  //
-  return ulClockFreq;
-}
-
-//*****************************************************************************
-//
-//! Performs a software reset of a peripheral.
-//!
-//! \param ulPeripheral is one of the valid peripheral.
-//!
-//! This assert or deassert reset to the specified peripheral based of the
-//! \e bAssert parameter.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMPeripheralReset(unsigned long ulPeripheral)
-{
-  volatile unsigned long ulDelay;
-
-  if( ulPeripheral != PRCM_DTHE)
-  {
-    //
-    // Assert the reset
-    //
-    HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulRstReg)
-                                                         |= PRCM_SOFT_RESET;
-    //
-    // Delay for a little bit.
-    //
-    for(ulDelay = 0; ulDelay < 16; ulDelay++)
-    {
-    }
-
-    //
-    // Deassert the reset
-    //
-    HWREG(ARCM_BASE+PRCM_PeriphRegsList[ulPeripheral].ulRstReg)
-                                                          &= ~PRCM_SOFT_RESET;
-  }
-}
-
-//*****************************************************************************
-//
-//! Determines if a peripheral is ready.
-//!
-//! \param ulPeripheral is one of the valid modules
-//!
-//! This function determines if a particular peripheral is ready to be
-//! accessed. The peripheral may be in a non-ready state if it is not enabled,
-//! is being held in reset, or is in the process of becoming ready after being
-//! enabled or taken out of reset.
-//!
-//! \return Returns \b true if the  peripheral is ready, \b false otherwise.
-//
-//*****************************************************************************
-tBoolean PRCMPeripheralStatusGet(unsigned long ulPeripheral)
-{
-  unsigned long ReadyBit;
-
-  //
-  // Read the ready bit status
-  //
-  ReadyBit = HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulRstReg);
-  ReadyBit = ReadyBit & PRCM_ENABLE_STATUS;
-
-  if (ReadyBit)
-  {
-    //
-    // Module is ready
-    //
-    return(true);
-  }
-  else
-  {
-    //
-    // Module is not ready
-    //
-    return(false);
-  }
-}
-
-//*****************************************************************************
-//
-//! Configure I2S fracactional divider
-//!
-//! \param ulI2CClkFreq is the required input clock for McAPS module
-//!
-//! This function configures I2S fractional divider. By default this
-//! divider is set to output 24 Mhz clock to I2S module.
-//!
-//! The minimum frequency that can be obtained by configuring this divider is
-//!
-//! (240000KHz/1023.99) =  234.377 KHz
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMI2SClockFreqSet(unsigned long ulI2CClkFreq)
-{
- unsigned long long ullDiv;
-  unsigned short usInteger;
-  unsigned short usFrac;
-
-  ullDiv = (((unsigned long long)240000000 * 65536)/ulI2CClkFreq);
-
-  usInteger = (ullDiv/65536);
-  usFrac    = (ullDiv%65536);
-
-  HWREG(ARCM_BASE + APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0) =
-    ((usInteger & 0x3FF) << 16 | usFrac);
-}
-
-//*****************************************************************************
-//
-//! Sets the LPDS exit PC and SP restore vlaues.
-//!
-//! \param ulStackPtr is the SP restore value.
-//! \param ulProgCntr is the PC restore value
-//!
-//! This function sets the LPDS exit PC and SP restore vlaues. Setting
-//! \e ulProgCntr to a non-zero value, forces bootloader to jump to that
-//! address with Stack Pointer initialized to \e ulStackPtr on LPDS exit,
-//! otherwise the application's vector table entries are used.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMLPDSRestoreInfoSet(unsigned long ulStackPtr, unsigned long ulProgCntr)
-{
-  //
-  // Set The SP Value
-  //
-  HWREG(0x4402E18C) = ulStackPtr;
-
-  //
-  // Set The PC Value
-  //
-  HWREG(0x4402E190) = ulProgCntr;
-}
-
-//*****************************************************************************
-//
-//! Puts the system into Low Power Deel Sleep (LPDS) power mode.
-//!
-//! This function puts the system into Low Power Deel Sleep (LPDS) power mode.
-//! A call to this function never returns and the execution starts from Reset.
-//! \sa PRCMLPDSRestoreInfoSet().
-//!
-//! \return None.
-//!
-//! \note The Test Power Domain is shutdown whenever the system
-//!  enters LPDS (by default). In order to avoid this and allow for
-//!  connecting back the debugger after waking up from LPDS,
-//!  the macro KEEP_TESTPD_ALIVE has to be defined while building the library.
-//!  This is recommended for development purposes only as it adds to
-//!  the current consumption of the system.
-//!
-//
-//*****************************************************************************
-void PRCMLPDSEnter(void)
-{
-#ifndef DEBUG
-  //
-  // Disable TestPD
-  //
-  HWREG(0x4402E168) |= (1<<9);
-#endif
-
-  //
-  // Set bandgap duty cycle to 1
-  //
-  HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1;
-
-  //
-  // Request LPDS
-  //
-  HWREG(ARCM_BASE + APPS_RCM_O_APPS_LPDS_REQ) = APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ;
-
-  __asm("    nop\n"
-        "    nop\n"
-        "    nop\n"
-        "    nop\n");
-}
-
-//*****************************************************************************
-//
-//! Enable the individual LPDS wakeup source(s).
-//!
-//! \param ulLpdsWakeupSrc is logical OR of wakeup sources.
-//!
-//! This function enable the individual LPDS wakeup source(s) and following
-//! three wakeup sources (\e ulLpdsWakeupSrc ) are supported by the device.
-//! -\b PRCM_LPDS_HOST_IRQ
-//! -\b PRCM_LPDS_GPIO
-//! -\b PRCM_LPDS_TIMER
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMLPDSWakeupSourceEnable(unsigned long ulLpdsWakeupSrc)
-{
-  unsigned long ulRegVal;
-
-  //
-  // Read the current wakup sources
-  //
-  ulRegVal = HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG);
-
-  //
-  // Enable individual wakeup source
-  //
-  ulRegVal = ((ulRegVal | ulLpdsWakeupSrc) & 0x91);
-
-  //
-  // Set the configuration in the register
-  //
-  HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG) = ulRegVal;
-}
-
-//*****************************************************************************
-//
-//! Disable the individual LPDS wakeup source(s).
-//!
-//! \param ulLpdsWakeupSrc is logical OR of wakeup sources.
-//!
-//! This function enable the individual LPDS wakeup source(s) and following
-//! three wake up sources (\e ulLpdsWakeupSrc ) are supported by the device.
-//! -\b PRCM_LPDS_HOST_IRQ
-//! -\b PRCM_LPDS_GPIO
-//! -\b PRCM_LPDS_TIMER
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMLPDSWakeupSourceDisable(unsigned long ulLpdsWakeupSrc)
-{
-  HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG) &= ~ulLpdsWakeupSrc;
-}
-
-
-//*****************************************************************************
-//
-//! Get LPDS wakeup cause
-//!
-//! This function gets LPDS wakeup caouse
-//!
-//! \return Returns values enumerated as described in
-//! PRCMLPDSWakeupSourceEnable().
-//
-//*****************************************************************************
-unsigned long PRCMLPDSWakeupCauseGet(void)
-{
-  return (HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_SRC));
-}
-
-//*****************************************************************************
-//
-//! Sets LPDS wakeup Timer
-//!
-//! \param ulTicks is number of 32.768 KHz clocks
-//!
-//! This function sets internal LPDS wakeup timer running at 32.768 KHz. The
-//! timer is only configured if the parameter \e ulTicks is in valid range i.e.
-//! from 21 to 2^32.
-//!
-//! \return Returns \b true on success, \b false otherwise.
-//
-//*****************************************************************************
-void PRCMLPDSIntervalSet(unsigned long ulTicks)
-{
-  //
-  // Check sleep is atleast for 21 cycles
-  // If not set the sleep time to 21 cycles
-  //
-  if( ulTicks < 21)
-  {
-      ulTicks = 21;
-  }
-
-  HWREG(GPRCM_BASE + GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG) = ulTicks;
-  HWREG(GPRCM_BASE + GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG) = ulTicks-20;
-}
-
-//*****************************************************************************
-//
-//! Selects the GPIO for LPDS wakeup
-//!
-//! \param ulGPIOPin is one of the valid GPIO fro LPDS wakeup.
-//! \param ulType is the wakeup trigger type.
-//!
-//! This function setects the wakeup GPIO for LPDS wakeup and can be
-//! used to select one out of 7 pre-defined GPIO(s).
-//!
-//! The parameter \e ulLpdsGPIOSel should be one of the following:-
-//! -\b PRCM_LPDS_GPIO2
-//! -\b PRCM_LPDS_GPIO4
-//! -\b PRCM_LPDS_GPIO13
-//! -\b PRCM_LPDS_GPIO17
-//! -\b PRCM_LPDS_GPIO11
-//! -\b PRCM_LPDS_GPIO24
-//! -\b PRCM_LPDS_GPIO26
-//!
-//! The parameter \e ulType sets the trigger type and can be one of the
-//! following:
-//! - \b PRCM_LPDS_LOW_LEVEL
-//! - \b PRCM_LPDS_HIGH_LEVEL
-//! - \b PRCM_LPDS_FALL_EDGE
-//! - \b PRCM_LPDS_RISE_EDGE
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin, unsigned long ulType)
-{
-  //
-  // Set the wakeup GPIO
-  //
-  MAP_PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL, ulGPIOPin);
-
-  //
-  // Set the trigger type.
-  //
-  HWREG(GPRCM_BASE + GPRCM_O_APPS_GPIO_WAKE_CONF) = (ulType & 0x3);
-}
-
-//*****************************************************************************
-//
-//! Puts the system into Sleep.
-//!
-//! This function puts the system into sleep power mode. System exits the power
-//! state on any one of the available interrupt. On exit from sleep mode the
-//! function returns to the calling function with all the processor core
-//! registers retained.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMSleepEnter(void)
-{
-  //
-  // Request Sleep
-  //
-  CPUwfi();
-}
-
-//*****************************************************************************
-//
-//! Puts the system into Deep Sleep power mode.
-//!
-//! This function puts the system into Deep Sleep power mode. System exits the
-//! power state on any one of the available interrupt. On exit from deep
-//! sleep the function returns to the calling function with all the processor
-//! core registers retained.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMDeepSleepEnter(void)
-{
-  //
-  // Set bandgap duty cycle to 1
-  //
-  HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1;
-
-  //
-  // Enable DSLP in cortex
-  //
-  HWREG(0xE000ED10)|=1<<2;
-
-  //
-  // Request Deep Sleep
-  //
-  CPUwfi();
-
-  //
-  // Disable DSLP in cortex before
-  // returning to the caller
-  //
-  HWREG(0xE000ED10) &= ~(1<<2);
-
-}
-
-//*****************************************************************************
-//
-//! Enable SRAM column retention during Deep Sleep and/or LPDS Power mode(s)
-//!
-//! \param ulSramColSel is bit mask of valid SRAM columns.
-//! \param ulModeFlags is the bit mask of power modes.
-//!
-//! This functions enables the SRAM retention. The device supports configurable
-//! SRAM column retention in Low Power Deep Sleep (LPDS) and Deep Sleep power
-//! modes. Each column is of 64 KB size.
-//!
-//! The parameter \e ulSramColSel should be logical OR of the following:-
-//! -\b PRCM_SRAM_COL_1
-//! -\b PRCM_SRAM_COL_2
-//! -\b PRCM_SRAM_COL_3
-//! -\b PRCM_SRAM_COL_4
-//!
-//! The parameter \e ulModeFlags selects the power modes and sholud be logical
-//! OR of one or more of the following
-//! -\b PRCM_SRAM_DSLP_RET
-//! -\b PRCM_SRAM_LPDS_RET
-//!
-//! \return None.
-//
-//****************************************************************************
-void PRCMSRAMRetentionEnable(unsigned long ulSramColSel, unsigned long ulModeFlags)
-{
-  if(ulModeFlags & PRCM_SRAM_DSLP_RET)
-  {
-    //
-    // Configure deep sleep SRAM retention register
-    //
-    HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_DSLP_CFG) = (ulSramColSel & 0xF);
-  }
-
-  if(ulModeFlags & PRCM_SRAM_LPDS_RET)
-  {
-    //
-    // Configure LPDS SRAM retention register
-    //
-    HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_LPDS_CFG) = (ulSramColSel & 0xF);
-  }
-}
-
-//*****************************************************************************
-//
-//! Disable SRAM column retention during Deep Sleep and/or LPDS Power mode(s).
-//!
-//! \param ulSramColSel is bit mask of valid SRAM columns.
-//! \param ulFlags is the bit mask of power modes.
-//!
-//! This functions disable the SRAM retention. The device supports configurable
-//! SRAM column retention in Low Power Deep Sleep (LPDS) and Deep Sleep power
-//! modes. Each column is of 64 KB size.
-//!
-//! The parameter \e ulSramColSel should be logical OR of the following:-
-//! -\b PRCM_SRAM_COL_1
-//! -\b PRCM_SRAM_COL_2
-//! -\b PRCM_SRAM_COL_3
-//! -\b PRCM_SRAM_COL_4
-//!
-//! The parameter \e ulFlags selects the power modes and sholud be logical OR
-//! of one or more of the following
-//! -\b PRCM_SRAM_DSLP_RET
-//! -\b PRCM_SRAM_LPDS_RET
-//!
-//! \return None.
-//
-//****************************************************************************
-void PRCMSRAMRetentionDisable(unsigned long ulSramColSel, unsigned long ulFlags)
-{
-  if(ulFlags & PRCM_SRAM_DSLP_RET)
-  {
-    //
-    // Configure deep sleep SRAM retention register
-    //
-    HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_DSLP_CFG) &= ~(ulSramColSel & 0xF);
-  }
-
-  if(ulFlags & PRCM_SRAM_LPDS_RET)
-  {
-    //
-    // Configure LPDS SRAM retention register
-    //
-    HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_LPDS_CFG) &= ~(ulSramColSel & 0xF);
-  }
-}
-
-
-//*****************************************************************************
-//
-//! Enables individual HIB wakeup source(s).
-//!
-//! \param ulHIBWakupSrc is logical OR of valid HIB wakeup sources.
-//!
-//! This function enables individual HIB wakeup source(s). The paramter
-//! \e ulHIBWakupSrc is the bit mask of HIB wakeup sources and should be
-//! logical OR of one or more of the follwoing :-
-//! -\b PRCM_HIB_SLOW_CLK_CTR
-//! -\b PRCM_HIB_GPIO2
-//! -\b PRCM_HIB_GPIO4
-//! -\b PRCM_HIB_GPIO13
-//! -\b PRCM_HIB_GPIO17
-//! -\b PRCM_HIB_GPIO11
-//! -\b PRCM_HIB_GPIO24
-//! -\b PRCM_HIB_GPIO26
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMHibernateWakeupSourceEnable(unsigned long ulHIBWakupSrc)
-{
-  unsigned long ulRegValue;
-
-  //
-  // Read the RTC register
-  //
-  ulRegValue = MAP_PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN);
-
-  //
-  // Enable the RTC as wakeup source if specified
-  //
-  ulRegValue |= (ulHIBWakupSrc & 0x1);
-
-  //
-  // Enable HIB wakeup sources
-  //
-  MAP_PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue);
-
-  //
-  // REad the GPIO wakeup configuration register
-  //
-  ulRegValue = MAP_PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN);
-
-  //
-  // Enable the specified GPIOs a wakeup sources
-  //
-  ulRegValue |= ((ulHIBWakupSrc>>16)&0xFF);
-
-  //
-  // Write the new register configuration
-  //
-  MAP_PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN,ulRegValue);
-}
-
-//*****************************************************************************
-//
-//! Disable individual HIB wakeup source(s).
-//!
-//! \param ulHIBWakupSrc is logical OR of valid HIB wakeup sources.
-//!
-//! This function disable individual HIB wakeup source(s). The paramter
-//! \e ulHIBWakupSrc is same as bit fileds defined in
-//! PRCMEnableHibernateWakeupSource()
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMHibernateWakeupSourceDisable(unsigned long ulHIBWakupSrc)
-{
-  unsigned long ulRegValue;
-
-  //
-  // Read the RTC register
-  //
-  ulRegValue = MAP_PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN);
-
-  //
-  // Disable the RTC as wakeup source if specified
-  //
-  ulRegValue &= ~(ulHIBWakupSrc & 0x1);
-
-  //
-  // Disable HIB wakeup sources
-  //
-  MAP_PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue);
-
-  //
-  // Read the GPIO wakeup configuration register
-  //
-  ulRegValue = MAP_PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN);
-
-  //
-  // Enable the specified GPIOs a wakeup sources
-  //
-  ulRegValue &= ~((ulHIBWakupSrc>>16)&0xFF);
-
-  //
-  // Write the new register configuration
-  //
-  MAP_PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN,ulRegValue);
-}
-
-
-//*****************************************************************************
-//
-//! Get hibernate wakeup cause
-//!
-//! This function gets the hibernate wakeup cause.
-//!
-//! \return Returns \b PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK or
-//! \b PRCM_HIB_WAKEUP_CAUSE_GPIO
-//
-//*****************************************************************************
-unsigned long PRCMHibernateWakeupCauseGet(void)
-{
-  return ((MAP_PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_WAKE_STATUS)>>1)&0xF);
-}
-
-//*****************************************************************************
-//
-//! Sets Hibernate wakeup Timer
-//!
-//! \param ullTicks is number of 32.768 KHz clocks
-//!
-//! This function sets internal hibernate wakeup timer running at 32.768 KHz.
-//!
-//! \return Returns \b true on success, \b false otherwise.
-//
-//*****************************************************************************
-void PRCMHibernateIntervalSet(unsigned long long ullTicks)
-{
-  unsigned long long ullRTCVal;
-
-  //
-  // Latch the RTC vlaue
-  //
-  MAP_PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_READ ,0x1);
-
-  //
-  // Read latched values as 2 32-bit vlaues
-  //
-  ullRTCVal  = MAP_PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_TIMER_MSW);
-  ullRTCVal  = ullRTCVal << 32;
-  ullRTCVal |= MAP_PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_LSW);
-
-  //
-  // Add the interval
-  //
-  ullRTCVal = ullRTCVal + ullTicks;
-
-  //
-  // Set RTC match value
-  //
-  MAP_PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF,
-                                            (unsigned long)(ullRTCVal));
-  MAP_PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF,
-                                           (unsigned long)(ullRTCVal>>32));
-}
-
-
-//*****************************************************************************
-//
-//! Selects the GPIO(s) for hibernate wakeup
-//!
-//! \param ulGPIOBitMap is the bit-map of valid hibernate wakeup GPIO.
-//! \param ulType is the wakeup trigger type.
-//!
-//! This function setects the wakeup GPIO for hibernate and can be
-//! used to select any combination of 7 pre-defined GPIO(s).
-//!
-//! This function enables individual HIB wakeup source(s). The paramter
-//! \e ulGPIOBitMap should be one of the follwoing :-
-//! -\b PRCM_HIB_GPIO2
-//! -\b PRCM_HIB_GPIO4
-//! -\b PRCM_HIB_GPIO13
-//! -\b PRCM_HIB_GPIO17
-//! -\b PRCM_HIB_GPIO11
-//! -\b PRCM_HIB_GPIO24
-//! -\b PRCM_HIB_GPIO26
-//!
-//! The parameter \e ulType sets the trigger type and can be one of the
-//! following:
-//! - \b PRCM_HIB_LOW_LEVEL
-//! - \b PRCM_HIB_HIGH_LEVEL
-//! - \b PRCM_HIB_FALL_EDGE
-//! - \b PRCM_HIB_RISE_EDGE
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMHibernateWakeUpGPIOSelect(unsigned long ulGPIOBitMap, unsigned long ulType)
-{
-  unsigned char ucLoop;
-  unsigned long ulRegValue;
-
-  //
-  // Shift the bits to extract the GPIO selection
-  //
-  ulGPIOBitMap >>= 16;
-
-  //
-  // Set the configuration for each GPIO
-  //
-  for(ucLoop=0; ucLoop < 7; ucLoop++)
-  {
-    if(ulGPIOBitMap & (1<<ucLoop))
-    {
-      ulRegValue  = MAP_PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_CONF);
-      ulRegValue |= (ulType << (ucLoop*2));
-      MAP_PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_CONF, ulRegValue);
-    }
-  }
-}
-
-//*****************************************************************************
-//
-//! Puts the system into Hibernate
-//!
-//! This function puts the system into Hibernate. The device enters HIB
-//! immediately and on exit from HIB device core starts its execution from
-//! reset thus the function never returns.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMHibernateEnter(void)
-{
-
-  //
-  // Request hibernate.
-  //
-  MAP_PRCMHIBRegWrite((HIB3P3_BASE+HIB3P3_O_MEM_HIB_REQ),0x1);
-
-  __asm("    nop\n"
-        "    nop\n"
-        "    nop\n"
-        "    nop\n");
-}
-
-//*****************************************************************************
-//
-//! Gets the current value of the internal slow clock counter
-//!
-//! This function latches and reads the internal RTC running at 32.768 Khz
-//!
-//! \return 64-bit current counter vlaue.
-//
-//*****************************************************************************
-unsigned long long PRCMSlowClkCtrGet(void)
-{
-  unsigned long long ullRTCVal;
-
-  //
-  // Latch the RTC vlaue
-  //
-  MAP_PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_READ, 0x1);
-
-  //
-  // Read latched values as 2 32-bit vlaues
-  //
-  ullRTCVal  = MAP_PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_TIMER_MSW);
-  ullRTCVal  = ullRTCVal << 32;
-  ullRTCVal |= MAP_PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_LSW);
-
-  return ullRTCVal;
-}
-
-//*****************************************************************************
-//
-//! Gets the current value of the internal slow clock counter
-//!
-//! This function is similar to \sa PRCMSlowClkCtrGet() but reads the counter
-//! value from a relatively faster interface using an auto-latch mechainsm.
-//!
-//! \note Due to the nature of implemetation of auto latching, when using this
-//! API, the recommendation is to read the value thrice and identify the right
-//! value (as 2 out the 3 read values will always be correct and with a max. of
-//! 1 LSB change)
-//!
-//! \return 64-bit current counter vlaue.
-//
-//*****************************************************************************
-unsigned long long PRCMSlowClkCtrFastGet(void)
-{
-  unsigned long long ullRTCVal;
-
-  //
-  // Read as 2 32-bit values
-  //
-  ullRTCVal = HWREG(HIB1P2_BASE + HIB1P2_O_HIB_RTC_TIMER_MSW_1P2);
-  ullRTCVal = ullRTCVal << 32;
-  ullRTCVal |= HWREG(HIB1P2_BASE + HIB1P2_O_HIB_RTC_TIMER_LSW_1P2);
-
-  return ullRTCVal;
-
-}
-
-//*****************************************************************************
-//
-//! Sets slow clock counter match value to interrupt the processor.
-//!
-//! \param ullValue is the match value.
-//!
-//! This function sets the match value for  slow clock counter. This is use
-//! to interrupt the processor when RTC counts to the specified value.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMSlowClkCtrMatchSet(unsigned long long ullValue)
-{
-  //
-  // Set RTC match value
-  //
-  MAP_PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF,
-                                           (unsigned long)(ullValue));
-  MAP_PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF,
-                                           (unsigned long)(ullValue>>32));
-}
-
-//*****************************************************************************
-//
-//! Gets slow clock counter match value.
-//!
-//! This function gets the match value for  slow clock counter. This is use
-//! to interrupt the processor when RTC counts to the specified value.
-//!
-//! \return None.
-//
-//*****************************************************************************
-unsigned long long PRCMSlowClkCtrMatchGet(void)
-{
-  unsigned long long ullValue;
-
-  //
-  // Get RTC match value
-  //
-  ullValue = MAP_PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF);
-  ullValue = ullValue<<32;
-  ullValue |= MAP_PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF);
-
-  //
-  // Return the value
-  //
-  return ullValue;
-}
-
-
-//*****************************************************************************
-//
-//! Write to On-Chip Retention (OCR) register.
-//!
-//! This function writes to On-Chip retention register. The device supports two
-//! 4-byte OCR register which are retained across all power mode.
-//!
-//! The parameter \e ucIndex is an index of the OCR and can be \b 0 or \b 1.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMOCRRegisterWrite(unsigned char ucIndex, unsigned long ulRegValue)
-{
-  MAP_PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_REG2+(ucIndex << 2),ulRegValue);
-}
-
-//*****************************************************************************
-//
-//! Read from On-Chip Retention (OCR) register.
-//!
-//! This function reads from On-Chip retention register. The device supports two
-//! 4-byte OCR register which are retained across all power mode.
-//!
-//! The parameter \e ucIndex is an index of the OCR and can be \b 0 or \b 1.
-//!
-//! \return None.
-//
-//*****************************************************************************
-unsigned long PRCMOCRRegisterRead(unsigned char ucIndex)
-{
-  //
-  // Return the read value.
-  //
-  return MAP_PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_REG2 + (ucIndex << 2));
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for the PRCM.
-//!
-//! \param pfnHandler is a pointer to the function to be called when the
-//! interrupt is activated.
-//!
-//! This function does the actual registering of the interrupt handler.  This
-//! function enables the global interrupt in the interrupt controller;
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMIntRegister(void (*pfnHandler)(void))
-{
-  //
-  // Register the interrupt handler.
-  //
-  IntRegister(INT_PRCM, pfnHandler);
-
-  //
-  // Enable the PRCM interrupt.
-  //
-  IntEnable(INT_PRCM);
-}
-
-//*****************************************************************************
-//
-//! Unregisters an interrupt handler for the PRCM.
-//!
-//! This function does the actual unregistering of the interrupt handler.  It
-//! clears the handler to be called when a PRCM interrupt occurs.  This
-//! function also masks off the interrupt in the interrupt controller so that
-//! the interrupt handler no longer is called.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMIntUnregister(void)
-{
-  //
-  // Enable the UART interrupt.
-  //
-  IntDisable(INT_PRCM);
-
-  //
-  // Register the interrupt handler.
-  //
-  IntUnregister(INT_PRCM);
-}
-
-//*****************************************************************************
-//
-//! Enables individual PRCM interrupt sources.
-//!
-//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
-//!
-//! This function enables the indicated ARCM interrupt sources.  Only the
-//! sources that are enabled can be reflected to the processor interrupt;
-//! disabled sources have no effect on the processor.
-//!
-//! The \e ulIntFlags parameter is the logical OR of any of the following:
-//! -\b PRCM_INT_SLOW_CLK_CTR
-//!
-//
-//*****************************************************************************
-void PRCMIntEnable(unsigned long ulIntFlags)
-{
-  unsigned long ulRegValue;
-
-  if(ulIntFlags & PRCM_INT_SLOW_CLK_CTR )
-  {
-    //
-    // Enable PRCM interrupt
-    //
-    HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE) |= 0x4;
-
-    //
-    // Enable RTC interrupt
-    //
-    ulRegValue = MAP_PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE);
-    ulRegValue |= 0x1;
-    MAP_PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE, ulRegValue);
-  }
-}
-
-//*****************************************************************************
-//
-//! Disables individual PRCM interrupt sources.
-//!
-//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
-//!
-//! This function disables the indicated ARCM interrupt sources.  Only the
-//! sources that are enabled can be reflected to the processor interrupt;
-//! disabled sources have no effect on the processor.
-//!
-//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
-//! parameter to PRCMEnableInterrupt().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMIntDisable(unsigned long ulIntFlags)
-{
-  unsigned long ulRegValue;
-
-  if(ulIntFlags & PRCM_INT_SLOW_CLK_CTR )
-  {
-    //
-    // Disable PRCM interrupt
-    //
-    HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE) &= ~0x4;
-
-    //
-    // Disable RTC interrupt
-    //
-    ulRegValue = MAP_PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE);
-    ulRegValue &= ~0x1;
-    MAP_PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE, ulRegValue);
-  }
-}
-
-//*****************************************************************************
-//
-//! Gets the current interrupt status.
-//!
-//! This function returns the PRCM interrupt status of interrupts that are
-//! allowed to reflect to the processor. The interrupts are cleared on read.
-//!
-//! \return Returns the current interrupt status.
-//
-//*****************************************************************************
-unsigned long PRCMIntStatus(void)
-{
-    return HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS);
-}
-
-//*****************************************************************************
-//
-//! Mark the function of RTC as being used
-//!
-//! This function marks in HW that feature to maintain calendar time in device
-//! is being used.
-//!
-//! Specifically, this feature reserves user's HIB Register-1 accessed through
-//! PRCMOCRRegisterWrite(1) for internal work / purpose, therefore, the stated
-//! register is not available to user. Also, users must not excercise the Slow
-//! Clock Counter API(s), if RTC has been set for use.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMRTCInUseSet(void)
-{
-        RTC_USE_SET();
-        return;
-}
-
-//*****************************************************************************
-//
-//! Clear the function of RTC as being used
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMRTCInUseClear(void)
-{
-        RTC_USE_CLR();
-        return;
-}
-
-//*****************************************************************************
-//
-//! Ascertain whether function of RTC is being used
-//!
-//! This function indicates whether function of RTC is being used on the device
-//! or not.
-//!
-//! This routine should be utilized by the application software, when returning
-//! from low-power, to confirm that RTC has been put to use and may not need to
-//! set the value of the RTC.
-//!
-//! The RTC feature, if set or marked, can be only reset either through reboot
-//! or power cycle.
-//!
-//! \return None.
-//
-//*****************************************************************************
-tBoolean PRCMRTCInUseGet(void)
-{
-        return IS_RTC_USED()? true : false;
-}
-
-//*****************************************************************************
-//
-//! Set the calendar time in the device.
-//!
-//! \param ulSecs refers to the seconds part of the  calendar time
-//! \param usMsec refers to the fractional (ms) part of the second
-//!
-//! This function sets the specified calendar time in the device. The calendar
-//! time is outlined in terms of seconds and milliseconds. However, the device
-//! makes no assumption about the origin or reference of the calendar time.
-//!
-//! The device uses the indicated calendar value to update and maintain the
-//! wall-clock time across active and low power states.
-//!
-//! The function PRCMRTCInUseSet() must be invoked prior to use of this feature.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMRTCSet(unsigned long ulSecs, unsigned short usMsec)
-{
-        unsigned long long ullMsec = 0;
-
-        if(IS_RTC_USED()) {
-                ullMsec = RTC_U64MSEC_MK(ulSecs, usMsec) - SCC_U64MSEC_GET();
-
-                 RTC_U32SECS_REG_WR(RTC_SECS_IN_U64MSEC(ullMsec));
-                 RTC_U32MSEC_REG_WR(RTC_MSEC_IN_U64MSEC(ullMsec));
-        }
-
-        return;
-}
-
-//*****************************************************************************
-//
-//! Get the instantaneous calendar time from the device.
-//!
-//! \param ulSecs refers to the seconds part of the  calendar time
-//! \param usMsec refers to the fractional (ms) part of the second
-//!
-//! This function fetches the instantaneous value of the ticking calendar time
-//! from the device. The calendar time is outlined in terms of seconds and
-//! milliseconds.
-//!
-//! The device provides the calendar value that has been maintained across
-//! active and low power states.
-//!
-//! The function PRCMRTCSet() must have been invoked once to set a reference.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMRTCGet(unsigned long *ulSecs, unsigned short *usMsec)
-{
-        unsigned long long ullMsec = 0;
-
-        if(IS_RTC_USED()) {
-                ullMsec  = RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(),
-                                          RTC_U32MSEC_REG_RD());
-                ullMsec += SCC_U64MSEC_GET();
-        }
-
-        *ulSecs = RTC_SECS_IN_U64MSEC(ullMsec);
-        *usMsec = RTC_MSEC_IN_U64MSEC(ullMsec);
-
-        return;
-}
-
-//*****************************************************************************
-//
-//! Set a calendar time alarm.
-//!
-//! \param ulSecs refers to the seconds part of the  calendar time
-//! \param usMsec refers to the fractional (ms) part of the second
-//!
-//! This function sets an wall-clock alarm in the device to be reported for  a
-//! futuristic calendar time. The calendar time is outlined in terms of seconds
-//! and milliseconds.
-//!
-//! The device provides uses the calendar value that has been maintained across
-//! active and low power states to report attainment of alarm time.
-//!
-//! The function PRCMRTCSet() must have been invoked once to set a reference.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMRTCMatchSet(unsigned long ulSecs, unsigned short usMsec)
-{
-        unsigned long long ullMsec = 0;
-
-        if(IS_RTC_USED()) {
-                ullMsec  = RTC_U64MSEC_MK(ulSecs, usMsec);
-                ullMsec -= RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(),
-                                          RTC_U32MSEC_REG_RD());
-                SCC_U64MSEC_MATCH_SET(SELECT_SCC_U42BITS(ullMsec));
-        }
-
-        return;
-}
-
-//*****************************************************************************
-//
-//! Get a previously set calendar time alarm.
-//!
-//! \param ulSecs refers to the seconds part of the  calendar time
-//! \param usMsec refers to the fractional (ms) part of the second
-//!
-//! This function fetches from the device a wall-clock alarm that would  have
-//! been previously set in the device. The calendar time is outlined in terms
-//! of seconds and milliseconds.
-//!
-//! If no alarm was set in the past, then this function would fetch a random
-//! information.
-//!
-//! The function PRCMRTCMatchSet() must have been invoked once to set an alarm.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void PRCMRTCMatchGet(unsigned long *ulSecs, unsigned short *usMsec)
-{
-        unsigned long long ullMsec = 0;
-
-        if(IS_RTC_USED()) {
-                ullMsec  = SCC_U64MSEC_MATCH_GET();
-                ullMsec += RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(),
-                                          RTC_U32MSEC_REG_RD());
-        }
-
-        *ulSecs = RTC_SECS_IN_U64MSEC(ullMsec);
-        *usMsec = RTC_MSEC_IN_U64MSEC(ullMsec);
-
-        return;
-}
-
-//*****************************************************************************
-//
-//! MCU Initialization Routine
-//!
-//! This function sets mandatory configurations for the MCU
-//!
-//! \return None
-//
-//*****************************************************************************
-void PRCMCC3200MCUInit(void)
-{
-    unsigned long ulRegValue;
-
-    //
-    // DIG DCDC LPDS ECO Enable
-    //
-    HWREG(0x4402F064) |= 0x800000;
-
-    //
-    // Enable hibernate ECO for PG 1.32 devices only. With this ECO enabled,
-    // any hibernate wakeup source will be kept masked until the device enters
-    // hibernate completely (analog + digital)
-    //
-    ulRegValue = MAP_PRCMHIBRegRead(HIB3P3_BASE  + HIB3P3_O_MEM_HIB_REG0);
-    MAP_PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0, ulRegValue | (1<<4));
-
-    //
-    // Handling the clock switching (for 1.32 only)
-    //
-    HWREG(0x4402E16C) |= 0x3C;
-
-    //
-    // Enable uDMA
-    //
-    MAP_PRCMPeripheralClkEnable(PRCM_UDMA,PRCM_RUN_MODE_CLK);
-
-    //
-    // Reset uDMA
-    //
-    MAP_PRCMPeripheralReset(PRCM_UDMA);
-
-    //
-    // Disable uDMA
-    //
-    MAP_PRCMPeripheralClkDisable(PRCM_UDMA,PRCM_RUN_MODE_CLK);
-
-    //
-    // Enable RTC
-    //
-    if(MAP_PRCMSysResetCauseGet()== PRCM_POWER_ON)
-    {
-        MAP_PRCMHIBRegWrite(0x4402F804,0x1);
-    }
-
-    //
-    // SWD mode
-    //
-    if (((HWREG(0x4402F0C8) & 0xFF) == 0x2))
-    {
-        HWREG(0x4402E110) = ((HWREG(0x4402E110) & ~0xC0F) | 0x2);
-        HWREG(0x4402E114) = ((HWREG(0x4402E110) & ~0xC0F) | 0x2);
-    }
-
-    //
-    // Override JTAG mux
-    //
-    HWREG(0x4402E184) |= 0x2;
-
-    //
-    // Change UART pins(55,57) mode to PIN_MODE_0 if they are in PIN_MODE_1
-    //
-    if ((HWREG(0x4402E0A4) & 0xF) == 0x1)
-    {
-        HWREG(0x4402E0A4) = ((HWREG(0x4402E0A4) & ~0xF));
-    }
-
-    if ((HWREG(0x4402E0A8) & 0xF) == 0x1)
-    {
-        HWREG(0x4402E0A8) = ((HWREG(0x4402E0A8) & ~0xF));
-    }
-
-    //
-    // DIG DCDC VOUT trim settings based on PROCESS INDICATOR
-    //
-    if (((HWREG(0x4402DC78) >> 22) & 0xF) == 0xE)
-    {
-        HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000))|(0x32 << 18));
-    }
-    else
-    {
-        HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000))|(0x29 << 18));
-    }
-
-    //
-    // Enable SOFT RESTART in case of DIG DCDC collapse
-    //
-    HWREG(0x4402FC74) &= ~(0x10000000);
-
-
-    //
-    // Disable the sleep for ANA DCDC
-    //
-    HWREG(0x4402F0A8) |= 0x00000004 ;
-}
-
-//*****************************************************************************
-//
-//! Reads 32-bit value from register at specified address
-//!
-//! \param ulRegAddr is the address of register to be read.
-//!
-//! This function reads 32-bit value from the register as specified by
-//! \e ulRegAddr.
-//!
-//! \return Return the value of the register.
-//
-//*****************************************************************************
-unsigned long PRCMHIBRegRead(unsigned long ulRegAddr)
-{
-  unsigned long ulValue;
-
-  //
-  // Read the Reg value
-  //
-  ulValue = HWREG(ulRegAddr);
-
-  //
-  // Wait for 200 uSec
-  //
-  UtilsDelay((80*200)/3);
-
-  //
-  // Return the value
-  //
-  return ulValue;
-}
-
-//*****************************************************************************
-//
-//! Writes 32-bit value to register at specified address
-//!
-//! \param ulRegAddr is the address of register to be read.
-//! \param ulValue is the 32-bit value to be written.
-//!
-//! This function writes 32-bit value passed as \e ulValue to the register as
-//! specified by \e ulRegAddr
-//!
-//! \return None
-//
-//*****************************************************************************
-void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue)
-{
-  //
-  // Read the Reg value
-  //
-  HWREG(ulRegAddr) = ulValue;
-
-  //
-  // Wait for 200 uSec
-  //
-  UtilsDelay((80*200)/3);
-}
-
-//*****************************************************************************
-//
-//! \param ulDivider is clock frequency divider value
-//! \param ulWidth is the width of the high pulse
-//!
-//! This function sets the input frequency for camera module.
-//!
-//! The frequency is calculated as follows:
-//!
-//!        f_out = 240MHz/ulDivider;
-//!
-//! The parameter \e ulWidth sets the width of the high pulse.
-//!
-//! For e.g.:
-//!
-//!     ulDivider = 4;
-//!     ulWidth   = 2;
-//!
-//!     f_out = 30 MHz and 50% duty cycle
-//!
-//! And,
-//!
-//!     ulDivider = 4;
-//!     ulWidth   = 1;
-//!
-//!     f_out = 30 MHz and 25% duty cycle
-//!
-//! \return 0 on success, 1 on error
-//
-//*****************************************************************************
-unsigned long PRCMCameraFreqSet(unsigned char ulDivider, unsigned char ulWidth)
-{
-    if(ulDivider > ulWidth && ulWidth != 0 )
-    {
-      //
-      // Set  the hifh pulse width
-      //
-      HWREG(ARCM_BASE +
-            APPS_RCM_O_CAMERA_CLK_GEN) = (((ulWidth & 0x07) -1) << 8);
-
-      //
-      // Set the low pulse width
-      //
-      HWREG(ARCM_BASE +
-            APPS_RCM_O_CAMERA_CLK_GEN) = ((ulDivider - ulWidth - 1) & 0x07);
-      //
-      // Return success
-      //
-      return 0;
-    }
-
-    //
-    // Success;
-    //
-    return 1;
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
diff --git a/cc3200/hal/prcm.h b/cc3200/hal/prcm.h
deleted file mode 100644
index 2f700ae2c..000000000
--- a/cc3200/hal/prcm.h
+++ /dev/null
@@ -1,285 +0,0 @@
-//*****************************************************************************
-//
-//  prcm.h
-//
-//  Prototypes for the PRCM control driver.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __PRCM_H__
-#define __PRCM_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Peripheral clock and reset control registers
-//
-//*****************************************************************************
-typedef struct _PRCM_PeripheralRegs_
-{
-
-unsigned char ulClkReg;
-unsigned char ulRstReg;
-
-}PRCM_PeriphRegs_t;
-
-//*****************************************************************************
-// Values that can be passed to PRCMPeripheralEnable() and
-// PRCMPeripheralDisable()
-//*****************************************************************************
-#define PRCM_RUN_MODE_CLK         0x00000001
-#define PRCM_SLP_MODE_CLK         0x00000100
-#define PRCM_DSLP_MODE_CLK        0x00010000
-
-//*****************************************************************************
-// Values that can be passed to PRCMSRAMRetentionEnable() and
-// PRCMSRAMRetentionDisable() as ulSramColSel.
-//*****************************************************************************
-#define PRCM_SRAM_COL_1           0x00000001
-#define PRCM_SRAM_COL_2           0x00000002
-#define PRCM_SRAM_COL_3           0x00000004
-#define PRCM_SRAM_COL_4           0x00000008
-
-//*****************************************************************************
-// Values that can be passed to PRCMSRAMRetentionEnable() and
-// PRCMSRAMRetentionDisable() as ulModeFlags.
-//*****************************************************************************
-#define PRCM_SRAM_DSLP_RET        0x00000001
-#define PRCM_SRAM_LPDS_RET        0x00000002
-
-//*****************************************************************************
-// Values that can be passed to PRCMLPDSWakeupSourceEnable(),
-// PRCMLPDSWakeupCauseGet() and PRCMLPDSWakeupSourceDisable().
-//*****************************************************************************
-#define PRCM_LPDS_HOST_IRQ        0x00000080
-#define PRCM_LPDS_GPIO            0x00000010
-#define PRCM_LPDS_TIMER           0x00000001
-
-//*****************************************************************************
-// Values that can be passed to PRCMLPDSWakeUpGPIOSelect() as Type
-//*****************************************************************************
-#define PRCM_LPDS_LOW_LEVEL       0x00000002
-#define PRCM_LPDS_HIGH_LEVEL      0x00000000
-#define PRCM_LPDS_FALL_EDGE       0x00000001
-#define PRCM_LPDS_RISE_EDGE       0x00000003
-
-//*****************************************************************************
-// Values that can be passed to PRCMLPDSWakeUpGPIOSelect()
-//*****************************************************************************
-#define PRCM_LPDS_GPIO2           0x00000000
-#define PRCM_LPDS_GPIO4           0x00000001
-#define PRCM_LPDS_GPIO13          0x00000002
-#define PRCM_LPDS_GPIO17          0x00000003
-#define PRCM_LPDS_GPIO11          0x00000004
-#define PRCM_LPDS_GPIO24          0x00000005
-#define PRCM_LPDS_GPIO26          0x00000006
-
-//*****************************************************************************
-// Values that can be passed to PRCMHibernateWakeupSourceEnable(),
-// PRCMHibernateWakeupSourceDisable().
-//*****************************************************************************
-#define PRCM_HIB_SLOW_CLK_CTR     0x00000001
-
-//*****************************************************************************
-// Values that can be passed to PRCMHibernateWakeUpGPIOSelect() as ulType
-//*****************************************************************************
-#define PRCM_HIB_LOW_LEVEL        0x00000000
-#define PRCM_HIB_HIGH_LEVEL       0x00000001
-#define PRCM_HIB_FALL_EDGE        0x00000002
-#define PRCM_HIB_RISE_EDGE        0x00000003
-
-//*****************************************************************************
-// Values that can be passed to PRCMHibernateWakeupSourceEnable(),
-// PRCMHibernateWakeupSourceDisable(), PRCMHibernateWakeUpGPIOSelect()
-//*****************************************************************************
-#define PRCM_HIB_GPIO2            0x00010000
-#define PRCM_HIB_GPIO4            0x00020000
-#define PRCM_HIB_GPIO13           0x00040000
-#define PRCM_HIB_GPIO17           0x00080000
-#define PRCM_HIB_GPIO11           0x00100000
-#define PRCM_HIB_GPIO24           0x00200000
-#define PRCM_HIB_GPIO26           0x00400000
-
-//*****************************************************************************
-// Values that will be returned from PRCMSysResetCauseGet().
-//*****************************************************************************
-#define PRCM_POWER_ON             0x00000000
-#define PRCM_LPDS_EXIT            0x00000001
-#define PRCM_CORE_RESET           0x00000003
-#define PRCM_MCU_RESET            0x00000004
-#define PRCM_WDT_RESET            0x00000005
-#define PRCM_SOC_RESET            0x00000006
-#define PRCM_HIB_EXIT             0x00000007
-
-//*****************************************************************************
-// Values that can be passed to PRCMHibernateWakeupCauseGet().
-//*****************************************************************************
-#define PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK  0x00000002
-#define PRCM_HIB_WAKEUP_CAUSE_GPIO        0x00000004
-
-//*****************************************************************************
-// Values that can be passed to PRCMIntEnable
-//*****************************************************************************
-#define PRCM_INT_SLOW_CLK_CTR     0x00004000
-
-//*****************************************************************************
-// Values that can be passed to PRCMPeripheralClkEnable(),
-// PRCMPeripheralClkDisable(), PRCMPeripheralReset()
-//*****************************************************************************
-#define PRCM_CAMERA               0x00000000
-#define PRCM_I2S                  0x00000001
-#define PRCM_SDHOST               0x00000002
-#define PRCM_GSPI                 0x00000003
-#define PRCM_LSPI                 0x00000004
-#define PRCM_UDMA                 0x00000005
-#define PRCM_GPIOA0               0x00000006
-#define PRCM_GPIOA1               0x00000007
-#define PRCM_GPIOA2               0x00000008
-#define PRCM_GPIOA3               0x00000009
-#define PRCM_GPIOA4               0x0000000A
-#define PRCM_WDT                  0x0000000B
-#define PRCM_UARTA0               0x0000000C
-#define PRCM_UARTA1               0x0000000D
-#define PRCM_TIMERA0              0x0000000E
-#define PRCM_TIMERA1              0x0000000F
-#define PRCM_TIMERA2              0x00000010
-#define PRCM_TIMERA3              0x00000011
-#define PRCM_DTHE                 0x00000012
-#define PRCM_SSPI                 0x00000013
-#define PRCM_I2CA0                0x00000014
-// Note : PRCM_ADC is a dummy define for pinmux utility code generation
-// PRCM_ADC should never be used in any user code. 
-#define PRCM_ADC                  0x000000FF 
-
-//*****************************************************************************
-// User bits in the PRCM persistent registers
-//*****************************************************************************
-#define PRCM_SAFE_BOOT_BIT              30
-#define PRCM_WDT_RESET_BIT              29
-#define PRCM_FIRST_BOOT_BIT             28
-
-//*****************************************************************************
-//
-// API Function prototypes
-//
-//*****************************************************************************
-extern void PRCMSetSpecialBit(unsigned char bit);
-extern void PRCMClearSpecialBit(unsigned char bit);
-extern tBoolean PRCMGetSpecialBit(unsigned char bit);
-extern void PRCMSOCReset(void);
-extern void PRCMMCUReset(tBoolean bIncludeSubsystem);
-extern unsigned long PRCMSysResetCauseGet(void);
-
-extern void PRCMPeripheralClkEnable(unsigned long ulPeripheral,
-                                    unsigned long ulClkFlags);
-extern void PRCMPeripheralClkDisable(unsigned long ulPeripheral,
-                                     unsigned long ulClkFlags);
-extern void PRCMPeripheralReset(unsigned long ulPeripheral);
-extern tBoolean PRCMPeripheralStatusGet(unsigned long ulPeripheral);
-
-extern void PRCMI2SClockFreqSet(unsigned long ulI2CClkFreq);
-extern unsigned long PRCMPeripheralClockGet(unsigned long ulPeripheral);
-
-extern void PRCMSleepEnter(void);
-extern void PRCMDeepSleepEnter(void);
-
-extern void PRCMSRAMRetentionEnable(unsigned long ulSramColSel,
-                                    unsigned long ulFlags);
-extern void PRCMSRAMRetentionDisable(unsigned long ulSramColSel,
-                                     unsigned long ulFlags);
-extern void PRCMLPDSRestoreInfoSet(unsigned long ulRestoreSP,
-                                   unsigned long ulRestorePC);
-extern void PRCMLPDSEnter(void);
-extern void PRCMLPDSIntervalSet(unsigned long ulTicks);
-extern void PRCMLPDSWakeupSourceEnable(unsigned long ulLpdsWakeupSrc);
-extern unsigned long PRCMLPDSWakeupCauseGet(void);
-extern void PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin,
-                                     unsigned long ulType);
-extern void PRCMLPDSWakeupSourceDisable(unsigned long ulLpdsWakeupSrc);
-
-extern void PRCMHibernateEnter(void);
-extern void PRCMHibernateWakeupSourceEnable(unsigned long ulHIBWakupSrc);
-extern unsigned long PRCMHibernateWakeupCauseGet(void);
-extern void PRCMHibernateWakeUpGPIOSelect(unsigned long ulMultiGPIOBitMap,
-                                          unsigned long ulType);
-extern void PRCMHibernateWakeupSourceDisable(unsigned long ulHIBWakupSrc);
-extern void PRCMHibernateIntervalSet(unsigned long long ullTicks);
-
-extern unsigned long long PRCMSlowClkCtrGet(void);
-extern unsigned long long PRCMSlowClkCtrFastGet(void);
-extern void PRCMSlowClkCtrMatchSet(unsigned long long ullTicks);
-extern unsigned long long PRCMSlowClkCtrMatchGet(void);
-
-extern void PRCMOCRRegisterWrite(unsigned char ucIndex,
-                                 unsigned long ulRegValue);
-extern unsigned long PRCMOCRRegisterRead(unsigned char ucIndex);
-
-extern void PRCMIntRegister(void (*pfnHandler)(void));
-extern void PRCMIntUnregister(void);
-extern void PRCMIntEnable(unsigned long ulIntFlags);
-extern void PRCMIntDisable(unsigned long ulIntFlags);
-extern unsigned long PRCMIntStatus(void);
-extern void PRCMRTCInUseSet(void);
-extern void PRCMRTCInUseClear(void);
-extern tBoolean PRCMRTCInUseGet(void);
-extern void PRCMRTCSet(unsigned long ulSecs, unsigned short usMsec);
-extern void PRCMRTCGet(unsigned long *ulSecs, unsigned short *usMsec);
-extern void PRCMRTCMatchSet(unsigned long ulSecs, unsigned short usMsec);
-extern void PRCMRTCMatchGet(unsigned long *ulSecs, unsigned short *usMsec);
-extern void PRCMCC3200MCUInit(void);
-extern unsigned long PRCMHIBRegRead(unsigned long ulRegAddr);
-extern void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue);
-extern unsigned long PRCMCameraFreqSet(unsigned char ulDivider, unsigned char ulWidth);
-
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif //  __PRCM_H__
diff --git a/cc3200/hal/rom.h b/cc3200/hal/rom.h
deleted file mode 100644
index 33a18b68f..000000000
--- a/cc3200/hal/rom.h
+++ /dev/null
@@ -1,2237 +0,0 @@
-//*****************************************************************************
-//
-//  rom.h
-//
-//  Macros to facilitate calling functions in the ROM.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-// THIS IS AN AUTO-GENERATED FILE.  DO NOT EDIT BY HAND.
-//
-//*****************************************************************************
-
-#ifndef __ROM_H__
-#define __ROM_H__
-
-//*****************************************************************************
-//
-// Pointers to the main API tables.
-//
-//*****************************************************************************
-#define ROM_APITABLE            ((unsigned long *)0x0000040C)
-#define ROM_VERSION             (ROM_APITABLE[0])
-#define ROM_UARTTABLE           ((unsigned long *)(ROM_APITABLE[1]))
-#define ROM_TIMERTABLE          ((unsigned long *)(ROM_APITABLE[2]))
-#define ROM_WATCHDOGTABLE       ((unsigned long *)(ROM_APITABLE[3]))
-#define ROM_INTERRUPTTABLE      ((unsigned long *)(ROM_APITABLE[4]))
-#define ROM_UDMATABLE           ((unsigned long *)(ROM_APITABLE[5]))
-#define ROM_PRCMTABLE           ((unsigned long *)(ROM_APITABLE[6]))
-#define ROM_I2CTABLE            ((unsigned long *)(ROM_APITABLE[7]))
-#define ROM_SPITABLE            ((unsigned long *)(ROM_APITABLE[8]))
-#define ROM_CAMERATABLE         ((unsigned long *)(ROM_APITABLE[9]))
-#define ROM_FLASHTABLE          ((unsigned long *)(ROM_APITABLE[10]))
-#define ROM_PINTABLE            ((unsigned long *)(ROM_APITABLE[11]))
-#define ROM_SYSTICKTABLE        ((unsigned long *)(ROM_APITABLE[12]))
-#define ROM_UTILSTABLE          ((unsigned long *)(ROM_APITABLE[13]))
-#define ROM_I2STABLE            ((unsigned long *)(ROM_APITABLE[14]))
-#define ROM_HWSPINLOCKTABLE     ((unsigned long *)(ROM_APITABLE[15]))
-#define ROM_GPIOTABLE           ((unsigned long *)(ROM_APITABLE[16]))
-#define ROM_AESTABLE            ((unsigned long *)(ROM_APITABLE[17]))
-#define ROM_DESTABLE            ((unsigned long *)(ROM_APITABLE[18]))
-#define ROM_SHAMD5TABLE         ((unsigned long *)(ROM_APITABLE[19]))
-#define ROM_CRCTABLE            ((unsigned long *)(ROM_APITABLE[20]))
-#define ROM_SDHOSTTABLE         ((unsigned long *)(ROM_APITABLE[21]))
-#define ROM_ADCTABLE            ((unsigned long *)(ROM_APITABLE[22]))
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the Interrupt API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_IntEnable                                                         \
-        ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_IntMasterEnable                                                   \
-        ((tBoolean (*)(void))ROM_INTERRUPTTABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_IntMasterDisable                                                  \
-        ((tBoolean (*)(void))ROM_INTERRUPTTABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_IntDisable                                                        \
-        ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_IntPriorityGroupingSet                                            \
-        ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_IntPriorityGroupingGet                                            \
-        ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_IntPrioritySet                                                    \
-        ((void (*)(unsigned long ulInterrupt,                                 \
-                   unsigned char ucPriority))ROM_INTERRUPTTABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_IntPriorityGet                                                    \
-        ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_IntPendSet                                                        \
-        ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_IntPendClear                                                      \
-        ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[9])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_IntPriorityMaskSet                                                \
-        ((void (*)(unsigned long ulPriorityMask))ROM_INTERRUPTTABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_IntPriorityMaskGet                                                \
-        ((unsigned long (*)(void))ROM_INTERRUPTTABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_IntRegister                                                       \
-        ((void (*)(unsigned long ulInterrupt,                                 \
-                   void (*pfnHandler)(void)))ROM_INTERRUPTTABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_IntUnregister                                                     \
-        ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[13])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_IntVTableBaseSet                                                  \
-        ((void (*)(unsigned long ulVtableBase))ROM_INTERRUPTTABLE[14])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the Timer API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerEnable                                                       \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer))ROM_TIMERTABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerDisable                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer))ROM_TIMERTABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerConfigure                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulConfig))ROM_TIMERTABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerControlLevel                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer,                                     \
-                   tBoolean bInvert))ROM_TIMERTABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerControlEvent                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer,                                     \
-                   unsigned long ulEvent))ROM_TIMERTABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerControlStall                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer,                                     \
-                   tBoolean bStall))ROM_TIMERTABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerPrescaleSet                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer,                                     \
-                   unsigned long ulValue))ROM_TIMERTABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerPrescaleGet                                                  \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulTimer))ROM_TIMERTABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerPrescaleMatchSet                                             \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer,                                     \
-                   unsigned long ulValue))ROM_TIMERTABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerPrescaleMatchGet                                             \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulTimer))ROM_TIMERTABLE[9])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerLoadSet                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer,                                     \
-                   unsigned long ulValue))ROM_TIMERTABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerLoadGet                                                      \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulTimer))ROM_TIMERTABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerValueGet                                                     \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulTimer))ROM_TIMERTABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerMatchSet                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer,                                     \
-                   unsigned long ulValue))ROM_TIMERTABLE[13])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerMatchGet                                                     \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulTimer))ROM_TIMERTABLE[14])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerIntRegister                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer,                                     \
-                   void (*pfnHandler)(void)))ROM_TIMERTABLE[15])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerIntUnregister                                                \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer))ROM_TIMERTABLE[16])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerIntEnable                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_TIMERTABLE[17])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerIntDisable                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_TIMERTABLE[18])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerIntStatus                                                    \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            tBoolean bMasked))ROM_TIMERTABLE[19])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_TimerIntClear                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_TIMERTABLE[20])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the UART API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTParityModeSet                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulParity))ROM_UARTTABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTParityModeGet                                                 \
-        ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTFIFOLevelSet                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTxLevel,                                   \
-                   unsigned long ulRxLevel))ROM_UARTTABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTFIFOLevelGet                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long *pulTxLevel,                                 \
-                   unsigned long *pulRxLevel))ROM_UARTTABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTConfigSetExpClk                                               \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulUARTClk,                                   \
-                   unsigned long ulBaud,                                      \
-                   unsigned long ulConfig))ROM_UARTTABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTConfigGetExpClk                                               \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulUARTClk,                                   \
-                   unsigned long *pulBaud,                                    \
-                   unsigned long *pulConfig))ROM_UARTTABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTEnable                                                        \
-        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTDisable                                                       \
-        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTFIFOEnable                                                    \
-        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTFIFODisable                                                   \
-        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[9])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTCharsAvail                                                    \
-        ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTSpaceAvail                                                    \
-        ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTCharGetNonBlocking                                            \
-        ((long (*)(unsigned long ulBase))ROM_UARTTABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTCharGet                                                       \
-        ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTCharPutNonBlocking                                            \
-        ((tBoolean (*)(unsigned long ulBase,                                  \
-                       unsigned char ucData))ROM_UARTTABLE[14])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTCharPut                                                       \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned char ucData))ROM_UARTTABLE[15])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTBreakCtl                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   tBoolean bBreakState))ROM_UARTTABLE[16])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTBusy                                                          \
-        ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[17])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTIntRegister                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   void(*pfnHandler)(void)))ROM_UARTTABLE[18])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTIntUnregister                                                 \
-        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[19])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTIntEnable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_UARTTABLE[20])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTIntDisable                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_UARTTABLE[21])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTIntStatus                                                     \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            tBoolean bMasked))ROM_UARTTABLE[22])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTIntClear                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_UARTTABLE[23])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTDMAEnable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulDMAFlags))ROM_UARTTABLE[24])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTDMADisable                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulDMAFlags))ROM_UARTTABLE[25])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTRxErrorGet                                                    \
-        ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[26])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTRxErrorClear                                                  \
-        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[27])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTModemControlSet                                               \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulControl))ROM_UARTTABLE[28])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTModemControlClear                                             \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulControl))ROM_UARTTABLE[29])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTModemControlGet                                               \
-        ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[30])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTModemStatusGet                                                \
-        ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[31])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTFlowControlSet                                                \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulMode))ROM_UARTTABLE[32])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTFlowControlGet                                                \
-        ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[33])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTTxIntModeSet                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulMode))ROM_UARTTABLE[34])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_UARTTxIntModeGet                                                  \
-        ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[35])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the uDMA API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAChannelTransferSet                                            \
-        ((void (*)(unsigned long ulChannelStructIndex,                        \
-                   unsigned long ulMode,                                      \
-                   void *pvSrcAddr,                                           \
-                   void *pvDstAddr,                                           \
-                   unsigned long ulTransferSize))ROM_UDMATABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAEnable                                                        \
-        ((void (*)(void))ROM_UDMATABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMADisable                                                       \
-        ((void (*)(void))ROM_UDMATABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAErrorStatusGet                                                \
-        ((unsigned long (*)(void))ROM_UDMATABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAErrorStatusClear                                              \
-        ((void (*)(void))ROM_UDMATABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAChannelEnable                                                 \
-        ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAChannelDisable                                                \
-        ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAChannelIsEnabled                                              \
-        ((tBoolean (*)(unsigned long ulChannelNum))ROM_UDMATABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAControlBaseSet                                                \
-        ((void (*)(void *pControlTable))ROM_UDMATABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAControlBaseGet                                                \
-        ((void * (*)(void))ROM_UDMATABLE[9])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAChannelRequest                                                \
-        ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAChannelAttributeEnable                                        \
-        ((void (*)(unsigned long ulChannelNum,                                \
-                   unsigned long ulAttr))ROM_UDMATABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAChannelAttributeDisable                                       \
-        ((void (*)(unsigned long ulChannelNum,                                \
-                   unsigned long ulAttr))ROM_UDMATABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAChannelAttributeGet                                           \
-        ((unsigned long (*)(unsigned long ulChannelNum))ROM_UDMATABLE[13])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAChannelControlSet                                             \
-        ((void (*)(unsigned long ulChannelStructIndex,                        \
-                   unsigned long ulControl))ROM_UDMATABLE[14])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAChannelSizeGet                                                \
-        ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[15])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAChannelModeGet                                                \
-        ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[16])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAIntStatus                                                     \
-        ((unsigned long (*)(void))ROM_UDMATABLE[17])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAIntClear                                                      \
-        ((void (*)(unsigned long ulChanMask))ROM_UDMATABLE[18])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAControlAlternateBaseGet                                       \
-        ((void * (*)(void))ROM_UDMATABLE[19])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAChannelScatterGatherSet                                       \
-        ((void (*)(unsigned long ulChannelNum,                                \
-                   unsigned ulTaskCount,                                      \
-                   void *pvTaskList,                                          \
-                   unsigned long ulIsPeriphSG))ROM_UDMATABLE[20])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAChannelAssign                                                 \
-        ((void (*)(unsigned long ulMapping))ROM_UDMATABLE[21])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAIntRegister                                                   \
-        ((void (*)(unsigned long ulIntChannel,                                \
-                   void (*pfnHandler)(void)))ROM_UDMATABLE[22])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_uDMAIntUnregister                                                 \
-        ((void (*)(unsigned long ulIntChannel))ROM_UDMATABLE[23])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the Watchdog API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_WatchdogIntClear                                                  \
-        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_WatchdogRunning                                                   \
-        ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_WatchdogEnable                                                    \
-        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_WatchdogLock                                                      \
-        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_WatchdogUnlock                                                    \
-        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_WatchdogLockState                                                 \
-        ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_WatchdogReloadSet                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulLoadVal))ROM_WATCHDOGTABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_WatchdogReloadGet                                                 \
-        ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_WatchdogValueGet                                                  \
-        ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_WatchdogIntStatus                                                 \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            tBoolean bMasked))ROM_WATCHDOGTABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_WatchdogStallEnable                                               \
-        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_WatchdogStallDisable                                              \
-        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_WatchdogIntRegister                                               \
-        ((void (*)(unsigned long ulBase,                                      \
-                   void(*pfnHandler)(void)))ROM_WATCHDOGTABLE[13])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_WatchdogIntUnregister                                             \
-        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the I2C API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CIntRegister                                                    \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   void(pfnHandler)(void)))ROM_I2CTABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CIntUnregister                                                  \
-        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CTxFIFOConfigSet                                                \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Config))ROM_I2CTABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CTxFIFOFlush                                                    \
-        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CRxFIFOConfigSet                                                \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Config))ROM_I2CTABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CRxFIFOFlush                                                    \
-        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CFIFOStatus                                                     \
-        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CFIFODataPut                                                    \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t ui8Data))ROM_I2CTABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CFIFODataPutNonBlocking                                         \
-        ((uint32_t (*)(uint32_t ui32Base,                                     \
-                       uint8_t ui8Data))ROM_I2CTABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CFIFODataGet                                                    \
-        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[9])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CFIFODataGetNonBlocking                                         \
-        ((uint32_t (*)(uint32_t ui32Base,                                     \
-                       uint8_t *pui8Data))ROM_I2CTABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterBurstLengthSet                                           \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t ui8Length))ROM_I2CTABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterBurstCountGet                                            \
-        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterGlitchFilterConfigSet                                    \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Config))ROM_I2CTABLE[13])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveFIFOEnable                                                \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Config))ROM_I2CTABLE[14])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveFIFODisable                                               \
-        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[15])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterBusBusy                                                  \
-        ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[16])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterBusy                                                     \
-        ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[17])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterControl                                                  \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Cmd))ROM_I2CTABLE[18])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterDataGet                                                  \
-        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[19])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterDataPut                                                  \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t ui8Data))ROM_I2CTABLE[20])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterDisable                                                  \
-        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[21])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterEnable                                                   \
-        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[22])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterErr                                                      \
-        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[23])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterIntClear                                                 \
-        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[24])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterIntDisable                                               \
-        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[25])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterIntEnable                                                \
-        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[26])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterIntStatus                                                \
-        ((bool (*)(uint32_t ui32Base,                                         \
-                   bool bMasked))ROM_I2CTABLE[27])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterIntEnableEx                                              \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32IntFlags))ROM_I2CTABLE[28])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterIntDisableEx                                             \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32IntFlags))ROM_I2CTABLE[29])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterIntStatusEx                                              \
-        ((uint32_t (*)(uint32_t ui32Base,                                     \
-                       bool bMasked))ROM_I2CTABLE[30])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterIntClearEx                                               \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32IntFlags))ROM_I2CTABLE[31])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterTimeoutSet                                               \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Value))ROM_I2CTABLE[32])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveACKOverride                                               \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   bool bEnable))ROM_I2CTABLE[33])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveACKValueSet                                               \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   bool bACK))ROM_I2CTABLE[34])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterLineStateGet                                             \
-        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[35])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterSlaveAddrSet                                             \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t ui8SlaveAddr,                                      \
-                   bool bReceive))ROM_I2CTABLE[36])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveDataGet                                                   \
-        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[37])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveDataPut                                                   \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t ui8Data))ROM_I2CTABLE[38])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveDisable                                                   \
-        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[39])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveEnable                                                    \
-        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[40])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveInit                                                      \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t ui8SlaveAddr))ROM_I2CTABLE[41])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveAddressSet                                                \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t ui8AddrNum,                                        \
-                   uint8_t ui8SlaveAddr))ROM_I2CTABLE[42])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveIntClear                                                  \
-        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[43])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveIntDisable                                                \
-        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[44])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveIntEnable                                                 \
-        ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[45])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveIntClearEx                                                \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32IntFlags))ROM_I2CTABLE[46])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveIntDisableEx                                              \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32IntFlags))ROM_I2CTABLE[47])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveIntEnableEx                                               \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32IntFlags))ROM_I2CTABLE[48])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveIntStatus                                                 \
-        ((bool (*)(uint32_t ui32Base,                                         \
-                   bool bMasked))ROM_I2CTABLE[49])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveIntStatusEx                                               \
-        ((uint32_t (*)(uint32_t ui32Base,                                     \
-                       bool bMasked))ROM_I2CTABLE[50])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CSlaveStatus                                                    \
-        ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[51])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2CMasterInitExpClk                                               \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32I2CClk,                                       \
-                   bool bFast))ROM_I2CTABLE[52])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the SPI API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIEnable                                                         \
-        ((void (*)(unsigned long ulBase))ROM_SPITABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIDisable                                                        \
-        ((void (*)(unsigned long ulBase))ROM_SPITABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIReset                                                          \
-        ((void (*)(unsigned long ulBase))ROM_SPITABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIConfigSetExpClk                                                \
-        ((void (*)(unsigned long ulBase,                                      \
-                  unsigned long ulSPIClk,                                     \
-                   unsigned long ulBitRate,                                   \
-                   unsigned long ulMode,                                      \
-                   unsigned long ulSubMode,                                   \
-                   unsigned long ulConfig))ROM_SPITABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIDataGetNonBlocking                                             \
-        ((long (*)(unsigned long ulBase,                                      \
-                   unsigned long * pulData))ROM_SPITABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIDataGet                                                        \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long *pulData))ROM_SPITABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIDataPutNonBlocking                                             \
-        ((long (*)(unsigned long ulBase,                                      \
-                   unsigned long ulData))ROM_SPITABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIDataPut                                                        \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulData))ROM_SPITABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIFIFOEnable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulFlags))ROM_SPITABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIFIFODisable                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulFlags))ROM_SPITABLE[9])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIFIFOLevelSet                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTxLevel,                                   \
-                   unsigned long ulRxLevel))ROM_SPITABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIFIFOLevelGet                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long *pulTxLevel,                                 \
-                   unsigned long *pulRxLevel))ROM_SPITABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIWordCountSet                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulWordCount))ROM_SPITABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIIntRegister                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   void(*pfnHandler)(void)))ROM_SPITABLE[13])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIIntUnregister                                                  \
-        ((void (*)(unsigned long ulBase))ROM_SPITABLE[14])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIIntEnable                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_SPITABLE[15])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIIntDisable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_SPITABLE[16])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIIntStatus                                                      \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            tBoolean bMasked))ROM_SPITABLE[17])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIIntClear                                                       \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_SPITABLE[18])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIDmaEnable                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulFlags))ROM_SPITABLE[19])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPIDmaDisable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulFlags))ROM_SPITABLE[20])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPICSEnable                                                       \
-        ((void (*)(unsigned long ulBase))ROM_SPITABLE[21])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPICSDisable                                                      \
-        ((void (*)(unsigned long ulBase))ROM_SPITABLE[22])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SPITransfer                                                       \
-        ((long (*)(unsigned long ulBase,                                      \
-                   unsigned char *ucDout,                                     \
-                   unsigned char *ucDin,                                      \
-                   unsigned long ulSize,                                      \
-                   unsigned long ulFlags))ROM_SPITABLE[23])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the CAM API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_CameraReset                                                       \
-        ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CameraParamsConfig                                                \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulHSPol,                                     \
-                   unsigned long ulVSPol,                                     \
-                   unsigned long ulFlags))ROM_CAMERATABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CameraXClkConfig                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulCamClkIn,                                  \
-                   unsigned long ulXClk))ROM_CAMERATABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CameraXClkSet                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned char bXClkFlags))ROM_CAMERATABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CameraDMAEnable                                                   \
-        ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CameraDMADisable                                                  \
-        ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CameraThresholdSet                                                \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulThreshold))ROM_CAMERATABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CameraIntRegister                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   void (*pfnHandler)(void)))ROM_CAMERATABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CameraIntUnregister                                               \
-        ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CameraIntEnable                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_CAMERATABLE[9])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CameraIntDisable                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_CAMERATABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CameraIntStatus                                                   \
-        ((unsigned long (*)(unsigned long ulBase))ROM_CAMERATABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CameraIntClear                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_CAMERATABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CameraCaptureStop                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   tBoolean bImmediate))ROM_CAMERATABLE[13])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CameraCaptureStart                                                \
-        ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[14])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CameraBufferRead                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                  unsigned long *pBuffer,                                     \
-                   unsigned char ucSize))ROM_CAMERATABLE[15])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the FLASH API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_FlashDisable                                                      \
-        ((void (*)(void))ROM_FLASHTABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_FlashErase                                                        \
-        ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_FlashMassErase                                                    \
-        ((long (*)(void))ROM_FLASHTABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_FlashMassEraseNonBlocking                                         \
-        ((void (*)(void))ROM_FLASHTABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_FlashEraseNonBlocking                                             \
-        ((void (*)(unsigned long ulAddress))ROM_FLASHTABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_FlashProgram                                                      \
-        ((long (*)(unsigned long *pulData,                                    \
-                   unsigned long ulAddress,                                   \
-                   unsigned long ulCount))ROM_FLASHTABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_FlashProgramNonBlocking                                           \
-        ((long (*)(unsigned long *pulData,                                    \
-                   unsigned long ulAddress,                                   \
-                   unsigned long ulCount))ROM_FLASHTABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_FlashIntRegister                                                  \
-        ((void (*)(void (*pfnHandler)(void)))ROM_FLASHTABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_FlashIntUnregister                                                \
-        ((void (*)(void))ROM_FLASHTABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_FlashIntEnable                                                    \
-        ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[9])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_FlashIntDisable                                                   \
-        ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_FlashIntStatus                                                    \
-        ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_FlashIntClear                                                     \
-        ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_FlashProtectGet                                                   \
-        ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[13])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the Pin API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_PinModeSet                                                        \
-        ((void (*)(unsigned long ulPin,                                       \
-                   unsigned long ulPinMode))ROM_PINTABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PinDirModeSet                                                     \
-        ((void (*)(unsigned long ulPin,                                       \
-                   unsigned long ulPinIO))ROM_PINTABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PinDirModeGet                                                     \
-        ((unsigned long (*)(unsigned long ulPin))ROM_PINTABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PinModeGet                                                        \
-        ((unsigned long (*)(unsigned long ulPin))ROM_PINTABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PinConfigGet                                                      \
-        ((void (*)(unsigned long ulPin,                                       \
-                  unsigned long  *pulPinStrength,                             \
-                   unsigned long *pulPinType))ROM_PINTABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PinConfigSet                                                      \
-        ((void (*)(unsigned long ulPin,                                       \
-                  unsigned long  ulPinStrength,                               \
-                   unsigned long ulPinType))ROM_PINTABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PinTypeUART                                                       \
-        ((void (*)(unsigned long ulPin,                                       \
-                  unsigned long ulPinMode))ROM_PINTABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PinTypeI2C                                                        \
-        ((void (*)(unsigned long ulPin,                                       \
-                  unsigned long ulPinMode))ROM_PINTABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PinTypeSPI                                                        \
-        ((void (*)(unsigned long ulPin,                                       \
-                  unsigned long ulPinMode))ROM_PINTABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PinTypeI2S                                                        \
-        ((void (*)(unsigned long ulPin,                                       \
-                  unsigned long ulPinMode))ROM_PINTABLE[9])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PinTypeTimer                                                      \
-        ((void (*)(unsigned long ulPin,                                       \
-                  unsigned long ulPinMode))ROM_PINTABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PinTypeCamera                                                     \
-        ((void (*)(unsigned long ulPin,                                       \
-                  unsigned long ulPinMode))ROM_PINTABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PinTypeGPIO                                                       \
-        ((void (*)(unsigned long ulPin,                                       \
-                  unsigned long ulPinMode,                                    \
-                   tBoolean bOpenDrain))ROM_PINTABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PinTypeADC                                                        \
-        ((void (*)(unsigned long ulPin,                                       \
-                  unsigned long ulPinMode))ROM_PINTABLE[13])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PinTypeSDHost                                                     \
-        ((void (*)(unsigned long ulPin,                                       \
-                  unsigned long ulPinMode))ROM_PINTABLE[14])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the SYSTICK API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_SysTickEnable                                                     \
-        ((void (*)(void))ROM_SYSTICKTABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SysTickDisable                                                    \
-        ((void (*)(void))ROM_SYSTICKTABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SysTickIntRegister                                                \
-        ((void (*)(void (*pfnHandler)(void)))ROM_SYSTICKTABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SysTickIntUnregister                                              \
-        ((void (*)(void))ROM_SYSTICKTABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SysTickIntEnable                                                  \
-        ((void (*)(void))ROM_SYSTICKTABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SysTickIntDisable                                                 \
-        ((void (*)(void))ROM_SYSTICKTABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SysTickPeriodSet                                                  \
-        ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SysTickPeriodGet                                                  \
-        ((unsigned long (*)(void))ROM_SYSTICKTABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SysTickValueGet                                                   \
-        ((unsigned long (*)(void))ROM_SYSTICKTABLE[8])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the UTILS API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_UtilsDelay                                                        \
-        ((void (*)(unsigned long ulCount))ROM_UTILSTABLE[0])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the I2S API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2SEnable                                                         \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulMode))ROM_I2STABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2SDisable                                                        \
-        ((void (*)(unsigned long ulBase))ROM_I2STABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2SDataPut                                                        \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulDataLine,                                  \
-                   unsigned long ulData))ROM_I2STABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2SDataPutNonBlocking                                             \
-        ((long (*)(unsigned long ulBase,                                      \
-                   unsigned long ulDataLine,                                  \
-                   unsigned long ulData))ROM_I2STABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2SDataGet                                                        \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulDataLine,                                  \
-                   unsigned long *pulData))ROM_I2STABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2SDataGetNonBlocking                                             \
-        ((long (*)(unsigned long ulBase,                                      \
-                   unsigned long ulDataLine,                                  \
-                   unsigned long *pulData))ROM_I2STABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2SConfigSetExpClk                                                \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulI2SClk,                                    \
-                   unsigned long ulBitClk,                                    \
-                   unsigned long ulConfig))ROM_I2STABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2STxFIFOEnable                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTxLevel,                                   \
-                   unsigned long ulWordsPerTransfer))ROM_I2STABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2STxFIFODisable                                                  \
-        ((void (*)(unsigned long ulBase))ROM_I2STABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2SRxFIFOEnable                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulRxLevel,                                   \
-                   unsigned long ulWordsPerTransfer))ROM_I2STABLE[9])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2SRxFIFODisable                                                  \
-        ((void (*)(unsigned long ulBase))ROM_I2STABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2STxFIFOStatusGet                                                \
-        ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2SRxFIFOStatusGet                                                \
-        ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2SSerializerConfig                                               \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulDataLine,                                  \
-                   unsigned long ulSerMode,                                   \
-                   unsigned long ulInActState))ROM_I2STABLE[13])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2SIntEnable                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_I2STABLE[14])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2SIntDisable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_I2STABLE[15])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2SIntStatus                                                      \
-        ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[16])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2SIntClear                                                       \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_I2STABLE[17])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2SIntRegister                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   void (*pfnHandler)(void)))ROM_I2STABLE[18])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_I2SIntUnregister                                                  \
-        ((void (*)(unsigned long ulBase))ROM_I2STABLE[19])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the GPIO API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_GPIODirModeSet                                                    \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins,                                      \
-                   unsigned long ulPinIO))ROM_GPIOTABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_GPIODirModeGet                                                    \
-        ((unsigned long (*)(unsigned long ulPort,                             \
-                            unsigned char ucPin))ROM_GPIOTABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_GPIOIntTypeSet                                                    \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins,                                      \
-                   unsigned long ulIntType))ROM_GPIOTABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_GPIODMATriggerEnable                                              \
-        ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_GPIODMATriggerDisable                                             \
-        ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_GPIOIntTypeGet                                                    \
-        ((unsigned long (*)(unsigned long ulPort,                             \
-                            unsigned char ucPin))ROM_GPIOTABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_GPIOIntEnable                                                     \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned long ulIntFlags))ROM_GPIOTABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_GPIOIntDisable                                                    \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned long ulIntFlags))ROM_GPIOTABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_GPIOIntStatus                                                     \
-        ((long (*)(unsigned long ulPort,                                      \
-                   tBoolean bMasked))ROM_GPIOTABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_GPIOIntClear                                                      \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned long ulIntFlags))ROM_GPIOTABLE[9])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_GPIOIntRegister                                                   \
-        ((void (*)(unsigned long ulPort,                                      \
-                   void (*pfnIntHandler)(void)))ROM_GPIOTABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_GPIOIntUnregister                                                 \
-        ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_GPIOPinRead                                                       \
-        ((long (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_GPIOPinWrite                                                      \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins,                                      \
-                   unsigned char ucVal))ROM_GPIOTABLE[13])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the AES API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESConfigSet                                                      \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Config))ROM_AESTABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESKey1Set                                                        \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Key,                                          \
-                   uint32_t ui32Keysize))ROM_AESTABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESKey2Set                                                        \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Key,                                          \
-                   uint32_t ui32Keysize))ROM_AESTABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESKey3Set                                                        \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Key))ROM_AESTABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESIVSet                                                          \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8IVdata))ROM_AESTABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESTagRead                                                        \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8TagData))ROM_AESTABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESDataLengthSet                                                  \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint64_t ui64Length))ROM_AESTABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESAuthDataLengthSet                                              \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Length))ROM_AESTABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESDataReadNonBlocking                                            \
-        ((bool (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Dest,                                         \
-                   uint8_t ui8Length))ROM_AESTABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESDataRead                                                       \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Dest,                                         \
-                   uint8_t ui8Length))ROM_AESTABLE[9])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESDataWriteNonBlocking                                           \
-        ((bool (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Src,                                          \
-                   uint8_t ui8Length))ROM_AESTABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESDataWrite                                                      \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Src,                                          \
-                   uint8_t ui8Length))ROM_AESTABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESDataProcess                                                    \
-        ((bool (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Src,                                          \
-                   uint8_t *pui8Dest,                                         \
-                   uint32_t ui32Length))ROM_AESTABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESDataMAC                                                        \
-        ((bool (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Src,                                          \
-                   uint32_t ui32Length,                                       \
-                   uint8_t *pui8Tag))ROM_AESTABLE[13])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESDataProcessAE                                                  \
-        ((bool (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Src,                                          \
-                   uint8_t *pui8Dest,                                         \
-                   uint32_t ui32Length,                                       \
-                   uint8_t *pui8AuthSrc,                                      \
-                   uint32_t ui32AuthLength,                                   \
-                   uint8_t *pui8Tag))ROM_AESTABLE[14])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESIntStatus                                                      \
-        ((uint32_t (*)(uint32_t ui32Base,                                     \
-                       bool bMasked))ROM_AESTABLE[15])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESIntEnable                                                      \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32IntFlags))ROM_AESTABLE[16])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESIntDisable                                                     \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32IntFlags))ROM_AESTABLE[17])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESIntClear                                                       \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32IntFlags))ROM_AESTABLE[18])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESIntRegister                                                    \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   void(*pfnHandler)(void)))ROM_AESTABLE[19])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESIntUnregister                                                  \
-        ((void (*)(uint32_t ui32Base))ROM_AESTABLE[20])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESDMAEnable                                                      \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Flags))ROM_AESTABLE[21])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_AESDMADisable                                                     \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Flags))ROM_AESTABLE[22])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the DES API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_DESConfigSet                                                      \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Config))ROM_DESTABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_DESDataRead                                                       \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Dest,                                         \
-                   uint8_t ui8Length))ROM_DESTABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_DESDataReadNonBlocking                                            \
-        ((bool (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Dest,                                         \
-                   uint8_t ui8Length))ROM_DESTABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_DESDataProcess                                                    \
-        ((bool (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Src,                                          \
-                   uint8_t *pui8Dest,                                         \
-                   uint32_t ui32Length))ROM_DESTABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_DESDataWrite                                                      \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Src,                                          \
-                   uint8_t ui8Length))ROM_DESTABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_DESDataWriteNonBlocking                                           \
-        ((bool (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Src,                                          \
-                   uint8_t ui8Length))ROM_DESTABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_DESDMADisable                                                     \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Flags))ROM_DESTABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_DESDMAEnable                                                      \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Flags))ROM_DESTABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_DESIntClear                                                       \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32IntFlags))ROM_DESTABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_DESIntDisable                                                     \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32IntFlags))ROM_DESTABLE[9])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_DESIntEnable                                                      \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32IntFlags))ROM_DESTABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_DESIntRegister                                                    \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   void(*pfnHandler)(void)))ROM_DESTABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_DESIntStatus                                                      \
-        ((uint32_t (*)(uint32_t ui32Base,                                     \
-                       bool bMasked))ROM_DESTABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_DESIntUnregister                                                  \
-        ((void (*)(uint32_t ui32Base))ROM_DESTABLE[13])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_DESIVSet                                                          \
-        ((bool (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8IVdata))ROM_DESTABLE[14])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_DESKeySet                                                         \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Key))ROM_DESTABLE[15])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_DESDataLengthSet                                                  \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Length))ROM_DESTABLE[16])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the SHAMD5 API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5ConfigSet                                                   \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Mode))ROM_SHAMD5TABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5DataProcess                                                 \
-        ((bool (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8DataSrc,                                      \
-                   uint32_t ui32DataLength,                                   \
-                   uint8_t *pui8HashResult))ROM_SHAMD5TABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5DataWrite                                                   \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Src))ROM_SHAMD5TABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5DataWriteNonBlocking                                        \
-        ((bool (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Src))ROM_SHAMD5TABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5DMADisable                                                  \
-        ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5DMAEnable                                                   \
-        ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5DataLengthSet                                               \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Length))ROM_SHAMD5TABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5HMACKeySet                                                  \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Src))ROM_SHAMD5TABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5HMACPPKeyGenerate                                           \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Key,                                          \
-                   uint8_t *pui8PPKey))ROM_SHAMD5TABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5HMACPPKeySet                                                \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Src))ROM_SHAMD5TABLE[9])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5HMACProcess                                                 \
-        ((bool (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8DataSrc,                                      \
-                   uint32_t ui32DataLength,                                   \
-                   uint8_t *pui8HashResult))ROM_SHAMD5TABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5IntClear                                                    \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32IntFlags))ROM_SHAMD5TABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5IntDisable                                                  \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32IntFlags))ROM_SHAMD5TABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5IntEnable                                                   \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32IntFlags))ROM_SHAMD5TABLE[13])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5IntRegister                                                 \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   void(*pfnHandler)(void)))ROM_SHAMD5TABLE[14])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5IntStatus                                                   \
-        ((uint32_t (*)(uint32_t ui32Base,                                     \
-                       bool bMasked))ROM_SHAMD5TABLE[15])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5IntUnregister                                               \
-        ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[16])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SHAMD5ResultRead                                                  \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint8_t *pui8Dest))ROM_SHAMD5TABLE[17])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the CRC API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_CRCConfigSet                                                      \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32CRCConfig))ROM_CRCTABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CRCDataProcess                                                    \
-        ((uint32_t (*)(uint32_t ui32Base,                                     \
-                       void *puiDataIn,                                       \
-                       uint32_t ui32DataLength,                               \
-                       uint32_t ui32Config))ROM_CRCTABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CRCDataWrite                                                      \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Data))ROM_CRCTABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CRCResultRead                                                     \
-        ((uint32_t (*)(uint32_t ui32Base))ROM_CRCTABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_CRCSeedSet                                                        \
-        ((void (*)(uint32_t ui32Base,                                         \
-                   uint32_t ui32Seed))ROM_CRCTABLE[4])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the SDHOST API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostCmdReset                                                    \
-        ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostInit                                                        \
-        ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostCmdSend                                                     \
-        ((long (*)(unsigned long ulBase,                                      \
-                  unsigned long ulCmd,                                        \
-                   unsigned ulArg))ROM_SDHOSTTABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostIntRegister                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   void (*pfnHandler)(void)))ROM_SDHOSTTABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostIntUnregister                                               \
-        ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostIntEnable                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                  unsigned long ulIntFlags))ROM_SDHOSTTABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostIntDisable                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                  unsigned long ulIntFlags))ROM_SDHOSTTABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostIntStatus                                                   \
-        ((unsigned long (*)(unsigned long ulBase))ROM_SDHOSTTABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostIntClear                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                  unsigned long ulIntFlags))ROM_SDHOSTTABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostRespStatus                                                  \
-        ((unsigned long (*)(unsigned long ulBase))ROM_SDHOSTTABLE[9])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostRespGet                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulRespnse[4]))ROM_SDHOSTTABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostBlockSizeSet                                                \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned short ulBlkSize))ROM_SDHOSTTABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostBlockCountSet                                               \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned short ulBlkCount))ROM_SDHOSTTABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostDataNonBlockingWrite                                        \
-        ((tBoolean (*)(unsigned long ulBase,                                  \
-                       unsigned long ulData))ROM_SDHOSTTABLE[13])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostDataNonBlockingRead                                         \
-        ((tBoolean (*)(unsigned long ulBase,                                  \
-                       unsigned long *pulData))ROM_SDHOSTTABLE[14])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostDataWrite                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulData))ROM_SDHOSTTABLE[15])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostDataRead                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long *ulData))ROM_SDHOSTTABLE[16])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_SDHostSetExpClk                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulSDHostClk,                                 \
-                   unsigned long ulCardClk))ROM_SDHOSTTABLE[17])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the PRCM API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMMCUReset                                                      \
-        ((void (*)(tBoolean bIncludeSubsystem))ROM_PRCMTABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMSysResetCauseGet                                              \
-        ((unsigned long (*)(void))ROM_PRCMTABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMPeripheralClkEnable                                           \
-        ((void (*)(unsigned long ulPeripheral,                                \
-                   unsigned long ulClkFlags))ROM_PRCMTABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMPeripheralClkDisable                                          \
-        ((void (*)(unsigned long ulPeripheral,                                \
-                   unsigned long ulClkFlags))ROM_PRCMTABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMPeripheralReset                                               \
-        ((void (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMPeripheralStatusGet                                           \
-        ((tBoolean (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMI2SClockFreqSet                                               \
-        ((void (*)(unsigned long ulI2CClkFreq))ROM_PRCMTABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMPeripheralClockGet                                            \
-        ((unsigned long (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMSleepEnter                                                    \
-        ((void (*)(void))ROM_PRCMTABLE[9])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMDeepSleepEnter                                                \
-        ((void (*)(void))ROM_PRCMTABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMSRAMRetentionEnable                                           \
-        ((void (*)(unsigned long ulSramColSel,                                \
-                   unsigned long ulFlags))ROM_PRCMTABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMSRAMRetentionDisable                                          \
-        ((void (*)(unsigned long ulSramColSel,                                \
-                   unsigned long ulFlags))ROM_PRCMTABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMLPDSEnter                                                     \
-        ((void (*)(void))ROM_PRCMTABLE[13])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMLPDSIntervalSet                                               \
-        ((void (*)(unsigned long ulTicks))ROM_PRCMTABLE[14])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMLPDSWakeupSourceEnable                                        \
-        ((void (*)(unsigned long ulLpdsWakeupSrc))ROM_PRCMTABLE[15])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMLPDSWakeupCauseGet                                            \
-        ((unsigned long (*)(void))ROM_PRCMTABLE[16])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMLPDSWakeUpGPIOSelect                                          \
-        ((void (*)(unsigned long ulGPIOPin,                                   \
-                   unsigned long ulType))ROM_PRCMTABLE[17])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMLPDSWakeupSourceDisable                                       \
-        ((void (*)(unsigned long ulLpdsWakeupSrc))ROM_PRCMTABLE[18])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMHibernateEnter                                                \
-        ((void (*)(void))ROM_PRCMTABLE[19])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMHibernateWakeupSourceEnable                                   \
-        ((void (*)(unsigned long ulHIBWakupSrc))ROM_PRCMTABLE[20])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMHibernateWakeupCauseGet                                       \
-        ((unsigned long (*)(void))ROM_PRCMTABLE[21])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMHibernateWakeUpGPIOSelect                                     \
-        ((void (*)(unsigned long ulMultiGPIOBitMap,                           \
-                   unsigned long ulType))ROM_PRCMTABLE[22])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMHibernateWakeupSourceDisable                                  \
-        ((void (*)(unsigned long ulHIBWakupSrc))ROM_PRCMTABLE[23])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMHibernateIntervalSet                                          \
-        ((void (*)(unsigned long long ullTicks))ROM_PRCMTABLE[24])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMSlowClkCtrGet                                                 \
-        ((unsigned long long (*)(void))ROM_PRCMTABLE[25])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMSlowClkCtrMatchSet                                            \
-        ((void (*)(unsigned long long ullTicks))ROM_PRCMTABLE[26])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMSlowClkCtrMatchGet                                            \
-        ((unsigned long long (*)(void))ROM_PRCMTABLE[27])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMOCRRegisterWrite                                              \
-        ((void (*)(unsigned char ucIndex,                                     \
-                   unsigned long ulRegValue))ROM_PRCMTABLE[28])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMOCRRegisterRead                                               \
-        ((unsigned long (*)(unsigned char ucIndex))ROM_PRCMTABLE[29])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMIntRegister                                                   \
-        ((void (*)(void (*pfnHandler)(void)))ROM_PRCMTABLE[30])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMIntUnregister                                                 \
-        ((void (*)(void))ROM_PRCMTABLE[31])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMIntEnable                                                     \
-        ((void (*)(unsigned long ulIntFlags))ROM_PRCMTABLE[32])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMIntDisable                                                    \
-        ((void (*)(unsigned long ulIntFlags))ROM_PRCMTABLE[33])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMIntStatus                                                     \
-        ((unsigned long (*)(void))ROM_PRCMTABLE[34])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMRTCInUseSet                                                   \
-        ((void (*)(void))ROM_PRCMTABLE[35])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMRTCInUseGet                                                   \
-        ((tBoolean (*)(void))ROM_PRCMTABLE[36])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMRTCSet                                                        \
-        ((void (*)(unsigned long ulSecs,                                      \
-                   unsigned short usMsec))ROM_PRCMTABLE[37])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMRTCGet                                                        \
-        ((void (*)(unsigned long *ulSecs,                                     \
-                   unsigned short *usMsec))ROM_PRCMTABLE[38])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMRTCMatchSet                                                   \
-        ((void (*)(unsigned long ulSecs,                                      \
-                   unsigned short usMsec))ROM_PRCMTABLE[39])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMRTCMatchGet                                                   \
-        ((void (*)(unsigned long *ulSecs,                                     \
-                   unsigned short *usMsec))ROM_PRCMTABLE[40])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_PRCMLPDSRestoreInfoSet                                            \
-        ((void (*)(unsigned long ulRestoreSP,                                 \
-                   unsigned long ulRestorePC))ROM_PRCMTABLE[41])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the HWSPINLOCK API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_HwSpinLockAcquire                                                 \
-        ((void (*)(uint32_t ui32LockID))ROM_HWSPINLOCKTABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_HwSpinLockTryAcquire                                              \
-        ((int32_t (*)(uint32_t ui32LockID,                                    \
-                      uint32_t ui32Retry))ROM_HWSPINLOCKTABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_HwSpinLockRelease                                                 \
-        ((void (*)(uint32_t ui32LockID))ROM_HWSPINLOCKTABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_HwSpinLockTest                                                    \
-        ((uint32_t (*)(uint32_t ui32LockID,                                   \
-                       bool bCurrentStatus))ROM_HWSPINLOCKTABLE[3])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the ADC API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCEnable                                                         \
-        ((void (*)(unsigned long ulBase))ROM_ADCTABLE[0])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCDisable                                                        \
-        ((void (*)(unsigned long ulBase))ROM_ADCTABLE[1])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCChannelEnable                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                  unsigned long ulChannel))ROM_ADCTABLE[2])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCChannelDisable                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                  unsigned long ulChannel))ROM_ADCTABLE[3])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCIntRegister                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulChannel,                                   \
-                   void (*pfnHandler)(void)))ROM_ADCTABLE[4])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCIntUnregister                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulChannel))ROM_ADCTABLE[5])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCIntEnable                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulChannel,                                   \
-                   unsigned long ulIntFlags))ROM_ADCTABLE[6])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCIntDisable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulChannel,                                   \
-                   unsigned long ulIntFlags))ROM_ADCTABLE[7])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCIntStatus                                                      \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                           unsigned long ulChannel))ROM_ADCTABLE[8])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCIntClear                                                       \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulChannel,                                   \
-                   unsigned long ulIntFlags))ROM_ADCTABLE[9])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCDMAEnable                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulChannel))ROM_ADCTABLE[10])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCDMADisable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulChannel))ROM_ADCTABLE[11])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCChannelGainSet                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulChannel,                                   \
-                   unsigned char ucGain))ROM_ADCTABLE[12])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCChannleGainGet                                                 \
-        ((unsigned char (*)(unsigned long ulBase,                             \
-                            unsigned long ulChannel))ROM_ADCTABLE[13])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCTimerConfig                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulValue))ROM_ADCTABLE[14])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCTimerEnable                                                    \
-        ((void (*)(unsigned long ulBase))ROM_ADCTABLE[15])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCTimerDisable                                                   \
-        ((void (*)(unsigned long ulBase))ROM_ADCTABLE[16])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCTimerReset                                                     \
-        ((void (*)(unsigned long ulBase))ROM_ADCTABLE[17])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCTimerValueGet                                                  \
-        ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[18])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCFIFOLvlGet                                                     \
-        ((unsigned char (*)(unsigned long ulBase,                             \
-                            unsigned long ulChannel))ROM_ADCTABLE[19])
-#endif
-#if defined(TARGET_IS_CC3200)
-#define ROM_ADCFIFORead                                                       \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulChannel))ROM_ADCTABLE[20])
-#endif
-
-#endif // __ROM_H__
diff --git a/cc3200/hal/rom_map.h b/cc3200/hal/rom_map.h
deleted file mode 100644
index 86a6c75fc..000000000
--- a/cc3200/hal/rom_map.h
+++ /dev/null
@@ -1,3177 +0,0 @@
-//*****************************************************************************
-//
-//  rom_map.h
-//
-//  Macros to facilitate calling functions in the ROM when they are
-//  available and in flash otherwise.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-// THIS IS AN AUTO-GENERATED FILE.  DO NOT EDIT BY HAND.
-//
-//*****************************************************************************
-
-#ifndef __ROM_MAP_H__
-#define __ROM_MAP_H__
-#ifndef DEBUG
-#include "rom.h"
-#endif
-#include "rom_patch.h"
-
-//*****************************************************************************
-//
-// Macros for the Interrupt API.
-//
-//*****************************************************************************
-#ifdef ROM_IntEnable
-#define MAP_IntEnable \
-        ROM_IntEnable
-#else
-#define MAP_IntEnable \
-        IntEnable
-#endif
-#ifdef ROM_IntMasterEnable
-#define MAP_IntMasterEnable \
-        ROM_IntMasterEnable
-#else
-#define MAP_IntMasterEnable \
-        IntMasterEnable
-#endif
-#ifdef ROM_IntMasterDisable
-#define MAP_IntMasterDisable \
-        ROM_IntMasterDisable
-#else
-#define MAP_IntMasterDisable \
-        IntMasterDisable
-#endif
-#ifdef ROM_IntDisable
-#define MAP_IntDisable \
-        ROM_IntDisable
-#else
-#define MAP_IntDisable \
-        IntDisable
-#endif
-#ifdef ROM_IntPriorityGroupingSet
-#define MAP_IntPriorityGroupingSet \
-        ROM_IntPriorityGroupingSet
-#else
-#define MAP_IntPriorityGroupingSet \
-        IntPriorityGroupingSet
-#endif
-#ifdef ROM_IntPriorityGroupingGet
-#define MAP_IntPriorityGroupingGet \
-        ROM_IntPriorityGroupingGet
-#else
-#define MAP_IntPriorityGroupingGet \
-        IntPriorityGroupingGet
-#endif
-#ifdef ROM_IntPrioritySet
-#define MAP_IntPrioritySet \
-        ROM_IntPrioritySet
-#else
-#define MAP_IntPrioritySet \
-        IntPrioritySet
-#endif
-#ifdef ROM_IntPriorityGet
-#define MAP_IntPriorityGet \
-        ROM_IntPriorityGet
-#else
-#define MAP_IntPriorityGet \
-        IntPriorityGet
-#endif
-#ifdef ROM_IntPendSet
-#define MAP_IntPendSet \
-        ROM_IntPendSet
-#else
-#define MAP_IntPendSet \
-        IntPendSet
-#endif
-#ifdef ROM_IntPendClear
-#define MAP_IntPendClear \
-        ROM_IntPendClear
-#else
-#define MAP_IntPendClear \
-        IntPendClear
-#endif
-#ifdef ROM_IntPriorityMaskSet
-#define MAP_IntPriorityMaskSet \
-        ROM_IntPriorityMaskSet
-#else
-#define MAP_IntPriorityMaskSet \
-        IntPriorityMaskSet
-#endif
-#ifdef ROM_IntPriorityMaskGet
-#define MAP_IntPriorityMaskGet \
-        ROM_IntPriorityMaskGet
-#else
-#define MAP_IntPriorityMaskGet \
-        IntPriorityMaskGet
-#endif
-#ifdef ROM_IntRegister
-#define MAP_IntRegister \
-        ROM_IntRegister
-#else
-#define MAP_IntRegister \
-        IntRegister
-#endif
-#ifdef ROM_IntUnregister
-#define MAP_IntUnregister \
-        ROM_IntUnregister
-#else
-#define MAP_IntUnregister \
-        IntUnregister
-#endif
-#ifdef ROM_IntVTableBaseSet
-#define MAP_IntVTableBaseSet \
-        ROM_IntVTableBaseSet
-#else
-#define MAP_IntVTableBaseSet \
-        IntVTableBaseSet
-#endif
-
-//*****************************************************************************
-//
-// Macros for the Timer API.
-//
-//*****************************************************************************
-#ifdef ROM_TimerEnable
-#define MAP_TimerEnable \
-        ROM_TimerEnable
-#else
-#define MAP_TimerEnable \
-        TimerEnable
-#endif
-#ifdef ROM_TimerDisable
-#define MAP_TimerDisable \
-        ROM_TimerDisable
-#else
-#define MAP_TimerDisable \
-        TimerDisable
-#endif
-#ifdef ROM_TimerConfigure
-#define MAP_TimerConfigure \
-        ROM_TimerConfigure
-#else
-#define MAP_TimerConfigure \
-        TimerConfigure
-#endif
-#ifdef ROM_TimerControlLevel
-#define MAP_TimerControlLevel \
-        ROM_TimerControlLevel
-#else
-#define MAP_TimerControlLevel \
-        TimerControlLevel
-#endif
-#ifdef ROM_TimerControlEvent
-#define MAP_TimerControlEvent \
-        ROM_TimerControlEvent
-#else
-#define MAP_TimerControlEvent \
-        TimerControlEvent
-#endif
-#ifdef ROM_TimerControlStall
-#define MAP_TimerControlStall \
-        ROM_TimerControlStall
-#else
-#define MAP_TimerControlStall \
-        TimerControlStall
-#endif
-#ifdef ROM_TimerPrescaleSet
-#define MAP_TimerPrescaleSet \
-        ROM_TimerPrescaleSet
-#else
-#define MAP_TimerPrescaleSet \
-        TimerPrescaleSet
-#endif
-#ifdef ROM_TimerPrescaleGet
-#define MAP_TimerPrescaleGet \
-        ROM_TimerPrescaleGet
-#else
-#define MAP_TimerPrescaleGet \
-        TimerPrescaleGet
-#endif
-#ifdef ROM_TimerPrescaleMatchSet
-#define MAP_TimerPrescaleMatchSet \
-        ROM_TimerPrescaleMatchSet
-#else
-#define MAP_TimerPrescaleMatchSet \
-        TimerPrescaleMatchSet
-#endif
-#ifdef ROM_TimerPrescaleMatchGet
-#define MAP_TimerPrescaleMatchGet \
-        ROM_TimerPrescaleMatchGet
-#else
-#define MAP_TimerPrescaleMatchGet \
-        TimerPrescaleMatchGet
-#endif
-#ifdef ROM_TimerLoadSet
-#define MAP_TimerLoadSet \
-        ROM_TimerLoadSet
-#else
-#define MAP_TimerLoadSet \
-        TimerLoadSet
-#endif
-#ifdef ROM_TimerLoadGet
-#define MAP_TimerLoadGet \
-        ROM_TimerLoadGet
-#else
-#define MAP_TimerLoadGet \
-        TimerLoadGet
-#endif
-#ifdef ROM_TimerValueGet
-#define MAP_TimerValueGet \
-        ROM_TimerValueGet
-#else
-#define MAP_TimerValueGet \
-        TimerValueGet
-#endif
-#ifdef ROM_TimerMatchSet
-#define MAP_TimerMatchSet \
-        ROM_TimerMatchSet
-#else
-#define MAP_TimerMatchSet \
-        TimerMatchSet
-#endif
-#ifdef ROM_TimerMatchGet
-#define MAP_TimerMatchGet \
-        ROM_TimerMatchGet
-#else
-#define MAP_TimerMatchGet \
-        TimerMatchGet
-#endif
-#ifdef ROM_TimerIntRegister
-#define MAP_TimerIntRegister \
-        ROM_TimerIntRegister
-#else
-#define MAP_TimerIntRegister \
-        TimerIntRegister
-#endif
-#ifdef ROM_TimerIntUnregister
-#define MAP_TimerIntUnregister \
-        ROM_TimerIntUnregister
-#else
-#define MAP_TimerIntUnregister \
-        TimerIntUnregister
-#endif
-#ifdef ROM_TimerIntEnable
-#define MAP_TimerIntEnable \
-        ROM_TimerIntEnable
-#else
-#define MAP_TimerIntEnable \
-        TimerIntEnable
-#endif
-#ifdef ROM_TimerIntDisable
-#define MAP_TimerIntDisable \
-        ROM_TimerIntDisable
-#else
-#define MAP_TimerIntDisable \
-        TimerIntDisable
-#endif
-#ifdef ROM_TimerIntStatus
-#define MAP_TimerIntStatus \
-        ROM_TimerIntStatus
-#else
-#define MAP_TimerIntStatus \
-        TimerIntStatus
-#endif
-#ifdef ROM_TimerIntClear
-#define MAP_TimerIntClear \
-        ROM_TimerIntClear
-#else
-#define MAP_TimerIntClear \
-        TimerIntClear
-#endif
-#ifdef ROM_TimerDMAEventSet
-#define MAP_TimerDMAEventSet \
-        ROM_TimerDMAEventSet
-#else
-#define MAP_TimerDMAEventSet \
-        TimerDMAEventSet
-#endif
-#ifdef ROM_TimerDMAEventGet
-#define MAP_TimerDMAEventGet \
-        ROM_TimerDMAEventGet
-#else
-#define MAP_TimerDMAEventGet \
-        TimerDMAEventGet
-#endif
-
-//*****************************************************************************
-//
-// Macros for the UART API.
-//
-//*****************************************************************************
-#ifdef ROM_UARTParityModeSet
-#define MAP_UARTParityModeSet \
-        ROM_UARTParityModeSet
-#else
-#define MAP_UARTParityModeSet \
-        UARTParityModeSet
-#endif
-#ifdef ROM_UARTParityModeGet
-#define MAP_UARTParityModeGet \
-        ROM_UARTParityModeGet
-#else
-#define MAP_UARTParityModeGet \
-        UARTParityModeGet
-#endif
-#ifdef ROM_UARTFIFOLevelSet
-#define MAP_UARTFIFOLevelSet \
-        ROM_UARTFIFOLevelSet
-#else
-#define MAP_UARTFIFOLevelSet \
-        UARTFIFOLevelSet
-#endif
-#ifdef ROM_UARTFIFOLevelGet
-#define MAP_UARTFIFOLevelGet \
-        ROM_UARTFIFOLevelGet
-#else
-#define MAP_UARTFIFOLevelGet \
-        UARTFIFOLevelGet
-#endif
-#ifdef ROM_UARTConfigSetExpClk
-#define MAP_UARTConfigSetExpClk \
-        ROM_UARTConfigSetExpClk
-#else
-#define MAP_UARTConfigSetExpClk \
-        UARTConfigSetExpClk
-#endif
-#ifdef ROM_UARTConfigGetExpClk
-#define MAP_UARTConfigGetExpClk \
-        ROM_UARTConfigGetExpClk
-#else
-#define MAP_UARTConfigGetExpClk \
-        UARTConfigGetExpClk
-#endif
-#ifdef ROM_UARTEnable
-#define MAP_UARTEnable \
-        ROM_UARTEnable
-#else
-#define MAP_UARTEnable \
-        UARTEnable
-#endif
-#ifdef ROM_UARTDisable
-#define MAP_UARTDisable \
-        ROM_UARTDisable
-#else
-#define MAP_UARTDisable \
-        UARTDisable
-#endif
-#ifdef ROM_UARTFIFOEnable
-#define MAP_UARTFIFOEnable \
-        ROM_UARTFIFOEnable
-#else
-#define MAP_UARTFIFOEnable \
-        UARTFIFOEnable
-#endif
-#ifdef ROM_UARTFIFODisable
-#define MAP_UARTFIFODisable \
-        ROM_UARTFIFODisable
-#else
-#define MAP_UARTFIFODisable \
-        UARTFIFODisable
-#endif
-#ifdef ROM_UARTCharsAvail
-#define MAP_UARTCharsAvail \
-        ROM_UARTCharsAvail
-#else
-#define MAP_UARTCharsAvail \
-        UARTCharsAvail
-#endif
-#ifdef ROM_UARTSpaceAvail
-#define MAP_UARTSpaceAvail \
-        ROM_UARTSpaceAvail
-#else
-#define MAP_UARTSpaceAvail \
-        UARTSpaceAvail
-#endif
-#ifdef ROM_UARTCharGetNonBlocking
-#define MAP_UARTCharGetNonBlocking \
-        ROM_UARTCharGetNonBlocking
-#else
-#define MAP_UARTCharGetNonBlocking \
-        UARTCharGetNonBlocking
-#endif
-#ifdef ROM_UARTCharGet
-#define MAP_UARTCharGet \
-        ROM_UARTCharGet
-#else
-#define MAP_UARTCharGet \
-        UARTCharGet
-#endif
-#ifdef ROM_UARTCharPutNonBlocking
-#define MAP_UARTCharPutNonBlocking \
-        ROM_UARTCharPutNonBlocking
-#else
-#define MAP_UARTCharPutNonBlocking \
-        UARTCharPutNonBlocking
-#endif
-#ifdef ROM_UARTCharPut
-#define MAP_UARTCharPut \
-        ROM_UARTCharPut
-#else
-#define MAP_UARTCharPut \
-        UARTCharPut
-#endif
-#ifdef ROM_UARTBreakCtl
-#define MAP_UARTBreakCtl \
-        ROM_UARTBreakCtl
-#else
-#define MAP_UARTBreakCtl \
-        UARTBreakCtl
-#endif
-#ifdef ROM_UARTBusy
-#define MAP_UARTBusy \
-        ROM_UARTBusy
-#else
-#define MAP_UARTBusy \
-        UARTBusy
-#endif
-#ifdef ROM_UARTIntRegister
-#define MAP_UARTIntRegister \
-        ROM_UARTIntRegister
-#else
-#define MAP_UARTIntRegister \
-        UARTIntRegister
-#endif
-#ifdef ROM_UARTIntUnregister
-#define MAP_UARTIntUnregister \
-        ROM_UARTIntUnregister
-#else
-#define MAP_UARTIntUnregister \
-        UARTIntUnregister
-#endif
-#ifdef ROM_UARTIntEnable
-#define MAP_UARTIntEnable \
-        ROM_UARTIntEnable
-#else
-#define MAP_UARTIntEnable \
-        UARTIntEnable
-#endif
-#ifdef ROM_UARTIntDisable
-#define MAP_UARTIntDisable \
-        ROM_UARTIntDisable
-#else
-#define MAP_UARTIntDisable \
-        UARTIntDisable
-#endif
-#ifdef ROM_UARTIntStatus
-#define MAP_UARTIntStatus \
-        ROM_UARTIntStatus
-#else
-#define MAP_UARTIntStatus \
-        UARTIntStatus
-#endif
-#ifdef ROM_UARTIntClear
-#define MAP_UARTIntClear \
-        ROM_UARTIntClear
-#else
-#define MAP_UARTIntClear \
-        UARTIntClear
-#endif
-#ifdef ROM_UARTDMAEnable
-#define MAP_UARTDMAEnable \
-        ROM_UARTDMAEnable
-#else
-#define MAP_UARTDMAEnable \
-        UARTDMAEnable
-#endif
-#ifdef ROM_UARTDMADisable
-#define MAP_UARTDMADisable \
-        ROM_UARTDMADisable
-#else
-#define MAP_UARTDMADisable \
-        UARTDMADisable
-#endif
-#ifdef ROM_UARTRxErrorGet
-#define MAP_UARTRxErrorGet \
-        ROM_UARTRxErrorGet
-#else
-#define MAP_UARTRxErrorGet \
-        UARTRxErrorGet
-#endif
-#ifdef ROM_UARTRxErrorClear
-#define MAP_UARTRxErrorClear \
-        ROM_UARTRxErrorClear
-#else
-#define MAP_UARTRxErrorClear \
-        UARTRxErrorClear
-#endif
-#ifdef ROM_UARTModemControlSet
-#define MAP_UARTModemControlSet \
-        ROM_UARTModemControlSet
-#else
-#define MAP_UARTModemControlSet \
-        UARTModemControlSet
-#endif
-#ifdef ROM_UARTModemControlClear
-#define MAP_UARTModemControlClear \
-        ROM_UARTModemControlClear
-#else
-#define MAP_UARTModemControlClear \
-        UARTModemControlClear
-#endif
-#ifdef ROM_UARTModemControlGet
-#define MAP_UARTModemControlGet \
-        ROM_UARTModemControlGet
-#else
-#define MAP_UARTModemControlGet \
-        UARTModemControlGet
-#endif
-#ifdef ROM_UARTModemStatusGet
-#define MAP_UARTModemStatusGet \
-        ROM_UARTModemStatusGet
-#else
-#define MAP_UARTModemStatusGet \
-        UARTModemStatusGet
-#endif
-#ifdef ROM_UARTFlowControlSet
-#define MAP_UARTFlowControlSet \
-        ROM_UARTFlowControlSet
-#else
-#define MAP_UARTFlowControlSet \
-        UARTFlowControlSet
-#endif
-#ifdef ROM_UARTFlowControlGet
-#define MAP_UARTFlowControlGet \
-        ROM_UARTFlowControlGet
-#else
-#define MAP_UARTFlowControlGet \
-        UARTFlowControlGet
-#endif
-#ifdef ROM_UARTTxIntModeSet
-#define MAP_UARTTxIntModeSet \
-        ROM_UARTTxIntModeSet
-#else
-#define MAP_UARTTxIntModeSet \
-        UARTTxIntModeSet
-#endif
-#ifdef ROM_UARTTxIntModeGet
-#define MAP_UARTTxIntModeGet \
-        ROM_UARTTxIntModeGet
-#else
-#define MAP_UARTTxIntModeGet \
-        UARTTxIntModeGet
-#endif
-
-//*****************************************************************************
-//
-// Macros for the uDMA API.
-//
-//*****************************************************************************
-#ifdef ROM_uDMAChannelTransferSet
-#define MAP_uDMAChannelTransferSet \
-        ROM_uDMAChannelTransferSet
-#else
-#define MAP_uDMAChannelTransferSet \
-        uDMAChannelTransferSet
-#endif
-#ifdef ROM_uDMAEnable
-#define MAP_uDMAEnable \
-        ROM_uDMAEnable
-#else
-#define MAP_uDMAEnable \
-        uDMAEnable
-#endif
-#ifdef ROM_uDMADisable
-#define MAP_uDMADisable \
-        ROM_uDMADisable
-#else
-#define MAP_uDMADisable \
-        uDMADisable
-#endif
-#ifdef ROM_uDMAErrorStatusGet
-#define MAP_uDMAErrorStatusGet \
-        ROM_uDMAErrorStatusGet
-#else
-#define MAP_uDMAErrorStatusGet \
-        uDMAErrorStatusGet
-#endif
-#ifdef ROM_uDMAErrorStatusClear
-#define MAP_uDMAErrorStatusClear \
-        ROM_uDMAErrorStatusClear
-#else
-#define MAP_uDMAErrorStatusClear \
-        uDMAErrorStatusClear
-#endif
-#ifdef ROM_uDMAChannelEnable
-#define MAP_uDMAChannelEnable \
-        ROM_uDMAChannelEnable
-#else
-#define MAP_uDMAChannelEnable \
-        uDMAChannelEnable
-#endif
-#ifdef ROM_uDMAChannelDisable
-#define MAP_uDMAChannelDisable \
-        ROM_uDMAChannelDisable
-#else
-#define MAP_uDMAChannelDisable \
-        uDMAChannelDisable
-#endif
-#ifdef ROM_uDMAChannelIsEnabled
-#define MAP_uDMAChannelIsEnabled \
-        ROM_uDMAChannelIsEnabled
-#else
-#define MAP_uDMAChannelIsEnabled \
-        uDMAChannelIsEnabled
-#endif
-#ifdef ROM_uDMAControlBaseSet
-#define MAP_uDMAControlBaseSet \
-        ROM_uDMAControlBaseSet
-#else
-#define MAP_uDMAControlBaseSet \
-        uDMAControlBaseSet
-#endif
-#ifdef ROM_uDMAControlBaseGet
-#define MAP_uDMAControlBaseGet \
-        ROM_uDMAControlBaseGet
-#else
-#define MAP_uDMAControlBaseGet \
-        uDMAControlBaseGet
-#endif
-#ifdef ROM_uDMAChannelRequest
-#define MAP_uDMAChannelRequest \
-        ROM_uDMAChannelRequest
-#else
-#define MAP_uDMAChannelRequest \
-        uDMAChannelRequest
-#endif
-#ifdef ROM_uDMAChannelAttributeEnable
-#define MAP_uDMAChannelAttributeEnable \
-        ROM_uDMAChannelAttributeEnable
-#else
-#define MAP_uDMAChannelAttributeEnable \
-        uDMAChannelAttributeEnable
-#endif
-#ifdef ROM_uDMAChannelAttributeDisable
-#define MAP_uDMAChannelAttributeDisable \
-        ROM_uDMAChannelAttributeDisable
-#else
-#define MAP_uDMAChannelAttributeDisable \
-        uDMAChannelAttributeDisable
-#endif
-#ifdef ROM_uDMAChannelAttributeGet
-#define MAP_uDMAChannelAttributeGet \
-        ROM_uDMAChannelAttributeGet
-#else
-#define MAP_uDMAChannelAttributeGet \
-        uDMAChannelAttributeGet
-#endif
-#ifdef ROM_uDMAChannelControlSet
-#define MAP_uDMAChannelControlSet \
-        ROM_uDMAChannelControlSet
-#else
-#define MAP_uDMAChannelControlSet \
-        uDMAChannelControlSet
-#endif
-#ifdef ROM_uDMAChannelSizeGet
-#define MAP_uDMAChannelSizeGet \
-        ROM_uDMAChannelSizeGet
-#else
-#define MAP_uDMAChannelSizeGet \
-        uDMAChannelSizeGet
-#endif
-#ifdef ROM_uDMAChannelModeGet
-#define MAP_uDMAChannelModeGet \
-        ROM_uDMAChannelModeGet
-#else
-#define MAP_uDMAChannelModeGet \
-        uDMAChannelModeGet
-#endif
-#ifdef ROM_uDMAIntStatus
-#define MAP_uDMAIntStatus \
-        ROM_uDMAIntStatus
-#else
-#define MAP_uDMAIntStatus \
-        uDMAIntStatus
-#endif
-#ifdef ROM_uDMAIntClear
-#define MAP_uDMAIntClear \
-        ROM_uDMAIntClear
-#else
-#define MAP_uDMAIntClear \
-        uDMAIntClear
-#endif
-#ifdef ROM_uDMAControlAlternateBaseGet
-#define MAP_uDMAControlAlternateBaseGet \
-        ROM_uDMAControlAlternateBaseGet
-#else
-#define MAP_uDMAControlAlternateBaseGet \
-        uDMAControlAlternateBaseGet
-#endif
-#ifdef ROM_uDMAChannelScatterGatherSet
-#define MAP_uDMAChannelScatterGatherSet \
-        ROM_uDMAChannelScatterGatherSet
-#else
-#define MAP_uDMAChannelScatterGatherSet \
-        uDMAChannelScatterGatherSet
-#endif
-#ifdef ROM_uDMAChannelAssign
-#define MAP_uDMAChannelAssign \
-        ROM_uDMAChannelAssign
-#else
-#define MAP_uDMAChannelAssign \
-        uDMAChannelAssign
-#endif
-#ifdef ROM_uDMAIntRegister
-#define MAP_uDMAIntRegister \
-        ROM_uDMAIntRegister
-#else
-#define MAP_uDMAIntRegister \
-        uDMAIntRegister
-#endif
-#ifdef ROM_uDMAIntUnregister
-#define MAP_uDMAIntUnregister \
-        ROM_uDMAIntUnregister
-#else
-#define MAP_uDMAIntUnregister \
-        uDMAIntUnregister
-#endif
-
-//*****************************************************************************
-//
-// Macros for the Watchdog API.
-//
-//*****************************************************************************
-#ifdef ROM_WatchdogIntClear
-#define MAP_WatchdogIntClear \
-        ROM_WatchdogIntClear
-#else
-#define MAP_WatchdogIntClear \
-        WatchdogIntClear
-#endif
-#ifdef ROM_WatchdogRunning
-#define MAP_WatchdogRunning \
-        ROM_WatchdogRunning
-#else
-#define MAP_WatchdogRunning \
-        WatchdogRunning
-#endif
-#ifdef ROM_WatchdogEnable
-#define MAP_WatchdogEnable \
-        ROM_WatchdogEnable
-#else
-#define MAP_WatchdogEnable \
-        WatchdogEnable
-#endif
-#ifdef ROM_WatchdogLock
-#define MAP_WatchdogLock \
-        ROM_WatchdogLock
-#else
-#define MAP_WatchdogLock \
-        WatchdogLock
-#endif
-#ifdef ROM_WatchdogUnlock
-#define MAP_WatchdogUnlock \
-        ROM_WatchdogUnlock
-#else
-#define MAP_WatchdogUnlock \
-        WatchdogUnlock
-#endif
-#ifdef ROM_WatchdogLockState
-#define MAP_WatchdogLockState \
-        ROM_WatchdogLockState
-#else
-#define MAP_WatchdogLockState \
-        WatchdogLockState
-#endif
-#ifdef ROM_WatchdogReloadSet
-#define MAP_WatchdogReloadSet \
-        ROM_WatchdogReloadSet
-#else
-#define MAP_WatchdogReloadSet \
-        WatchdogReloadSet
-#endif
-#ifdef ROM_WatchdogReloadGet
-#define MAP_WatchdogReloadGet \
-        ROM_WatchdogReloadGet
-#else
-#define MAP_WatchdogReloadGet \
-        WatchdogReloadGet
-#endif
-#ifdef ROM_WatchdogValueGet
-#define MAP_WatchdogValueGet \
-        ROM_WatchdogValueGet
-#else
-#define MAP_WatchdogValueGet \
-        WatchdogValueGet
-#endif
-#ifdef ROM_WatchdogIntStatus
-#define MAP_WatchdogIntStatus \
-        ROM_WatchdogIntStatus
-#else
-#define MAP_WatchdogIntStatus \
-        WatchdogIntStatus
-#endif
-#ifdef ROM_WatchdogStallEnable
-#define MAP_WatchdogStallEnable \
-        ROM_WatchdogStallEnable
-#else
-#define MAP_WatchdogStallEnable \
-        WatchdogStallEnable
-#endif
-#ifdef ROM_WatchdogStallDisable
-#define MAP_WatchdogStallDisable \
-        ROM_WatchdogStallDisable
-#else
-#define MAP_WatchdogStallDisable \
-        WatchdogStallDisable
-#endif
-#ifdef ROM_WatchdogIntRegister
-#define MAP_WatchdogIntRegister \
-        ROM_WatchdogIntRegister
-#else
-#define MAP_WatchdogIntRegister \
-        WatchdogIntRegister
-#endif
-#ifdef ROM_WatchdogIntUnregister
-#define MAP_WatchdogIntUnregister \
-        ROM_WatchdogIntUnregister
-#else
-#define MAP_WatchdogIntUnregister \
-        WatchdogIntUnregister
-#endif
-
-//*****************************************************************************
-//
-// Macros for the I2C API.
-//
-//*****************************************************************************
-#ifdef ROM_I2CIntRegister
-#define MAP_I2CIntRegister \
-        ROM_I2CIntRegister
-#else
-#define MAP_I2CIntRegister \
-        I2CIntRegister
-#endif
-#ifdef ROM_I2CIntUnregister
-#define MAP_I2CIntUnregister \
-        ROM_I2CIntUnregister
-#else
-#define MAP_I2CIntUnregister \
-        I2CIntUnregister
-#endif
-#ifdef ROM_I2CTxFIFOConfigSet
-#define MAP_I2CTxFIFOConfigSet \
-        ROM_I2CTxFIFOConfigSet
-#else
-#define MAP_I2CTxFIFOConfigSet \
-        I2CTxFIFOConfigSet
-#endif
-#ifdef ROM_I2CTxFIFOFlush
-#define MAP_I2CTxFIFOFlush \
-        ROM_I2CTxFIFOFlush
-#else
-#define MAP_I2CTxFIFOFlush \
-        I2CTxFIFOFlush
-#endif
-#ifdef ROM_I2CRxFIFOConfigSet
-#define MAP_I2CRxFIFOConfigSet \
-        ROM_I2CRxFIFOConfigSet
-#else
-#define MAP_I2CRxFIFOConfigSet \
-        I2CRxFIFOConfigSet
-#endif
-#ifdef ROM_I2CRxFIFOFlush
-#define MAP_I2CRxFIFOFlush \
-        ROM_I2CRxFIFOFlush
-#else
-#define MAP_I2CRxFIFOFlush \
-        I2CRxFIFOFlush
-#endif
-#ifdef ROM_I2CFIFOStatus
-#define MAP_I2CFIFOStatus \
-        ROM_I2CFIFOStatus
-#else
-#define MAP_I2CFIFOStatus \
-        I2CFIFOStatus
-#endif
-#ifdef ROM_I2CFIFODataPut
-#define MAP_I2CFIFODataPut \
-        ROM_I2CFIFODataPut
-#else
-#define MAP_I2CFIFODataPut \
-        I2CFIFODataPut
-#endif
-#ifdef ROM_I2CFIFODataPutNonBlocking
-#define MAP_I2CFIFODataPutNonBlocking \
-        ROM_I2CFIFODataPutNonBlocking
-#else
-#define MAP_I2CFIFODataPutNonBlocking \
-        I2CFIFODataPutNonBlocking
-#endif
-#ifdef ROM_I2CFIFODataGet
-#define MAP_I2CFIFODataGet \
-        ROM_I2CFIFODataGet
-#else
-#define MAP_I2CFIFODataGet \
-        I2CFIFODataGet
-#endif
-#ifdef ROM_I2CFIFODataGetNonBlocking
-#define MAP_I2CFIFODataGetNonBlocking \
-        ROM_I2CFIFODataGetNonBlocking
-#else
-#define MAP_I2CFIFODataGetNonBlocking \
-        I2CFIFODataGetNonBlocking
-#endif
-#ifdef ROM_I2CMasterBurstLengthSet
-#define MAP_I2CMasterBurstLengthSet \
-        ROM_I2CMasterBurstLengthSet
-#else
-#define MAP_I2CMasterBurstLengthSet \
-        I2CMasterBurstLengthSet
-#endif
-#ifdef ROM_I2CMasterBurstCountGet
-#define MAP_I2CMasterBurstCountGet \
-        ROM_I2CMasterBurstCountGet
-#else
-#define MAP_I2CMasterBurstCountGet \
-        I2CMasterBurstCountGet
-#endif
-#ifdef ROM_I2CMasterGlitchFilterConfigSet
-#define MAP_I2CMasterGlitchFilterConfigSet \
-        ROM_I2CMasterGlitchFilterConfigSet
-#else
-#define MAP_I2CMasterGlitchFilterConfigSet \
-        I2CMasterGlitchFilterConfigSet
-#endif
-#ifdef ROM_I2CSlaveFIFOEnable
-#define MAP_I2CSlaveFIFOEnable \
-        ROM_I2CSlaveFIFOEnable
-#else
-#define MAP_I2CSlaveFIFOEnable \
-        I2CSlaveFIFOEnable
-#endif
-#ifdef ROM_I2CSlaveFIFODisable
-#define MAP_I2CSlaveFIFODisable \
-        ROM_I2CSlaveFIFODisable
-#else
-#define MAP_I2CSlaveFIFODisable \
-        I2CSlaveFIFODisable
-#endif
-#ifdef ROM_I2CMasterBusBusy
-#define MAP_I2CMasterBusBusy \
-        ROM_I2CMasterBusBusy
-#else
-#define MAP_I2CMasterBusBusy \
-        I2CMasterBusBusy
-#endif
-#ifdef ROM_I2CMasterBusy
-#define MAP_I2CMasterBusy \
-        ROM_I2CMasterBusy
-#else
-#define MAP_I2CMasterBusy \
-        I2CMasterBusy
-#endif
-#ifdef ROM_I2CMasterControl
-#define MAP_I2CMasterControl \
-        ROM_I2CMasterControl
-#else
-#define MAP_I2CMasterControl \
-        I2CMasterControl
-#endif
-#ifdef ROM_I2CMasterDataGet
-#define MAP_I2CMasterDataGet \
-        ROM_I2CMasterDataGet
-#else
-#define MAP_I2CMasterDataGet \
-        I2CMasterDataGet
-#endif
-#ifdef ROM_I2CMasterDataPut
-#define MAP_I2CMasterDataPut \
-        ROM_I2CMasterDataPut
-#else
-#define MAP_I2CMasterDataPut \
-        I2CMasterDataPut
-#endif
-#ifdef ROM_I2CMasterDisable
-#define MAP_I2CMasterDisable \
-        ROM_I2CMasterDisable
-#else
-#define MAP_I2CMasterDisable \
-        I2CMasterDisable
-#endif
-#ifdef ROM_I2CMasterEnable
-#define MAP_I2CMasterEnable \
-        ROM_I2CMasterEnable
-#else
-#define MAP_I2CMasterEnable \
-        I2CMasterEnable
-#endif
-#ifdef ROM_I2CMasterErr
-#define MAP_I2CMasterErr \
-        ROM_I2CMasterErr
-#else
-#define MAP_I2CMasterErr \
-        I2CMasterErr
-#endif
-#ifdef ROM_I2CMasterIntClear
-#define MAP_I2CMasterIntClear \
-        ROM_I2CMasterIntClear
-#else
-#define MAP_I2CMasterIntClear \
-        I2CMasterIntClear
-#endif
-#ifdef ROM_I2CMasterIntDisable
-#define MAP_I2CMasterIntDisable \
-        ROM_I2CMasterIntDisable
-#else
-#define MAP_I2CMasterIntDisable \
-        I2CMasterIntDisable
-#endif
-#ifdef ROM_I2CMasterIntEnable
-#define MAP_I2CMasterIntEnable \
-        ROM_I2CMasterIntEnable
-#else
-#define MAP_I2CMasterIntEnable \
-        I2CMasterIntEnable
-#endif
-#ifdef ROM_I2CMasterIntStatus
-#define MAP_I2CMasterIntStatus \
-        ROM_I2CMasterIntStatus
-#else
-#define MAP_I2CMasterIntStatus \
-        I2CMasterIntStatus
-#endif
-#ifdef ROM_I2CMasterIntEnableEx
-#define MAP_I2CMasterIntEnableEx \
-        ROM_I2CMasterIntEnableEx
-#else
-#define MAP_I2CMasterIntEnableEx \
-        I2CMasterIntEnableEx
-#endif
-#ifdef ROM_I2CMasterIntDisableEx
-#define MAP_I2CMasterIntDisableEx \
-        ROM_I2CMasterIntDisableEx
-#else
-#define MAP_I2CMasterIntDisableEx \
-        I2CMasterIntDisableEx
-#endif
-#ifdef ROM_I2CMasterIntStatusEx
-#define MAP_I2CMasterIntStatusEx \
-        ROM_I2CMasterIntStatusEx
-#else
-#define MAP_I2CMasterIntStatusEx \
-        I2CMasterIntStatusEx
-#endif
-#ifdef ROM_I2CMasterIntClearEx
-#define MAP_I2CMasterIntClearEx \
-        ROM_I2CMasterIntClearEx
-#else
-#define MAP_I2CMasterIntClearEx \
-        I2CMasterIntClearEx
-#endif
-#ifdef ROM_I2CMasterTimeoutSet
-#define MAP_I2CMasterTimeoutSet \
-        ROM_I2CMasterTimeoutSet
-#else
-#define MAP_I2CMasterTimeoutSet \
-        I2CMasterTimeoutSet
-#endif
-#ifdef ROM_I2CSlaveACKOverride
-#define MAP_I2CSlaveACKOverride \
-        ROM_I2CSlaveACKOverride
-#else
-#define MAP_I2CSlaveACKOverride \
-        I2CSlaveACKOverride
-#endif
-#ifdef ROM_I2CSlaveACKValueSet
-#define MAP_I2CSlaveACKValueSet \
-        ROM_I2CSlaveACKValueSet
-#else
-#define MAP_I2CSlaveACKValueSet \
-        I2CSlaveACKValueSet
-#endif
-#ifdef ROM_I2CMasterLineStateGet
-#define MAP_I2CMasterLineStateGet \
-        ROM_I2CMasterLineStateGet
-#else
-#define MAP_I2CMasterLineStateGet \
-        I2CMasterLineStateGet
-#endif
-#ifdef ROM_I2CMasterSlaveAddrSet
-#define MAP_I2CMasterSlaveAddrSet \
-        ROM_I2CMasterSlaveAddrSet
-#else
-#define MAP_I2CMasterSlaveAddrSet \
-        I2CMasterSlaveAddrSet
-#endif
-#ifdef ROM_I2CSlaveDataGet
-#define MAP_I2CSlaveDataGet \
-        ROM_I2CSlaveDataGet
-#else
-#define MAP_I2CSlaveDataGet \
-        I2CSlaveDataGet
-#endif
-#ifdef ROM_I2CSlaveDataPut
-#define MAP_I2CSlaveDataPut \
-        ROM_I2CSlaveDataPut
-#else
-#define MAP_I2CSlaveDataPut \
-        I2CSlaveDataPut
-#endif
-#ifdef ROM_I2CSlaveDisable
-#define MAP_I2CSlaveDisable \
-        ROM_I2CSlaveDisable
-#else
-#define MAP_I2CSlaveDisable \
-        I2CSlaveDisable
-#endif
-#ifdef ROM_I2CSlaveEnable
-#define MAP_I2CSlaveEnable \
-        ROM_I2CSlaveEnable
-#else
-#define MAP_I2CSlaveEnable \
-        I2CSlaveEnable
-#endif
-#ifdef ROM_I2CSlaveInit
-#define MAP_I2CSlaveInit \
-        ROM_I2CSlaveInit
-#else
-#define MAP_I2CSlaveInit \
-        I2CSlaveInit
-#endif
-#ifdef ROM_I2CSlaveAddressSet
-#define MAP_I2CSlaveAddressSet \
-        ROM_I2CSlaveAddressSet
-#else
-#define MAP_I2CSlaveAddressSet \
-        I2CSlaveAddressSet
-#endif
-#ifdef ROM_I2CSlaveIntClear
-#define MAP_I2CSlaveIntClear \
-        ROM_I2CSlaveIntClear
-#else
-#define MAP_I2CSlaveIntClear \
-        I2CSlaveIntClear
-#endif
-#ifdef ROM_I2CSlaveIntDisable
-#define MAP_I2CSlaveIntDisable \
-        ROM_I2CSlaveIntDisable
-#else
-#define MAP_I2CSlaveIntDisable \
-        I2CSlaveIntDisable
-#endif
-#ifdef ROM_I2CSlaveIntEnable
-#define MAP_I2CSlaveIntEnable \
-        ROM_I2CSlaveIntEnable
-#else
-#define MAP_I2CSlaveIntEnable \
-        I2CSlaveIntEnable
-#endif
-#ifdef ROM_I2CSlaveIntClearEx
-#define MAP_I2CSlaveIntClearEx \
-        ROM_I2CSlaveIntClearEx
-#else
-#define MAP_I2CSlaveIntClearEx \
-        I2CSlaveIntClearEx
-#endif
-#ifdef ROM_I2CSlaveIntDisableEx
-#define MAP_I2CSlaveIntDisableEx \
-        ROM_I2CSlaveIntDisableEx
-#else
-#define MAP_I2CSlaveIntDisableEx \
-        I2CSlaveIntDisableEx
-#endif
-#ifdef ROM_I2CSlaveIntEnableEx
-#define MAP_I2CSlaveIntEnableEx \
-        ROM_I2CSlaveIntEnableEx
-#else
-#define MAP_I2CSlaveIntEnableEx \
-        I2CSlaveIntEnableEx
-#endif
-#ifdef ROM_I2CSlaveIntStatus
-#define MAP_I2CSlaveIntStatus \
-        ROM_I2CSlaveIntStatus
-#else
-#define MAP_I2CSlaveIntStatus \
-        I2CSlaveIntStatus
-#endif
-#ifdef ROM_I2CSlaveIntStatusEx
-#define MAP_I2CSlaveIntStatusEx \
-        ROM_I2CSlaveIntStatusEx
-#else
-#define MAP_I2CSlaveIntStatusEx \
-        I2CSlaveIntStatusEx
-#endif
-#ifdef ROM_I2CSlaveStatus
-#define MAP_I2CSlaveStatus \
-        ROM_I2CSlaveStatus
-#else
-#define MAP_I2CSlaveStatus \
-        I2CSlaveStatus
-#endif
-#ifdef ROM_I2CMasterInitExpClk
-#define MAP_I2CMasterInitExpClk \
-        ROM_I2CMasterInitExpClk
-#else
-#define MAP_I2CMasterInitExpClk \
-        I2CMasterInitExpClk
-#endif
-
-//*****************************************************************************
-//
-// Macros for the SPI API.
-//
-//*****************************************************************************
-#ifdef ROM_SPIEnable
-#define MAP_SPIEnable \
-        ROM_SPIEnable
-#else
-#define MAP_SPIEnable \
-        SPIEnable
-#endif
-#ifdef ROM_SPIDisable
-#define MAP_SPIDisable \
-        ROM_SPIDisable
-#else
-#define MAP_SPIDisable \
-        SPIDisable
-#endif
-#ifdef ROM_SPIReset
-#define MAP_SPIReset \
-        ROM_SPIReset
-#else
-#define MAP_SPIReset \
-        SPIReset
-#endif
-#ifdef ROM_SPIConfigSetExpClk
-#define MAP_SPIConfigSetExpClk \
-        ROM_SPIConfigSetExpClk
-#else
-#define MAP_SPIConfigSetExpClk \
-        SPIConfigSetExpClk
-#endif
-#ifdef ROM_SPIDataGetNonBlocking
-#define MAP_SPIDataGetNonBlocking \
-        ROM_SPIDataGetNonBlocking
-#else
-#define MAP_SPIDataGetNonBlocking \
-        SPIDataGetNonBlocking
-#endif
-#ifdef ROM_SPIDataGet
-#define MAP_SPIDataGet \
-        ROM_SPIDataGet
-#else
-#define MAP_SPIDataGet \
-        SPIDataGet
-#endif
-#ifdef ROM_SPIDataPutNonBlocking
-#define MAP_SPIDataPutNonBlocking \
-        ROM_SPIDataPutNonBlocking
-#else
-#define MAP_SPIDataPutNonBlocking \
-        SPIDataPutNonBlocking
-#endif
-#ifdef ROM_SPIDataPut
-#define MAP_SPIDataPut \
-        ROM_SPIDataPut
-#else
-#define MAP_SPIDataPut \
-        SPIDataPut
-#endif
-#ifdef ROM_SPIFIFOEnable
-#define MAP_SPIFIFOEnable \
-        ROM_SPIFIFOEnable
-#else
-#define MAP_SPIFIFOEnable \
-        SPIFIFOEnable
-#endif
-#ifdef ROM_SPIFIFODisable
-#define MAP_SPIFIFODisable \
-        ROM_SPIFIFODisable
-#else
-#define MAP_SPIFIFODisable \
-        SPIFIFODisable
-#endif
-#ifdef ROM_SPIFIFOLevelSet
-#define MAP_SPIFIFOLevelSet \
-        ROM_SPIFIFOLevelSet
-#else
-#define MAP_SPIFIFOLevelSet \
-        SPIFIFOLevelSet
-#endif
-#ifdef ROM_SPIFIFOLevelGet
-#define MAP_SPIFIFOLevelGet \
-        ROM_SPIFIFOLevelGet
-#else
-#define MAP_SPIFIFOLevelGet \
-        SPIFIFOLevelGet
-#endif
-#ifdef ROM_SPIWordCountSet
-#define MAP_SPIWordCountSet \
-        ROM_SPIWordCountSet
-#else
-#define MAP_SPIWordCountSet \
-        SPIWordCountSet
-#endif
-#ifdef ROM_SPIIntRegister
-#define MAP_SPIIntRegister \
-        ROM_SPIIntRegister
-#else
-#define MAP_SPIIntRegister \
-        SPIIntRegister
-#endif
-#ifdef ROM_SPIIntUnregister
-#define MAP_SPIIntUnregister \
-        ROM_SPIIntUnregister
-#else
-#define MAP_SPIIntUnregister \
-        SPIIntUnregister
-#endif
-#ifdef ROM_SPIIntEnable
-#define MAP_SPIIntEnable \
-        ROM_SPIIntEnable
-#else
-#define MAP_SPIIntEnable \
-        SPIIntEnable
-#endif
-#ifdef ROM_SPIIntDisable
-#define MAP_SPIIntDisable \
-        ROM_SPIIntDisable
-#else
-#define MAP_SPIIntDisable \
-        SPIIntDisable
-#endif
-#ifdef ROM_SPIIntStatus
-#define MAP_SPIIntStatus \
-        ROM_SPIIntStatus
-#else
-#define MAP_SPIIntStatus \
-        SPIIntStatus
-#endif
-#ifdef ROM_SPIIntClear
-#define MAP_SPIIntClear \
-        ROM_SPIIntClear
-#else
-#define MAP_SPIIntClear \
-        SPIIntClear
-#endif
-#ifdef ROM_SPIDmaEnable
-#define MAP_SPIDmaEnable \
-        ROM_SPIDmaEnable
-#else
-#define MAP_SPIDmaEnable \
-        SPIDmaEnable
-#endif
-#ifdef ROM_SPIDmaDisable
-#define MAP_SPIDmaDisable \
-        ROM_SPIDmaDisable
-#else
-#define MAP_SPIDmaDisable \
-        SPIDmaDisable
-#endif
-#ifdef ROM_SPICSEnable
-#define MAP_SPICSEnable \
-        ROM_SPICSEnable
-#else
-#define MAP_SPICSEnable \
-        SPICSEnable
-#endif
-#ifdef ROM_SPICSDisable
-#define MAP_SPICSDisable \
-        ROM_SPICSDisable
-#else
-#define MAP_SPICSDisable \
-        SPICSDisable
-#endif
-#ifdef ROM_SPITransfer
-#define MAP_SPITransfer \
-        ROM_SPITransfer
-#else
-#define MAP_SPITransfer \
-        SPITransfer
-#endif
-
-//*****************************************************************************
-//
-// Macros for the CAM API.
-//
-//*****************************************************************************
-#ifdef ROM_CameraReset
-#define MAP_CameraReset \
-        ROM_CameraReset
-#else
-#define MAP_CameraReset \
-        CameraReset
-#endif
-#ifdef ROM_CameraParamsConfig
-#define MAP_CameraParamsConfig \
-        ROM_CameraParamsConfig
-#else
-#define MAP_CameraParamsConfig \
-        CameraParamsConfig
-#endif
-#ifdef ROM_CameraXClkConfig
-#define MAP_CameraXClkConfig \
-        ROM_CameraXClkConfig
-#else
-#define MAP_CameraXClkConfig \
-        CameraXClkConfig
-#endif
-#ifdef ROM_CameraXClkSet
-#define MAP_CameraXClkSet \
-        ROM_CameraXClkSet
-#else
-#define MAP_CameraXClkSet \
-        CameraXClkSet
-#endif
-#ifdef ROM_CameraDMAEnable
-#define MAP_CameraDMAEnable \
-        ROM_CameraDMAEnable
-#else
-#define MAP_CameraDMAEnable \
-        CameraDMAEnable
-#endif
-#ifdef ROM_CameraDMADisable
-#define MAP_CameraDMADisable \
-        ROM_CameraDMADisable
-#else
-#define MAP_CameraDMADisable \
-        CameraDMADisable
-#endif
-#ifdef ROM_CameraThresholdSet
-#define MAP_CameraThresholdSet \
-        ROM_CameraThresholdSet
-#else
-#define MAP_CameraThresholdSet \
-        CameraThresholdSet
-#endif
-#ifdef ROM_CameraIntRegister
-#define MAP_CameraIntRegister \
-        ROM_CameraIntRegister
-#else
-#define MAP_CameraIntRegister \
-        CameraIntRegister
-#endif
-#ifdef ROM_CameraIntUnregister
-#define MAP_CameraIntUnregister \
-        ROM_CameraIntUnregister
-#else
-#define MAP_CameraIntUnregister \
-        CameraIntUnregister
-#endif
-#ifdef ROM_CameraIntEnable
-#define MAP_CameraIntEnable \
-        ROM_CameraIntEnable
-#else
-#define MAP_CameraIntEnable \
-        CameraIntEnable
-#endif
-#ifdef ROM_CameraIntDisable
-#define MAP_CameraIntDisable \
-        ROM_CameraIntDisable
-#else
-#define MAP_CameraIntDisable \
-        CameraIntDisable
-#endif
-#ifdef ROM_CameraIntStatus
-#define MAP_CameraIntStatus \
-        ROM_CameraIntStatus
-#else
-#define MAP_CameraIntStatus \
-        CameraIntStatus
-#endif
-#ifdef ROM_CameraIntClear
-#define MAP_CameraIntClear \
-        ROM_CameraIntClear
-#else
-#define MAP_CameraIntClear \
-        CameraIntClear
-#endif
-#ifdef ROM_CameraCaptureStop
-#define MAP_CameraCaptureStop \
-        ROM_CameraCaptureStop
-#else
-#define MAP_CameraCaptureStop \
-        CameraCaptureStop
-#endif
-#ifdef ROM_CameraCaptureStart
-#define MAP_CameraCaptureStart \
-        ROM_CameraCaptureStart
-#else
-#define MAP_CameraCaptureStart \
-        CameraCaptureStart
-#endif
-#ifdef ROM_CameraBufferRead
-#define MAP_CameraBufferRead \
-        ROM_CameraBufferRead
-#else
-#define MAP_CameraBufferRead \
-        CameraBufferRead
-#endif
-
-//*****************************************************************************
-//
-// Macros for the FLASH API.
-//
-//*****************************************************************************
-#ifdef ROM_FlashDisable
-#define MAP_FlashDisable \
-        ROM_FlashDisable
-#else
-#define MAP_FlashDisable \
-        FlashDisable
-#endif
-#ifdef ROM_FlashErase
-#define MAP_FlashErase \
-        ROM_FlashErase
-#else
-#define MAP_FlashErase \
-        FlashErase
-#endif
-#ifdef ROM_FlashMassErase
-#define MAP_FlashMassErase \
-        ROM_FlashMassErase
-#else
-#define MAP_FlashMassErase \
-        FlashMassErase
-#endif
-#ifdef ROM_FlashMassEraseNonBlocking
-#define MAP_FlashMassEraseNonBlocking \
-        ROM_FlashMassEraseNonBlocking
-#else
-#define MAP_FlashMassEraseNonBlocking \
-        FlashMassEraseNonBlocking
-#endif
-#ifdef ROM_FlashEraseNonBlocking
-#define MAP_FlashEraseNonBlocking \
-        ROM_FlashEraseNonBlocking
-#else
-#define MAP_FlashEraseNonBlocking \
-        FlashEraseNonBlocking
-#endif
-#ifdef ROM_FlashProgram
-#define MAP_FlashProgram \
-        ROM_FlashProgram
-#else
-#define MAP_FlashProgram \
-        FlashProgram
-#endif
-#ifdef ROM_FlashProgramNonBlocking
-#define MAP_FlashProgramNonBlocking \
-        ROM_FlashProgramNonBlocking
-#else
-#define MAP_FlashProgramNonBlocking \
-        FlashProgramNonBlocking
-#endif
-#ifdef ROM_FlashIntRegister
-#define MAP_FlashIntRegister \
-        ROM_FlashIntRegister
-#else
-#define MAP_FlashIntRegister \
-        FlashIntRegister
-#endif
-#ifdef ROM_FlashIntUnregister
-#define MAP_FlashIntUnregister \
-        ROM_FlashIntUnregister
-#else
-#define MAP_FlashIntUnregister \
-        FlashIntUnregister
-#endif
-#ifdef ROM_FlashIntEnable
-#define MAP_FlashIntEnable \
-        ROM_FlashIntEnable
-#else
-#define MAP_FlashIntEnable \
-        FlashIntEnable
-#endif
-#ifdef ROM_FlashIntDisable
-#define MAP_FlashIntDisable \
-        ROM_FlashIntDisable
-#else
-#define MAP_FlashIntDisable \
-        FlashIntDisable
-#endif
-#ifdef ROM_FlashIntStatus
-#define MAP_FlashIntStatus \
-        ROM_FlashIntStatus
-#else
-#define MAP_FlashIntStatus \
-        FlashIntStatus
-#endif
-#ifdef ROM_FlashIntClear
-#define MAP_FlashIntClear \
-        ROM_FlashIntClear
-#else
-#define MAP_FlashIntClear \
-        FlashIntClear
-#endif
-#ifdef ROM_FlashProtectGet
-#define MAP_FlashProtectGet \
-        ROM_FlashProtectGet
-#else
-#define MAP_FlashProtectGet \
-        FlashProtectGet
-#endif
-
-//*****************************************************************************
-//
-// Macros for the Pin API.
-//
-//*****************************************************************************
-#ifdef ROM_PinModeSet
-#define MAP_PinModeSet \
-        ROM_PinModeSet
-#else
-#define MAP_PinModeSet \
-        PinModeSet
-#endif
-#ifdef ROM_PinDirModeSet
-#define MAP_PinDirModeSet \
-        ROM_PinDirModeSet
-#else
-#define MAP_PinDirModeSet \
-        PinDirModeSet
-#endif
-#ifdef ROM_PinDirModeGet
-#define MAP_PinDirModeGet \
-        ROM_PinDirModeGet
-#else
-#define MAP_PinDirModeGet \
-        PinDirModeGet
-#endif
-#ifdef ROM_PinModeGet
-#define MAP_PinModeGet \
-        ROM_PinModeGet
-#else
-#define MAP_PinModeGet \
-        PinModeGet
-#endif
-#ifdef ROM_PinConfigGet
-#define MAP_PinConfigGet \
-        ROM_PinConfigGet
-#else
-#define MAP_PinConfigGet \
-        PinConfigGet
-#endif
-#ifdef ROM_PinConfigSet
-#define MAP_PinConfigSet \
-        ROM_PinConfigSet
-#else
-#define MAP_PinConfigSet \
-        PinConfigSet
-#endif
-#ifdef ROM_PinTypeUART
-#define MAP_PinTypeUART \
-        ROM_PinTypeUART
-#else
-#define MAP_PinTypeUART \
-        PinTypeUART
-#endif
-#ifdef ROM_PinTypeI2C
-#define MAP_PinTypeI2C \
-        ROM_PinTypeI2C
-#else
-#define MAP_PinTypeI2C \
-        PinTypeI2C
-#endif
-#ifdef ROM_PinTypeSPI
-#define MAP_PinTypeSPI \
-        ROM_PinTypeSPI
-#else
-#define MAP_PinTypeSPI \
-        PinTypeSPI
-#endif
-#ifdef ROM_PinTypeI2S
-#define MAP_PinTypeI2S \
-        ROM_PinTypeI2S
-#else
-#define MAP_PinTypeI2S \
-        PinTypeI2S
-#endif
-#ifdef ROM_PinTypeTimer
-#define MAP_PinTypeTimer \
-        ROM_PinTypeTimer
-#else
-#define MAP_PinTypeTimer \
-        PinTypeTimer
-#endif
-#ifdef ROM_PinTypeCamera
-#define MAP_PinTypeCamera \
-        ROM_PinTypeCamera
-#else
-#define MAP_PinTypeCamera \
-        PinTypeCamera
-#endif
-#ifdef ROM_PinTypeGPIO
-#define MAP_PinTypeGPIO \
-        ROM_PinTypeGPIO
-#else
-#define MAP_PinTypeGPIO \
-        PinTypeGPIO
-#endif
-#ifdef ROM_PinTypeADC
-#define MAP_PinTypeADC \
-        ROM_PinTypeADC
-#else
-#define MAP_PinTypeADC \
-        PinTypeADC
-#endif
-#ifdef ROM_PinTypeSDHost
-#define MAP_PinTypeSDHost \
-        ROM_PinTypeSDHost
-#else
-#define MAP_PinTypeSDHost \
-        PinTypeSDHost
-#endif
-
-//*****************************************************************************
-//
-// Macros for the SYSTICK API.
-//
-//*****************************************************************************
-#ifdef ROM_SysTickEnable
-#define MAP_SysTickEnable \
-        ROM_SysTickEnable
-#else
-#define MAP_SysTickEnable \
-        SysTickEnable
-#endif
-#ifdef ROM_SysTickDisable
-#define MAP_SysTickDisable \
-        ROM_SysTickDisable
-#else
-#define MAP_SysTickDisable \
-        SysTickDisable
-#endif
-#ifdef ROM_SysTickIntRegister
-#define MAP_SysTickIntRegister \
-        ROM_SysTickIntRegister
-#else
-#define MAP_SysTickIntRegister \
-        SysTickIntRegister
-#endif
-#ifdef ROM_SysTickIntUnregister
-#define MAP_SysTickIntUnregister \
-        ROM_SysTickIntUnregister
-#else
-#define MAP_SysTickIntUnregister \
-        SysTickIntUnregister
-#endif
-#ifdef ROM_SysTickIntEnable
-#define MAP_SysTickIntEnable \
-        ROM_SysTickIntEnable
-#else
-#define MAP_SysTickIntEnable \
-        SysTickIntEnable
-#endif
-#ifdef ROM_SysTickIntDisable
-#define MAP_SysTickIntDisable \
-        ROM_SysTickIntDisable
-#else
-#define MAP_SysTickIntDisable \
-        SysTickIntDisable
-#endif
-#ifdef ROM_SysTickPeriodSet
-#define MAP_SysTickPeriodSet \
-        ROM_SysTickPeriodSet
-#else
-#define MAP_SysTickPeriodSet \
-        SysTickPeriodSet
-#endif
-#ifdef ROM_SysTickPeriodGet
-#define MAP_SysTickPeriodGet \
-        ROM_SysTickPeriodGet
-#else
-#define MAP_SysTickPeriodGet \
-        SysTickPeriodGet
-#endif
-#ifdef ROM_SysTickValueGet
-#define MAP_SysTickValueGet \
-        ROM_SysTickValueGet
-#else
-#define MAP_SysTickValueGet \
-        SysTickValueGet
-#endif
-
-//*****************************************************************************
-//
-// Macros for the UTILS API.
-//
-//*****************************************************************************
-#ifdef ROM_UtilsDelay
-#define MAP_UtilsDelay \
-        ROM_UtilsDelay
-#else
-#define MAP_UtilsDelay \
-        UtilsDelay
-#endif
-
-//*****************************************************************************
-//
-// Macros for the I2S API.
-//
-//*****************************************************************************
-#ifdef ROM_I2SEnable
-#define MAP_I2SEnable \
-        ROM_I2SEnable
-#else
-#define MAP_I2SEnable \
-        I2SEnable
-#endif
-#ifdef ROM_I2SDisable
-#define MAP_I2SDisable \
-        ROM_I2SDisable
-#else
-#define MAP_I2SDisable \
-        I2SDisable
-#endif
-#ifdef ROM_I2SDataPut
-#define MAP_I2SDataPut \
-        ROM_I2SDataPut
-#else
-#define MAP_I2SDataPut \
-        I2SDataPut
-#endif
-#ifdef ROM_I2SDataPutNonBlocking
-#define MAP_I2SDataPutNonBlocking \
-        ROM_I2SDataPutNonBlocking
-#else
-#define MAP_I2SDataPutNonBlocking \
-        I2SDataPutNonBlocking
-#endif
-#ifdef ROM_I2SDataGet
-#define MAP_I2SDataGet \
-        ROM_I2SDataGet
-#else
-#define MAP_I2SDataGet \
-        I2SDataGet
-#endif
-#ifdef ROM_I2SDataGetNonBlocking
-#define MAP_I2SDataGetNonBlocking \
-        ROM_I2SDataGetNonBlocking
-#else
-#define MAP_I2SDataGetNonBlocking \
-        I2SDataGetNonBlocking
-#endif
-#ifdef ROM_I2SConfigSetExpClk
-#define MAP_I2SConfigSetExpClk \
-        ROM_I2SConfigSetExpClk
-#else
-#define MAP_I2SConfigSetExpClk \
-        I2SConfigSetExpClk
-#endif
-#ifdef ROM_I2STxFIFOEnable
-#define MAP_I2STxFIFOEnable \
-        ROM_I2STxFIFOEnable
-#else
-#define MAP_I2STxFIFOEnable \
-        I2STxFIFOEnable
-#endif
-#ifdef ROM_I2STxFIFODisable
-#define MAP_I2STxFIFODisable \
-        ROM_I2STxFIFODisable
-#else
-#define MAP_I2STxFIFODisable \
-        I2STxFIFODisable
-#endif
-#ifdef ROM_I2SRxFIFOEnable
-#define MAP_I2SRxFIFOEnable \
-        ROM_I2SRxFIFOEnable
-#else
-#define MAP_I2SRxFIFOEnable \
-        I2SRxFIFOEnable
-#endif
-#ifdef ROM_I2SRxFIFODisable
-#define MAP_I2SRxFIFODisable \
-        ROM_I2SRxFIFODisable
-#else
-#define MAP_I2SRxFIFODisable \
-        I2SRxFIFODisable
-#endif
-#ifdef ROM_I2STxFIFOStatusGet
-#define MAP_I2STxFIFOStatusGet \
-        ROM_I2STxFIFOStatusGet
-#else
-#define MAP_I2STxFIFOStatusGet \
-        I2STxFIFOStatusGet
-#endif
-#ifdef ROM_I2SRxFIFOStatusGet
-#define MAP_I2SRxFIFOStatusGet \
-        ROM_I2SRxFIFOStatusGet
-#else
-#define MAP_I2SRxFIFOStatusGet \
-        I2SRxFIFOStatusGet
-#endif
-#ifdef ROM_I2SSerializerConfig
-#define MAP_I2SSerializerConfig \
-        ROM_I2SSerializerConfig
-#else
-#define MAP_I2SSerializerConfig \
-        I2SSerializerConfig
-#endif
-#ifdef ROM_I2SIntEnable
-#define MAP_I2SIntEnable \
-        ROM_I2SIntEnable
-#else
-#define MAP_I2SIntEnable \
-        I2SIntEnable
-#endif
-#ifdef ROM_I2SIntDisable
-#define MAP_I2SIntDisable \
-        ROM_I2SIntDisable
-#else
-#define MAP_I2SIntDisable \
-        I2SIntDisable
-#endif
-#ifdef ROM_I2SIntStatus
-#define MAP_I2SIntStatus \
-        ROM_I2SIntStatus
-#else
-#define MAP_I2SIntStatus \
-        I2SIntStatus
-#endif
-#ifdef ROM_I2SIntClear
-#define MAP_I2SIntClear \
-        ROM_I2SIntClear
-#else
-#define MAP_I2SIntClear \
-        I2SIntClear
-#endif
-#ifdef ROM_I2SIntRegister
-#define MAP_I2SIntRegister \
-        ROM_I2SIntRegister
-#else
-#define MAP_I2SIntRegister \
-        I2SIntRegister
-#endif
-#ifdef ROM_I2SIntUnregister
-#define MAP_I2SIntUnregister \
-        ROM_I2SIntUnregister
-#else
-#define MAP_I2SIntUnregister \
-        I2SIntUnregister
-#endif
-
-//*****************************************************************************
-//
-// Macros for the GPIO API.
-//
-//*****************************************************************************
-#ifdef ROM_GPIODirModeSet
-#define MAP_GPIODirModeSet \
-        ROM_GPIODirModeSet
-#else
-#define MAP_GPIODirModeSet \
-        GPIODirModeSet
-#endif
-#ifdef ROM_GPIODirModeGet
-#define MAP_GPIODirModeGet \
-        ROM_GPIODirModeGet
-#else
-#define MAP_GPIODirModeGet \
-        GPIODirModeGet
-#endif
-#ifdef ROM_GPIOIntTypeSet
-#define MAP_GPIOIntTypeSet \
-        ROM_GPIOIntTypeSet
-#else
-#define MAP_GPIOIntTypeSet \
-        GPIOIntTypeSet
-#endif
-#ifdef ROM_GPIODMATriggerEnable
-#define MAP_GPIODMATriggerEnable \
-        ROM_GPIODMATriggerEnable
-#else
-#define MAP_GPIODMATriggerEnable \
-        GPIODMATriggerEnable
-#endif
-#ifdef ROM_GPIODMATriggerDisable
-#define MAP_GPIODMATriggerDisable \
-        ROM_GPIODMATriggerDisable
-#else
-#define MAP_GPIODMATriggerDisable \
-        GPIODMATriggerDisable
-#endif
-#ifdef ROM_GPIOIntTypeGet
-#define MAP_GPIOIntTypeGet \
-        ROM_GPIOIntTypeGet
-#else
-#define MAP_GPIOIntTypeGet \
-        GPIOIntTypeGet
-#endif
-#ifdef ROM_GPIOIntEnable
-#define MAP_GPIOIntEnable \
-        ROM_GPIOIntEnable
-#else
-#define MAP_GPIOIntEnable \
-        GPIOIntEnable
-#endif
-#ifdef ROM_GPIOIntDisable
-#define MAP_GPIOIntDisable \
-        ROM_GPIOIntDisable
-#else
-#define MAP_GPIOIntDisable \
-        GPIOIntDisable
-#endif
-#ifdef ROM_GPIOIntStatus
-#define MAP_GPIOIntStatus \
-        ROM_GPIOIntStatus
-#else
-#define MAP_GPIOIntStatus \
-        GPIOIntStatus
-#endif
-#ifdef ROM_GPIOIntClear
-#define MAP_GPIOIntClear \
-        ROM_GPIOIntClear
-#else
-#define MAP_GPIOIntClear \
-        GPIOIntClear
-#endif
-#ifdef ROM_GPIOIntRegister
-#define MAP_GPIOIntRegister \
-        ROM_GPIOIntRegister
-#else
-#define MAP_GPIOIntRegister \
-        GPIOIntRegister
-#endif
-#ifdef ROM_GPIOIntUnregister
-#define MAP_GPIOIntUnregister \
-        ROM_GPIOIntUnregister
-#else
-#define MAP_GPIOIntUnregister \
-        GPIOIntUnregister
-#endif
-#ifdef ROM_GPIOPinRead
-#define MAP_GPIOPinRead \
-        ROM_GPIOPinRead
-#else
-#define MAP_GPIOPinRead \
-        GPIOPinRead
-#endif
-#ifdef ROM_GPIOPinWrite
-#define MAP_GPIOPinWrite \
-        ROM_GPIOPinWrite
-#else
-#define MAP_GPIOPinWrite \
-        GPIOPinWrite
-#endif
-
-//*****************************************************************************
-//
-// Macros for the AES API.
-//
-//*****************************************************************************
-#ifdef ROM_AESConfigSet
-#define MAP_AESConfigSet \
-        ROM_AESConfigSet
-#else
-#define MAP_AESConfigSet \
-        AESConfigSet
-#endif
-#ifdef ROM_AESKey1Set
-#define MAP_AESKey1Set \
-        ROM_AESKey1Set
-#else
-#define MAP_AESKey1Set \
-        AESKey1Set
-#endif
-#ifdef ROM_AESKey2Set
-#define MAP_AESKey2Set \
-        ROM_AESKey2Set
-#else
-#define MAP_AESKey2Set \
-        AESKey2Set
-#endif
-#ifdef ROM_AESKey3Set
-#define MAP_AESKey3Set \
-        ROM_AESKey3Set
-#else
-#define MAP_AESKey3Set \
-        AESKey3Set
-#endif
-#ifdef ROM_AESIVSet
-#define MAP_AESIVSet \
-        ROM_AESIVSet
-#else
-#define MAP_AESIVSet \
-        AESIVSet
-#endif
-#ifdef ROM_AESTagRead
-#define MAP_AESTagRead \
-        ROM_AESTagRead
-#else
-#define MAP_AESTagRead \
-        AESTagRead
-#endif
-#ifdef ROM_AESDataLengthSet
-#define MAP_AESDataLengthSet \
-        ROM_AESDataLengthSet
-#else
-#define MAP_AESDataLengthSet \
-        AESDataLengthSet
-#endif
-#ifdef ROM_AESAuthDataLengthSet
-#define MAP_AESAuthDataLengthSet \
-        ROM_AESAuthDataLengthSet
-#else
-#define MAP_AESAuthDataLengthSet \
-        AESAuthDataLengthSet
-#endif
-#ifdef ROM_AESDataReadNonBlocking
-#define MAP_AESDataReadNonBlocking \
-        ROM_AESDataReadNonBlocking
-#else
-#define MAP_AESDataReadNonBlocking \
-        AESDataReadNonBlocking
-#endif
-#ifdef ROM_AESDataRead
-#define MAP_AESDataRead \
-        ROM_AESDataRead
-#else
-#define MAP_AESDataRead \
-        AESDataRead
-#endif
-#ifdef ROM_AESDataWriteNonBlocking
-#define MAP_AESDataWriteNonBlocking \
-        ROM_AESDataWriteNonBlocking
-#else
-#define MAP_AESDataWriteNonBlocking \
-        AESDataWriteNonBlocking
-#endif
-#ifdef ROM_AESDataWrite
-#define MAP_AESDataWrite \
-        ROM_AESDataWrite
-#else
-#define MAP_AESDataWrite \
-        AESDataWrite
-#endif
-#ifdef ROM_AESDataProcess
-#define MAP_AESDataProcess \
-        ROM_AESDataProcess
-#else
-#define MAP_AESDataProcess \
-        AESDataProcess
-#endif
-#ifdef ROM_AESDataMAC
-#define MAP_AESDataMAC \
-        ROM_AESDataMAC
-#else
-#define MAP_AESDataMAC \
-        AESDataMAC
-#endif
-#ifdef ROM_AESDataProcessAE
-#define MAP_AESDataProcessAE \
-        ROM_AESDataProcessAE
-#else
-#define MAP_AESDataProcessAE \
-        AESDataProcessAE
-#endif
-#ifdef ROM_AESIntStatus
-#define MAP_AESIntStatus \
-        ROM_AESIntStatus
-#else
-#define MAP_AESIntStatus \
-        AESIntStatus
-#endif
-#ifdef ROM_AESIntEnable
-#define MAP_AESIntEnable \
-        ROM_AESIntEnable
-#else
-#define MAP_AESIntEnable \
-        AESIntEnable
-#endif
-#ifdef ROM_AESIntDisable
-#define MAP_AESIntDisable \
-        ROM_AESIntDisable
-#else
-#define MAP_AESIntDisable \
-        AESIntDisable
-#endif
-#ifdef ROM_AESIntClear
-#define MAP_AESIntClear \
-        ROM_AESIntClear
-#else
-#define MAP_AESIntClear \
-        AESIntClear
-#endif
-#ifdef ROM_AESIntRegister
-#define MAP_AESIntRegister \
-        ROM_AESIntRegister
-#else
-#define MAP_AESIntRegister \
-        AESIntRegister
-#endif
-#ifdef ROM_AESIntUnregister
-#define MAP_AESIntUnregister \
-        ROM_AESIntUnregister
-#else
-#define MAP_AESIntUnregister \
-        AESIntUnregister
-#endif
-#ifdef ROM_AESDMAEnable
-#define MAP_AESDMAEnable \
-        ROM_AESDMAEnable
-#else
-#define MAP_AESDMAEnable \
-        AESDMAEnable
-#endif
-#ifdef ROM_AESDMADisable
-#define MAP_AESDMADisable \
-        ROM_AESDMADisable
-#else
-#define MAP_AESDMADisable \
-        AESDMADisable
-#endif
-
-//*****************************************************************************
-//
-// Macros for the DES API.
-//
-//*****************************************************************************
-#ifdef ROM_DESConfigSet
-#define MAP_DESConfigSet \
-        ROM_DESConfigSet
-#else
-#define MAP_DESConfigSet \
-        DESConfigSet
-#endif
-#ifdef ROM_DESDataRead
-#define MAP_DESDataRead \
-        ROM_DESDataRead
-#else
-#define MAP_DESDataRead \
-        DESDataRead
-#endif
-#ifdef ROM_DESDataReadNonBlocking
-#define MAP_DESDataReadNonBlocking \
-        ROM_DESDataReadNonBlocking
-#else
-#define MAP_DESDataReadNonBlocking \
-        DESDataReadNonBlocking
-#endif
-#ifdef ROM_DESDataProcess
-#define MAP_DESDataProcess \
-        ROM_DESDataProcess
-#else
-#define MAP_DESDataProcess \
-        DESDataProcess
-#endif
-#ifdef ROM_DESDataWrite
-#define MAP_DESDataWrite \
-        ROM_DESDataWrite
-#else
-#define MAP_DESDataWrite \
-        DESDataWrite
-#endif
-#ifdef ROM_DESDataWriteNonBlocking
-#define MAP_DESDataWriteNonBlocking \
-        ROM_DESDataWriteNonBlocking
-#else
-#define MAP_DESDataWriteNonBlocking \
-        DESDataWriteNonBlocking
-#endif
-#ifdef ROM_DESDMADisable
-#define MAP_DESDMADisable \
-        ROM_DESDMADisable
-#else
-#define MAP_DESDMADisable \
-        DESDMADisable
-#endif
-#ifdef ROM_DESDMAEnable
-#define MAP_DESDMAEnable \
-        ROM_DESDMAEnable
-#else
-#define MAP_DESDMAEnable \
-        DESDMAEnable
-#endif
-#ifdef ROM_DESIntClear
-#define MAP_DESIntClear \
-        ROM_DESIntClear
-#else
-#define MAP_DESIntClear \
-        DESIntClear
-#endif
-#ifdef ROM_DESIntDisable
-#define MAP_DESIntDisable \
-        ROM_DESIntDisable
-#else
-#define MAP_DESIntDisable \
-        DESIntDisable
-#endif
-#ifdef ROM_DESIntEnable
-#define MAP_DESIntEnable \
-        ROM_DESIntEnable
-#else
-#define MAP_DESIntEnable \
-        DESIntEnable
-#endif
-#ifdef ROM_DESIntRegister
-#define MAP_DESIntRegister \
-        ROM_DESIntRegister
-#else
-#define MAP_DESIntRegister \
-        DESIntRegister
-#endif
-#ifdef ROM_DESIntStatus
-#define MAP_DESIntStatus \
-        ROM_DESIntStatus
-#else
-#define MAP_DESIntStatus \
-        DESIntStatus
-#endif
-#ifdef ROM_DESIntUnregister
-#define MAP_DESIntUnregister \
-        ROM_DESIntUnregister
-#else
-#define MAP_DESIntUnregister \
-        DESIntUnregister
-#endif
-#ifdef ROM_DESIVSet
-#define MAP_DESIVSet \
-        ROM_DESIVSet
-#else
-#define MAP_DESIVSet \
-        DESIVSet
-#endif
-#ifdef ROM_DESKeySet
-#define MAP_DESKeySet \
-        ROM_DESKeySet
-#else
-#define MAP_DESKeySet \
-        DESKeySet
-#endif
-#ifdef ROM_DESDataLengthSet
-#define MAP_DESDataLengthSet \
-        ROM_DESDataLengthSet
-#else
-#define MAP_DESDataLengthSet \
-        DESDataLengthSet
-#endif
-
-//*****************************************************************************
-//
-// Macros for the SHAMD5 API.
-//
-//*****************************************************************************
-#ifdef ROM_SHAMD5ConfigSet
-#define MAP_SHAMD5ConfigSet \
-        ROM_SHAMD5ConfigSet
-#else
-#define MAP_SHAMD5ConfigSet \
-        SHAMD5ConfigSet
-#endif
-#ifdef ROM_SHAMD5DataProcess
-#define MAP_SHAMD5DataProcess \
-        ROM_SHAMD5DataProcess
-#else
-#define MAP_SHAMD5DataProcess \
-        SHAMD5DataProcess
-#endif
-#ifdef ROM_SHAMD5DataWrite
-#define MAP_SHAMD5DataWrite \
-        ROM_SHAMD5DataWrite
-#else
-#define MAP_SHAMD5DataWrite \
-        SHAMD5DataWrite
-#endif
-#ifdef ROM_SHAMD5DataWriteNonBlocking
-#define MAP_SHAMD5DataWriteNonBlocking \
-        ROM_SHAMD5DataWriteNonBlocking
-#else
-#define MAP_SHAMD5DataWriteNonBlocking \
-        SHAMD5DataWriteNonBlocking
-#endif
-#ifdef ROM_SHAMD5DMADisable
-#define MAP_SHAMD5DMADisable \
-        ROM_SHAMD5DMADisable
-#else
-#define MAP_SHAMD5DMADisable \
-        SHAMD5DMADisable
-#endif
-#ifdef ROM_SHAMD5DMAEnable
-#define MAP_SHAMD5DMAEnable \
-        ROM_SHAMD5DMAEnable
-#else
-#define MAP_SHAMD5DMAEnable \
-        SHAMD5DMAEnable
-#endif
-#ifdef ROM_SHAMD5DataLengthSet
-#define MAP_SHAMD5DataLengthSet \
-        ROM_SHAMD5DataLengthSet
-#else
-#define MAP_SHAMD5DataLengthSet \
-        SHAMD5DataLengthSet
-#endif
-#ifdef ROM_SHAMD5HMACKeySet
-#define MAP_SHAMD5HMACKeySet \
-        ROM_SHAMD5HMACKeySet
-#else
-#define MAP_SHAMD5HMACKeySet \
-        SHAMD5HMACKeySet
-#endif
-#ifdef ROM_SHAMD5HMACPPKeyGenerate
-#define MAP_SHAMD5HMACPPKeyGenerate \
-        ROM_SHAMD5HMACPPKeyGenerate
-#else
-#define MAP_SHAMD5HMACPPKeyGenerate \
-        SHAMD5HMACPPKeyGenerate
-#endif
-#ifdef ROM_SHAMD5HMACPPKeySet
-#define MAP_SHAMD5HMACPPKeySet \
-        ROM_SHAMD5HMACPPKeySet
-#else
-#define MAP_SHAMD5HMACPPKeySet \
-        SHAMD5HMACPPKeySet
-#endif
-#ifdef ROM_SHAMD5HMACProcess
-#define MAP_SHAMD5HMACProcess \
-        ROM_SHAMD5HMACProcess
-#else
-#define MAP_SHAMD5HMACProcess \
-        SHAMD5HMACProcess
-#endif
-#ifdef ROM_SHAMD5IntClear
-#define MAP_SHAMD5IntClear \
-        ROM_SHAMD5IntClear
-#else
-#define MAP_SHAMD5IntClear \
-        SHAMD5IntClear
-#endif
-#ifdef ROM_SHAMD5IntDisable
-#define MAP_SHAMD5IntDisable \
-        ROM_SHAMD5IntDisable
-#else
-#define MAP_SHAMD5IntDisable \
-        SHAMD5IntDisable
-#endif
-#ifdef ROM_SHAMD5IntEnable
-#define MAP_SHAMD5IntEnable \
-        ROM_SHAMD5IntEnable
-#else
-#define MAP_SHAMD5IntEnable \
-        SHAMD5IntEnable
-#endif
-#ifdef ROM_SHAMD5IntRegister
-#define MAP_SHAMD5IntRegister \
-        ROM_SHAMD5IntRegister
-#else
-#define MAP_SHAMD5IntRegister \
-        SHAMD5IntRegister
-#endif
-#ifdef ROM_SHAMD5IntStatus
-#define MAP_SHAMD5IntStatus \
-        ROM_SHAMD5IntStatus
-#else
-#define MAP_SHAMD5IntStatus \
-        SHAMD5IntStatus
-#endif
-#ifdef ROM_SHAMD5IntUnregister
-#define MAP_SHAMD5IntUnregister \
-        ROM_SHAMD5IntUnregister
-#else
-#define MAP_SHAMD5IntUnregister \
-        SHAMD5IntUnregister
-#endif
-#ifdef ROM_SHAMD5ResultRead
-#define MAP_SHAMD5ResultRead \
-        ROM_SHAMD5ResultRead
-#else
-#define MAP_SHAMD5ResultRead \
-        SHAMD5ResultRead
-#endif
-
-//*****************************************************************************
-//
-// Macros for the CRC API.
-//
-//*****************************************************************************
-#ifdef ROM_CRCConfigSet
-#define MAP_CRCConfigSet \
-        ROM_CRCConfigSet
-#else
-#define MAP_CRCConfigSet \
-        CRCConfigSet
-#endif
-#ifdef ROM_CRCDataProcess
-#define MAP_CRCDataProcess \
-        ROM_CRCDataProcess
-#else
-#define MAP_CRCDataProcess \
-        CRCDataProcess
-#endif
-#ifdef ROM_CRCDataWrite
-#define MAP_CRCDataWrite \
-        ROM_CRCDataWrite
-#else
-#define MAP_CRCDataWrite \
-        CRCDataWrite
-#endif
-#ifdef ROM_CRCResultRead
-#define MAP_CRCResultRead \
-        ROM_CRCResultRead
-#else
-#define MAP_CRCResultRead \
-        CRCResultRead
-#endif
-#ifdef ROM_CRCSeedSet
-#define MAP_CRCSeedSet \
-        ROM_CRCSeedSet
-#else
-#define MAP_CRCSeedSet \
-        CRCSeedSet
-#endif
-
-//*****************************************************************************
-//
-// Macros for the SDHOST API.
-//
-//*****************************************************************************
-#ifdef ROM_SDHostCmdReset
-#define MAP_SDHostCmdReset \
-        ROM_SDHostCmdReset
-#else
-#define MAP_SDHostCmdReset \
-        SDHostCmdReset
-#endif
-#ifdef ROM_SDHostInit
-#define MAP_SDHostInit \
-        ROM_SDHostInit
-#else
-#define MAP_SDHostInit \
-        SDHostInit
-#endif
-#ifdef ROM_SDHostCmdSend
-#define MAP_SDHostCmdSend \
-        ROM_SDHostCmdSend
-#else
-#define MAP_SDHostCmdSend \
-        SDHostCmdSend
-#endif
-#ifdef ROM_SDHostIntRegister
-#define MAP_SDHostIntRegister \
-        ROM_SDHostIntRegister
-#else
-#define MAP_SDHostIntRegister \
-        SDHostIntRegister
-#endif
-#ifdef ROM_SDHostIntUnregister
-#define MAP_SDHostIntUnregister \
-        ROM_SDHostIntUnregister
-#else
-#define MAP_SDHostIntUnregister \
-        SDHostIntUnregister
-#endif
-#ifdef ROM_SDHostIntEnable
-#define MAP_SDHostIntEnable \
-        ROM_SDHostIntEnable
-#else
-#define MAP_SDHostIntEnable \
-        SDHostIntEnable
-#endif
-#ifdef ROM_SDHostIntDisable
-#define MAP_SDHostIntDisable \
-        ROM_SDHostIntDisable
-#else
-#define MAP_SDHostIntDisable \
-        SDHostIntDisable
-#endif
-#ifdef ROM_SDHostIntStatus
-#define MAP_SDHostIntStatus \
-        ROM_SDHostIntStatus
-#else
-#define MAP_SDHostIntStatus \
-        SDHostIntStatus
-#endif
-#ifdef ROM_SDHostIntClear
-#define MAP_SDHostIntClear \
-        ROM_SDHostIntClear
-#else
-#define MAP_SDHostIntClear \
-        SDHostIntClear
-#endif
-#ifdef ROM_SDHostRespStatus
-#define MAP_SDHostRespStatus \
-        ROM_SDHostRespStatus
-#else
-#define MAP_SDHostRespStatus \
-        SDHostRespStatus
-#endif
-#ifdef ROM_SDHostRespGet
-#define MAP_SDHostRespGet \
-        ROM_SDHostRespGet
-#else
-#define MAP_SDHostRespGet \
-        SDHostRespGet
-#endif
-#ifdef ROM_SDHostBlockSizeSet
-#define MAP_SDHostBlockSizeSet \
-        ROM_SDHostBlockSizeSet
-#else
-#define MAP_SDHostBlockSizeSet \
-        SDHostBlockSizeSet
-#endif
-#ifdef ROM_SDHostBlockCountSet
-#define MAP_SDHostBlockCountSet \
-        ROM_SDHostBlockCountSet
-#else
-#define MAP_SDHostBlockCountSet \
-        SDHostBlockCountSet
-#endif
-#ifdef ROM_SDHostDataNonBlockingWrite
-#define MAP_SDHostDataNonBlockingWrite \
-        ROM_SDHostDataNonBlockingWrite
-#else
-#define MAP_SDHostDataNonBlockingWrite \
-        SDHostDataNonBlockingWrite
-#endif
-#ifdef ROM_SDHostDataNonBlockingRead
-#define MAP_SDHostDataNonBlockingRead \
-        ROM_SDHostDataNonBlockingRead
-#else
-#define MAP_SDHostDataNonBlockingRead \
-        SDHostDataNonBlockingRead
-#endif
-#ifdef ROM_SDHostDataWrite
-#define MAP_SDHostDataWrite \
-        ROM_SDHostDataWrite
-#else
-#define MAP_SDHostDataWrite \
-        SDHostDataWrite
-#endif
-#ifdef ROM_SDHostDataRead
-#define MAP_SDHostDataRead \
-        ROM_SDHostDataRead
-#else
-#define MAP_SDHostDataRead \
-        SDHostDataRead
-#endif
-#ifdef ROM_SDHostSetExpClk
-#define MAP_SDHostSetExpClk \
-        ROM_SDHostSetExpClk
-#else
-#define MAP_SDHostSetExpClk \
-        SDHostSetExpClk
-#endif
-
-//*****************************************************************************
-//
-// Macros for the PRCM API.
-//
-//*****************************************************************************
-#ifdef ROM_PRCMMCUReset
-#define MAP_PRCMMCUReset \
-        ROM_PRCMMCUReset
-#else
-#define MAP_PRCMMCUReset \
-        PRCMMCUReset
-#endif
-#ifdef ROM_PRCMSysResetCauseGet
-#define MAP_PRCMSysResetCauseGet \
-        ROM_PRCMSysResetCauseGet
-#else
-#define MAP_PRCMSysResetCauseGet \
-        PRCMSysResetCauseGet
-#endif
-#ifdef ROM_PRCMPeripheralClkEnable
-#define MAP_PRCMPeripheralClkEnable \
-        ROM_PRCMPeripheralClkEnable
-#else
-#define MAP_PRCMPeripheralClkEnable \
-        PRCMPeripheralClkEnable
-#endif
-#ifdef ROM_PRCMPeripheralClkDisable
-#define MAP_PRCMPeripheralClkDisable \
-        ROM_PRCMPeripheralClkDisable
-#else
-#define MAP_PRCMPeripheralClkDisable \
-        PRCMPeripheralClkDisable
-#endif
-#ifdef ROM_PRCMPeripheralReset
-#define MAP_PRCMPeripheralReset \
-        ROM_PRCMPeripheralReset
-#else
-#define MAP_PRCMPeripheralReset \
-        PRCMPeripheralReset
-#endif
-#ifdef ROM_PRCMPeripheralStatusGet
-#define MAP_PRCMPeripheralStatusGet \
-        ROM_PRCMPeripheralStatusGet
-#else
-#define MAP_PRCMPeripheralStatusGet \
-        PRCMPeripheralStatusGet
-#endif
-#ifdef ROM_PRCMI2SClockFreqSet
-#define MAP_PRCMI2SClockFreqSet \
-        ROM_PRCMI2SClockFreqSet
-#else
-#define MAP_PRCMI2SClockFreqSet \
-        PRCMI2SClockFreqSet
-#endif
-#ifdef ROM_PRCMPeripheralClockGet
-#define MAP_PRCMPeripheralClockGet \
-        ROM_PRCMPeripheralClockGet
-#else
-#define MAP_PRCMPeripheralClockGet \
-        PRCMPeripheralClockGet
-#endif
-#ifdef ROM_PRCMSleepEnter
-#define MAP_PRCMSleepEnter \
-        ROM_PRCMSleepEnter
-#else
-#define MAP_PRCMSleepEnter \
-        PRCMSleepEnter
-#endif
-#ifdef ROM_PRCMDeepSleepEnter
-#define MAP_PRCMDeepSleepEnter \
-        ROM_PRCMDeepSleepEnter
-#else
-#define MAP_PRCMDeepSleepEnter \
-        PRCMDeepSleepEnter
-#endif
-#ifdef ROM_PRCMSRAMRetentionEnable
-#define MAP_PRCMSRAMRetentionEnable \
-        ROM_PRCMSRAMRetentionEnable
-#else
-#define MAP_PRCMSRAMRetentionEnable \
-        PRCMSRAMRetentionEnable
-#endif
-#ifdef ROM_PRCMSRAMRetentionDisable
-#define MAP_PRCMSRAMRetentionDisable \
-        ROM_PRCMSRAMRetentionDisable
-#else
-#define MAP_PRCMSRAMRetentionDisable \
-        PRCMSRAMRetentionDisable
-#endif
-#ifdef ROM_PRCMLPDSEnter
-#define MAP_PRCMLPDSEnter \
-        ROM_PRCMLPDSEnter
-#else
-#define MAP_PRCMLPDSEnter \
-        PRCMLPDSEnter
-#endif
-#ifdef ROM_PRCMLPDSIntervalSet
-#define MAP_PRCMLPDSIntervalSet \
-        ROM_PRCMLPDSIntervalSet
-#else
-#define MAP_PRCMLPDSIntervalSet \
-        PRCMLPDSIntervalSet
-#endif
-#ifdef ROM_PRCMLPDSWakeupSourceEnable
-#define MAP_PRCMLPDSWakeupSourceEnable \
-        ROM_PRCMLPDSWakeupSourceEnable
-#else
-#define MAP_PRCMLPDSWakeupSourceEnable \
-        PRCMLPDSWakeupSourceEnable
-#endif
-#ifdef ROM_PRCMLPDSWakeupCauseGet
-#define MAP_PRCMLPDSWakeupCauseGet \
-        ROM_PRCMLPDSWakeupCauseGet
-#else
-#define MAP_PRCMLPDSWakeupCauseGet \
-        PRCMLPDSWakeupCauseGet
-#endif
-#ifdef ROM_PRCMLPDSWakeUpGPIOSelect
-#define MAP_PRCMLPDSWakeUpGPIOSelect \
-        ROM_PRCMLPDSWakeUpGPIOSelect
-#else
-#define MAP_PRCMLPDSWakeUpGPIOSelect \
-        PRCMLPDSWakeUpGPIOSelect
-#endif
-#ifdef ROM_PRCMLPDSWakeupSourceDisable
-#define MAP_PRCMLPDSWakeupSourceDisable \
-        ROM_PRCMLPDSWakeupSourceDisable
-#else
-#define MAP_PRCMLPDSWakeupSourceDisable \
-        PRCMLPDSWakeupSourceDisable
-#endif
-#ifdef ROM_PRCMHibernateEnter
-#define MAP_PRCMHibernateEnter \
-        ROM_PRCMHibernateEnter
-#else
-#define MAP_PRCMHibernateEnter \
-        PRCMHibernateEnter
-#endif
-#ifdef ROM_PRCMHibernateWakeupSourceEnable
-#define MAP_PRCMHibernateWakeupSourceEnable \
-        ROM_PRCMHibernateWakeupSourceEnable
-#else
-#define MAP_PRCMHibernateWakeupSourceEnable \
-        PRCMHibernateWakeupSourceEnable
-#endif
-#ifdef ROM_PRCMHibernateWakeupCauseGet
-#define MAP_PRCMHibernateWakeupCauseGet \
-        ROM_PRCMHibernateWakeupCauseGet
-#else
-#define MAP_PRCMHibernateWakeupCauseGet \
-        PRCMHibernateWakeupCauseGet
-#endif
-#ifdef ROM_PRCMHibernateWakeUpGPIOSelect
-#define MAP_PRCMHibernateWakeUpGPIOSelect \
-        ROM_PRCMHibernateWakeUpGPIOSelect
-#else
-#define MAP_PRCMHibernateWakeUpGPIOSelect \
-        PRCMHibernateWakeUpGPIOSelect
-#endif
-#ifdef ROM_PRCMHibernateWakeupSourceDisable
-#define MAP_PRCMHibernateWakeupSourceDisable \
-        ROM_PRCMHibernateWakeupSourceDisable
-#else
-#define MAP_PRCMHibernateWakeupSourceDisable \
-        PRCMHibernateWakeupSourceDisable
-#endif
-#ifdef ROM_PRCMHibernateIntervalSet
-#define MAP_PRCMHibernateIntervalSet \
-        ROM_PRCMHibernateIntervalSet
-#else
-#define MAP_PRCMHibernateIntervalSet \
-        PRCMHibernateIntervalSet
-#endif
-#ifdef ROM_PRCMSlowClkCtrGet
-#define MAP_PRCMSlowClkCtrGet \
-        ROM_PRCMSlowClkCtrGet
-#else
-#define MAP_PRCMSlowClkCtrGet \
-        PRCMSlowClkCtrGet
-#endif
-#ifdef ROM_PRCMSlowClkCtrMatchSet
-#define MAP_PRCMSlowClkCtrMatchSet \
-        ROM_PRCMSlowClkCtrMatchSet
-#else
-#define MAP_PRCMSlowClkCtrMatchSet \
-        PRCMSlowClkCtrMatchSet
-#endif
-#ifdef ROM_PRCMSlowClkCtrMatchGet
-#define MAP_PRCMSlowClkCtrMatchGet \
-        ROM_PRCMSlowClkCtrMatchGet
-#else
-#define MAP_PRCMSlowClkCtrMatchGet \
-        PRCMSlowClkCtrMatchGet
-#endif
-#ifdef ROM_PRCMOCRRegisterWrite
-#define MAP_PRCMOCRRegisterWrite \
-        ROM_PRCMOCRRegisterWrite
-#else
-#define MAP_PRCMOCRRegisterWrite \
-        PRCMOCRRegisterWrite
-#endif
-#ifdef ROM_PRCMOCRRegisterRead
-#define MAP_PRCMOCRRegisterRead \
-        ROM_PRCMOCRRegisterRead
-#else
-#define MAP_PRCMOCRRegisterRead \
-        PRCMOCRRegisterRead
-#endif
-#ifdef ROM_PRCMIntRegister
-#define MAP_PRCMIntRegister \
-        ROM_PRCMIntRegister
-#else
-#define MAP_PRCMIntRegister \
-        PRCMIntRegister
-#endif
-#ifdef ROM_PRCMIntUnregister
-#define MAP_PRCMIntUnregister \
-        ROM_PRCMIntUnregister
-#else
-#define MAP_PRCMIntUnregister \
-        PRCMIntUnregister
-#endif
-#ifdef ROM_PRCMIntEnable
-#define MAP_PRCMIntEnable \
-        ROM_PRCMIntEnable
-#else
-#define MAP_PRCMIntEnable \
-        PRCMIntEnable
-#endif
-#ifdef ROM_PRCMIntDisable
-#define MAP_PRCMIntDisable \
-        ROM_PRCMIntDisable
-#else
-#define MAP_PRCMIntDisable \
-        PRCMIntDisable
-#endif
-#ifdef ROM_PRCMIntStatus
-#define MAP_PRCMIntStatus \
-        ROM_PRCMIntStatus
-#else
-#define MAP_PRCMIntStatus \
-        PRCMIntStatus
-#endif
-#ifdef ROM_PRCMRTCInUseSet
-#define MAP_PRCMRTCInUseSet \
-        ROM_PRCMRTCInUseSet
-#else
-#define MAP_PRCMRTCInUseSet \
-        PRCMRTCInUseSet
-#endif
-#ifdef ROM_PRCMRTCInUseGet
-#define MAP_PRCMRTCInUseGet \
-        ROM_PRCMRTCInUseGet
-#else
-#define MAP_PRCMRTCInUseGet \
-        PRCMRTCInUseGet
-#endif
-#ifdef ROM_PRCMRTCSet
-#define MAP_PRCMRTCSet \
-        ROM_PRCMRTCSet
-#else
-#define MAP_PRCMRTCSet \
-        PRCMRTCSet
-#endif
-#ifdef ROM_PRCMRTCGet
-#define MAP_PRCMRTCGet \
-        ROM_PRCMRTCGet
-#else
-#define MAP_PRCMRTCGet \
-        PRCMRTCGet
-#endif
-#ifdef ROM_PRCMRTCMatchSet
-#define MAP_PRCMRTCMatchSet \
-        ROM_PRCMRTCMatchSet
-#else
-#define MAP_PRCMRTCMatchSet \
-        PRCMRTCMatchSet
-#endif
-#ifdef ROM_PRCMRTCMatchGet
-#define MAP_PRCMRTCMatchGet \
-        ROM_PRCMRTCMatchGet
-#else
-#define MAP_PRCMRTCMatchGet \
-        PRCMRTCMatchGet
-#endif
-#ifdef ROM_PRCMLPDSRestoreInfoSet
-#define MAP_PRCMLPDSRestoreInfoSet \
-        ROM_PRCMLPDSRestoreInfoSet
-#else
-#define MAP_PRCMLPDSRestoreInfoSet \
-        PRCMLPDSRestoreInfoSet
-#endif
-
-#ifdef ROM_PRCMHIBRegRead
-#define MAP_PRCMHIBRegRead \
-        ROM_PRCMHIBRegRead
-#else
-#define MAP_PRCMHIBRegRead \
-        PRCMHIBRegRead
-#endif
-
-#ifdef ROM_PRCMHIBRegWrite
-#define MAP_PRCMHIBRegWrite \
-        ROM_PRCMHIBRegWrite
-#else
-#define MAP_PRCMHIBRegWrite \
-        PRCMHIBRegWrite
-#endif
-
-//*****************************************************************************
-//
-// Macros for the HWSPINLOCK API.
-//
-//*****************************************************************************
-#ifdef ROM_HwSpinLockAcquire
-#define MAP_HwSpinLockAcquire \
-        ROM_HwSpinLockAcquire
-#else
-#define MAP_HwSpinLockAcquire \
-        HwSpinLockAcquire
-#endif
-#ifdef ROM_HwSpinLockTryAcquire
-#define MAP_HwSpinLockTryAcquire \
-        ROM_HwSpinLockTryAcquire
-#else
-#define MAP_HwSpinLockTryAcquire \
-        HwSpinLockTryAcquire
-#endif
-#ifdef ROM_HwSpinLockRelease
-#define MAP_HwSpinLockRelease \
-        ROM_HwSpinLockRelease
-#else
-#define MAP_HwSpinLockRelease \
-        HwSpinLockRelease
-#endif
-#ifdef ROM_HwSpinLockTest
-#define MAP_HwSpinLockTest \
-        ROM_HwSpinLockTest
-#else
-#define MAP_HwSpinLockTest \
-        HwSpinLockTest
-#endif
-
-//*****************************************************************************
-//
-// Macros for the ADC API.
-//
-//*****************************************************************************
-#ifdef ROM_ADCEnable
-#define MAP_ADCEnable \
-        ROM_ADCEnable
-#else
-#define MAP_ADCEnable \
-        ADCEnable
-#endif
-#ifdef ROM_ADCDisable
-#define MAP_ADCDisable \
-        ROM_ADCDisable
-#else
-#define MAP_ADCDisable \
-        ADCDisable
-#endif
-#ifdef ROM_ADCChannelEnable
-#define MAP_ADCChannelEnable \
-        ROM_ADCChannelEnable
-#else
-#define MAP_ADCChannelEnable \
-        ADCChannelEnable
-#endif
-#ifdef ROM_ADCChannelDisable
-#define MAP_ADCChannelDisable \
-        ROM_ADCChannelDisable
-#else
-#define MAP_ADCChannelDisable \
-        ADCChannelDisable
-#endif
-#ifdef ROM_ADCIntRegister
-#define MAP_ADCIntRegister \
-        ROM_ADCIntRegister
-#else
-#define MAP_ADCIntRegister \
-        ADCIntRegister
-#endif
-#ifdef ROM_ADCIntUnregister
-#define MAP_ADCIntUnregister \
-        ROM_ADCIntUnregister
-#else
-#define MAP_ADCIntUnregister \
-        ADCIntUnregister
-#endif
-#ifdef ROM_ADCIntEnable
-#define MAP_ADCIntEnable \
-        ROM_ADCIntEnable
-#else
-#define MAP_ADCIntEnable \
-        ADCIntEnable
-#endif
-#ifdef ROM_ADCIntDisable
-#define MAP_ADCIntDisable \
-        ROM_ADCIntDisable
-#else
-#define MAP_ADCIntDisable \
-        ADCIntDisable
-#endif
-#ifdef ROM_ADCIntStatus
-#define MAP_ADCIntStatus \
-        ROM_ADCIntStatus
-#else
-#define MAP_ADCIntStatus \
-        ADCIntStatus
-#endif
-#ifdef ROM_ADCIntClear
-#define MAP_ADCIntClear \
-        ROM_ADCIntClear
-#else
-#define MAP_ADCIntClear \
-        ADCIntClear
-#endif
-#ifdef ROM_ADCDMAEnable
-#define MAP_ADCDMAEnable \
-        ROM_ADCDMAEnable
-#else
-#define MAP_ADCDMAEnable \
-        ADCDMAEnable
-#endif
-#ifdef ROM_ADCDMADisable
-#define MAP_ADCDMADisable \
-        ROM_ADCDMADisable
-#else
-#define MAP_ADCDMADisable \
-        ADCDMADisable
-#endif
-#ifdef ROM_ADCChannelGainSet
-#define MAP_ADCChannelGainSet \
-        ROM_ADCChannelGainSet
-#else
-#define MAP_ADCChannelGainSet \
-        ADCChannelGainSet
-#endif
-#ifdef ROM_ADCChannleGainGet
-#define MAP_ADCChannleGainGet \
-        ROM_ADCChannleGainGet
-#else
-#define MAP_ADCChannleGainGet \
-        ADCChannleGainGet
-#endif
-#ifdef ROM_ADCTimerConfig
-#define MAP_ADCTimerConfig \
-        ROM_ADCTimerConfig
-#else
-#define MAP_ADCTimerConfig \
-        ADCTimerConfig
-#endif
-#ifdef ROM_ADCTimerEnable
-#define MAP_ADCTimerEnable \
-        ROM_ADCTimerEnable
-#else
-#define MAP_ADCTimerEnable \
-        ADCTimerEnable
-#endif
-#ifdef ROM_ADCTimerDisable
-#define MAP_ADCTimerDisable \
-        ROM_ADCTimerDisable
-#else
-#define MAP_ADCTimerDisable \
-        ADCTimerDisable
-#endif
-#ifdef ROM_ADCTimerReset
-#define MAP_ADCTimerReset \
-        ROM_ADCTimerReset
-#else
-#define MAP_ADCTimerReset \
-        ADCTimerReset
-#endif
-#ifdef ROM_ADCTimerValueGet
-#define MAP_ADCTimerValueGet \
-        ROM_ADCTimerValueGet
-#else
-#define MAP_ADCTimerValueGet \
-        ADCTimerValueGet
-#endif
-#ifdef ROM_ADCFIFOLvlGet
-#define MAP_ADCFIFOLvlGet \
-        ROM_ADCFIFOLvlGet
-#else
-#define MAP_ADCFIFOLvlGet \
-        ADCFIFOLvlGet
-#endif
-#ifdef ROM_ADCFIFORead
-#define MAP_ADCFIFORead \
-        ROM_ADCFIFORead
-#else
-#define MAP_ADCFIFORead \
-        ADCFIFORead
-#endif
-
-#endif // __ROM_MAP_H__
diff --git a/cc3200/hal/rom_patch.h b/cc3200/hal/rom_patch.h
deleted file mode 100644
index 9fb8017f8..000000000
--- a/cc3200/hal/rom_patch.h
+++ /dev/null
@@ -1,98 +0,0 @@
-//*****************************************************************************
-//
-//  rom_patch.h
-//
-//  Macros to facilitate patching driverlib API's in the ROM.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-// List of API's in the ROM that need to be patched.
-// For e.g. to patch ROM_UARTCharPut add the line #undef ROM_UARTCharPut
-//*****************************************************************************
-#undef ROM_ADCIntClear
-#undef ROM_IntEnable
-#undef ROM_IntDisable
-#undef ROM_IntPendSet
-#undef ROM_SDHostCardErrorMaskSet
-#undef ROM_SDHostCardErrorMaskGet
-#undef ROM_TimerConfigure
-#undef ROM_TimerDMAEventSet
-#undef ROM_TimerDMAEventGet
-#undef ROM_SDHostDataNonBlockingWrite
-#undef ROM_SDHostDataWrite
-#undef ROM_SDHostDataRead
-#undef ROM_SDHostDataNonBlockingRead
-#undef ROM_PRCMSysResetCauseGet
-#undef ROM_PRCMPeripheralClkEnable
-#undef ROM_PRCMLPDSWakeUpGPIOSelect
-#undef ROM_PRCMHibernateWakeupSourceEnable
-#undef ROM_PRCMHibernateWakeupSourceDisable
-#undef ROM_PRCMHibernateWakeupCauseGet
-#undef ROM_PRCMHibernateIntervalSet
-#undef ROM_PRCMHibernateWakeUpGPIOSelect
-#undef ROM_PRCMHibernateEnter
-#undef ROM_PRCMSlowClkCtrGet
-#undef ROM_PRCMSlowClkCtrMatchSet
-#undef ROM_PRCMSlowClkCtrMatchGet
-#undef ROM_PRCMOCRRegisterWrite
-#undef ROM_PRCMOCRRegisterRead
-#undef ROM_PRCMIntEnable
-#undef ROM_PRCMIntDisable
-#undef ROM_PRCMRTCInUseSet
-#undef ROM_PRCMRTCInUseGet
-#undef ROM_PRCMRTCSet
-#undef ROM_PRCMRTCGet
-#undef ROM_PRCMRTCMatchSet
-#undef ROM_PRCMRTCMatchGet
-#undef ROM_PRCMPeripheralClkDisable
-#undef ROM_PRCMPeripheralReset
-#undef ROM_PRCMPeripheralStatusGet
-#undef ROM_SPIConfigSetExpClk
-#undef ROM_GPIODirModeGet
-#undef ROM_GPIOIntTypeGet
-#undef ROM_I2CMasterInitExpClk
-#undef ROM_AESDataProcess
-#undef ROM_DESDataProcess
-#undef ROM_I2SEnable
-#undef ROM_I2SConfigSetExpClk
-#undef ROM_PinConfigSet
-#undef ROM_PRCMLPDSEnter
-#undef ROM_PRCMCC3200MCUInit
-#undef ROM_SDHostIntStatus
-#undef ROM_SDHostBlockCountSet
-#undef ROM_UARTModemControlSet
-#undef ROM_UARTModemControlClear
-
diff --git a/cc3200/hal/sdhost.c b/cc3200/hal/sdhost.c
deleted file mode 100644
index ba98e359e..000000000
--- a/cc3200/hal/sdhost.c
+++ /dev/null
@@ -1,744 +0,0 @@
-//*****************************************************************************
-//
-//  sdhost.c
-//
-//  Driver for the SD Host (SDHost) Interface
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup Secure_Digital_Host_api
-//! @{
-//
-//*****************************************************************************
-
-#include "inc/hw_types.h"
-#include "inc/hw_memmap.h"
-#include "inc/hw_mmchs.h"
-#include "inc/hw_ints.h"
-#include "inc/hw_apps_config.h"
-#include "interrupt.h"
-#include "sdhost.h"
-
-
-//*****************************************************************************
-//
-//! Configures SDHost module.
-//!
-//! \param ulBase is the base address of SDHost module.
-//!
-//! This function configures the SDHost module, enabling internal sub-modules.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SDHostInit(unsigned long ulBase)
-{
-  //
-  // Assert module reset
-  //
-  HWREG(ulBase + MMCHS_O_SYSCONFIG) = 0x2;
-
-  //
-  // Wait for soft reset to complete
-  //
-  while( !(HWREG(ulBase + MMCHS_O_SYSCONFIG) & 0x1) )
-  {
-
-  }
-
-  //
-  // Assert internal reset
-  //
-  HWREG(ulBase + MMCHS_O_SYSCTL) |= (1 << 24);
-
-  //
-  // Wait for Reset to complete
-  //
-  while( (HWREG(ulBase + MMCHS_O_SYSCTL) & (0x1 << 24)) )
-  {
-
-  }
-
-  //
-  // Set capability register, 1.8 and 3.0 V
-  //
-  HWREG(ulBase + MMCHS_O_CAPA) = (0x7 <<24);
-
-  //
-  // Select bus voltage, 3.0 V
-  //
-  HWREG(ulBase + MMCHS_O_HCTL) |= 0x7 << 9;
-
-  //
-  // Power up the bus
-  //
-  HWREG(ulBase + MMCHS_O_HCTL) |= 1 << 8;
-
-  //
-  // Wait for power on
-  //
-  while( !(HWREG(ulBase + MMCHS_O_HCTL) & (1<<8)) )
-  {
-
-  }
-
-  HWREG(ulBase + MMCHS_O_CON) |= 1 << 21;
-
-  //
-  // Un-mask all events
-  //
-  HWREG(ulBase + MMCHS_O_IE) = 0xFFFFFFFF;
-}
-
-
-//*****************************************************************************
-//
-//! Resets SDHost command line
-//!
-//! \param ulBase is the base address of SDHost module.
-//!
-//! This function assers a soft reset for the command line
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SDHostCmdReset(unsigned long ulBase)
-{
-  HWREG(ulBase + MMCHS_O_SYSCTL) |= 1 << 25;
-  while( (HWREG(ulBase + MMCHS_O_SYSCTL) & (1 << 25)) )
-  {
-
-  }
-}
-
-//*****************************************************************************
-//
-//! Sends command over SDHost interface
-//!
-//! \param ulBase is the base address of SDHost module.
-//! \param ulCmd is the command to send.
-//! \param ulArg is the argument for the command.
-//!
-//! This function send command to the attached card over the SDHost interface.
-//!
-//! The \e ulCmd parameter can be one of \b SDHOST_CMD_0 to \b SDHOST_CMD_63.
-//! It can be logically ORed with one or more of the following:
-//! - \b SDHOST_MULTI_BLK for multi-block transfer
-//! - \b SDHOST_WR_CMD          if command is followed by write data
-//! - \b SDHOST_RD_CMD          if command is followed by read data
-//! - \b SDHOST_DMA_EN          if SDHost need to generate DMA request.
-//! - \b SDHOST_RESP_LEN_136    if 136 bit response is expected
-//! - \b SDHOST_RESP_LEN_48     if 48 bit response is expected
-//! - \b SDHOST_RESP_LEN_48B    if 48 bit response with busy bit is expected
-//!
-//! The parameter \e ulArg is the argument for the command
-//!
-//! \return Returns 0 on success, -1 otherwise.
-//
-//*****************************************************************************
-long
-SDHostCmdSend(unsigned long ulBase, unsigned long ulCmd, unsigned ulArg)
-{
-  //
-  // Set Data Timeout
-  //
-  HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x000E0000;
-
-  //
-  // Check for cmd inhabit
-  //
-  if( (HWREG(ulBase + MMCHS_O_PSTATE) & 0x1))
-  {
-    return -1;
-  }
-
-  //
-  // Set the argument
-  //
-  HWREG(ulBase + MMCHS_O_ARG) = ulArg;
-
-  //
-  // Send the command
-  //
-  HWREG(ulBase + MMCHS_O_CMD) = ulCmd;
-
-  return 0;
-}
-
-//*****************************************************************************
-//
-//! Writes a data word into the SDHost write buffer.
-//!
-//! \param ulBase is the base address of SDHost module.
-//! \param ulData is data word to be transfered.
-//!
-//! This function writes a single data word into the SDHost write buffer. The
-//! function returns \b true if there was a space available in the buffer else
-//! returns \b false.
-//!
-//! \return Return \b true on success, \b false otherwise.
-//
-//*****************************************************************************
-tBoolean
-SDHostDataNonBlockingWrite(unsigned long ulBase, unsigned long ulData)
-{
-
-  //
-  // See if there is a space in the write buffer
-  //
-  if( (HWREG(ulBase + MMCHS_O_PSTATE) & (1<<10)) )
-  {
-    //
-    // Write the data into the buffer
-    //
-    HWREG(ulBase + MMCHS_O_DATA) = ulData;
-
-    //
-    // Success.
-    //
-    return(true);
-  }
-  else
-  {
-    //
-    // No free sapce, failure.
-    //
-    return(false);
-  }
-}
-
-//*****************************************************************************
-//
-//! Waits to write a data word into the SDHost write buffer.
-//!
-//! \param ulBase is the base address of SDHost module.
-//! \param ulData is data word to be transfered.
-//!
-//! This function writes \e ulData into the SDHost write buffer. If there is no
-//! space in the write buffer this function waits until there is a space
-//! available before returning.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SDHostDataWrite(unsigned long ulBase, unsigned long ulData)
-{
-  //
-  // Wait until space is available
-  //
-  while( !(HWREG(ulBase + MMCHS_O_PSTATE) & (1<<10)) )
-  {
-
-  }
-
-  //
-  // Write the data
-  //
-  HWREG(ulBase + MMCHS_O_DATA) = ulData;
-}
-
-
-//*****************************************************************************
-//
-//! Waits for a data word from the SDHost read buffer
-//!
-//! \param ulBase is the base address of SDHost module.
-//! \param pulData is pointer to read data variable.
-//!
-//! This function reads a single data word from the SDHost read buffer. If there
-//! is no data available in the buffer the function will wait until a data
-//! word is received before returning.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SDHostDataRead(unsigned long ulBase, unsigned long *pulData)
-{
-  //
-  // Wait until data is available
-  //
-  while( !(HWREG(ulBase + MMCHS_O_PSTATE) & (1<<11)) )
-  {
-
-  }
-
-  //
-  // Read the data
-  //
-  *pulData = HWREG(ulBase + MMCHS_O_DATA);
-}
-
-//*****************************************************************************
-//
-//! Reads single data word from the SDHost read buffer
-//!
-//! \param ulBase is the base address of SDHost module.
-//! \param pulData is pointer to read data variable.
-//!
-//! This function reads a data word from the SDHost read buffer. The
-//! function returns \b true if there was data available in to buffer else
-//! returns \b false.
-//!
-//! \return Return \b true on success, \b false otherwise.
-//
-//*****************************************************************************
-tBoolean
-SDHostDataNonBlockingRead(unsigned long ulBase, unsigned long *pulData)
-{
-
-  //
-  // See if there is any data in the read buffer.
-  //
-  if( (HWREG(ulBase + MMCHS_O_PSTATE) & (1<11)) )
-  {
-    //
-    // Read the data word.
-    //
-    *pulData = HWREG(ulBase + MMCHS_O_DATA);
-
-    //
-    // Success
-    //
-    return(true);
-  }
-  else
-  {
-    //
-    // No data available, failure.
-    //
-    return(false);
-  }
-}
-
-
-//*****************************************************************************
-//
-//! Registers the interrupt handler for SDHost interrupt
-//!
-//! \param ulBase is the base address of SDHost module
-//! \param pfnHandler is a pointer to the function to be called when the
-//! SDHost interrupt occurs.
-//!
-//! This function does the actual registering of the interrupt handler.  This
-//! function enables the global interrupt in the interrupt controller; specific
-//! SDHost interrupts must be enabled via SDHostIntEnable(). It is the
-//! interrupt handler's responsibility to clear the interrupt source.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
-{
-  //
-  // Register the interrupt handler.
-  //
-  IntRegister(INT_MMCHS, pfnHandler);
-
-  //
-  // Enable the SDHost interrupt.
-  //
-  IntEnable(INT_MMCHS);
-}
-
-//*****************************************************************************
-//
-//! Unregisters the interrupt handler for SDHost interrupt
-//!
-//! \param ulBase is the base address of SDHost module
-//!
-//! This function does the actual unregistering of the interrupt handler.  It
-//! clears the handler to be called when a SDHost interrupt occurs.  This
-//! function also masks off the interrupt in the interrupt controller so that
-//! the interrupt handler no longer is called.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SDHostIntUnregister(unsigned long ulBase)
-{
-  //
-  // Disable the SDHost interrupt.
-  //
-  IntDisable(INT_MMCHS);
-
-  //
-  // Unregister the interrupt handler.
-  //
-  IntUnregister(INT_MMCHS);
-}
-
-//*****************************************************************************
-//
-//! Enable individual interrupt source for the specified SDHost
-//!
-//! \param ulBase is the base address of SDHost module.
-//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
-//!
-//! This function enables the indicated SDHost interrupt sources.  Only the
-//! sources that are enabled can be reflected to the processor interrupt;
-//! disabled sources have no effect on the processor.
-//!
-//! The \e ulIntFlags parameter is the logical OR of any of the following:
-//! - \b SDHOST_INT_CC    Command Complete interrupt
-//! - \b SDHOST_INT_TC    Transfer Complete interrupt
-//! - \b SDHOST_INT_BWR   Buffer Write Ready interrupt
-//! - \b SDHOST_INT_BRR   Buffer Read Ready interrupt
-//! - \b SDHOST_INT_ERRI  Error interrupt
-//! - \b SDHOST_INT_CTO   Command Timeout error interrupt
-//! - \b SDHOST_INT_CEB   Command End Bit error interrupt
-//! - \b SDHOST_INT_DTO   Data Timeout error interrupt
-//! - \b SDHOST_INT_DCRC  Data CRC error interrupt
-//! - \b SDHOST_INT_DEB   Data End Bit error
-//! - \b SDHOST_INT_CERR  Cart Status Error interrupt
-//! - \b SDHOST_INT_BADA  Bad Data error interrupt
-//! - \b SDHOST_INT_DMARD Read DMA done interrupt
-//! - \b SDHOST_INT_DMAWR Write DMA done interrupt
-//!
-//!     Note that SDHOST_INT_ERRI can only be used with \sa SDHostIntStatus()
-//! and is internally logical OR of all error status bits. Setting this bit
-//! alone as \e ulIntFlags doesn't generates any interrupt.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags)
-{
-  //
-  // Enable DMA done interrupts
-  //
-  HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) =
-                                                          (ulIntFlags >> 30);
-
-  //
-  // Enable the individual interrupt sources
-  //
-  HWREG(ulBase + MMCHS_O_ISE) |= (ulIntFlags & 0x3FFFFFFF);
-}
-
-//*****************************************************************************
-//
-//! Enable individual interrupt source for the specified SDHost
-//!
-//! \param ulBase is the base address of SDHost module.
-//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
-//!
-//! This function disables the indicated SDHost interrupt sources.  Only the
-//! sources that are enabled can be reflected to the processor interrupt;
-//! disabled sources have no effect on the processor.
-//!
-//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
-//! parameter to SDHostIntEnable().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags)
-{
-  //
-  // Disable DMA done interrupts
-  //
-  HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) =
-                                                          (ulIntFlags >> 30);
-  //
-  // Disable the individual interrupt sources
-  //
-  HWREG(ulBase + MMCHS_O_ISE) &= ~(ulIntFlags & 0x3FFFFFFF);
-}
-
-//*****************************************************************************
-//
-//! Gets the current interrupt status.
-//!
-//! \param ulBase is the base address of SDHost module.
-//!
-//! This function returns the interrupt status for the specified SDHost.
-//!
-//! \return Returns the current interrupt status, enumerated as a bit field of
-//! values described in SDHostIntEnable().
-//
-//*****************************************************************************
-unsigned long
-SDHostIntStatus(unsigned long ulBase)
-{
-  unsigned long ulIntStatus;
-
-  //
-  // Get DMA done interrupt status
-  //
-  ulIntStatus = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW);
-  ulIntStatus = (ulIntStatus << 30);
-
-  //
-  // Return the status of individual interrupt sources
-  //
-  ulIntStatus |= (HWREG(ulBase + MMCHS_O_STAT) & 0x3FFFFFFF);
-
-  return(ulIntStatus);
-}
-
-//*****************************************************************************
-//
-//! Clears the individual interrupt sources.
-//!
-//! \param ulBase is the base address of SDHost module.
-//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
-//!
-//! The specified SDHost interrupt sources are cleared, so that they no longer
-//! assert.  This function must be called in the interrupt handler to keep the
-//! interrupt from being recognized again immediately upon exit.
-//!
-//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
-//! parameter to SDHostIntEnable().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags)
-{
-  //
-  // Clear DMA done interrupts
-  //
-  HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) =
-                                                          (ulIntFlags >> 30);
-  //
-  // Clear the individual interrupt sources
-  //
-  HWREG(ulBase + MMCHS_O_STAT) = (ulIntFlags & 0x3FFFFFFF);
-}
-
-//*****************************************************************************
-//
-//! Sets the card status error mask.
-//!
-//! \param ulBase is the base address of SDHost module
-//! \param ulErrMask is the bit mask of card status errors to be enabled
-//!
-//! This function sets the card status error mask for response type R1, R1b,
-//! R5, R5b and R6 response. The parameter \e ulErrMask is the bit mask of card
-//! status errors to be enabled, if the corresponding bits in the 'card status'
-//! field of a respose are set then the host controller indicates a card error
-//! interrupt status. Only bits referenced as type E (error) in status field in
-//! the response can set a card status error.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-SDHostCardErrorMaskSet(unsigned long ulBase, unsigned long ulErrMask)
-{
-  //
-  // Set the card status error mask
-  //
-  HWREG(ulBase + MMCHS_O_CSRE) = ulErrMask;
-}
-
-
-//*****************************************************************************
-//
-//! Gets the card status error mask.
-//!
-//! \param ulBase is the base address of SDHost module
-//!
-//! This function gets the card status error mask for response type R1, R1b,
-//! R5, R5b and R6 response.
-//!
-//! \return Returns the current card status error.
-//
-//*****************************************************************************
-unsigned long
-SDHostCardErrorMaskGet(unsigned long ulBase)
-{
-  //
-  // Return the card status error mask
-  //
-  return(HWREG(ulBase + MMCHS_O_CSRE));
-}
-
-//*****************************************************************************
-//
-//! Sets the SD Card clock.
-//!
-//! \param ulBase is the base address of SDHost module
-//! \param ulSDHostClk is the rate of clock supplied to SDHost module
-//! \param ulCardClk is the required SD interface clock
-//!
-//! This function configures the SDHost interface to supply the specified clock
-//! to the connected card.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk,
-             unsigned long ulCardClk)
-{
-  unsigned long ulDiv;
-
-  //
-  // Disable card clock
-  //
-  HWREG(ulBase + MMCHS_O_SYSCTL) &= ~0x4;
-
-  //
-  // Enable internal clock
-  //
-  HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x1;
-
-  ulDiv = ((ulSDHostClk/ulCardClk) & 0x3FF);
-
-  //
-  // Set clock divider,
-  //
-  HWREG(ulBase + MMCHS_O_SYSCTL) = ((HWREG(ulBase + MMCHS_O_SYSCTL) &
-                                     ~0x0000FFC0)| (ulDiv) << 6);
-
-  //
-  // Wait for clock to stablize
-  //
-  while( !(HWREG(ulBase + MMCHS_O_SYSCTL) & 0x2) )
-  {
-
-  }
-
-  //
-  // Enable card clock
-  //
-  HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x4;
-}
-
-//*****************************************************************************
-//
-//! Get the response for the last command.
-//!
-//! \param ulBase is the base address of SDHost module
-//! \param ulRespnse is 128-bit response.
-//!
-//! This function gets the response from the SD card for the last command
-//! send.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4])
-{
-
-  //
-  // Read the responses.
-  //
-  ulRespnse[0] = HWREG(ulBase + MMCHS_O_RSP10);
-  ulRespnse[1] = HWREG(ulBase + MMCHS_O_RSP32);
-  ulRespnse[2] = HWREG(ulBase + MMCHS_O_RSP54);
-  ulRespnse[3] = HWREG(ulBase + MMCHS_O_RSP76);
-
-}
-
-//*****************************************************************************
-//
-//! Set the block size for data transfer
-//!
-//! \param ulBase is the base address of SDHost module
-//! \param ulBlkSize is the transfer block size in bytes
-//!
-//! This function sets the block size the data transfer.
-//!
-//! The parameter \e ulBlkSize is size of each data block in bytes.
-//! This should be in range 0 - 2^10.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize)
-{
-  //
-  // Set the block size
-  //
-  HWREG(ulBase + MMCHS_O_BLK) = ((HWREG(ulBase + MMCHS_O_BLK) & 0x00000FFF)|
-                                  (ulBlkSize & 0xFFF));
-}
-
-//*****************************************************************************
-//
-//! Set the block size and count for data transfer
-//!
-//! \param ulBase is the base address of SDHost module
-//! \param ulBlkCount is the number of blocks
-//!
-//! This function sets block count for the data transfer. This needs to be set
-//! for each block transfer. \sa SDHostBlockSizeSet()
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SDHostBlockCountSet(unsigned long ulBase, unsigned short ulBlkCount)
-{
-  unsigned long ulRegVal;
-
-  //
-  // Read the current value
-  //
-  ulRegVal = HWREG(ulBase + MMCHS_O_BLK);
-
-  //
-  // Set the number of blocks
-  //
-  HWREG(ulBase + MMCHS_O_BLK) = ((ulRegVal & 0x0000FFFF)|
-                                  (ulBlkCount << 16));
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
diff --git a/cc3200/hal/sdhost.h b/cc3200/hal/sdhost.h
deleted file mode 100644
index d0d398497..000000000
--- a/cc3200/hal/sdhost.h
+++ /dev/null
@@ -1,204 +0,0 @@
-//*****************************************************************************
-//
-//  sdhost.h
-//
-//  Defines and Macros for the SDHost.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __SDHOST_H__
-#define __SDHOST_H__
-
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-//{
-#endif
-
-
-//*****************************************************************************
-// Values that can be passed to SDHostRespGet().
-//*****************************************************************************
-#define SDHOST_RESP_10 0x00000003
-#define SDHOST_RESP_32 0x00000002
-#define SDHOST_RESP_54 0x00000001
-#define SDHOST_RESP_76 0x00000000
-
-
-//*****************************************************************************
-// Values that can be passed to SDHostIntEnable(), SDHostIntDisable(),
-// SDHostIntClear() ,and returned from SDHostIntStatus().
-//*****************************************************************************
-#define SDHOST_INT_CC    0x00000001
-#define SDHOST_INT_TC    0x00000002
-#define SDHOST_INT_BWR   0x00000010
-#define SDHOST_INT_BRR   0x00000020
-#define SDHOST_INT_ERRI  0x00008000
-#define SDHOST_INT_CTO   0x00010000
-#define SDHOST_INT_CEB   0x00040000
-#define SDHOST_INT_DTO   0x00100000
-#define SDHOST_INT_DCRC  0x00200000
-#define SDHOST_INT_DEB   0x00400000
-#define SDHOST_INT_CERR  0x10000000
-#define SDHOST_INT_BADA  0x20000000
-#define SDHOST_INT_DMARD 0x40000000
-#define SDHOST_INT_DMAWR 0x80000000
-
-//*****************************************************************************
-// Values that can be passed to SDHostCmdSend().
-//*****************************************************************************
-#define SDHOST_CMD_0     0x00000000
-#define SDHOST_CMD_1     0x01000000
-#define SDHOST_CMD_2     0x02000000
-#define SDHOST_CMD_3     0x03000000
-#define SDHOST_CMD_4     0x04000000
-#define SDHOST_CMD_5     0x05000000
-#define SDHOST_CMD_6     0x06000000
-#define SDHOST_CMD_7     0x07000000
-#define SDHOST_CMD_8     0x08000000
-#define SDHOST_CMD_9     0x09000000
-#define SDHOST_CMD_10    0x0A000000
-#define SDHOST_CMD_11    0x0B000000
-#define SDHOST_CMD_12    0x0C000000
-#define SDHOST_CMD_13    0x0D000000
-#define SDHOST_CMD_14    0x0E000000
-#define SDHOST_CMD_15    0x0F000000
-#define SDHOST_CMD_16    0x10000000
-#define SDHOST_CMD_17    0x11000000
-#define SDHOST_CMD_18    0x12000000
-#define SDHOST_CMD_19    0x13000000
-#define SDHOST_CMD_20    0x14000000
-#define SDHOST_CMD_21    0x15000000
-#define SDHOST_CMD_22    0x16000000
-#define SDHOST_CMD_23    0x17000000
-#define SDHOST_CMD_24    0x18000000
-#define SDHOST_CMD_25    0x19000000
-#define SDHOST_CMD_26    0x1A000000
-#define SDHOST_CMD_27    0x1B000000
-#define SDHOST_CMD_28    0x1C000000
-#define SDHOST_CMD_29    0x1D000000
-#define SDHOST_CMD_30    0x1E000000
-#define SDHOST_CMD_31    0x1F000000
-#define SDHOST_CMD_32    0x20000000
-#define SDHOST_CMD_33    0x21000000
-#define SDHOST_CMD_34    0x22000000
-#define SDHOST_CMD_35    0x23000000
-#define SDHOST_CMD_36    0x24000000
-#define SDHOST_CMD_37    0x25000000
-#define SDHOST_CMD_38    0x26000000
-#define SDHOST_CMD_39    0x27000000
-#define SDHOST_CMD_40    0x28000000
-#define SDHOST_CMD_41    0x29000000
-#define SDHOST_CMD_42    0x2A000000
-#define SDHOST_CMD_43    0x2B000000
-#define SDHOST_CMD_44    0x2C000000
-#define SDHOST_CMD_45    0x2D000000
-#define SDHOST_CMD_46    0x2E000000
-#define SDHOST_CMD_47    0x2F000000
-#define SDHOST_CMD_48    0x30000000
-#define SDHOST_CMD_49    0x31000000
-#define SDHOST_CMD_50    0x32000000
-#define SDHOST_CMD_51    0x33000000
-#define SDHOST_CMD_52    0x34000000
-#define SDHOST_CMD_53    0x35000000
-#define SDHOST_CMD_54    0x36000000
-#define SDHOST_CMD_55    0x37000000
-#define SDHOST_CMD_56    0x38000000
-#define SDHOST_CMD_57    0x39000000
-#define SDHOST_CMD_58    0x3A000000
-#define SDHOST_CMD_59    0x3B000000
-#define SDHOST_CMD_60    0x3C000000
-#define SDHOST_CMD_61    0x3D000000
-#define SDHOST_CMD_62    0x3E000000
-#define SDHOST_CMD_63    0x3F000000
-
-//*****************************************************************************
-// Values that can be logically ORed with ulCmd parameter for SDHostCmdSend().
-//*****************************************************************************
-#define SDHOST_MULTI_BLK    0x00000022
-#define SDHOST_DMA_EN       0x00000001
-#define SDHOST_WR_CMD       0x00200000
-#define SDHOST_RD_CMD       0x00200010
-#define SDHOST_RESP_LEN_136 0x00010000
-#define SDHOST_RESP_LEN_48  0x00020000
-#define SDHOST_RESP_LEN_48B 0x00030000
-
-
-//*****************************************************************************
-//
-// API Function prototypes
-//
-//*****************************************************************************
-extern void SDHostCmdReset(unsigned long ulBase);
-extern void SDHostInit(unsigned long ulBase);
-extern long SDHostCmdSend(unsigned long ulBase,unsigned long ulCmd,
-                       unsigned ulArg);
-extern void SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
-extern void SDHostIntUnregister(unsigned long ulBase);
-extern void SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags);
-extern void SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags);
-extern unsigned long SDHostIntStatus(unsigned long ulBase);
-extern void SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags);
-extern void SDHostCardErrorMaskSet(unsigned long ulBase,
-                                   unsigned long ulErrMask);
-extern unsigned long SDHostCardErrorMaskGet(unsigned long ulBase);
-extern void SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk,
-              unsigned long ulCardClk);
-extern void SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4]);
-extern void SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize);
-extern void SDHostBlockCountSet(unsigned long ulBase,
-                                unsigned short ulBlkCount);
-extern tBoolean SDHostDataNonBlockingWrite(unsigned long ulBase,
-                                        unsigned long ulData);
-extern tBoolean SDHostDataNonBlockingRead(unsigned long ulBase,
-                                   unsigned long *pulData);
-extern void SDHostDataWrite(unsigned long ulBase, unsigned long ulData);
-extern void SDHostDataRead(unsigned long ulBase, unsigned long *ulData);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-//}
-#endif
-
-#endif // __SDHOST_H__
diff --git a/cc3200/hal/shamd5.c b/cc3200/hal/shamd5.c
deleted file mode 100644
index 6a3cc1cc3..000000000
--- a/cc3200/hal/shamd5.c
+++ /dev/null
@@ -1,1085 +0,0 @@
-//*****************************************************************************
-//
-//  shamd5.c
-//
-//  Driver for the SHA/MD5 module.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup SHA_Secure_Hash_Algorithm_api
-//! @{
-//
-//*****************************************************************************
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "inc/hw_dthe.h"
-#include "inc/hw_ints.h"
-#include "inc/hw_memmap.h"
-#include "inc/hw_nvic.h"
-#include "inc/hw_shamd5.h"
-#include "inc/hw_types.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "shamd5.h"
-#include "rom_map.h"
-
-#define SHAMD5_MODE_ALGO_MD5         0x00000000  // MD5
-#define SHAMD5_MODE_ALGO_SHA1        0x00000002  // SHA-1
-#define SHAMD5_MODE_ALGO_SHA224      0x00000004  // SHA-224
-#define SHAMD5_MODE_ALGO_SHA256      0x00000006  // SHA-256
-
-//*****************************************************************************
-//
-//! Enables the uDMA requests in the SHA/MD5 module.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//!
-//! This function configures the DMA options of the SHA/MD5 module.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-SHAMD5DMAEnable(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-
-    //
-    // Write the new configuration into the register.
-    //
-    HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |=
-        SHAMD5_SYSCONFIG_PADVANCED | SHAMD5_SYSCONFIG_PDMA_EN;
-}
-
-//*****************************************************************************
-//
-//! Disables the uDMA requests in the SHA/MD5 module.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//!
-//! This function configures the DMA options of the SHA/MD5 module.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-SHAMD5DMADisable(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-
-    //
-    // Write the new configuration into the register.
-    //
-    HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &=
-        ~(SHAMD5_SYSCONFIG_PADVANCED | SHAMD5_SYSCONFIG_PDMA_EN);
-}
-
-//*****************************************************************************
-//
-//! Get the interrupt status of the SHA/MD5 module.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//! \param bMasked is \b false if the raw interrupt status is required and
-//! \b true if the masked interrupt status is required.
-//!
-//! This function returns the current value of the IRQSTATUS register.  The
-//! value will be a logical OR of the following:
-//!
-//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready.
-//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after
-//! a context switch.
-//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data.
-//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready.
-//!
-//! \return Interrupt status
-//
-//*****************************************************************************
-uint32_t
-SHAMD5IntStatus(uint32_t ui32Base, bool bMasked)
-{
-    uint32_t ui32Temp;
-    uint32_t ui32IrqEnable;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-
-    //
-    // Return the value of the IRQSTATUS register.
-    //
-    if(bMasked)
-    {
-        ui32Temp = HWREG(DTHE_BASE + DTHE_O_SHA_MIS);
-        ui32IrqEnable = HWREG(ui32Base + SHAMD5_O_IRQENABLE);
-        return((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) &
-                ui32IrqEnable) | (ui32Temp & 0x00000007) << 16);
-    }
-    else
-    {
-        ui32Temp = HWREG(DTHE_BASE + DTHE_O_SHA_RIS);
-        return(HWREG(ui32Base + SHAMD5_O_IRQSTATUS) |
-               (ui32Temp & 0x00000007) << 16);
-
-    }
-}
-
-//*****************************************************************************
-//
-//! Enable interrupt sources in the SHA/MD5 module.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//! \param ui32IntFlags contains desired interrupts to enable.
-//!
-//! This function enables interrupt sources in the SHA/MD5 module.
-//! ui32IntFlags must be a logical OR of one or more of the following
-//! values:
-//!
-//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready.
-//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after
-//! a context switch.
-//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data.
-//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-    ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) ||
-           (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) ||
-           (ui32IntFlags == SHAMD5_INT_INPUT_READY) ||
-           (ui32IntFlags == SHAMD5_INT_OUTPUT_READY));
-
-    //
-    // Enable the interrupt sources.
-    //
-    HWREG(DTHE_BASE + DTHE_O_SHA_IM) &= ~((ui32IntFlags & 0x00070000) >> 16);
-    HWREG(ui32Base + SHAMD5_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff;
-
-    //
-    // Enable all interrupts.
-    //
-    HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= SHAMD5_SYSCONFIG_PIT_EN;
-}
-
-//*****************************************************************************
-//
-//! Disable interrupt sources in the SHA/MD5 module.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//! \param ui32IntFlags contains desired interrupts to disable.
-//!
-//! \e ui32IntFlags must be a logical OR of one or more of the following
-//! values:
-//!
-//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready.
-//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after
-//! a context switch.
-//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data.
-//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-    ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) ||
-           (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) ||
-           (ui32IntFlags == SHAMD5_INT_INPUT_READY) ||
-           (ui32IntFlags == SHAMD5_INT_OUTPUT_READY));
-
-    //
-    // Clear the corresponding flags disabling the interrupt sources.
-    //
-    HWREG(DTHE_BASE + DTHE_O_SHA_IM) |= ((ui32IntFlags & 0x00070000) >> 16);
-    HWREG(ui32Base + SHAMD5_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff);
-
-    //
-    // If there are no interrupts enabled, then disable all interrupts.
-    //
-    if(HWREG(ui32Base + SHAMD5_O_IRQENABLE) == 0x0)
-    {
-        HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= ~SHAMD5_SYSCONFIG_PIT_EN;
-    }
-}
-
-//*****************************************************************************
-//
-//! Clears interrupt sources in the SHA/MD5 module.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//! \param ui32IntFlags contains desired interrupts to disable.
-//!
-//! \e ui32IntFlags must be a logical OR of one or more of the following
-//! values:
-//!
-//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready.
-//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after
-//! a context switch.
-//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data.
-//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-    ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) ||
-           (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) ||
-           (ui32IntFlags == SHAMD5_INT_INPUT_READY) ||
-           (ui32IntFlags == SHAMD5_INT_OUTPUT_READY));
-
-    //
-    // Clear the corresponding flags disabling the interrupt sources.
-    //
-    HWREG(DTHE_BASE + DTHE_O_SHA_IC) = ((ui32IntFlags & 0x00070000) >> 16);
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for the SHA/MD5 module.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//! \param pfnHandler is a pointer to the function to be called when the
-//! enabled SHA/MD5 interrupts occur.
-//!
-//! This function registers the interrupt handler in the interrupt vector
-//! table, and enables SHA/MD5 interrupts on the interrupt controller;
-//! specific SHA/MD5 interrupt sources must be enabled using
-//! SHAMD5IntEnable().  The interrupt handler being registered must clear
-//! the source of the interrupt using SHAMD5IntClear().
-//!
-//! If the application is using a static interrupt vector table stored in
-//! flash, then it is not necessary to register the interrupt handler this way.
-//! Instead, IntEnable() should be used to enable SHA/MD5 interrupts on the
-//! interrupt controller.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SHAMD5IntRegister(uint32_t ui32Base, void(*pfnHandler)(void))
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-
-    //
-    // Register the interrupt handler.
-    //
-    IntRegister(INT_SHA, pfnHandler);
-
-    //
-    // Enable the interrupt
-    //
-    IntEnable(INT_SHA);
-}
-
-//*****************************************************************************
-//
-//! Unregisters an interrupt handler for the SHA/MD5 module.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//!
-//! This function unregisters the previously registered interrupt handler and
-//! disables the interrupt in the interrupt controller.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SHAMD5IntUnregister(uint32_t ui32Base)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-
-    //
-    // Disable the interrupt.
-    //
-    IntDisable(INT_SHA);
-
-    //
-    // Unregister the interrupt handler.
-    //
-    IntUnregister(INT_SHA);
-}
-
-//*****************************************************************************
-//
-//! Write the hash length to the SHA/MD5 module.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//! \param ui32Length is the hash length in bytes.
-//!
-//! This function writes the length of the hash data of the current operation
-//! to the SHA/MD5 module.  The value must be a multiple of 64 if the close
-//! hash is not set in the mode register.
-//!
-//! \note When this register is written, hash processing is triggered.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SHAMD5DataLengthSet(uint32_t ui32Base, uint32_t ui32Length)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-
-    //
-    // Set the LENGTH register and start processing.
-    //
-    HWREG(ui32Base + SHAMD5_O_LENGTH) = ui32Length;
-}
-
-//*****************************************************************************
-//
-//! Writes the mode in the SHA/MD5 module.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//! \param ui32Mode is the mode of the SHA/MD5 module.
-//!
-//! This function writes the mode register configuring the SHA/MD5 module.
-//!
-//! The ui32Mode paramerter is a bit-wise OR of values:
-//!
-//! - \b SHAMD5_ALGO_MD5 - Regular hash with MD5
-//! - \b SHAMD5_ALGO_SHA1 - Regular hash with SHA-1
-//! - \b SHAMD5_ALGO_SHA224 - Regular hash with SHA-224
-//! - \b SHAMD5_ALGO_SHA256 - Regular hash with SHA-256
-//! - \b SHAMD5_ALGO_HMAC_MD5 - HMAC with MD5
-//! - \b SHAMD5_ALGO_HMAC_SHA1 - HMAC with SHA-1
-//! - \b SHAMD5_ALGO_HMAC_SHA224 - HMAC with SHA-224
-//! - \b SHAMD5_ALGO_HMAC_SHA256 - HMAC with SHA-256
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32Mode)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-    ASSERT((ui32Mode == SHAMD5_ALGO_MD5) ||
-           (ui32Mode == SHAMD5_ALGO_SHA1) ||
-           (ui32Mode == SHAMD5_ALGO_SHA224) ||
-           (ui32Mode == SHAMD5_ALGO_SHA256) ||
-           (ui32Mode == SHAMD5_ALGO_HMAC_MD5) ||
-           (ui32Mode == SHAMD5_ALGO_HMAC_SHA1) ||
-           (ui32Mode == SHAMD5_ALGO_HMAC_SHA224) ||
-           (ui32Mode == SHAMD5_ALGO_HMAC_SHA256));
-
-    //
-    // Write the value in the MODE register.
-    //
-    HWREG(ui32Base + SHAMD5_O_MODE) = ui32Mode;
-}
-
-//*****************************************************************************
-//
-//! Perform a non-blocking write of 16 words of data to the SHA/MD5 module.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//! \param pui8Src is the pointer to the 16-word array of data that will be
-//! written.
-//!
-//! This function writes 16 words of data into the data register.
-//!
-//! \return This function returns true if the write completed successfully.
-//! It returns false if the module was not ready.
-//
-//*****************************************************************************
-bool
-SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src)
-{
-    uint32_t ui8Counter;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-
-    //
-    // Check that the SHA/MD5 module is ready for data.  If not, return false.
-    //
-    if((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0)
-    {
-        return(false);
-    }
-
-    //
-    // Write the 16 words of data.
-    //
-    for(ui8Counter = 0; ui8Counter < 64; ui8Counter += 4)
-    {
-        HWREG(ui32Base + SHAMD5_O_DATA0_IN + ui8Counter) = *((uint32_t *)(pui8Src + ui8Counter));
-    }
-
-    //
-    // Return true as a sign of successfully completing the function.
-    //
-    return(true);
-}
-
-//*****************************************************************************
-//
-//! Perform a blocking write of 64 bytes of data to the SHA/MD5 module.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//! \param pui8Src is the pointer to the 64-byte array of data that will be
-//! written.
-//!
-//! This function does not return until the module is ready to accept data and
-//! the data has been written.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SHAMD5DataWrite(uint32_t ui32Base, uint8_t *pui8Src)
-{
-    uint8_t ui8Counter;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-
-    //
-    // Wait for the module to be ready to accept data.
-    //
-    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0)
-    {
-    }
-
-    //
-    // Write the 64 bytes of data.
-    //
-    for(ui8Counter = 0; ui8Counter < 64; ui8Counter += 4)
-    {
-        HWREG(ui32Base + SHAMD5_O_DATA0_IN + ui8Counter) =
-                                        *((uint32_t *) (pui8Src + ui8Counter));
-    }
-}
-
-
-//*****************************************************************************
-//
-//! Reads the result of a hashing operation.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//! \param pui8Dest is the pointer to the byte array of data that will be
-//! written.
-//!
-//! This function does not return until the module is ready to accept data and
-//! the data has been written.
-//! -----------------------------------------
-//! | Algorithm | Number of Words in Result |
-//! -----------------------------------------
-//! | MD5       | 16 Bytes (128 bits)        |
-//! | SHA-1     | 20 Bytes (160 bits)        |
-//! | SHA-224   | 28 Bytes (224 bits)        |
-//! | SHA-256   | 32 Bytes (256 bits)        |
-//! -----------------------------------------
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SHAMD5ResultRead(uint32_t ui32Base, uint8_t *pui8Dest)
-{
-    uint32_t ui32Idx, ui32Count;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-
-    //
-    // Determine the number of bytes in the result, based on the hash type.
-    //
-    switch(HWREG(ui32Base + SHAMD5_O_MODE) & SHAMD5_MODE_ALGO_M)
-    {
-        //
-        // The MD5 hash is being used.
-        //
-        case SHAMD5_MODE_ALGO_MD5:
-        {
-            //
-            // There are 16 bytes in the MD5 hash.
-            //
-            ui32Count = 16;
-
-            //
-            // Done.
-            //
-            break;
-        }
-
-        //
-        // The SHA-1 hash is being used.
-        //
-        case SHAMD5_MODE_ALGO_SHA1:
-        {
-            //
-            // There are 20 bytes in the SHA-1 hash.
-            //
-            ui32Count = 20;
-
-            //
-            // Done.
-            //
-            break;
-        }
-
-        //
-        // The SHA-224 hash is being used.
-        //
-        case SHAMD5_MODE_ALGO_SHA224:
-        {
-            //
-            // There are 28 bytes in the SHA-224 hash.
-            //
-            ui32Count = 28;
-
-            //
-            // Done.
-            //
-            break;
-        }
-
-        //
-        // The SHA-256 hash is being used.
-        //
-        case SHAMD5_MODE_ALGO_SHA256:
-        {
-            //
-            // There are 32 bytes in the SHA-256 hash.
-            //
-            ui32Count = 32;
-
-            //
-            // Done.
-            //
-            break;
-        }
-
-        //
-        // The hash type is not recognized.
-        //
-        default:
-        {
-            //
-            // Return without reading a result since the hardware appears to be
-            // misconfigured.
-            //
-            return;
-        }
-    }
-
-    //
-    // Read the hash result.
-    //
-    for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx += 4)
-    {
-    	*((uint32_t *)(pui8Dest+ui32Idx)) =
-                                HWREG(ui32Base + SHAMD5_O_IDIGEST_A + ui32Idx);
-    }
-}
-
-//*****************************************************************************
-//
-//! Writes multiple words of data into the SHA/MD5 data registers.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//! \param pui8DataSrc is a pointer to an array of data to be written.
-//! \param ui32DataLength is the length of the data to be written in bytes.
-//!
-//! This function writes a variable number of words into the SHA/MD5 data
-//! registers.  The function waits for each block of data to be processed
-//! before another is written.
-//!
-//! \note This function is used by SHAMD5HashCompute(), SHAMD5HMACWithKPP(),
-//! and SHAMD5HMACNoKPP() to process data.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SHAMD5DataWriteMultiple(uint8_t *pui8DataSrc, uint32_t ui32DataLength)
-{
-    uint32_t ui32Idx, ui32Count, ui32Lastword, ui32TempData = 0;
-    uint8_t * ui8TempData;
-
-
-    //
-    // Calculate the number of blocks of data.
-    //
-    ui32Count = ui32DataLength / 64;
-
-    //
-    // Loop through all the blocks and write them into the data registers
-    // making sure to block additional operations until we can write the
-    // next 16 words.
-    //
-    for (ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++)
-    {
-        //
-        // Write the block of data.
-        //
-        MAP_SHAMD5DataWrite(SHAMD5_BASE, pui8DataSrc);
-        //
-        // Increment the pointer to next block of data.
-        //
-        pui8DataSrc += 64;
-    }
-
-    //
-    // Calculate the remaining bytes of data that don't make up a full block.
-    //
-    ui32Count = ui32DataLength % 64;
-
-    //
-    // If there are bytes that do not make up a whole block, then
-    // write them separately.
-    //
-    if(ui32Count)
-    {
-        //
-        // Wait until the engine has finished processing the previous block.
-        //
-        while ((HWREG(SHAMD5_BASE + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0);
-
-        //
-        // Loop through the remaining words.
-        //
-        ui32Count = ui32Count / 4;
-        for (ui32Idx = 0; ui32Idx < ui32Count; ui32Idx ++)
-        {
-            //
-            // Write the word into the data register.
-            //
-            HWREG(SHAMD5_BASE + SHAMD5_O_DATA0_IN + (ui32Idx * 4)) =* ( (uint32_t *) pui8DataSrc);
-            pui8DataSrc +=4;
-        }
-        //
-        // Loop through the remaining bytes
-        //
-        ui32Count = ui32DataLength % 4;
-        ui8TempData = (uint8_t *) &ui32TempData;
-        if(ui32Count)
-        {
-        	ui32Lastword = 0;
-        	if(ui32Idx)
-        	{
-        		ui32Lastword = (ui32Idx-1) *4;
-        	}
-        	for(ui32Idx=0 ; ui32Idx<ui32Count ; ui32Idx++)
-        	{
-        		*(ui8TempData+ui32Idx) = *(pui8DataSrc+ui32Idx);
-        	}
-        	HWREG(SHAMD5_BASE + SHAMD5_O_DATA0_IN + ui32Lastword) = ui32TempData;
-        }
-    }
-}
-
-//*****************************************************************************
-//
-//! Compute a hash using the SHA/MD5 module.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//! \param pui8DataSrc is a pointer to an array of data that contains the
-//! data that will be hashed.
-//! \param ui32DataLength specifies the length of the data to be hashed in
-//! bytes.
-//! \param pui8HashResult is a pointer to an array that holds the result
-//! of the hashing operation.
-//!
-//! This function computes the hash of an array of data using the SHA/MD5
-//! module.
-//!
-//! The length of the hash result is dependent on the algorithm that is in use.
-//! The following table shows the correct array size for each algorithm:
-//!
-//! -----------------------------------------
-//! | Algorithm | Number of Words in Result |
-//! -----------------------------------------
-//! | MD5       | 4 Words (128 bits)        |
-//! | SHA-1     | 5 Words (160 bits)        |
-//! | SHA-224   | 7 Words (224 bits)        |
-//! | SHA-256   | 8 Words (256 bits)        |
-//! -----------------------------------------
-//!
-//! \return None
-//
-//*****************************************************************************
-bool
-SHAMD5DataProcess(uint32_t ui32Base, uint8_t *pui8DataSrc,
-                  uint32_t ui32DataLength, uint8_t *pui8HashResult)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-    ASSERT((ui32DataLength % 64) == 0);
-
-    //
-    // Wait for the context to be ready before writing the mode.
-    //
-    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) ==
-          0)
-    {
-    }
-
-    //
-    // Write the length.
-    //
-    SHAMD5DataLengthSet(ui32Base, ui32DataLength);
-
-    //
-    // Write the data.
-    //
-    SHAMD5DataWriteMultiple(pui8DataSrc, ui32DataLength);
-
-    //
-    // Wait for the output to be ready.
-    //
-    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) ==
-          0)
-    {
-    }
-
-    //
-    // Read the result.
-    //
-    SHAMD5ResultRead(ui32Base, pui8HashResult);
-
-    //
-    // Return true to indicate successful completion of the function.
-    //
-    return(true);
-}
-
-//*****************************************************************************
-//
-//! Compute a HMAC with key pre-processing using the SHA/MD5 module.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//! \param pui8DataSrc is a pointer to an array of data that contains the
-//! data that is to be hashed.
-//! \param ui32DataLength specifies the length of the data to be hashed in
-//! bytes.
-//! \param pui8HashResult is a pointer to an array that holds the result
-//! of the hashing operation.
-//!
-//! This function computes a HMAC with the given data using the SHA/MD5
-//! module with a preprocessed key.
-//!
-//! The length of the hash result is dependent on the algorithm that is
-//! selected with the \e ui32Algo argument.  The following table shows the
-//! correct array size for each algorithm:
-//!
-//! -----------------------------------------
-//! | Algorithm | Number of Words in Result |
-//! -----------------------------------------
-//! | MD5       | 4 Words (128 bits)        |
-//! | SHA-1     | 5 Words (160 bits)        |
-//! | SHA-224   | 7 Words (224 bits)        |
-//! | SHA-256   | 8 Words (256 bits)        |
-//! -----------------------------------------
-//!
-//! \return None
-//
-//*****************************************************************************
-bool
-SHAMD5HMACProcess(uint32_t ui32Base, uint8_t *pui8DataSrc,
-                  uint32_t ui32DataLength, uint8_t *pui8HashResult)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-
-    //
-    // Wait for the context to be ready before writing the mode.
-    //
-    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) ==
-          0)
-    {
-    }
-
-    //
-    // Write the length.
-    //
-    SHAMD5DataLengthSet(ui32Base, ui32DataLength);
-
-    //
-    // Write the data in the registers.
-    //
-    SHAMD5DataWriteMultiple(pui8DataSrc, ui32DataLength);
-
-    //
-    // Wait for the output to be ready.
-    //
-    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) ==
-          0)
-    {
-    }
-
-    //
-    // Read the result.
-    //
-    SHAMD5ResultRead(ui32Base, pui8HashResult);
-
-    //
-    // Return true to indicate successful completion of the function.
-    //
-    return(true);
-
-}
-
-//*****************************************************************************
-//
-//! Process an HMAC key using the SHA/MD5 module.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//! \param pui8Key is a pointer to an array that contains the key to be
-//! processed.
-//! \param pui8PPKey is the pointer to the array that contains the
-//! pre-processed key.
-//!
-//! This function processes an HMAC key using the SHA/MD5.  The resultant
-//! pre-processed key can then be used with later HMAC operations to speed
-//! processing time.
-//!
-//! The \e pui8Key array must be 512 bits long. If the key is
-//! less than 512 bits, it must be padded with zeros.  The
-//! \e pui8PPKey array must each be 512 bits long.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint8_t *pui8Key,
-                        uint8_t *pui8PPKey)
-{
-    uint32_t ui32Index;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-
-    //
-    // Wait for the context to be ready before writing the mode.
-    //
-    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) ==
-          0)
-    {
-    }
-
-    //
-    // Write the HMAC key.
-    //
-    for(ui32Index = 0; ui32Index < 64; ui32Index += 4)
-    {
-        HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Index) =
-                                          *((uint32_t *)(pui8Key + ui32Index));
-    }
-
-    //
-    // Set the flag to cause the HMAC key to be pre-processed.
-    //
-    HWREG(ui32Base + SHAMD5_O_MODE) |= SHAMD5_MODE_HMAC_KEY_PROC;
-
-    //
-    // Set the length to zero to start the HMAC key pre-processing.
-    //
-    HWREG(ui32Base + SHAMD5_O_LENGTH) = 0;
-
-    //
-    // Wait for key to be processed.
-    //
-    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) ==
-          0)
-    {
-    }
-
-    //
-    // Read the pre-processed key from the SHA/MD5 module.
-    //
-    for(ui32Index = 0; ui32Index < 64; ui32Index += 4)
-    {
-    	*((uint32_t *)(pui8PPKey+ui32Index)) =
-                              HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Index);
-    }
-}
-
-//*****************************************************************************
-//
-//! Writes an HMAC key to the digest registers in the SHA/MD5 module.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//! \param pui8Src is the pointer to the 16-word array of the HMAC key.
-//!
-//! This function is used to write HMAC key to the digest registers for
-//! key preprocessing.  The size of pui8Src must be 512 bytes.  If the key is
-//! less than 512 bytes, then it must be padded with zeros.
-//!
-//! \note It is recommended to use the SHAMD5GetIntStatus function to check
-//! whether the context is ready before writing the key.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-SHAMD5HMACKeySet(uint32_t ui32Base, uint8_t *pui8Src)
-{
-    uint32_t ui32Idx;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-
-    //
-    // Write the key to the digest registers.
-    //
-    for(ui32Idx = 0; ui32Idx < 64; ui32Idx += 4)
-    {
-        HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Idx) =
-                                           * ((uint32_t *)(pui8Src + ui32Idx));
-    }
-
-    //
-    // Configure the SHA engine for HMAC operation.
-    //
-    HWREG(ui32Base + SHAMD5_O_MODE) |= (SHAMD5_MODE_HMAC_OUTER_HASH |
-                                        SHAMD5_MODE_HMAC_KEY_PROC |
-                                        SHAMD5_MODE_CLOSE_HASH);
-}
-
-//*****************************************************************************
-//
-//! Writes a pre-processed HMAC key to the digest registers in the SHA/MD5
-//! module.
-//!
-//! \param ui32Base is the base address of the SHA/MD5 module.
-//! \param pui8Src is the pointer to the 16-word array of the HMAC key.
-//!
-//! This function is used to write HMAC key to the digest registers for
-//! key preprocessing.  The size of pui8Src must be 512 bytes.  If the key is
-//! less than 512 bytes, then it must be padded with zeros.
-//!
-//! \note It is recommended to use the SHAMD5GetIntStatus function to check
-//! whether the context is ready before writing the key.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-SHAMD5HMACPPKeySet(uint32_t ui32Base, uint8_t *pui8Src)
-{
-    uint32_t ui32Idx;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(ui32Base == SHAMD5_BASE);
-
-    //
-    // Write the key to the digest registers.
-    //
-    for(ui32Idx = 0; ui32Idx < 64; ui32Idx += 4)
-    {
-        HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Idx) =
-                                           *((uint32_t *) (pui8Src + ui32Idx));
-    }
-
-    //
-    // Configure the SHA engine to continue the HMAC.
-    //
-    HWREG(ui32Base + SHAMD5_O_MODE) |= (SHAMD5_MODE_HMAC_OUTER_HASH |
-                                        SHAMD5_MODE_CLOSE_HASH);
-
-    //
-    // Write the digest count to 64 to account for the preprocessed key.
-    //
-    HWREG(ui32Base + SHAMD5_O_DIGEST_COUNT) = 64;
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
diff --git a/cc3200/hal/shamd5.h b/cc3200/hal/shamd5.h
deleted file mode 100644
index 21f5b4eb0..000000000
--- a/cc3200/hal/shamd5.h
+++ /dev/null
@@ -1,121 +0,0 @@
-//*****************************************************************************
-//
-//  shamd5.h
-//
-//  Defines and Macros for the SHA/MD5.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __DRIVERLIB_SHAMD5_H__
-#define __DRIVERLIB_SHAMD5_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// The following defines are used to specify the algorithm in use in the
-// SHA/MD5 module.
-//
-//*****************************************************************************
-#define SHAMD5_ALGO_MD5         0x00000018  // MD5
-#define SHAMD5_ALGO_SHA1        0x0000001a  // SHA-1
-#define SHAMD5_ALGO_SHA224      0x0000001c  // SHA-224
-#define SHAMD5_ALGO_SHA256      0x0000001e  // SHA-256
-#define SHAMD5_ALGO_HMAC_MD5    0x00000000  // HMAC-MD5
-#define SHAMD5_ALGO_HMAC_SHA1   0x00000002  // HMAC-SHA-1
-#define SHAMD5_ALGO_HMAC_SHA224 0x00000004  // HMAC-SHA-224
-#define SHAMD5_ALGO_HMAC_SHA256 0x00000006  // HMAC-SHA-256
-
-//*****************************************************************************
-//
-// The following defines are used to represent the different interrupt sources
-// in SHAMD5IntEnable(), SHAMD5IntDisable(), SHAMD5GetIntStatus(), and
-// SHAMD5BlockOnIntStatus() functions.
-//
-//*****************************************************************************
-#define SHAMD5_INT_CONTEXT_READY   0x00000008
-#define SHAMD5_INT_PARTHASH_READY  0x00000004
-#define SHAMD5_INT_INPUT_READY     0x00000002
-#define SHAMD5_INT_OUTPUT_READY    0x00000001
-#define SHAMD5_INT_DMA_CONTEXT_IN  0x00010000
-#define SHAMD5_INT_DMA_DATA_IN     0x00020000
-#define SHAMD5_INT_DMA_CONTEXT_OUT 0x00040000
-
-//*****************************************************************************
-//
-// Function prototypes
-//
-//*****************************************************************************
-extern void SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32Mode);
-extern bool SHAMD5DataProcess(uint32_t ui32Base, uint8_t *pui8DataSrc,
-                  uint32_t ui32DataLength, uint8_t *pui8HashResult);
-extern void SHAMD5DataWrite(uint32_t ui32Base, uint8_t *pui8Src);
-extern void SHAMD5DataWriteMultiple(uint8_t *pui8DataSrc, uint32_t ui32DataLength);
-extern bool SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src);
-extern void SHAMD5DMADisable(uint32_t ui32Base);
-extern void SHAMD5DMAEnable(uint32_t ui32Base);
-extern void SHAMD5DataLengthSet(uint32_t ui32Base, uint32_t ui32Length);
-extern void SHAMD5HMACKeySet(uint32_t ui32Base, uint8_t *pui8Src);
-extern void SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint8_t *pui8Key,
-                        uint8_t *pui8PPKey);
-extern void SHAMD5HMACPPKeySet(uint32_t ui32Base, uint8_t *pui8Src);
-extern bool SHAMD5HMACProcess(uint32_t ui32Base, uint8_t *pui8DataSrc,
-                  uint32_t ui32DataLength, uint8_t *pui8HashResult);
-extern void SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
-extern void SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
-extern void SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
-extern void SHAMD5IntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
-extern uint32_t SHAMD5IntStatus(uint32_t ui32Base, bool bMasked);
-extern void SHAMD5IntUnregister(uint32_t ui32Base);
-extern void SHAMD5ResultRead(uint32_t ui32Base, uint8_t *pui8Dest);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif //  __DRIVERLIB_SHAMD5_H__
diff --git a/cc3200/hal/spi.c b/cc3200/hal/spi.c
deleted file mode 100644
index 8c8c67828..000000000
--- a/cc3200/hal/spi.c
+++ /dev/null
@@ -1,1521 +0,0 @@
-//*****************************************************************************
-//
-//  spi.c
-//
-//  Driver for the SPI.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup SPI_Serial_Peripheral_Interface_api
-//! @{
-//
-//*****************************************************************************
-
-
-#include "inc/hw_ints.h"
-#include "inc/hw_types.h"
-#include "inc/hw_memmap.h"
-#include "inc/hw_mcspi.h"
-#include "inc/hw_apps_config.h"
-#include "interrupt.h"
-#include "spi.h"
-
-
-//*****************************************************************************
-//
-// A mapping of SPI base address to interupt number.
-//
-//*****************************************************************************
-static const unsigned long g_ppulSPIIntMap[][3] =
-{
-    { SSPI_BASE, INT_SSPI }, // Shared SPI
-    { GSPI_BASE, INT_GSPI }, // Generic SPI
-    { LSPI_BASE, INT_LSPI }, // LINK SPI
-};
-
-//*****************************************************************************
-//
-// A mapping of SPI base address to DMA done interrupt mask bit(s).
-//
-//*****************************************************************************
-static const unsigned long g_ulSPIDmaMaskMap[][2]=
-{
-  {SSPI_BASE,APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK},
-  {LSPI_BASE,APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK},
-  {GSPI_BASE,APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK},
-};
-
-//*****************************************************************************
-//
-//! \internal
-//! Transfer bytes over SPI channel
-//!
-//! \param ulBase is the base address of SPI module
-//! \param ucDout is the pointer to Tx data buffer or 0.
-//! \param ucDin is pointer to Rx data buffer or 0
-//! \param ulCount is the size of data in bytes.
-//!
-//! This function transfers \e ulCount bytes of data over SPI channel.
-//!
-//! The function will not return until data has been transmitted
-//!
-//! \return Returns 0 on success, -1 otherwise.
-//
-//*****************************************************************************
-static long SPITransfer8(unsigned long ulBase, unsigned char *ucDout,
-                   unsigned char *ucDin, unsigned long ulCount,
-                   unsigned long ulFlags)
-{
-  unsigned long ulReadReg;
-  unsigned long ulWriteReg;
-  unsigned long ulStatReg;
-  unsigned long ulOutIncr;
-  unsigned long ulInIncr;
-  unsigned long ulTxDummy;
-  unsigned long ulRxDummy;
-
-  //
-  // Initialize the variables
-  //
-  ulOutIncr = 1;
-  ulInIncr  = 1;
-
-  //
-  // Check if output buffer pointer is 0
-  //
-  if(ucDout == 0)
-  {
-    ulOutIncr = 0;
-    ulTxDummy = 0xFFFFFFFF;
-    ucDout = (unsigned char *)&ulTxDummy;
-  }
-
-  //
-  // Check if input buffer pointer is 0
-  //
-  if(ucDin == 0)
-  {
-    ulInIncr = 0;
-    ucDin = (unsigned char *)&ulRxDummy;
-  }
-
-  //
-  // Load the register addresses.
-  //
-  ulReadReg  = (ulBase + MCSPI_O_RX0);
-  ulWriteReg = (ulBase + MCSPI_O_TX0);
-  ulStatReg  = (ulBase + MCSPI_O_CH0STAT);
-
-  //
-  // Enable CS based on Flag
-  //
-  if( ulFlags & SPI_CS_ENABLE)
-  {
-    HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE;
-  }
-
-  while(ulCount)
-  {
-    //
-    // Wait for space in output register/FIFO.
-    //
-    while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) )
-    {
-    }
-
-    //
-    // Write the data
-    //
-    HWREG(ulWriteReg) = *ucDout;
-
-    //
-    // Wait for data in input register/FIFO.
-    //
-    while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) )
-    {
-    }
-
-    //
-    // Read the data
-    //
-    *ucDin = HWREG(ulReadReg);
-
-    //
-    // Increment pointers.
-    //
-    ucDout = ucDout + ulOutIncr;
-    ucDin  = ucDin  + ulInIncr;
-
-    //
-    // Decrement the count.
-    //
-    ulCount--;
-  }
-
-  //
-  // Disable CS based on Flag
-  //
-  if( ulFlags & SPI_CS_DISABLE)
-  {
-    HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE;
-  }
-
-  return 0;
-}
-
-//*****************************************************************************
-//
-//! \internal
-//! Transfer half-words over SPI channel
-//!
-//! \param ulBase is the base address of SPI module
-//! \param usDout is the pointer to Tx data buffer or 0.
-//! \param usDin is pointer to Rx data buffer or 0
-//! \param ulCount is the size of data in bytes.
-//!
-//! This function transfers \e ulCount bytes of data over SPI channel. Since
-//! the API sends a half-word at a time \e ulCount should be a multiple
-//! of two.
-//!
-//! The function will not return until data has been transmitted
-//!
-//! \return Returns 0 on success, -1 otherwise.
-//
-//*****************************************************************************
-static long SPITransfer16(unsigned long ulBase, unsigned short *usDout,
-                   unsigned short *usDin, unsigned long ulCount,
-                   unsigned long ulFlags)
-{
-  unsigned long ulReadReg;
-  unsigned long ulWriteReg;
-  unsigned long ulStatReg;
-  unsigned long ulOutIncr;
-  unsigned long ulInIncr;
-  unsigned long ulTxDummy;
-  unsigned long ulRxDummy;
-
-  //
-  // Initialize the variables.
-  //
-  ulOutIncr = 1;
-  ulInIncr  = 1;
-
-  //
-  // Check if count is multiple of half-word
-  //
-  if(ulCount%2)
-  {
-    return -1;
-  }
-
-  //
-  // Compute number of half words.
-  //
-  ulCount = ulCount/2;
-
-  //
-  // Check if output buffer pointer is 0
-  //
-  if(usDout == 0)
-  {
-    ulOutIncr = 0;
-    ulTxDummy = 0xFFFFFFFF;
-    usDout = (unsigned short *)&ulTxDummy;
-  }
-
-  //
-  // Check if input buffer pointer is 0
-  //
-  if(usDin == 0)
-  {
-    ulInIncr = 0;
-    usDin = (unsigned short *)&ulRxDummy;
-  }
-
-  //
-  // Load the register addresses.
-  //
-  ulReadReg  = (ulBase + MCSPI_O_RX0);
-  ulWriteReg = (ulBase + MCSPI_O_TX0);
-  ulStatReg  = (ulBase + MCSPI_O_CH0STAT);
-
-  //
-  // Enable CS based on Flag
-  //
-  if( ulFlags & SPI_CS_ENABLE)
-  {
-    HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE;
-  }
-
-  while(ulCount)
-  {
-    //
-    // Wait for space in output register/FIFO.
-    //
-    while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) )
-    {
-    }
-
-    //
-    // Write the data
-    //
-    HWREG(ulWriteReg) = *usDout;
-
-    //
-    // Wait for data in input register/FIFO.
-    //
-    while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) )
-    {
-    }
-
-    //
-    // Read the data
-    //
-    *usDin = HWREG(ulReadReg);
-
-    //
-    // Increment pointers.
-    //
-    usDout = usDout + ulOutIncr;
-    usDin  = usDin  + ulInIncr;
-
-    //
-    // Decrement the count.
-    //
-    ulCount--;
-  }
-
-  //
-  // Disable CS based on Flag
-  //
-  if( ulFlags & SPI_CS_DISABLE)
-  {
-    HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE;
-  }
-
-  return 0;
-}
-
-//*****************************************************************************
-//
-//! \internal
-//! Transfer words over SPI channel
-//!
-//! \param ulBase is the base address of SPI module
-//! \param ulDout is the pointer to Tx data buffer or 0.
-//! \param ulDin is pointer to Rx data buffer or 0
-//! \param ulCount is the size of data in bytes.
-//!
-//! This function transfers \e ulCount bytes of data over SPI channel. Since
-//! the API sends a word at a time \e ulCount should be a multiple of four.
-//!
-//! The function will not return until data has been transmitted
-//!
-//! \return Returns 0 on success, -1 otherwise.
-//
-//*****************************************************************************
-static long SPITransfer32(unsigned long ulBase, unsigned long *ulDout,
-                   unsigned long *ulDin, unsigned long ulCount,
-                   unsigned long ulFlags)
-{
-  unsigned long ulReadReg;
-  unsigned long ulWriteReg;
-  unsigned long ulStatReg;
-  unsigned long ulOutIncr;
-  unsigned long ulInIncr;
-  unsigned long ulTxDummy;
-  unsigned long ulRxDummy;
-
-  //
-  // Initialize the variables.
-  //
-  ulOutIncr = 1;
-  ulInIncr  = 1;
-
-  //
-  // Check if count is multiple of word
-  //
-  if(ulCount%4)
-  {
-    return -1;
-  }
-
-  //
-  // Compute the number of words to be transferd
-  //
-  ulCount = ulCount/4;
-
-  //
-  // Check if output buffer pointer is 0
-  //
-  if(ulDout == 0)
-  {
-    ulOutIncr = 0;
-    ulTxDummy = 0xFFFFFFFF;
-    ulDout = &ulTxDummy;
-  }
-
-  //
-  // Check if input buffer pointer is 0
-  //
-  if(ulDin == 0)
-  {
-    ulInIncr = 0;
-    ulDin = &ulRxDummy;
-  }
-
-
-  //
-  // Load the register addresses.
-  //
-  ulReadReg  = (ulBase + MCSPI_O_RX0);
-  ulWriteReg = (ulBase + MCSPI_O_TX0);
-  ulStatReg  = (ulBase + MCSPI_O_CH0STAT);
-
-  //
-  // Enable CS based on Flag
-  //
-  if( ulFlags & SPI_CS_ENABLE)
-  {
-    HWREG( ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE;
-  }
-
-  while(ulCount)
-  {
-    //
-    // Wait for space in output register/FIFO.
-    //
-    while( !(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS) )
-    {
-    }
-
-    //
-    // Write the data
-    //
-    HWREG(ulWriteReg) = *ulDout;
-
-    //
-    // Wait for data in input register/FIFO.
-    //
-    while( !( HWREG(ulStatReg) & MCSPI_CH0STAT_RXS) )
-    {
-    }
-
-    //
-    // Read the data
-    //
-    *ulDin = HWREG(ulReadReg);
-
-    //
-    // Increment pointers.
-    //
-    ulDout = ulDout + ulOutIncr;
-    ulDin  = ulDin  + ulInIncr;
-
-    //
-    // Decrement the count.
-    //
-    ulCount--;
-  }
-
-  //
-  // Disable CS based on Flag
-  //
-  if( ulFlags & SPI_CS_DISABLE)
-  {
-    HWREG( ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE;
-  }
-
-  return 0;
-}
-
-//*****************************************************************************
-//
-//! \internal
-//! Gets the SPI interrupt number.
-//!
-//! \param ulBase is the base address of the SPI module
-//!
-//! Given a SPI base address, returns the corresponding interrupt number.
-//!
-//! \return Returns a SPI interrupt number, or -1 if \e ulBase is invalid.
-//
-//*****************************************************************************
-static long
-SPIIntNumberGet(unsigned long ulBase)
-{
-    unsigned long ulIdx;
-
-    //
-    // Loop through the table that maps SPI base addresses to interrupt
-    // numbers.
-    //
-    for(ulIdx = 0; ulIdx < (sizeof(g_ppulSPIIntMap) /
-                            sizeof(g_ppulSPIIntMap[0])); ulIdx++)
-    {
-        //
-        // See if this base address matches.
-        //
-        if(g_ppulSPIIntMap[ulIdx][0] == ulBase)
-        {
-            //
-            // Return the corresponding interrupt number.
-            //
-            return(g_ppulSPIIntMap[ulIdx][1]);
-        }
-    }
-
-    //
-    // The base address could not be found, so return an error.
-    //
-    return(-1);
-}
-
-//*****************************************************************************
-//
-//! \internal
-//! Gets the SPI DMA interrupt mask bit.
-//!
-//! \param ulBase is the base address of the SPI module
-//!
-//! Given a SPI base address, DMA interrupt mask bit.
-//!
-//! \return Returns a DMA interrupt mask bit, or -1 if \e ulBase is invalid.
-//
-//*****************************************************************************
-static long
-SPIDmaMaskGet(unsigned long ulBase)
-{
-    unsigned long ulIdx;
-
-    //
-    // Loop through the table that maps SPI base addresses to interrupt
-    // numbers.
-    //
-    for(ulIdx = 0; ulIdx < (sizeof(g_ulSPIDmaMaskMap) /
-                            sizeof(g_ulSPIDmaMaskMap[0])); ulIdx++)
-    {
-        //
-        // See if this base address matches.
-        //
-        if(g_ulSPIDmaMaskMap[ulIdx][0] == ulBase)
-        {
-            //
-            // Return the corresponding interrupt number.
-            //
-            return(g_ulSPIDmaMaskMap[ulIdx][1]);
-        }
-    }
-
-    //
-    // The base address could not be found, so return an error.
-    //
-    return(-1);
-}
-
-//*****************************************************************************
-//
-//! Enables transmitting and receiving.
-//!
-//! \param ulBase is the base address of the SPI module
-//!
-//! This function enables the SPI channel for transmitting and receiving.
-//!
-//! \return None
-//!
-//
-//*****************************************************************************
-void
-SPIEnable(unsigned long ulBase)
-{
-  //
-  // Set Channel Enable Bit
-  //
-  HWREG(ulBase + MCSPI_O_CH0CTRL) |= MCSPI_CH0CTRL_EN;
-}
-
-//*****************************************************************************
-//
-//! Disables the transmitting and receiving.
-//!
-//! \param ulBase is the base address of the SPI module
-//!
-//! This function disables the SPI channel for transmitting and receiving.
-//!
-//! \return None
-//!
-//
-//*****************************************************************************
-void
-SPIDisable(unsigned long ulBase)
-{
-  //
-  // Reset Channel Enable Bit
-  //
-  HWREG(ulBase + MCSPI_O_CH0CTRL) &= ~MCSPI_CH0CTRL_EN;
-}
-
-
-//*****************************************************************************
-//
-//! Enables the SPI DMA operation for transmitting and/or receving.
-//!
-//! \param ulBase is the base address of the SPI module
-//! \param ulFlags selectes the DMA signal for transmit and/or receive.
-//!
-//! This function enables transmit and/or receive DMA request based on the
-//! \e ulFlags parameter.
-//!
-//! The parameter \e ulFlags is the logical OR of one or more of
-//! the following :
-//! - \b SPI_RX_DMA
-//! - \b SPI_TX_DMA
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SPIDmaEnable(unsigned long ulBase, unsigned long ulFlags)
-{
-  //
-  // Enable DMA based on ulFlags
-  //
-  HWREG(ulBase + MCSPI_O_CH0CONF) |= ulFlags;
-}
-
-//*****************************************************************************
-//
-//! Disables the SPI DMA operation for transmitting and/or receving.
-//!
-//! \param ulBase is the base address of the SPI module
-//! \param ulFlags selectes the DMA signal for transmit and/or receive.
-//!
-//! This function disables transmit and/or receive DMA request based on the
-//! \e ulFlags parameter.
-//!
-//! The parameter \e ulFlags is the logical OR of one or more of
-//! the following :
-//! - \b SPI_RX_DMA
-//! - \b SPI_TX_DMA
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SPIDmaDisable(unsigned long ulBase, unsigned long ulFlags)
-{
-  //
-  // Disable DMA based on ulFlags
-  //
-  HWREG(ulBase + MCSPI_O_CH0CONF) &= ulFlags;
-}
-
-//*****************************************************************************
-//
-//! Performs a software reset of the specified SPI module
-//!
-//! \param ulBase is the base address of the SPI module
-//!
-//! This function performs a software reset of the specified SPI module
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SPIReset(unsigned long ulBase)
-{
-
-  //
-  // Assert soft reset (auto clear)
-  //
-  HWREG(ulBase + MCSPI_O_SYSCONFIG) |= MCSPI_SYSCONFIG_SOFTRESET;
-
-  //
-  // wait until reset is done
-  //
-  while(!(HWREG(ulBase + MCSPI_O_SYSSTATUS)& MCSPI_SYSSTATUS_RESETDONE))
-  {
-  }
-}
-
-//*****************************************************************************
-//
-//! Sets the configuration of a SPI module
-//!
-//! \param ulBase is the base address of the SPI module
-//! \param ulSPIClk is the rate of clock supplied to the SPI module.
-//! \param ulBitRate is the desired bit rate.(master mode)
-//! \param ulMode is the mode of operation.
-//! \param ulSubMode is one of the valid sub-modes.
-//! \param ulConfig is logical OR of configuration paramaters.
-//!
-//! This function configures SPI port for operation in specified sub-mode and
-//! required bit rated as specified by \e ulMode and \e ulBitRate parameters
-//! respectively.
-//!
-//! The SPI module can operate in either master or slave mode. The parameter
-//! \e ulMode can be one of the following
-//! -\b SPI_MODE_MASTER
-//! -\b SPI_MODE_SLAVE
-//!
-//! The SPI module supports 4 sub modes based on SPI clock polarity and phase.
-//!
-//! <pre>
-//! Polarity Phase  Sub-Mode
-//!   0       0        0
-//!   0       1        1
-//!   1       0        2
-//!   1       1        3
-//! </pre>
-//!
-//! Required sub mode can be select by setting \e ulSubMode parameter to one
-//! of the following
-//! - \b SPI_SUB_MODE_0
-//! - \b SPI_SUB_MODE_1
-//! - \b SPI_SUB_MODE_2
-//! - \b SPI_SUB_MODE_3
-//!
-//! The parameter \e ulConfig is logical OR of five values: the word length,
-//! active level for chip select, software or hardware controled chip select,
-//! 3 or 4 pin mode and turbo mode.
-//! mode.
-//!
-//! SPI support 8, 16 and 32 bit word lengths defined by:-
-//! - \b SPI_WL_8
-//! - \b SPI_WL_16
-//! - \b SPI_WL_32
-//!
-//! Active state of Chip Select can be defined by:-
-//! - \b SPI_CS_ACTIVELOW
-//! - \b SPI_CS_ACTIVEHIGH
-//!
-//! SPI chip select can be configured to be controlled either by hardware or
-//! software:-
-//! - \b SPI_SW_CS
-//! - \b SPI_HW_CS
-//!
-//! The module can work in 3 or 4 pin mode defined by:-
-//! - \b SPI_3PIN_MODE
-//! - \b SPI_4PIN_MODE
-//!
-//! Turbo mode can be set on or turned off using:-
-//! - \b SPI_TURBO_MODE_ON
-//! - \b SPI_TURBO_MODE_OFF
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk,
-            unsigned long ulBitRate, unsigned long ulMode,
-            unsigned long ulSubMode, unsigned long ulConfig)
-{
-
-  unsigned long ulRegData;
-  unsigned long ulDivider;
-
-  //
-  // Read MODULCTRL register
-  //
-  ulRegData = HWREG(ulBase + MCSPI_O_MODULCTRL);
-
-  //
-  // Set Master mode with h/w chip select
-  //
-  ulRegData &= ~(MCSPI_MODULCTRL_MS |
-                 MCSPI_MODULCTRL_SINGLE);
-
-  //
-  // Enable software control Chip Select, Init delay
-  // and 3-pin mode
-  //
-  ulRegData |= (((ulConfig >> 24) | ulMode) & 0xFF); 
-
-  //
-  // Write the configuration
-  //
-  HWREG(ulBase + MCSPI_O_MODULCTRL) = ulRegData;
-
-  //
-  // Set IS, DPE0, DPE1 based on master or slave mode
-  //
-  if(ulMode == SPI_MODE_MASTER)
-  {
-    ulRegData = 0x1 << 16;
-  }
-  else
-  {
-    ulRegData = 0x6 << 16;
-  }
-
-  //
-  // set clock divider granularity to 1 cycle
-  //
-  ulRegData |= MCSPI_CH0CONF_CLKG;
-
-  //
-  // Get the divider value
-  //
-  ulDivider = ((ulSPIClk/ulBitRate) - 1);
-
-  //
-  // The least significant four bits of the divider is used to configure
-  // CLKD in MCSPI_CHCONF next eight least significant bits are used to
-  // configure the EXTCLK in MCSPI_CHCTRL
-  //
-  ulRegData |= ((ulDivider & 0x0000000F) << 2);
-  HWREG(ulBase + MCSPI_O_CH0CTRL) = ((ulDivider & 0x00000FF0) << 4);
-
-  //
-  // Set the protocol, CS polarity, word length
-  // and turbo mode
-  //
-  ulRegData = ((ulRegData  |
-                ulSubMode) | (ulConfig & 0x0008FFFF));
-
-  //
-  // Write back the CONF register
-  //
-  HWREG(ulBase + MCSPI_O_CH0CONF) = ulRegData;
-
-}
-
-//*****************************************************************************
-//
-//! Receives a word from the specified port.
-//!
-//! \param ulBase is the base address of the SPI module.
-//! \param pulData is pointer to receive data variable.
-//!
-//! This function gets a SPI word from the receive FIFO for the specified
-//! port.
-//!
-//! \return Returns the number of elements read from the receive FIFO.
-//
-//*****************************************************************************
-long
-SPIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
-{
-  unsigned long ulRegVal;
-
-  //
-  // Read register status register
-  //
-  ulRegVal = HWREG(ulBase + MCSPI_O_CH0STAT);
-
-  //
-  // Check is data is available
-  //
-  if(ulRegVal & MCSPI_CH0STAT_RXS)
-  {
-    *pulData = HWREG(ulBase + MCSPI_O_RX0);
-    return(1);
-  }
-
-   return(0);
-}
-
-//*****************************************************************************
-//
-//! Waits for the word to be received on the specified port.
-//!
-//! \param ulBase is the base address of the SPI module.
-//! \param pulData is pointer to receive data variable.
-//!
-//! This function gets a SPI word from the receive FIFO for the specified
-//! port.  If there is no word available, this function waits until a
-//! word is received before returning.
-//!
-//! \return Returns the word read from the specified port, cast as an
-//! \e unsigned long.
-//
-//*****************************************************************************
-void
-SPIDataGet(unsigned long ulBase, unsigned long *pulData)
-{
-  //
-  // Wait for Rx data
-  //
-  while(!(HWREG(ulBase + MCSPI_O_CH0STAT) & MCSPI_CH0STAT_RXS))
-  {
-  }
-
-  //
-  // Read the value
-  //
-  *pulData = HWREG(ulBase + MCSPI_O_RX0);
-}
-
-//*****************************************************************************
-//
-//! Transmits a word on the specified port.
-//!
-//! \param ulBase is the base address of the SPI module
-//! \param ulData is data to be transmitted.
-//!
-//! This function transmits a SPI word on the transmit FIFO for the specified
-//! port.
-//!
-//! \return  Returns the number of elements written to the transmit FIFO.
-//!
-//*****************************************************************************
-long
-SPIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
-{
-    unsigned long ulRegVal;
-
-    //
-    // Read status register
-    //
-    ulRegVal = HWREG(ulBase + MCSPI_O_CH0STAT);
-
-    //
-    // Write value into Tx register/FIFO
-    // if space is available
-    //
-    if(ulRegVal & MCSPI_CH0STAT_TXS)
-    {
-      HWREG(ulBase + MCSPI_O_TX0) = ulData;
-      return(1);
-    }
-
-    return(0);
-}
-
-//*****************************************************************************
-//
-//! Waits until the word is transmitted on the specified port.
-//!
-//! \param ulBase is the base address of the SPI module
-//! \param ulData is data to be transmitted.
-//!
-//! This function transmits a SPI word on the transmit FIFO for the specified
-//! port. This function waits until the space is available on transmit FIFO
-//!
-//! \return None
-//!
-//*****************************************************************************
-void
-SPIDataPut(unsigned long ulBase, unsigned long ulData)
-{
-  //
-  // Wait for space in FIFO
-  //
-  while(!(HWREG(ulBase + MCSPI_O_CH0STAT)&MCSPI_CH0STAT_TXS))
-  {
-  }
-
-  //
-  // Write the data
-  //
-  HWREG(ulBase + MCSPI_O_TX0) = ulData;
-}
-
-//*****************************************************************************
-//
-//! Enables the transmit and/or receive FIFOs.
-//!
-//! \param ulBase is the base address of the SPI module
-//! \param ulFlags selects the FIFO(s) to be enabled
-//!
-//! This function enables the transmit and/or receive FIFOs as specified by
-//! \e ulFlags.
-//! The parameter \e ulFlags shoulde be logical OR of one or more of the
-//! following:
-//! - \b SPI_TX_FIFO
-//! - \b SPI_RX_FIFO
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags)
-{
-  //
-  // Set FIFO enable bits.
-  //
-  HWREG(ulBase + MCSPI_O_CH0CONF) |= ulFlags;
-}
-
-//*****************************************************************************
-//
-//! Disables the transmit and/or receive FIFOs.
-//!
-//! \param ulBase is the base address of the SPI module
-//! \param ulFlags selects the FIFO(s) to be enabled
-//!
-//! This function disables transmit and/or receive FIFOs. as specified by
-//! \e ulFlags.
-//! The parameter \e ulFlags shoulde be logical OR of one or more of the
-//! following:
-//! - \b SPI_TX_FIFO
-//! - \b SPI_RX_FIFO
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags)
-{
-  //
-  // Reset FIFO Enable bits.
-  //
-  HWREG(ulBase + MCSPI_O_CH0CONF) &= ~(ulFlags);
-}
-
-//*****************************************************************************
-//
-//! Sets the FIFO level at which DMA requests or interrupts are generated.
-//!
-//! \param ulBase is the base address of the SPI module
-//! \param ulTxLevel is the Almost Empty Level for transmit FIFO.
-//! \param ulRxLevel is the Almost Full Level for the receive FIFO.
-//!
-//! This function Sets the FIFO level at which DMA requests or interrupts
-//! are generated.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
-                   unsigned long ulRxLevel)
-{
-  unsigned long ulRegVal;
-
-  //
-  // Read the current configuration
-  //
-  ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL);
-
-  //
-  // Mask and set new FIFO thresholds.
-  //
-  ulRegVal = ((ulRegVal & 0xFFFF0000) | (((ulRxLevel-1) << 8) | (ulTxLevel-1)));
-
-  //
-  // Set the transmit and receive FIFO thresholds.
-  //
-  HWREG(ulBase + MCSPI_O_XFERLEVEL) = ulRegVal;
-
-}
-
-//*****************************************************************************
-//
-//! Gets the FIFO level at which DMA requests or interrupts are generated.
-//!
-//! \param ulBase is the base address of the SPI module
-//! \param pulTxLevel is a pointer to storage for the transmit FIFO level
-//! \param pulRxLevel is a pointer to storage for the receive FIFO level
-//!
-//! This function gets the FIFO level at which DMA requests or interrupts
-//! are generated.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
-                 unsigned long *pulRxLevel)
-{
-  unsigned long ulRegVal;
-
-  //
-  // Read the current configuration
-  //
-  ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL);
-
-  *pulTxLevel = (ulRegVal & 0xFF);
-
-  *pulRxLevel = ((ulRegVal >> 8) & 0xFF);
-
-}
-
-//*****************************************************************************
-//
-//! Sets the word count.
-//!
-//! \param ulBase is the base address of the SPI module
-//! \param ulWordCount is number of SPI words to be transmitted.
-//!
-//! This function sets the word count, which is the number of SPI word to
-//! be transferred on channel when using the FIFO buffer.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount)
-{
-  unsigned long ulRegVal;
-
-  //
-  // Read the current configuration
-  //
-  ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL);
-
-  //
-  // Mask and set the word count
-  //
-  HWREG(ulBase + MCSPI_O_XFERLEVEL) = ((ulRegVal & 0x0000FFFF)|
-                                      (ulWordCount & 0xFFFF) << 16);
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for a SPI interrupt.
-//!
-//! \param ulBase is the base address of the SPI module
-//! \param pfnHandler is a pointer to the function to be called when the
-//! SPI interrupt occurs.
-//!
-//! This function does the actual registering of the interrupt handler.  This
-//! function enables the global interrupt in the interrupt controller; specific
-//! SPI interrupts must be enabled via SPIIntEnable(). It is the interrupt
-//! handler's responsibility to clear the interrupt source.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SPIIntRegister(unsigned long ulBase, void(*pfnHandler)(void))
-{
-    unsigned long ulInt;
-
-    //
-    // Determine the interrupt number based on the SPI module
-    //
-    ulInt = SPIIntNumberGet(ulBase);
-
-    //
-    // Register the interrupt handler.
-    //
-    IntRegister(ulInt, pfnHandler);
-
-    //
-    // Enable the SPI interrupt.
-    //
-    IntEnable(ulInt);
-}
-
-//*****************************************************************************
-//
-//! Unregisters an interrupt handler for a SPI interrupt.
-//!
-//! \param ulBase is the base address of the SPI module
-//!
-//! This function does the actual unregistering of the interrupt handler.  It
-//! clears the handler to be called when a SPI interrupt occurs.  This
-//! function also masks off the interrupt in the interrupt controller so that
-//! the interrupt handler no longer is called.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SPIIntUnregister(unsigned long ulBase)
-{
-    unsigned long ulInt;
-
-    //
-    // Determine the interrupt number based on the SPI module
-    //
-    ulInt = SPIIntNumberGet(ulBase);
-
-    //
-    // Disable the interrupt.
-    //
-    IntDisable(ulInt);
-
-    //
-    // Unregister the interrupt handler.
-    //
-    IntUnregister(ulInt);
-}
-
-//*****************************************************************************
-//
-//! Enables individual SPI interrupt sources.
-//!
-//! \param ulBase is the base address of the SPI module
-//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
-//!
-//! This function enables the indicated SPI interrupt sources.  Only the
-//! sources that are enabled can be reflected to the processor interrupt;
-//! disabled sources have no effect on the processor.
-//!
-//! The \e ulIntFlags parameter is the logical OR of any of the following:
-//!
-//! - \b SPI_INT_DMATX
-//! - \b SPI_INT_DMARX
-//! - \b SPI_INT_EOW
-//! - \b SPI_INT_RX_OVRFLOW
-//! - \b SPI_INT_RX_FULL
-//! - \b SPI_INT_TX_UDRFLOW
-//! - \b SPI_INT_TX_EMPTY
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
-{
-  unsigned long ulDmaMsk;
-
-  //
-  // Enable DMA  Tx Interrupt
-  //
-  if(ulIntFlags & SPI_INT_DMATX)
-  {
-      ulDmaMsk = SPIDmaMaskGet(ulBase);
-      HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk;
-  }
-
-  //
-  // Enable DMA  Rx Interrupt
-  //
-  if(ulIntFlags & SPI_INT_DMARX)
-  {
-      ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1);
-      HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk;
-  }
-
-  //
-  // Enable the specific Interrupts
-  //
-  HWREG(ulBase + MCSPI_O_IRQENABLE) |= (ulIntFlags & 0x0003000F);
-}
-
-
-//*****************************************************************************
-//
-//! Disables individual SPI interrupt sources.
-//!
-//! \param ulBase is the base address of the SPI module
-//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
-//!
-//! This function disables the indicated SPI interrupt sources.  Only the
-//! sources that are enabled can be reflected to the processor interrupt;
-//! disabled sources have no effect on the processor.
-//!
-//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
-//! parameter to SPIIntEnable().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
-{
-  unsigned long ulDmaMsk;
-
-  //
-  // Disable DMA  Tx Interrupt
-  //
-  if(ulIntFlags & SPI_INT_DMATX)
-  {
-      ulDmaMsk = SPIDmaMaskGet(ulBase);
-      HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk;
-  }
-
-  //
-  // Disable DMA  Tx Interrupt
-  //
-  if(ulIntFlags & SPI_INT_DMARX)
-  {
-      ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1);
-      HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk;
-  }
-
-  //
-  // Disable the specific Interrupts
-  //
-  HWREG(ulBase + MCSPI_O_IRQENABLE) &= ~(ulIntFlags & 0x0003000F);
-}
-
-//*****************************************************************************
-//
-//! Gets the current interrupt status.
-//!
-//! \param ulBase is the base address of the SPI module
-//! \param bMasked is \b false if the raw interrupt status is required and
-//! \b true if the masked interrupt status is required.
-//!
-//! This function returns the interrupt status for the specified SPI.
-//! The status of interrupts that are allowed to reflect to the processor can
-//! be returned.
-//!
-//! \return Returns the current interrupt status, enumerated as a bit field of
-//! values described in SPIIntEnable().
-//
-//*****************************************************************************
-unsigned long
-SPIIntStatus(unsigned long ulBase, tBoolean bMasked)
-{
-  unsigned long ulIntStat;
-  unsigned long ulIntFlag;
-  unsigned long ulDmaMsk;
-
-  //
-  // Get SPI interrupt status
-  //
-  ulIntFlag = HWREG(ulBase + MCSPI_O_IRQSTATUS) & 0x0003000F;
-
-  if(bMasked)
-  {
-     ulIntFlag &= HWREG(ulBase + MCSPI_O_IRQENABLE);
-  }
-
-  //
-  // Get the interrupt bit
-  //
-  ulDmaMsk = SPIDmaMaskGet(ulBase);
-
-  //
-  // Get the DMA interrupt status
-  //
-  if(bMasked)
-  {
-    ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED);
-  }
-  else
-  {
-    ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW);
-  }
-
-  //
-  // Get SPI Tx DMA done status
-  //
-  if(ulIntStat & ulDmaMsk)
-  {
-     ulIntFlag |= SPI_INT_DMATX;
-  }
-
-  //
-  // Get SPI Rx DMA done status
-  //
-  if(ulIntStat & (ulDmaMsk >> 1))
-  {
-     ulIntFlag |= SPI_INT_DMARX;
-  }
-
-  //
-  // Return status
-  //
-  return(ulIntFlag);
-}
-
-//*****************************************************************************
-//
-//! Clears SPI interrupt sources.
-//!
-//! \param ulBase is the base address of the SPI module
-//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
-//!
-//! The specified SPI interrupt sources are cleared, so that they no longer
-//! assert.  This function must be called in the interrupt handler to keep the
-//! interrupt from being recognized again immediately upon exit.
-//!
-//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
-//! parameter to SPIIntEnable().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
-{
-  unsigned long ulDmaMsk;
-
-  //
-  // Disable DMA  Tx Interrupt
-  //
-  if(ulIntFlags & SPI_INT_DMATX)
-  {
-      ulDmaMsk = SPIDmaMaskGet(ulBase);
-      HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk;
-  }
-
-  //
-  // Disable DMA  Tx Interrupt
-  //
-  if(ulIntFlags & SPI_INT_DMARX)
-  {
-      ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1);
-      HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk;
-  }
-
-  //
-  // Clear Interrupts
-  //
-  HWREG(ulBase + MCSPI_O_IRQSTATUS) = (ulIntFlags & 0x0003000F);
-}
-
-//*****************************************************************************
-//
-//! Enables the chip select in software controlled mode
-//!
-//! \param ulBase is the base address of the SPI module.
-//!
-//! This function enables the Chip select in software controlled mode. The
-//! active state of CS will depend on the configuration done via
-//! \sa SPIConfigExpClkSet().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void SPICSEnable(unsigned long ulBase)
-{
-  //
-  // Set Chip Select enable bit.
-  //
-  HWREG( ulBase+MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE;
-}
-
-//*****************************************************************************
-//
-//! Disables the chip select in software controlled mode
-//!
-//! \param ulBase is the base address of the SPI module.
-//!
-//! This function disables the Chip select in software controlled mode. The
-//! active state of CS will depend on the configuration done via
-//! sa SPIConfigSetExpClk().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void SPICSDisable(unsigned long ulBase)
-{
-  //
-  // Reset Chip Select enable bit.
-  //
-  HWREG( ulBase+MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE;
-}
-
-//*****************************************************************************
-//
-//! Send/Receive data buffer over SPI channel
-//!
-//! \param ulBase is the base address of SPI module
-//! \param ucDout is the pointer to Tx data buffer or 0.
-//! \param ucDin is pointer to Rx data buffer or 0
-//! \param ulCount is the size of data in bytes.
-//! \param ulFlags controlls chip select toggling.
-//!
-//! This function transfers \e ulCount bytes of data over SPI channel. Since
-//! the API sends a SPI word at a time \e ulCount should be a multiple of
-//! word length set using SPIConfigSetExpClk().
-//!
-//! If the \e ucDout parameter is set to 0, the function will send 0xFF over
-//! the SPI MOSI line.
-//!
-//! If the \e ucDin parameter is set to 0, the function will ignore data on SPI
-//! MISO line.
-//!
-//! The parameter \e ulFlags is logical OR of one or more of the following
-//!
-//! - \b SPI_CS_ENABLE if CS needs to be enabled at start of transfer.
-//! - \b SPI_CS_DISABLE if CS need to be disabled at the end of transfer.
-//!
-//! This function will not return until data has been transmitted
-//!
-//! \return Returns 0 on success, -1 otherwise.
-//
-//*****************************************************************************
-long SPITransfer(unsigned long ulBase, unsigned char *ucDout,
-                   unsigned char *ucDin, unsigned long ulCount,
-                   unsigned long ulFlags)
-{
-  unsigned long ulWordLength;
-  long lRet;
-
-  //
-  // Get the word length
-  //
-  ulWordLength = (HWREG(ulBase + MCSPI_O_CH0CONF) & MCSPI_CH0CONF_WL_M);
-
-  //
-  // Check for word length.
-  //
-  if( !((ulWordLength == SPI_WL_8) || (ulWordLength == SPI_WL_16) ||
-     (ulWordLength == SPI_WL_32)) )
-  {
-    return -1;
-  }
-
-  if( ulWordLength == SPI_WL_8 )
-  {
-    //
-    // Do byte transfer
-    //
-    lRet = SPITransfer8(ulBase,ucDout,ucDin,ulCount,ulFlags);
-  }
-  else if( ulWordLength == SPI_WL_16 )
-  {
-
-    //
-    // Do half-word transfer
-    //
-    lRet = SPITransfer16(ulBase,(unsigned short *)ucDout,
-                  (unsigned short *)ucDin,ulCount,ulFlags);
-  }
-  else
-  {
-    //
-    // Do word transfer
-    //
-    lRet = SPITransfer32(ulBase,(unsigned long *)ucDout,
-                  (unsigned long *)ucDin,ulCount,ulFlags);
-  }
-
-  //
-  // return
-  //
-  return lRet;
-
-}
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
diff --git a/cc3200/hal/spi.h b/cc3200/hal/spi.h
deleted file mode 100644
index 593986bc6..000000000
--- a/cc3200/hal/spi.h
+++ /dev/null
@@ -1,163 +0,0 @@
-//*****************************************************************************
-//
-//  spi.h
-//
-// Defines and Macros for the SPI.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __SPI_H__
-#define __SPI_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-// Values that can be passed to SPIConfigSetExpClk() as ulMode parameter
-//*****************************************************************************
-#define SPI_MODE_MASTER    0x00000000
-#define SPI_MODE_SLAVE     0x00000004
-
-//*****************************************************************************
-// Values that can be passed to SPIConfigSetExpClk() as ulSubMode parameter
-//*****************************************************************************
-#define SPI_SUB_MODE_0     0x00000000
-#define SPI_SUB_MODE_1     0x00000001
-#define SPI_SUB_MODE_2     0x00000002
-#define SPI_SUB_MODE_3     0x00000003
-
-
-//*****************************************************************************
-// Values that can be passed to SPIConfigSetExpClk() as ulConfigFlags parameter
-//*****************************************************************************
-#define SPI_SW_CTRL_CS      0x01000000
-#define SPI_HW_CTRL_CS      0x00000000
-#define SPI_3PIN_MODE       0x02000000
-#define SPI_4PIN_MODE       0x00000000
-#define SPI_TURBO_ON        0x00080000
-#define SPI_TURBO_OFF       0x00000000
-#define SPI_CS_ACTIVEHIGH   0x00000000
-#define SPI_CS_ACTIVELOW    0x00000040
-#define SPI_WL_8            0x00000380
-#define SPI_WL_16           0x00000780
-#define SPI_WL_32           0x00000F80
-
-//*****************************************************************************
-// Values that can be passed to SPIFIFOEnable() and SPIFIFODisable()
-//*****************************************************************************
-#define SPI_TX_FIFO        0x08000000
-#define SPI_RX_FIFO        0x10000000
-
-//*****************************************************************************
-// Values that can be passed to SPIDMAEnable() and SPIDMADisable()
-//*****************************************************************************
-#define SPI_RX_DMA         0x00008000
-#define SPI_TX_DMA         0x00004000
-
-//*****************************************************************************
-// Values that can be passed to SPIIntEnable(), SPIIntDiasble(),
-// SPIIntClear() or returned from SPIStatus()
-//*****************************************************************************
-#define SPI_INT_DMATX         0x20000000
-#define SPI_INT_DMARX         0x10000000
-#define SPI_INT_EOW           0x00020000
-#define SPI_INT_WKS           0x00010000
-#define SPI_INT_RX_OVRFLOW    0x00000008
-#define SPI_INT_RX_FULL       0x00000004
-#define SPI_INT_TX_UDRFLOW    0x00000002
-#define SPI_INT_TX_EMPTY      0x00000001
-
-//*****************************************************************************
-// Values that can be passed to SPITransfer()
-//*****************************************************************************
-#define SPI_CS_ENABLE  0x00000001
-#define SPI_CS_DISABLE 0x00000002
-
-//*****************************************************************************
-//
-// API Function prototypes
-//
-//*****************************************************************************
-extern void SPIEnable(unsigned long ulBase);
-extern void SPIDisable(unsigned long ulBase);
-extern void SPIReset(unsigned long ulBase);
-extern void SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk,
-            unsigned long ulBitRate, unsigned long ulMode,
-            unsigned long ulSubMode, unsigned long ulConfig);
-extern long SPIDataGetNonBlocking(unsigned long ulBase,
-                                        unsigned long * pulData);
-extern void SPIDataGet(unsigned long ulBase, unsigned long *pulData);
-extern long SPIDataPutNonBlocking(unsigned long ulBase,
-                                        unsigned long ulData);
-extern void SPIDataPut(unsigned long ulBase, unsigned long ulData);
-extern void SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags);
-extern void SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags);
-extern void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
-                   unsigned long ulRxLevel);
-extern void SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
-                 unsigned long *pulRxLevel);
-extern void SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount);
-extern void SPIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
-extern void SPIIntUnregister(unsigned long ulBase);
-extern void SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
-extern void SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
-extern unsigned long SPIIntStatus(unsigned long ulBase, tBoolean bMasked);
-extern void SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
-extern void SPIDmaEnable(unsigned long ulBase, unsigned long ulFlags);
-extern void SPIDmaDisable(unsigned long ulBase, unsigned long ulFlags);
-extern void SPICSEnable(unsigned long ulBase);
-extern void SPICSDisable(unsigned long ulBase);
-extern long SPITransfer(unsigned long ulBase, unsigned char *ucDout,
-                   unsigned char *ucDin, unsigned long ulSize,
-                   unsigned long ulFlags);
-
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif //  __SPI_H__
diff --git a/cc3200/hal/startup_gcc.c b/cc3200/hal/startup_gcc.c
deleted file mode 100644
index e173e8fda..000000000
--- a/cc3200/hal/startup_gcc.c
+++ /dev/null
@@ -1,421 +0,0 @@
-//*****************************************************************************
-// startup_gcc.c
-//
-// Startup code for use with GCC.
-//
-// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#include <stdint.h>
-#include "inc/hw_nvic.h"
-#include "inc/hw_types.h"
-#include "fault_registers.h"
-
-//*****************************************************************************
-//
-// The following are constructs created by the linker, indicating where the
-// the "data" and "bss" segments reside in memory.  The initializers for the
-// for the "data" segment resides immediately following the "text" segment.
-//
-//*****************************************************************************
-extern uint32_t _data;
-extern uint32_t _edata;
-extern uint32_t _bss;
-extern uint32_t _ebss;
-extern uint32_t _estack;
-
-//*****************************************************************************
-//
-// Forward declaration of the default fault handlers.
-//
-//*****************************************************************************
-#ifndef BOOTLOADER
-__attribute__ ((section (".boot")))
-#endif
-void ResetISR(void);
-#ifdef DEBUG
-static void NmiSR(void) __attribute__( ( naked ) );
-static void FaultISR( void ) __attribute__( ( naked ) );
-void HardFault_HandlerC(uint32_t *pulFaultStackAddress);
-static void BusFaultHandler(void) __attribute__( ( naked ) );
-#endif
-static void IntDefaultHandler(void) __attribute__( ( naked ) );
-
-//*****************************************************************************
-//
-// External declaration for the freeRTOS handlers
-//
-//*****************************************************************************
-#ifdef USE_FREERTOS
-extern void vPortSVCHandler(void);
-extern void xPortPendSVHandler(void);
-extern void xPortSysTickHandler(void);
-#endif
-
-//*****************************************************************************
-//
-// The entry point for the application.
-//
-//*****************************************************************************
-extern int main(void);
-
-//*****************************************************************************
-//
-// The vector table.  Note that the proper constructs must be placed on this to
-// ensure that it ends up at physical address 0x0000.0000.
-//
-//*****************************************************************************
-__attribute__ ((section(".intvecs")))
-void (* const g_pfnVectors[256])(void) =
-{
-    (void (*)(void))((uint32_t)&_estack),   // The initial stack pointer
-    ResetISR,                               // The reset handler
-#ifdef DEBUG
-    NmiSR,                                  // The NMI handler
-    FaultISR,                               // The hard fault handler
-#else
-    IntDefaultHandler,                      // The NMI handler
-    IntDefaultHandler,                      // The hard fault handler
-#endif
-    IntDefaultHandler,                      // The MPU fault handler
-#ifdef DEBUG
-    BusFaultHandler,                        // The bus fault handler
-#else
-    IntDefaultHandler,                      // The bus fault handler
-#endif
-    IntDefaultHandler,                      // The usage fault handler
-    0,                                      // Reserved
-    0,                                      // Reserved
-    0,                                      // Reserved
-    0,                                      // Reserved
-#ifdef USE_FREERTOS
-    vPortSVCHandler,                        // SVCall handler
-#else
-    IntDefaultHandler,                      // SVCall handler
-#endif
-    IntDefaultHandler,                      // Debug monitor handler
-    0,                                      // Reserved
-#ifdef USE_FREERTOS
-    xPortPendSVHandler,                     // The PendSV handler
-    xPortSysTickHandler,                    // The SysTick handler
-#else
-    IntDefaultHandler,                      // The PendSV handler
-    IntDefaultHandler,                      // The SysTick handler
-#endif
-    IntDefaultHandler,                      // GPIO Port A
-    IntDefaultHandler,                      // GPIO Port B
-    IntDefaultHandler,                      // GPIO Port C
-    IntDefaultHandler,                      // GPIO Port D
-    0,                                      // Reserved
-    IntDefaultHandler,                      // UART0 Rx and Tx
-    IntDefaultHandler,                      // UART1 Rx and Tx
-    0,                                      // Reserved
-    IntDefaultHandler,                      // I2C0 Master and Slave
-    0,0,0,0,0,                              // Reserved
-    IntDefaultHandler,                      // ADC Channel 0
-    IntDefaultHandler,                      // ADC Channel 1
-    IntDefaultHandler,                      // ADC Channel 2
-    IntDefaultHandler,                      // ADC Channel 3
-    IntDefaultHandler,                      // Watchdog Timer
-    IntDefaultHandler,                      // Timer 0 subtimer A
-    IntDefaultHandler,                      // Timer 0 subtimer B
-    IntDefaultHandler,                      // Timer 1 subtimer A
-    IntDefaultHandler,                      // Timer 1 subtimer B
-    IntDefaultHandler,                      // Timer 2 subtimer A
-    IntDefaultHandler,                      // Timer 2 subtimer B
-    0,0,0,0,                                // Reserved
-    IntDefaultHandler,                      // Flash
-    0,0,0,0,0,                              // Reserved
-    IntDefaultHandler,                      // Timer 3 subtimer A
-    IntDefaultHandler,                      // Timer 3 subtimer B
-    0,0,0,0,0,0,0,0,0,                      // Reserved
-    IntDefaultHandler,                      // uDMA Software Transfer
-    IntDefaultHandler,                      // uDMA Error
-    0,0,0,0,0,0,0,0,0,0,                    // Reserved
-    0,0,0,0,0,0,0,0,0,0,                    // Reserved
-    0,0,0,0,0,0,0,0,0,0,                    // Reserved
-    0,0,0,0,0,0,0,0,0,0,                    // Reserved
-    0,0,0,0,0,0,0,0,0,0,                    // Reserved
-    0,0,0,0,0,0,0,0,0,0,                    // Reserved
-    0,0,0,0,0,0,0,0,0,0,                    // Reserved
-    0,0,0,0,0,0,0,0,0,0,                    // Reserved
-    0,0,0,0,0,0,0,0,0,0,                    // Reserved
-    0,0,0,0,0,0,0,0,0,0,                    // Reserved
-    IntDefaultHandler,                      // SHA
-    0,0,                                    // Reserved
-    IntDefaultHandler,                      // AES
-    0,                                      // Reserved
-    IntDefaultHandler,                      // DES
-    0,0,0,0,0,                              // Reserved
-    IntDefaultHandler,                      // SDHost
-    0,                                      // Reserved
-    IntDefaultHandler,                      // I2S
-    0,                                      // Reserved
-    IntDefaultHandler,                      // Camera
-    0,0,0,0,0,0,0,                          // Reserved
-    IntDefaultHandler,                      // NWP to APPS Interrupt
-    IntDefaultHandler,                      // Power, Reset and Clock module
-    0,0,                                    // Reserved
-    IntDefaultHandler,                      // Shared SPI
-    IntDefaultHandler,                      // Generic SPI
-    IntDefaultHandler,                      // Link SPI
-    0,0,0,0,0,0,0,0,0,0,                    // Reserved
-    0,0,0,0,0,0,0,0,0,0,                    // Reserved
-    0,0,0,0,0,0,0,0,0,0,                    // Reserved
-    0,0,0,0,0,0,0,0,0,0,                    // Reserved
-    0,0,0,0,0,0,0,0,0,0,                    // Reserved
-    0,0,0,0,0,0,0,0,0,0,                    // Reserved
-    0,0                                     // Reserved
-};
-
-
-
-//*****************************************************************************
-//
-// This is the code that gets called when the processor first starts execution
-// following a reset event.  Only the absolutely necessary set is performed,
-// after which the application supplied entry() routine is called.  Any fancy
-// actions (such as making decisions based on the reset cause register, and
-// resetting the bits in that register) are left solely in the hands of the
-// application.
-//
-//*****************************************************************************
-
-void ResetISR(void)
-{
-#if defined(DEBUG) && !defined(BOOTLOADER)
-    {
-        //
-        // Fill the main stack with a known value so that
-        // we can measure the main stack high water mark
-        //
-        __asm volatile
-        (
-                "ldr     r0, =_stack        \n"
-                "ldr     r1, =_estack       \n"
-                "mov     r2, #0x55555555    \n"
-        ".thumb_func                        \n"
-        "fill_loop:                         \n"
-                "cmp     r0, r1             \n"
-                "it      lt                 \n"
-                "strlt   r2, [r0], #4       \n"
-                "blt     fill_loop          \n"
-        );
-    }
-#endif
-
-    {
-        // Get the initial stack pointer location from the vector table
-        // and write this value to the msp register
-        __asm volatile
-        (
-                "ldr r0, =_text             \n"
-                "ldr r0, [r0]               \n"
-                "msr msp, r0                \n"
-        );
-    }
-
-    {
-        //
-        // Zero fill the bss segment.
-        //
-        __asm volatile
-        (
-                "ldr     r0, =_bss      \n"
-                "ldr     r1, =_ebss     \n"
-                "mov     r2, #0         \n"
-        ".thumb_func                    \n"
-        "zero_loop:                     \n"
-                "cmp     r0, r1         \n"
-                "it      lt             \n"
-                "strlt   r2, [r0], #4   \n"
-                "blt     zero_loop      \n"
-        );
-    }
-
-    {
-        //
-        // Call the application's entry point.
-        //
-        main();
-    }
-}
-
-#ifdef DEBUG
-//*****************************************************************************
-//
-// This is the code that gets called when the processor receives a NMI.  This
-// simply enters an infinite loop, preserving the system state for examination
-// by a debugger.
-//
-//*****************************************************************************
-
-static void NmiSR(void)
-{
-    // Break into the debugger
-    __asm volatile ("bkpt #0  \n");
-
-    //
-    // Enter an infinite loop.
-    //
-    for ( ; ; )
-    {
-    }
-}
-
-//*****************************************************************************
-//
-// This is the code that gets called when the processor receives a hard fault
-// interrupt.  This simply enters an infinite loop, preserving the system state
-// for examination by a debugger.
-//
-//*****************************************************************************
-
-static void FaultISR(void)
-{
-        /*
-         * Get the appropriate stack pointer, depending on our mode,
-         * and use it as the parameter to the C handler. This function
-         * will never return
-         */
-
-        __asm volatile
-        (
-                "movs   r0, #4  \n"
-                "mov    r1, lr  \n"
-                "tst    r0, r1  \n"
-                "beq    _msp    \n"
-                "mrs    r0, psp \n"
-                "b      HardFault_HandlerC      \n"
-        "_msp:  \n"
-                "mrs    r0, msp \n"
-                "b      HardFault_HandlerC      \n"
-        ) ;
-}
-
-//***********************************************************************************
-// HardFaultHandler_C:
-// This is called from the FaultISR with a pointer the Fault stack
-// as the parameter. We can then read the values from the stack and place them
-// into local variables for ease of reading.
-// We then read the various Fault Status and Address Registers to help decode
-// cause of the fault.
-// The function ends with a BKPT instruction to force control back into the debugger
-//***********************************************************************************
-void HardFault_HandlerC(uint32_t *pulFaultStackAddress)
-{
-    volatile uint32_t r0 ;
-    volatile uint32_t r1 ;
-    volatile uint32_t r2 ;
-    volatile uint32_t r3 ;
-    volatile uint32_t r12 ;
-    volatile uint32_t lr ;
-    volatile uint32_t pc ;
-    volatile uint32_t psr ;
-    volatile _CFSR_t _CFSR ;
-    volatile _HFSR_t _HFSR ;
-    volatile uint32_t _BFAR ;
-
-
-    r0  = pulFaultStackAddress[0];
-    r1  = pulFaultStackAddress[1];
-    r2  = pulFaultStackAddress[2];
-    r3  = pulFaultStackAddress[3];
-    r12 = pulFaultStackAddress[4];
-    lr  = pulFaultStackAddress[5];
-    pc  = pulFaultStackAddress[6];
-    psr = pulFaultStackAddress[7];
-
-    // Configurable Fault Status Register
-    // Consists of MMSR, BFSR and UFSR
-    _CFSR = (*((volatile _CFSR_t *)(0xE000ED28)));
-    // Hard Fault Status Register
-    _HFSR = (*((volatile _HFSR_t *)(0xE000ED2C)));
-    // Bus Fault Address Register
-    _BFAR = (*((volatile uint32_t *)(0xE000ED38)));
-
-    // Break into the debugger
-    __asm volatile ("bkpt #0  \n");
-
-    for ( ; ; )
-    {
-        // Keep the compiler happy
-        (void)r0, (void)r1, (void)r2, (void)r3, (void)r12, (void)lr, (void)pc, (void)psr;
-        (void)_CFSR, (void)_HFSR, (void)_BFAR;
-    }
-}
-
-//*****************************************************************************
-//
-// This is the code that gets called when the processor receives an unexpected
-// interrupt.  This simply enters an infinite loop, preserving the system state
-// for examination by a debugger.
-//
-//*****************************************************************************
-
-static void BusFaultHandler(void)
-{
-    // Break into the debugger
-    __asm volatile ("bkpt #0  \n");
-
-    //
-    // Enter an infinite loop.
-    //
-    for ( ; ; )
-    {
-    }
-}
-#endif
-
-//*****************************************************************************
-//
-// This is the code that gets called when the processor receives an unexpected
-// interrupt.  This simply enters an infinite loop, preserving the system state
-// for examination by a debugger.
-//
-//*****************************************************************************
-static void IntDefaultHandler(void)
-{
-#ifdef DEBUG
-    // Break into the debugger
-    __asm volatile ("bkpt #0  \n");
-#endif
-
-    //
-    // Enter an infinite loop.
-    //
-    for ( ; ; )
-    {
-    }
-}
-
diff --git a/cc3200/hal/systick.c b/cc3200/hal/systick.c
deleted file mode 100644
index 550e3ed1d..000000000
--- a/cc3200/hal/systick.c
+++ /dev/null
@@ -1,275 +0,0 @@
-//*****************************************************************************
-//
-//  systick.c
-//
-//  Driver for the SysTick timer in NVIC.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup systick_api
-//! @{
-//
-//*****************************************************************************
-
-#include "inc/hw_ints.h"
-#include "inc/hw_nvic.h"
-#include "inc/hw_types.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "systick.h"
-
-//*****************************************************************************
-//
-//! Enables the SysTick counter.
-//!
-//! This function starts the SysTick counter.  If an interrupt handler has been
-//! registered, it is called when the SysTick counter rolls over.
-//!
-//! \note Calling this function causes the SysTick counter to (re)commence
-//! counting from its current value.  The counter is not automatically reloaded
-//! with the period as specified in a previous call to SysTickPeriodSet().  If
-//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
-//! written to force the reload.  Any write to this register clears the SysTick
-//! counter to 0 and causes a reload with the supplied period on the next
-//! clock.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickEnable(void)
-{
-    //
-    // Enable SysTick.
-    //
-    HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE;
-}
-
-//*****************************************************************************
-//
-//! Disables the SysTick counter.
-//!
-//! This function stops the SysTick counter.  If an interrupt handler has been
-//! registered, it is not called until SysTick is restarted.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickDisable(void)
-{
-    //
-    // Disable SysTick.
-    //
-    HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE);
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for the SysTick interrupt.
-//!
-//! \param pfnHandler is a pointer to the function to be called when the
-//! SysTick interrupt occurs.
-//!
-//! This function registers the handler to be called when a SysTick interrupt
-//! occurs.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickIntRegister(void (*pfnHandler)(void))
-{
-    //
-    // Register the interrupt handler, returning an error if an error occurs.
-    //
-    IntRegister(FAULT_SYSTICK, pfnHandler);
-
-    //
-    // Enable the SysTick interrupt.
-    //
-    HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
-}
-
-//*****************************************************************************
-//
-//! Unregisters the interrupt handler for the SysTick interrupt.
-//!
-//! This function unregisters the handler to be called when a SysTick interrupt
-//! occurs.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickIntUnregister(void)
-{
-    //
-    // Disable the SysTick interrupt.
-    //
-    HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
-
-    //
-    // Unregister the interrupt handler.
-    //
-    IntUnregister(FAULT_SYSTICK);
-}
-
-//*****************************************************************************
-//
-//! Enables the SysTick interrupt.
-//!
-//! This function enables the SysTick interrupt, allowing it to be
-//! reflected to the processor.
-//!
-//! \note The SysTick interrupt handler is not required to clear the SysTick
-//! interrupt source because it is cleared automatically by the NVIC when the
-//! interrupt handler is called.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickIntEnable(void)
-{
-    //
-    // Enable the SysTick interrupt.
-    //
-    HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
-}
-
-//*****************************************************************************
-//
-//! Disables the SysTick interrupt.
-//!
-//! This function disables the SysTick interrupt, preventing it from being
-//! reflected to the processor.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickIntDisable(void)
-{
-    //
-    // Disable the SysTick interrupt.
-    //
-    HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
-}
-
-//*****************************************************************************
-//
-//! Sets the period of the SysTick counter.
-//!
-//! \param ulPeriod is the number of clock ticks in each period of the SysTick
-//! counter and must be between 1 and 16,777,216, inclusive.
-//!
-//! This function sets the rate at which the SysTick counter wraps, which
-//! equates to the number of processor clocks between interrupts.
-//!
-//! \note Calling this function does not cause the SysTick counter to reload
-//! immediately.  If an immediate reload is required, the \b NVIC_ST_CURRENT
-//! register must be written.  Any write to this register clears the SysTick
-//! counter to 0 and causes a reload with the \e ulPeriod supplied here on
-//! the next clock after SysTick is enabled.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-SysTickPeriodSet(unsigned long ulPeriod)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216));
-
-    //
-    // Set the period of the SysTick counter.
-    //
-    HWREG(NVIC_ST_RELOAD) = ulPeriod - 1;
-}
-
-//*****************************************************************************
-//
-//! Gets the period of the SysTick counter.
-//!
-//! This function returns the rate at which the SysTick counter wraps, which
-//! equates to the number of processor clocks between interrupts.
-//!
-//! \return Returns the period of the SysTick counter.
-//
-//*****************************************************************************
-unsigned long
-SysTickPeriodGet(void)
-{
-    //
-    // Return the period of the SysTick counter.
-    //
-    return(HWREG(NVIC_ST_RELOAD) + 1);
-}
-
-//*****************************************************************************
-//
-//! Gets the current value of the SysTick counter.
-//!
-//! This function returns the current value of the SysTick counter, which is
-//! a value between the period - 1 and zero, inclusive.
-//!
-//! \return Returns the current value of the SysTick counter.
-//
-//*****************************************************************************
-unsigned long
-SysTickValueGet(void)
-{
-    //
-    // Return the current value of the SysTick counter.
-    //
-    return(HWREG(NVIC_ST_CURRENT));
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
diff --git a/cc3200/hal/systick.h b/cc3200/hal/systick.h
deleted file mode 100644
index 3d1a33aaa..000000000
--- a/cc3200/hal/systick.h
+++ /dev/null
@@ -1,78 +0,0 @@
-//*****************************************************************************
-//
-//  systick.h
-//
-//  Prototypes for the SysTick driver.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __SYSTICK_H__
-#define __SYSTICK_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-extern void SysTickEnable(void);
-extern void SysTickDisable(void);
-extern void SysTickIntRegister(void (*pfnHandler)(void));
-extern void SysTickIntUnregister(void);
-extern void SysTickIntEnable(void);
-extern void SysTickIntDisable(void);
-extern void SysTickPeriodSet(unsigned long ulPeriod);
-extern unsigned long SysTickPeriodGet(void);
-extern unsigned long SysTickValueGet(void);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __SYSTICK_H__
diff --git a/cc3200/hal/timer.c b/cc3200/hal/timer.c
deleted file mode 100644
index eaa2ed143..000000000
--- a/cc3200/hal/timer.c
+++ /dev/null
@@ -1,1106 +0,0 @@
-//*****************************************************************************
-//
-//  timer.c
-//
-//  Driver for the timer module.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup GPT_General_Purpose_Timer_api
-//! @{
-//
-//*****************************************************************************
-
-#include "inc/hw_ints.h"
-#include "inc/hw_memmap.h"
-#include "inc/hw_timer.h"
-#include "inc/hw_types.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "timer.h"
-
-
-//*****************************************************************************
-//
-//! \internal
-//! Checks a timer base address.
-//!
-//! \param ulBase is the base address of the timer module.
-//!
-//! This function determines if a timer module base address is valid.
-//!
-//! \return Returns \b true if the base address is valid and \b false
-//! otherwise.
-//
-//*****************************************************************************
-#ifdef DEBUG
-static tBoolean
-TimerBaseValid(unsigned long ulBase)
-{
-    return((ulBase == TIMERA0_BASE) || (ulBase == TIMERA1_BASE) ||
-           (ulBase == TIMERA2_BASE) || (ulBase == TIMERA3_BASE));
-}
-#else
-#define TimerBaseValid(ulBase)      (ulBase)
-#endif
-
-//*****************************************************************************
-//
-//! Enables the timer(s).
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A,
-//! \b TIMER_B, or \b TIMER_BOTH.
-//!
-//! This function enables operation of the timer module.  The timer must be
-//! configured before it is enabled.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerEnable(unsigned long ulBase, unsigned long ulTimer)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
-           (ulTimer == TIMER_BOTH));
-
-    //
-    // Enable the timer(s) module.
-    //
-    HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN);
-}
-
-//*****************************************************************************
-//
-//! Disables the timer(s).
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s) to disable; must be one of
-//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
-//!
-//! This function disables operation of the timer module.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerDisable(unsigned long ulBase, unsigned long ulTimer)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
-           (ulTimer == TIMER_BOTH));
-
-    //
-    // Disable the timer module.
-    //
-    HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer &
-                                     (TIMER_CTL_TAEN | TIMER_CTL_TBEN));
-}
-
-//*****************************************************************************
-//
-//! Configures the timer(s).
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulConfig is the configuration for the timer.
-//!
-//! This function configures the operating mode of the timer(s).  The timer
-//! module is disabled before being configured, and is left in the disabled
-//! state. The 16/32-bit timer is comprised of two 16-bit timers that can
-//! operate independently or be concatenated to form a 32-bit timer.
-//!
-//! The configuration is specified in \e ulConfig as one of the following
-//! values:
-//!
-//! - \b TIMER_CFG_ONE_SHOT - Full-width one-shot timer
-//! - \b TIMER_CFG_ONE_SHOT_UP - Full-width one-shot timer that counts up
-//!   instead of down (not available on all parts)
-//! - \b TIMER_CFG_PERIODIC - Full-width periodic timer
-//! - \b TIMER_CFG_PERIODIC_UP - Full-width periodic timer that counts up
-//!   instead of down (not available on all parts)
-//! - \b TIMER_CFG_SPLIT_PAIR - Two half-width timers
-//!
-//! When configured for a pair of half-width timers, each timer is separately
-//! configured.  The first timer is configured by setting \e ulConfig to
-//! the result of a logical OR operation between one of the following values
-//! and \e ulConfig:
-//!
-//! - \b TIMER_CFG_A_ONE_SHOT - Half-width one-shot timer
-//! - \b TIMER_CFG_A_ONE_SHOT_UP - Half-width one-shot timer that counts up
-//!   instead of down (not available on all parts)
-//! - \b TIMER_CFG_A_PERIODIC - Half-width periodic timer
-//! - \b TIMER_CFG_A_PERIODIC_UP - Half-width periodic timer that counts up
-//!   instead of down (not available on all parts)
-//! - \b TIMER_CFG_A_CAP_COUNT - Half-width edge count capture
-//! - \b TIMER_CFG_A_CAP_TIME - Half-width edge time capture
-//! - \b TIMER_CFG_A_PWM - Half-width PWM output
-//!
-//! Similarly, the second timer is configured by setting \e ulConfig to
-//! the result of a logical OR operation between one of the corresponding
-//! \b TIMER_CFG_B_* values and \e ulConfig.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerConfigure(unsigned long ulBase, unsigned long ulConfig)
-{
-
-    ASSERT((ulConfig == TIMER_CFG_ONE_SHOT) ||
-           (ulConfig == TIMER_CFG_ONE_SHOT_UP) ||
-           (ulConfig == TIMER_CFG_PERIODIC) ||
-           (ulConfig == TIMER_CFG_PERIODIC_UP) ||
-           ((ulConfig & 0xff000000) == TIMER_CFG_SPLIT_PAIR));
-    ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_SPLIT_PAIR) ||
-           ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) ||
-             ((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) ||
-             ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) ||
-             ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) ||
-             ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) ||
-             ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) ||
-             ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) &&
-            (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) ||
-             ((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) ||
-             ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) ||
-             ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) ||
-             ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) ||
-             ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) ||
-             ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM))));
-
-    //
-    // Enable CCP to IO path
-    //
-    HWREG(0x440260B0) = 0xFF;
-
-    //
-    // Disable the timers.
-    //
-    HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN);
-
-    //
-    // Set the global timer configuration.
-    //
-    HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24;
-
-    //
-    // Set the configuration of the A and B timers.  Note that the B timer
-    // configuration is ignored by the hardware in 32-bit modes.
-    //
-    HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255;
-    HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255;
-}
-
-//*****************************************************************************
-//
-//! Controls the output level.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
-//! \b TIMER_B, or \b TIMER_BOTH.
-//! \param bInvert specifies the output level.
-//!
-//! This function sets the PWM output level for the specified timer.  If the
-//! \e bInvert parameter is \b true, then the timer's output is made active
-//! low; otherwise, it is made active high.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
-                  tBoolean bInvert)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
-           (ulTimer == TIMER_BOTH));
-
-    //
-    // Set the output levels as requested.
-    //
-    ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML;
-    HWREG(ulBase + TIMER_O_CTL) = (bInvert ?
-                                   (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
-                                   (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
-}
-
-//*****************************************************************************
-//
-//! Controls the event type.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s) to be adjusted; must be one of
-//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
-//! \param ulEvent specifies the type of event; must be one of
-//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or
-//! \b TIMER_EVENT_BOTH_EDGES.
-//!
-//! This function sets the signal edge(s) that triggers the timer when in
-//! capture mode.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
-                  unsigned long ulEvent)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
-           (ulTimer == TIMER_BOTH));
-
-    //
-    // Set the event type.
-    //
-    ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M);
-    HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) &
-                                    ~(TIMER_CTL_TAEVENT_M |
-                                      TIMER_CTL_TBEVENT_M)) | ulEvent);
-}
-
-//*****************************************************************************
-//
-//! Controls the stall handling.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s) to be adjusted; must be one of
-//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
-//! \param bStall specifies the response to a stall signal.
-//!
-//! This function controls the stall response for the specified timer.  If the
-//! \e bStall parameter is \b true, then the timer stops counting if the
-//! processor enters debug mode; otherwise the timer keeps running while in
-//! debug mode.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
-                  tBoolean  bStall)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
-           (ulTimer == TIMER_BOTH));
-
-    //
-    // Set the stall mode.
-    //
-    ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL;
-    HWREG(ulBase + TIMER_O_CTL) = (bStall ?
-                                   (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
-                                   (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
-}
-
-//*****************************************************************************
-//
-//! Set the timer prescale value.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
-//! \b TIMER_B, or \b TIMER_BOTH.
-//! \param ulValue is the timer prescale value which must be between 0 and 255
-//! (inclusive) for 16/32-bit timers.
-//!
-//! This function sets the value of the input clock prescaler.  The prescaler
-//! is only operational when in half-width mode and is used to extend the range
-//! of the half-width timer modes.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
-                 unsigned long ulValue)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
-           (ulTimer == TIMER_BOTH));
-    ASSERT(ulValue < 256);
-
-    //
-    // Set the timer A prescaler if requested.
-    //
-    if(ulTimer & TIMER_A)
-    {
-        HWREG(ulBase + TIMER_O_TAPR) = ulValue;
-    }
-
-    //
-    // Set the timer B prescaler if requested.
-    //
-    if(ulTimer & TIMER_B)
-    {
-        HWREG(ulBase + TIMER_O_TBPR) = ulValue;
-    }
-}
-
-
-//*****************************************************************************
-//
-//! Get the timer prescale value.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
-//! \b TIMER_B.
-//!
-//! This function gets the value of the input clock prescaler.  The prescaler
-//! is only operational when in half-width mode and is used to extend the range
-//! of the half-width timer modes.
-//!
-//! \return The value of the timer prescaler.
-//
-//*****************************************************************************
-
-unsigned long
-TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
-           (ulTimer == TIMER_BOTH));
-
-    //
-    // Return the appropriate prescale value.
-    //
-    return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) :
-           HWREG(ulBase + TIMER_O_TBPR));
-}
-
-//*****************************************************************************
-//
-//! Set the timer prescale match value.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
-//! \b TIMER_B, or \b TIMER_BOTH.
-//! \param ulValue is the timer prescale match value which must be between 0
-//! and 255 (inclusive) for 16/32-bit timers.
-//!
-//! This function sets the value of the input clock prescaler match value.
-//! When in a half-width mode that uses the counter match and the prescaler,
-//! the prescale match effectively extends the range of the match.
-//!
-//! \note The availability of the prescaler match varies with the
-//! part and timer mode in use.  Please consult the datasheet for the part you
-//! are using to determine whether this support is available.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
-                      unsigned long ulValue)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
-           (ulTimer == TIMER_BOTH));
-    ASSERT(ulValue < 256);
-
-    //
-    // Set the timer A prescale match if requested.
-    //
-    if(ulTimer & TIMER_A)
-    {
-        HWREG(ulBase + TIMER_O_TAPMR) = ulValue;
-    }
-
-    //
-    // Set the timer B prescale match if requested.
-    //
-    if(ulTimer & TIMER_B)
-    {
-        HWREG(ulBase + TIMER_O_TBPMR) = ulValue;
-    }
-}
-
-//*****************************************************************************
-//
-//! Get the timer prescale match value.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
-//! \b TIMER_B.
-//!
-//! This function gets the value of the input clock prescaler match value.
-//! When in a half-width mode that uses the counter match and prescaler, the
-//! prescale match effectively extends the range of the match.
-//!
-//! \note The availability of the prescaler match varies with the
-//! part and timer mode in use.  Please consult the datasheet for the part you
-//! are using to determine whether this support is available.
-//!
-//! \return The value of the timer prescale match.
-//
-//*****************************************************************************
-unsigned long
-TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
-           (ulTimer == TIMER_BOTH));
-
-    //
-    // Return the appropriate prescale match value.
-    //
-    return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPMR) :
-           HWREG(ulBase + TIMER_O_TBPMR));
-}
-
-//*****************************************************************************
-//
-//! Sets the timer load value.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
-//! \b TIMER_B, or \b TIMER_BOTH.  Only \b TIMER_A should be used when the
-//! timer is configured for full-width operation.
-//! \param ulValue is the load value.
-//!
-//! This function sets the timer load value; if the timer is running then the
-//! value is immediately loaded into the timer.
-//!
-//! \note This function can be used for both full- and half-width modes of
-//! 16/32-bit timers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
-             unsigned long ulValue)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
-           (ulTimer == TIMER_BOTH));
-
-    //
-    // Set the timer A load value if requested.
-    //
-    if(ulTimer & TIMER_A)
-    {
-        HWREG(ulBase + TIMER_O_TAILR) = ulValue;
-    }
-
-    //
-    // Set the timer B load value if requested.
-    //
-    if(ulTimer & TIMER_B)
-    {
-        HWREG(ulBase + TIMER_O_TBILR) = ulValue;
-    }
-}
-
-//*****************************************************************************
-//
-//! Gets the timer load value.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
-//! \b TIMER_B.  Only \b TIMER_A should be used when the timer is configured
-//! for full-width operation.
-//!
-//! This function gets the currently programmed interval load value for the
-//! specified timer.
-//!
-//! \note This function can be used for both full- and half-width modes of
-//! 16/32-bit timers.
-//!
-//! \return Returns the load value for the timer.
-//
-//*****************************************************************************
-unsigned long
-TimerLoadGet(unsigned long ulBase, unsigned long ulTimer)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
-
-    //
-    // Return the appropriate load value.
-    //
-    return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) :
-           HWREG(ulBase + TIMER_O_TBILR));
-}
-
-//*****************************************************************************
-//
-//! Gets the current timer value.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
-//! \b TIMER_B.  Only \b TIMER_A should be used when the timer is configured
-//! for 32-bit operation.
-//!
-//! This function reads the current value of the specified timer.
-//!
-//! \return Returns the current value of the timer.
-//
-//*****************************************************************************
-unsigned long
-TimerValueGet(unsigned long ulBase, unsigned long ulTimer)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
-
-    //
-    // Return the appropriate timer value.
-    //
-    return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAR) :
-           HWREG(ulBase + TIMER_O_TBR));
-}
-
-//*****************************************************************************
-//
-//! Sets the current timer value.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
-//! \b TIMER_B.  Only \b TIMER_A should be used when the timer is configured
-//! for 32-bit operation.
-//! \param ulValue is the new value of the timer to be set.
-//!
-//! This function sets the current value of the specified timer.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerValueSet(unsigned long ulBase, unsigned long ulTimer,
-              unsigned long ulValue)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
-
-    //
-    // Set the appropriate timer value.
-    //
-    if( (ulTimer == TIMER_A) )
-    {
-      HWREG(ulBase + TIMER_O_TAV) = ulValue;
-    }
-    else
-    {
-      HWREG(ulBase + TIMER_O_TBV) = ulValue;
-    }
-}
-
-
-//*****************************************************************************
-//
-//! Sets the timer match value.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
-//! \b TIMER_B, or \b TIMER_BOTH.  Only \b TIMER_A should be used when the
-//! timer is configured for 32-bit operation.
-//! \param ulValue is the match value.
-//!
-//! This function sets the match value for a timer.  This is used in capture
-//! count mode to determine when to interrupt the processor and in PWM mode to
-//! determine the duty cycle of the output signal.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
-              unsigned long ulValue)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
-           (ulTimer == TIMER_BOTH));
-
-    //
-    // Set the timer A match value if requested.
-    //
-    if(ulTimer & TIMER_A)
-    {
-        HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue;
-    }
-
-    //
-    // Set the timer B match value if requested.
-    //
-    if(ulTimer & TIMER_B)
-    {
-        HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue;
-    }
-}
-
-//*****************************************************************************
-//
-//! Gets the timer match value.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
-//! \b TIMER_B.  Only \b TIMER_A should be used when the timer is configured
-//! for 32-bit operation.
-//!
-//! This function gets the match value for the specified timer.
-//!
-//! \return Returns the match value for the timer.
-//
-//********************************************************************************
-unsigned long
-TimerMatchGet(unsigned long ulBase, unsigned long ulTimer)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
-
-    //
-    // Return the appropriate match value.
-    //
-    return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) :
-           HWREG(ulBase + TIMER_O_TBMATCHR));
-}
-
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for the timer interrupt.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,
-//! \b TIMER_B, or \b TIMER_BOTH.
-//! \param pfnHandler is a pointer to the function to be called when the timer
-//! interrupt occurs.
-//!
-//! This function sets the handler to be called when a timer interrupt occurs.
-//! In addition, this function enables the global interrupt in the interrupt
-//! controller; specific timer interrupts must be enabled via TimerIntEnable().
-//! It is the interrupt handler's responsibility to clear the interrupt source
-//! via TimerIntClear().
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
-                 void (*pfnHandler)(void))
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
-           (ulTimer == TIMER_BOTH));
-
-    ulBase = ((ulBase == TIMERA0_BASE) ? INT_TIMERA0A :
-              ((ulBase == TIMERA1_BASE) ? INT_TIMERA1A :
-               ((ulBase == TIMERA2_BASE) ? INT_TIMERA2A : INT_TIMERA3A)));
-
-    //
-    // Register an interrupt handler for timer A if requested.
-    //
-    if(ulTimer & TIMER_A)
-    {
-        //
-        // Register the interrupt handler.
-        //
-        IntRegister(ulBase, pfnHandler);
-
-        //
-        // Enable the interrupt.
-        //
-        IntEnable(ulBase);
-    }
-
-    //
-    // Register an interrupt handler for timer B if requested.
-    //
-    if(ulTimer & TIMER_B)
-    {
-        //
-        // Register the interrupt handler.
-        //
-        IntRegister(ulBase + 1, pfnHandler);
-
-        //
-        // Enable the interrupt.
-        //
-        IntEnable(ulBase + 1);
-    }
-}
-
-//*****************************************************************************
-//
-//! Unregisters an interrupt handler for the timer interrupt.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,
-//! \b TIMER_B, or \b TIMER_BOTH.
-//!
-//! This function clears the handler to be called when a timer interrupt
-//! occurs.  This function also masks off the interrupt in the interrupt
-//! controller so that the interrupt handler no longer is called.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
-           (ulTimer == TIMER_BOTH));
-
-    //
-    // Get the interrupt number for this timer module.
-    //
-
-    ulBase = ((ulBase == TIMERA0_BASE) ? INT_TIMERA0A :
-              ((ulBase == TIMERA1_BASE) ? INT_TIMERA1A :
-               ((ulBase == TIMERA2_BASE) ? INT_TIMERA2A : INT_TIMERA3A)));
-
-
-
-    //
-    // Unregister the interrupt handler for timer A if requested.
-    //
-    if(ulTimer & TIMER_A)
-    {
-        //
-        // Disable the interrupt.
-        //
-        IntDisable(ulBase);
-
-        //
-        // Unregister the interrupt handler.
-        //
-        IntUnregister(ulBase);
-    }
-
-    //
-    // Unregister the interrupt handler for timer B if requested.
-    //
-    if(ulTimer & TIMER_B)
-    {
-        //
-        // Disable the interrupt.
-        //
-        IntDisable(ulBase + 1);
-
-        //
-        // Unregister the interrupt handler.
-        //
-        IntUnregister(ulBase + 1);
-    }
-}
-
-//*****************************************************************************
-//
-//! Enables individual timer interrupt sources.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
-//!
-//! Enables the indicated timer interrupt sources.  Only the sources that are
-//! enabled can be reflected to the processor interrupt; disabled sources have
-//! no effect on the processor.
-//!
-//! The \e ulIntFlags parameter must be the logical OR of any combination of
-//! the following:
-//!
-//! - \b TIMER_CAPB_EVENT  - Capture B event interrupt
-//! - \b TIMER_CAPB_MATCH  - Capture B match interrupt
-//! - \b TIMER_TIMB_TIMEOUT  - Timer B timeout interrupt
-//! - \b TIMER_CAPA_EVENT  - Capture A event interrupt
-//! - \b TIMER_CAPA_MATCH  - Capture A match interrupt
-//! - \b TIMER_TIMA_TIMEOUT  - Timer A timeout interrupt
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-
-    //
-    // Enable the specified interrupts.
-    //
-    HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags;
-}
-
-//*****************************************************************************
-//
-//! Disables individual timer interrupt sources.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
-//!
-//! Disables the indicated timer interrupt sources.  Only the sources that are
-//! enabled can be reflected to the processor interrupt; disabled sources have
-//! no effect on the processor.
-//!
-//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
-//! parameter to TimerIntEnable().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-
-    //
-    // Disable the specified interrupts.
-    //
-    HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags);
-}
-
-//*****************************************************************************
-//
-//! Gets the current interrupt status.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param bMasked is false if the raw interrupt status is required and true if
-//! the masked interrupt status is required.
-//!
-//! This function returns the interrupt status for the timer module.  Either
-//! the raw interrupt status or the status of interrupts that are allowed to
-//! reflect to the processor can be returned.
-//!
-//! \return The current interrupt status, enumerated as a bit field of
-//! values described in TimerIntEnable().
-//
-//*****************************************************************************
-unsigned long
-TimerIntStatus(unsigned long ulBase, tBoolean bMasked)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-
-    //
-    // Return either the interrupt status or the raw interrupt status as
-    // requested.
-    //
-    return(bMasked ? HWREG(ulBase + TIMER_O_MIS) :
-           HWREG(ulBase + TIMER_O_RIS));
-}
-
-//*****************************************************************************
-//
-//! Clears timer interrupt sources.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
-//!
-//! The specified timer interrupt sources are cleared, so that they no longer
-//! assert.  This function must be called in the interrupt handler to keep the
-//! interrupt from being triggered again immediately upon exit.
-//!
-//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
-//! parameter to TimerIntEnable().
-//!
-//! \note Because there is a write buffer in the Cortex-M3 processor, it may
-//! take several clock cycles before the interrupt source is actually cleared.
-//! Therefore, it is recommended that the interrupt source be cleared early in
-//! the interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (because the interrupt controller still sees
-//! the interrupt source asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-
-    //
-    // Clear the requested interrupt sources.
-    //
-    HWREG(ulBase + TIMER_O_ICR) = ulIntFlags;
-}
-
-//*****************************************************************************
-//
-//! Enables the events that can trigger a DMA request.
-//!
-//! \param ulBase is the base address of the timer module.
-//! \param ulDMAEvent is a bit mask of the events that can trigger DMA.
-//!
-//! This function enables the timer events that can trigger the start of a DMA
-//! sequence.  The DMA trigger events are specified in the \e ui32DMAEvent
-//! parameter by passing in the logical OR of the following values:
-//!
-//! - \b TIMER_DMA_MODEMATCH_B - The mode match DMA trigger for timer B is
-//!   enabled.
-//! - \b TIMER_DMA_CAPEVENT_B - The capture event DMA trigger for timer B is
-//!   enabled.
-//! - \b TIMER_DMA_CAPMATCH_B - The capture match DMA trigger for timer B is
-//!   enabled.
-//! - \b TIMER_DMA_TIMEOUT_B - The timeout DMA trigger for timer B is enabled.
-//! - \b TIMER_DMA_MODEMATCH_A - The mode match DMA trigger for timer A is
-//!   enabled.
-//! - \b TIMER_DMA_CAPEVENT_A - The capture event DMA trigger for timer A is
-//!   enabled.
-//! - \b TIMER_DMA_CAPMATCH_A - The capture match DMA trigger for timer A is
-//!   enabled.
-//! - \b TIMER_DMA_TIMEOUT_A - The timeout DMA trigger for timer A is enabled.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-TimerDMAEventSet(unsigned long ulBase, unsigned long ulDMAEvent)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-
-    //
-    // Set the DMA triggers.
-    //
-    HWREG(ulBase + TIMER_O_DMAEV) = ulDMAEvent;
-}
-
-//*****************************************************************************
-//
-//! Returns the events that can trigger a DMA request.
-//!
-//! \param ulBase is the base address of the timer module.
-//!
-//! This function returns the timer events that can trigger the start of a DMA
-//! sequence.  The DMA trigger events are the logical OR of the following
-//! values:
-//!
-//! - \b TIMER_DMA_MODEMATCH_B - Enables the mode match DMA trigger for timer
-//!   B.
-//! - \b TIMER_DMA_CAPEVENT_B - Enables the capture event DMA trigger for
-//!   timer B.
-//! - \b TIMER_DMA_CAPMATCH_B - Enables the capture match DMA trigger for
-//!   timer B.
-//! - \b TIMER_DMA_TIMEOUT_B - Enables the timeout DMA trigger for timer B.
-//! - \b TIMER_DMA_MODEMATCH_A - Enables the mode match DMA trigger for timer
-//!   A.
-//! - \b TIMER_DMA_CAPEVENT_A - Enables the capture event DMA trigger for
-//!   timer A.
-//! - \b TIMER_DMA_CAPMATCH_A - Enables the capture match DMA trigger for
-//!   timer A.
-//! - \b TIMER_DMA_TIMEOUT_A - Enables the timeout DMA trigger for timer A.
-//!
-//! \return The timer events that trigger the uDMA.
-//
-//*****************************************************************************
-unsigned long
-TimerDMAEventGet(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(TimerBaseValid(ulBase));
-
-    //
-    // Return the current DMA triggers.
-    //
-    return(HWREG(ulBase + TIMER_O_DMAEV));
-}
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
diff --git a/cc3200/hal/timer.h b/cc3200/hal/timer.h
deleted file mode 100644
index cbe4d2cb1..000000000
--- a/cc3200/hal/timer.h
+++ /dev/null
@@ -1,210 +0,0 @@
-//*****************************************************************************
-//
-//  timer.h
-//
-//  Prototypes for the timer module
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __TIMER_H__
-#define __TIMER_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Values that can be passed to TimerConfigure as the ulConfig parameter.
-//
-//*****************************************************************************
-
-#define TIMER_CFG_ONE_SHOT       0x00000021  // Full-width one-shot timer
-#define TIMER_CFG_ONE_SHOT_UP    0x00000031  // Full-width one-shot up-count
-                                             // timer
-#define TIMER_CFG_PERIODIC       0x00000022  // Full-width periodic timer
-#define TIMER_CFG_PERIODIC_UP    0x00000032  // Full-width periodic up-count
-                                             // timer
-#define TIMER_CFG_SPLIT_PAIR     0x04000000  // Two half-width timers
-
-#define TIMER_CFG_A_ONE_SHOT     0x00000021  // Timer A one-shot timer
-#define TIMER_CFG_A_ONE_SHOT_UP  0x00000031  // Timer A one-shot up-count timer
-#define TIMER_CFG_A_PERIODIC     0x00000022  // Timer A periodic timer
-#define TIMER_CFG_A_PERIODIC_UP  0x00000032  // Timer A periodic up-count timer
-#define TIMER_CFG_A_CAP_COUNT    0x00000003  // Timer A event counter
-#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013  // Timer A event up-counter
-#define TIMER_CFG_A_CAP_TIME     0x00000007  // Timer A event timer
-#define TIMER_CFG_A_CAP_TIME_UP  0x00000017  // Timer A event up-count timer
-#define TIMER_CFG_A_PWM          0x0000000A  // Timer A PWM output
-#define TIMER_CFG_B_ONE_SHOT     0x00002100  // Timer B one-shot timer
-#define TIMER_CFG_B_ONE_SHOT_UP  0x00003100  // Timer B one-shot up-count timer
-#define TIMER_CFG_B_PERIODIC     0x00002200  // Timer B periodic timer
-#define TIMER_CFG_B_PERIODIC_UP  0x00003200  // Timer B periodic up-count timer
-#define TIMER_CFG_B_CAP_COUNT    0x00000300  // Timer B event counter
-#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300  // Timer B event up-counter
-#define TIMER_CFG_B_CAP_TIME     0x00000700  // Timer B event timer
-#define TIMER_CFG_B_CAP_TIME_UP  0x00001700  // Timer B event up-count timer
-#define TIMER_CFG_B_PWM          0x00000A00  // Timer B PWM output
-
-//*****************************************************************************
-//
-// Values that can be passed to TimerIntEnable, TimerIntDisable, and
-// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
-//
-//*****************************************************************************
-
-#define TIMER_TIMB_DMA          0x00002000  // TimerB DMA Done interrupt
-#define TIMER_TIMB_MATCH        0x00000800  // TimerB match interrupt
-#define TIMER_CAPB_EVENT        0x00000400  // CaptureB event interrupt
-#define TIMER_CAPB_MATCH        0x00000200  // CaptureB match interrupt
-#define TIMER_TIMB_TIMEOUT      0x00000100  // TimerB time out interrupt
-#define TIMER_TIMA_DMA          0x00000020  // TimerA DMA Done interrupt
-#define TIMER_TIMA_MATCH        0x00000010  // TimerA match interrupt
-#define TIMER_CAPA_EVENT        0x00000004  // CaptureA event interrupt
-#define TIMER_CAPA_MATCH        0x00000002  // CaptureA match interrupt
-#define TIMER_TIMA_TIMEOUT      0x00000001  // TimerA time out interrupt
-
-//*****************************************************************************
-//
-// Values that can be passed to TimerControlEvent as the ulEvent parameter.
-//
-//*****************************************************************************
-#define TIMER_EVENT_POS_EDGE    0x00000000  // Count positive edges
-#define TIMER_EVENT_NEG_EDGE    0x00000404  // Count negative edges
-#define TIMER_EVENT_BOTH_EDGES  0x00000C0C  // Count both edges
-
-//*****************************************************************************
-//
-// Values that can be passed to most of the timer APIs as the ulTimer
-// parameter.
-//
-//*****************************************************************************
-#define TIMER_A                 0x000000ff  // Timer A
-#define TIMER_B                 0x0000ff00  // Timer B
-#define TIMER_BOTH              0x0000ffff  // Timer Both
-
-
-//*****************************************************************************
-//
-// Values that can be passed to TimerSynchronize as the ulTimers parameter.
-//
-//*****************************************************************************
-#define TIMER_0A_SYNC           0x00000001  // Synchronize Timer 0A
-#define TIMER_0B_SYNC           0x00000002  // Synchronize Timer 0B
-#define TIMER_1A_SYNC           0x00000004  // Synchronize Timer 1A
-#define TIMER_1B_SYNC           0x00000008  // Synchronize Timer 1B
-#define TIMER_2A_SYNC           0x00000010  // Synchronize Timer 2A
-#define TIMER_2B_SYNC           0x00000020  // Synchronize Timer 2B
-#define TIMER_3A_SYNC           0x00000040  // Synchronize Timer 3A
-#define TIMER_3B_SYNC           0x00000080  // Synchronize Timer 3B
-
-//*****************************************************************************
-//
-// Values that can be passed to TimerDMAEventSet() or returned from
-// TimerDMAEventGet().
-//
-//*****************************************************************************
-#define TIMER_DMA_MODEMATCH_B   0x00000800
-#define TIMER_DMA_CAPEVENT_B    0x00000400
-#define TIMER_DMA_CAPMATCH_B    0x00000200
-#define TIMER_DMA_TIMEOUT_B     0x00000100
-#define TIMER_DMA_MODEMATCH_A   0x00000010
-#define TIMER_DMA_CAPEVENT_A    0x00000004
-#define TIMER_DMA_CAPMATCH_A    0x00000002
-#define TIMER_DMA_TIMEOUT_A     0x00000001
-
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
-extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
-extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
-extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
-                              tBoolean bInvert);
-extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
-                              unsigned long ulEvent);
-extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
-                              tBoolean bStall);
-extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
-                             unsigned long ulValue);
-extern unsigned long TimerPrescaleGet(unsigned long ulBase,
-                                      unsigned long ulTimer);
-extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
-                                  unsigned long ulValue);
-extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
-                                           unsigned long ulTimer);
-extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
-                         unsigned long ulValue);
-extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
-
-extern unsigned long TimerValueGet(unsigned long ulBase,
-                                   unsigned long ulTimer);
-extern void TimerValueSet(unsigned long ulBase, unsigned long ulTimer,
-              unsigned long ulValue);
-
-extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
-                          unsigned long ulValue);
-extern unsigned long TimerMatchGet(unsigned long ulBase,
-                                   unsigned long ulTimer);
-extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
-                             void (*pfnHandler)(void));
-extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
-extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
-extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
-extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
-extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
-extern void TimerDMAEventSet(unsigned long ulBase, unsigned long ulDMAEvent);
-extern unsigned long TimerDMAEventGet(unsigned long ulBase);
-
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __TIMER_H__
diff --git a/cc3200/hal/uart.c b/cc3200/hal/uart.c
deleted file mode 100644
index 33d91414b..000000000
--- a/cc3200/hal/uart.c
+++ /dev/null
@@ -1,1508 +0,0 @@
-//*****************************************************************************
-//
-//  uart.c
-//
-//  Driver for the UART.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup UART_api
-//! @{
-//
-//*****************************************************************************
-
-#include "inc/hw_ints.h"
-#include "inc/hw_memmap.h"
-#include "inc/hw_types.h"
-#include "inc/hw_uart.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "uart.h"
-
-
-//*****************************************************************************
-//
-// A mapping of UART base address to interupt number.
-//
-//*****************************************************************************
-static const unsigned long g_ppulUARTIntMap[][2] =
-{
-    { UARTA0_BASE, INT_UARTA0 },
-    { UARTA1_BASE, INT_UARTA1 },
-};
-
-//*****************************************************************************
-//
-//! \internal
-//! Checks a UART base address.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function determines if a UART port base address is valid.
-//!
-//! \return Returns \b true if the base address is valid and \b false
-//! otherwise.
-//
-//*****************************************************************************
-#ifdef DEBUG
-static tBoolean
-UARTBaseValid(unsigned long ulBase)
-{
-    return((ulBase == UARTA0_BASE) || (ulBase == UARTA1_BASE));
-}
-#else
-#define UARTBaseValid(ulBase)       (ulBase)
-#endif
-
-//*****************************************************************************
-//
-//! \internal
-//! Gets the UART interrupt number.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! Given a UART base address, returns the corresponding interrupt number.
-//!
-//! \return Returns a UART interrupt number, or -1 if \e ulBase is invalid.
-//
-//*****************************************************************************
-static long
-UARTIntNumberGet(unsigned long ulBase)
-{
-    unsigned long ulIdx;
-
-    //
-    // Loop through the table that maps UART base addresses to interrupt
-    // numbers.
-    //
-    for(ulIdx = 0; ulIdx < (sizeof(g_ppulUARTIntMap) /
-                            sizeof(g_ppulUARTIntMap[0])); ulIdx++)
-    {
-        //
-        // See if this base address matches.
-        //
-        if(g_ppulUARTIntMap[ulIdx][0] == ulBase)
-        {
-            //
-            // Return the corresponding interrupt number.
-            //
-            return(g_ppulUARTIntMap[ulIdx][1]);
-        }
-    }
-
-    //
-    // The base address could not be found, so return an error.
-    //
-    return(-1);
-}
-
-//*****************************************************************************
-//
-//! Sets the type of parity.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulParity specifies the type of parity to use.
-//!
-//! This function sets the type of parity to use for transmitting and expect
-//! when receiving.  The \e ulParity parameter must be one of
-//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
-//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.  The last two allow
-//! direct control of the parity bit; it is always either one or zero based on
-//! the mode.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTParityModeSet(unsigned long ulBase, unsigned long ulParity)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-    ASSERT((ulParity == UART_CONFIG_PAR_NONE) ||
-           (ulParity == UART_CONFIG_PAR_EVEN) ||
-           (ulParity == UART_CONFIG_PAR_ODD) ||
-           (ulParity == UART_CONFIG_PAR_ONE) ||
-           (ulParity == UART_CONFIG_PAR_ZERO));
-
-    //
-    // Set the parity mode.
-    //
-    HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) &
-                                    ~(UART_LCRH_SPS | UART_LCRH_EPS |
-                                      UART_LCRH_PEN)) | ulParity);
-}
-
-//*****************************************************************************
-//
-//! Gets the type of parity currently being used.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function gets the type of parity used for transmitting data and
-//! expected when receiving data.
-//!
-//! \return Returns the current parity settings, specified as one of
-//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
-//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.
-//
-//*****************************************************************************
-unsigned long
-UARTParityModeGet(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Return the current parity setting.
-    //
-    return(HWREG(ulBase + UART_O_LCRH) &
-           (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN));
-}
-
-//*****************************************************************************
-//
-//! Sets the FIFO level at which interrupts are generated.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulTxLevel is the transmit FIFO interrupt level, specified as one of
-//! \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8,
-//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
-//! \param ulRxLevel is the receive FIFO interrupt level, specified as one of
-//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8,
-//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
-//!
-//! This function sets the FIFO level at which transmit and receive interrupts
-//! are generated.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
-                 unsigned long ulRxLevel)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-    ASSERT((ulTxLevel == UART_FIFO_TX1_8) ||
-           (ulTxLevel == UART_FIFO_TX2_8) ||
-           (ulTxLevel == UART_FIFO_TX4_8) ||
-           (ulTxLevel == UART_FIFO_TX6_8) ||
-           (ulTxLevel == UART_FIFO_TX7_8));
-    ASSERT((ulRxLevel == UART_FIFO_RX1_8) ||
-           (ulRxLevel == UART_FIFO_RX2_8) ||
-           (ulRxLevel == UART_FIFO_RX4_8) ||
-           (ulRxLevel == UART_FIFO_RX6_8) ||
-           (ulRxLevel == UART_FIFO_RX7_8));
-
-    //
-    // Set the FIFO interrupt levels.
-    //
-    HWREG(ulBase + UART_O_IFLS) = ulTxLevel | ulRxLevel;
-}
-
-//*****************************************************************************
-//
-//! Gets the FIFO level at which interrupts are generated.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param pulTxLevel is a pointer to storage for the transmit FIFO level,
-//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8,
-//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
-//! \param pulRxLevel is a pointer to storage for the receive FIFO level,
-//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8,
-//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
-//!
-//! This function gets the FIFO level at which transmit and receive interrupts
-//! are generated.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
-                 unsigned long *pulRxLevel)
-{
-    unsigned long ulTemp;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Read the FIFO level register.
-    //
-    ulTemp = HWREG(ulBase + UART_O_IFLS);
-
-    //
-    // Extract the transmit and receive FIFO levels.
-    //
-    *pulTxLevel = ulTemp & UART_IFLS_TX_M;
-    *pulRxLevel = ulTemp & UART_IFLS_RX_M;
-}
-
-//*****************************************************************************
-//
-//! Sets the configuration of a UART.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulUARTClk is the rate of the clock supplied to the UART module.
-//! \param ulBaud is the desired baud rate.
-//! \param ulConfig is the data format for the port (number of data bits,
-//! number of stop bits, and parity).
-//!
-//! This function configures the UART for operation in the specified data
-//! format.  The baud rate is provided in the \e ulBaud parameter and the data
-//! format in the \e ulConfig parameter.
-//!
-//! The \e ulConfig parameter is the logical OR of three values: the number of
-//! data bits, the number of stop bits, and the parity.  \b UART_CONFIG_WLEN_8,
-//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5
-//! select from eight to five data bits per byte (respectively).
-//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop
-//! bits (respectively).  \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN,
-//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO
-//! select the parity mode (no parity bit, even parity bit, odd parity bit,
-//! parity bit always one, and parity bit always zero, respectively).
-//!
-//! The peripheral clock is the same as the processor clock.  The frequency of
-//! the system clock is the value returned by SysCtlClockGet(), or it can be
-//! explicitly hard coded if it is constant and known (to save the
-//! code/execution overhead of a call to SysCtlClockGet()).
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
-                    unsigned long ulBaud, unsigned long ulConfig)
-{
-    unsigned long ulDiv;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-    ASSERT(ulBaud != 0);
-
-    //
-    // Stop the UART.
-    //
-    UARTDisable(ulBase);
-
-    //
-    // Is the required baud rate greater than the maximum rate supported
-    // without the use of high speed mode?
-    //
-    if((ulBaud * 16) > ulUARTClk)
-    {
-        //
-        // Enable high speed mode.
-        //
-        HWREG(ulBase + UART_O_CTL) |= UART_CTL_HSE;
-
-        //
-        // Half the supplied baud rate to compensate for enabling high speed
-        // mode.  This allows the following code to be common to both cases.
-        //
-        ulBaud /= 2;
-    }
-    else
-    {
-        //
-        // Disable high speed mode.
-        //
-        HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_HSE);
-    }
-
-    //
-    // Compute the fractional baud rate divider.
-    //
-    ulDiv = (((ulUARTClk * 8) / ulBaud) + 1) / 2;
-
-    //
-    // Set the baud rate.
-    //
-    HWREG(ulBase + UART_O_IBRD) = ulDiv / 64;
-    HWREG(ulBase + UART_O_FBRD) = ulDiv % 64;
-
-    //
-    // Set parity, data length, and number of stop bits.
-    //
-    HWREG(ulBase + UART_O_LCRH) = ulConfig;
-
-    //
-    // Clear the flags register.
-    //
-    HWREG(ulBase + UART_O_FR) = 0;
-
-    //
-    // Start the UART.
-    //
-    UARTEnable(ulBase);
-}
-
-//*****************************************************************************
-//
-//! Gets the current configuration of a UART.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulUARTClk is the rate of the clock supplied to the UART module.
-//! \param pulBaud is a pointer to storage for the baud rate.
-//! \param pulConfig is a pointer to storage for the data format.
-//!
-//! The baud rate and data format for the UART is determined, given an
-//! explicitly provided peripheral clock (hence the ExpClk suffix).  The
-//! returned baud rate is the actual baud rate; it may not be the exact baud
-//! rate requested or an ``official'' baud rate.  The data format returned in
-//! \e pulConfig is enumerated the same as the \e ulConfig parameter of
-//! UARTConfigSetExpClk().
-//!
-//! The peripheral clock is the same as the processor clock.  The frequency of
-//! the system clock is the value returned by SysCtlClockGet(), or it can be
-//! explicitly hard coded if it is constant and known (to save the
-//! code/execution overhead of a call to SysCtlClockGet()).
-//!
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
-                    unsigned long *pulBaud, unsigned long *pulConfig)
-{
-    unsigned long ulInt, ulFrac;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Compute the baud rate.
-    //
-    ulInt = HWREG(ulBase + UART_O_IBRD);
-    ulFrac = HWREG(ulBase + UART_O_FBRD);
-    *pulBaud = (ulUARTClk * 4) / ((64 * ulInt) + ulFrac);
-
-    //
-    // See if high speed mode enabled.
-    //
-    if(HWREG(ulBase + UART_O_CTL) & UART_CTL_HSE)
-    {
-        //
-        // High speed mode is enabled so the actual baud rate is actually
-        // double what was just calculated.
-        //
-        *pulBaud *= 2;
-    }
-
-    //
-    // Get the parity, data length, and number of stop bits.
-    //
-    *pulConfig = (HWREG(ulBase + UART_O_LCRH) &
-                  (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 |
-                   UART_LCRH_EPS | UART_LCRH_PEN));
-}
-
-//*****************************************************************************
-//
-//! Enables transmitting and receiving.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function sets the UARTEN, TXE, and RXE bits, and enables the transmit
-//! and receive FIFOs.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTEnable(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Enable the FIFO.
-    //
-    HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN;
-
-    //
-    // Enable RX, TX, and the UART.
-    //
-    HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE |
-                                   UART_CTL_RXE);
-}
-
-//*****************************************************************************
-//
-//! Disables transmitting and receiving.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function clears the UARTEN, TXE, and RXE bits, waits for the end of
-//! transmission of the current character, and flushes the transmit FIFO.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTDisable(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Wait for end of TX.
-    //
-    while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY)
-    {
-    }
-
-    //
-    // Disable the FIFO.
-    //
-    HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN);
-
-    //
-    // Disable the UART.
-    //
-    HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE |
-                                    UART_CTL_RXE);
-}
-
-//*****************************************************************************
-//
-//! Enables the transmit and receive FIFOs.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This functions enables the transmit and receive FIFOs in the UART.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTFIFOEnable(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Enable the FIFO.
-    //
-    HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN;
-}
-
-//*****************************************************************************
-//
-//! Disables the transmit and receive FIFOs.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This functions disables the transmit and receive FIFOs in the UART.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTFIFODisable(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Disable the FIFO.
-    //
-    HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN);
-}
-
-//*****************************************************************************
-//
-//! Sets the states of the RTS modem control signals.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulControl is a bit-mapped flag indicating which modem control bits
-//! should be set.
-//!
-//! This function sets the states of the RTS modem handshake outputs
-//! from the UART.
-//!
-//! The \e ulControl parameter is the logical OR of any of the following:
-//!
-//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
-//!
-//! \note The availability of hardware modem handshake signals varies with the
-//!  part and UART in use.  Please consult the datasheet for the part
-//! you are using to determine whether this support is available.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTModemControlSet(unsigned long ulBase, unsigned long ulControl)
-{
-    unsigned long ulTemp;
-
-    //
-    // Check the arguments.
-    //
-
-    ASSERT(ulBase == UARTA1_BASE);
-    ASSERT((ulControl & ~(UART_OUTPUT_RTS)) == 0);
-
-    //
-    // Set the appropriate modem control output bits.
-    //
-    ulTemp = HWREG(ulBase + UART_O_CTL);
-    ulTemp |= (ulControl & (UART_OUTPUT_RTS));
-    HWREG(ulBase + UART_O_CTL) = ulTemp;
-}
-
-//*****************************************************************************
-//
-//! Clears the states of the RTS modem control signals.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulControl is a bit-mapped flag indicating which modem control bits
-//! should be set.
-//!
-//! This function clears the states of the RTS modem handshake outputs
-//! from the UART.
-//!
-//! The \e ulControl parameter is the logical OR of any of the following:
-//!
-//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
-//!
-//! \note The availability of hardware modem handshake signals varies with the
-//!  part and UART in use.  Please consult the datasheet for the part
-//! you are using to determine whether this support is available.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTModemControlClear(unsigned long ulBase, unsigned long ulControl)
-{
-    unsigned long ulTemp;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(ulBase == UARTA1_BASE);
-    ASSERT((ulControl & ~(UART_OUTPUT_RTS)) == 0);
-
-    //
-    // Set the appropriate modem control output bits.
-    //
-    ulTemp = HWREG(ulBase + UART_O_CTL);
-    ulTemp &= ~(ulControl & (UART_OUTPUT_RTS));
-    HWREG(ulBase + UART_O_CTL) = ulTemp;
-}
-
-//*****************************************************************************
-//
-//! Gets the states of the RTS modem control signals.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function returns the current states of each of the UART modem
-//! control signal, RTS.
-//!
-//! \note The availability of hardware modem handshake signals varies with the
-//!  part and UART in use.  Please consult the datasheet for the part
-//! you are using to determine whether this support is available.
-//!
-//! \return Returns the states of the handshake output signal.
-//
-//*****************************************************************************
-unsigned long
-UARTModemControlGet(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(ulBase == UARTA1_BASE);
-
-    return(HWREG(ulBase + UART_O_CTL) & (UART_OUTPUT_RTS));
-}
-
-//*****************************************************************************
-//
-//! Gets the states of the CTS modem status signal.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function returns the current states of the UART modem status signal,
-//! CTS.
-//!
-//! \note The availability of hardware modem handshake signals varies with the
-//!  part and UART in use.  Please consult the datasheet for the part
-//! you are using to determine whether this support is available.
-//!
-//! \return Returns the states of the handshake output signal
-//
-//*****************************************************************************
-unsigned long
-UARTModemStatusGet(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-
-    ASSERT(ulBase == UARTA1_BASE);
-
-    return(HWREG(ulBase + UART_O_FR) & (UART_INPUT_CTS));
-}
-
-//*****************************************************************************
-//
-//! Sets the UART hardware flow control mode to be used.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulMode indicates the flow control modes to be used.  This parameter
-//! is a logical OR combination of values \b UART_FLOWCONTROL_TX and
-//! \b UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS)
-//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control.
-//!
-//! This function sets the required hardware flow control modes.  If \e ulMode
-//! contains flag \b UART_FLOWCONTROL_TX, data is only transmitted if the
-//! incoming CTS signal is asserted. If \e ulMode contains flag
-//! \b UART_FLOWCONTROL_RX, the RTS output is controlled by the hardware and is
-//! asserted only when there is space available in the receive FIFO.  If no
-//! hardware flow control is required, \b UART_FLOWCONTROL_NONE should be
-//! passed.
-//!
-//! \note The availability of hardware flow control varies with the
-//! part and UART in use.  Please consult the datasheet for the part you are
-//! using to determine whether this support is available.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode)
-{
-    //
-    // Check the arguments.
-    //
-
-    ASSERT(UARTBaseValid(ulBase));
-    ASSERT((ulMode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0);
-
-    //
-    // Set the flow control mode as requested.
-    //
-    HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) &
-                                 ~(UART_FLOWCONTROL_TX |
-                                   UART_FLOWCONTROL_RX)) | ulMode);
-}
-
-//*****************************************************************************
-//
-//! Returns the UART hardware flow control mode currently in use.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function returns the current hardware flow control mode.
-//!
-//! \note The availability of hardware flow control varies with the
-//! part and UART in use.  Please consult the datasheet for the part you are
-//! using to determine whether this support is available.
-//!
-//! \return Returns the current flow control mode in use.  This is a
-//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit
-//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS)
-//! flow control is in use.  If hardware flow control is disabled,
-//! \b UART_FLOWCONTROL_NONE is returned.
-//
-//*****************************************************************************
-unsigned long
-UARTFlowControlGet(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-
-    ASSERT(UARTBaseValid(ulBase));
-
-    return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX |
-                                         UART_FLOWCONTROL_RX));
-}
-
-//*****************************************************************************
-//
-//! Sets the operating mode for the UART transmit interrupt.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulMode is the operating mode for the transmit interrupt.  It may be
-//! \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is idle
-//! or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit FIFO
-//! level.
-//!
-//! This function allows the mode of the UART transmit interrupt to be set.  By
-//! default, the transmit interrupt is asserted when the FIFO level falls past
-//! a threshold set via a call to UARTFIFOLevelSet().  Alternatively, if this
-//! function is called with \e ulMode set to \b UART_TXINT_MODE_EOT, the
-//! transmit interrupt is asserted once the transmitter is completely idle -
-//! the transmit FIFO is empty and all bits, including any stop bits, have
-//! cleared the transmitter.
-//!
-//! \note The availability of end-of-transmission mode varies with the
-//!  part in use.  Please consult the datasheet for the part you are
-//! using to determine whether this support is available.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-    ASSERT((ulMode == UART_TXINT_MODE_EOT) ||
-           (ulMode == UART_TXINT_MODE_FIFO));
-
-    //
-    // Set or clear the EOT bit of the UART control register as appropriate.
-    //
-    HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) &
-                                 ~(UART_TXINT_MODE_EOT |
-                                   UART_TXINT_MODE_FIFO)) | ulMode);
-}
-
-//*****************************************************************************
-//
-//! Returns the current operating mode for the UART transmit interrupt.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function returns the current operating mode for the UART transmit
-//! interrupt.  The return value is \b UART_TXINT_MODE_EOT if the transmit
-//! interrupt is currently set to be asserted once the transmitter is
-//! completely idle - the transmit FIFO is empty and all bits, including any
-//! stop bits, have cleared the transmitter.  The return value is
-//! \b UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon
-//! the level of the transmit FIFO.
-//!
-//! \note The availability of end-of-transmission mode varies with the
-//!  part in use.  Please consult the datasheet for the part you are
-//! using to determine whether this support is available.
-//!
-//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT.
-//
-//*****************************************************************************
-unsigned long
-UARTTxIntModeGet(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Return the current transmit interrupt mode.
-    //
-    return(HWREG(ulBase + UART_O_CTL) & (UART_TXINT_MODE_EOT |
-                                         UART_TXINT_MODE_FIFO));
-}
-
-//*****************************************************************************
-//
-//! Determines if there are any characters in the receive FIFO.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function returns a flag indicating whether or not there is data
-//! available in the receive FIFO.
-//!
-//! \return Returns \b true if there is data in the receive FIFO or \b false
-//! if there is no data in the receive FIFO.
-//
-//*****************************************************************************
-tBoolean
-UARTCharsAvail(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Return the availability of characters.
-    //
-    return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true);
-}
-
-//*****************************************************************************
-//
-//! Determines if there is any space in the transmit FIFO.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function returns a flag indicating whether or not there is space
-//! available in the transmit FIFO.
-//!
-//! \return Returns \b true if there is space available in the transmit FIFO
-//! or \b false if there is no space available in the transmit FIFO.
-//
-//*****************************************************************************
-tBoolean
-UARTSpaceAvail(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Return the availability of space.
-    //
-    return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true);
-}
-
-//*****************************************************************************
-//
-//! Receives a character from the specified port.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function gets a character from the receive FIFO for the specified
-//! port.
-//!
-//!
-//! \return Returns the character read from the specified port, cast as a
-//! \e long.  A \b -1 is returned if there are no characters present in the
-//! receive FIFO.  The UARTCharsAvail() function should be called before
-//! attempting to call this function.
-//
-//*****************************************************************************
-long
-UARTCharGetNonBlocking(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // See if there are any characters in the receive FIFO.
-    //
-    if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE))
-    {
-        //
-        // Read and return the next character.
-        //
-        return(HWREG(ulBase + UART_O_DR));
-    }
-    else
-    {
-        //
-        // There are no characters, so return a failure.
-        //
-        return(-1);
-    }
-}
-
-//*****************************************************************************
-//
-//! Waits for a character from the specified port.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function gets a character from the receive FIFO for the specified
-//! port.  If there are no characters available, this function waits until a
-//! character is received before returning.
-//!
-//! \return Returns the character read from the specified port, cast as a
-//! \e long.
-//
-//*****************************************************************************
-long
-UARTCharGet(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Wait until a char is available.
-    //
-    while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)
-    {
-    }
-
-    //
-    // Now get the char.
-    //
-    return(HWREG(ulBase + UART_O_DR));
-}
-
-//*****************************************************************************
-//
-//! Sends a character to the specified port.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ucData is the character to be transmitted.
-//!
-//! This function writes the character \e ucData to the transmit FIFO for the
-//! specified port.  This function does not block, so if there is no space
-//! available, then a \b false is returned, and the application must retry the
-//! function later.
-//!
-//! \return Returns \b true if the character was successfully placed in the
-//! transmit FIFO or \b false if there was no space available in the transmit
-//! FIFO.
-//
-//*****************************************************************************
-tBoolean
-UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // See if there is space in the transmit FIFO.
-    //
-    if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF))
-    {
-        //
-        // Write this character to the transmit FIFO.
-        //
-        HWREG(ulBase + UART_O_DR) = ucData;
-
-        //
-        // Success.
-        //
-        return(true);
-    }
-    else
-    {
-        //
-        // There is no space in the transmit FIFO, so return a failure.
-        //
-        return(false);
-    }
-}
-
-//*****************************************************************************
-//
-//! Waits to send a character from the specified port.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ucData is the character to be transmitted.
-//!
-//! This function sends the character \e ucData to the transmit FIFO for the
-//! specified port.  If there is no space available in the transmit FIFO, this
-//! function waits until there is space available before returning.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTCharPut(unsigned long ulBase, unsigned char ucData)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Wait until space is available.
-    //
-    while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)
-    {
-    }
-
-    //
-    // Send the char.
-    //
-    HWREG(ulBase + UART_O_DR) = ucData;
-}
-
-//*****************************************************************************
-//
-//! Causes a BREAK to be sent.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param bBreakState controls the output level.
-//!
-//! Calling this function with \e bBreakState set to \b true asserts a break
-//! condition on the UART.  Calling this function with \e bBreakState set to
-//! \b false removes the break condition.  For proper transmission of a break
-//! command, the break must be asserted for at least two complete frames.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Set the break condition as requested.
-    //
-    HWREG(ulBase + UART_O_LCRH) =
-        (bBreakState ?
-         (HWREG(ulBase + UART_O_LCRH) | UART_LCRH_BRK) :
-         (HWREG(ulBase + UART_O_LCRH) & ~(UART_LCRH_BRK)));
-}
-
-//*****************************************************************************
-//
-//! Determines whether the UART transmitter is busy or not.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! Allows the caller to determine whether all transmitted bytes have cleared
-//! the transmitter hardware.  If \b false is returned, the transmit FIFO is
-//! empty and all bits of the last transmitted character, including all stop
-//! bits, have left the hardware shift register.
-//!
-//! \return Returns \b true if the UART is transmitting or \b false if all
-//! transmissions are complete.
-//
-//*****************************************************************************
-tBoolean
-UARTBusy(unsigned long ulBase)
-{
-    //
-    // Check the argument.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Determine if the UART is busy.
-    //
-    return((HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) ? true : false);
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for a UART interrupt.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param pfnHandler is a pointer to the function to be called when the
-//! UART interrupt occurs.
-//!
-//! This function does the actual registering of the interrupt handler.  This
-//! function enables the global interrupt in the interrupt controller; specific
-//! UART interrupts must be enabled via UARTIntEnable().  It is the interrupt
-//! handler's responsibility to clear the interrupt source.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
-{
-    unsigned long ulInt;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Determine the interrupt number based on the UART port.
-    //
-
-    ulInt = UARTIntNumberGet(ulBase);
-
-    //
-    // Register the interrupt handler.
-    //
-    IntRegister(ulInt, pfnHandler);
-
-    //
-    // Enable the UART interrupt.
-    //
-    IntEnable(ulInt);
-}
-
-//*****************************************************************************
-//
-//! Unregisters an interrupt handler for a UART interrupt.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function does the actual unregistering of the interrupt handler.  It
-//! clears the handler to be called when a UART interrupt occurs.  This
-//! function also masks off the interrupt in the interrupt controller so that
-//! the interrupt handler no longer is called.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTIntUnregister(unsigned long ulBase)
-{
-    unsigned long ulInt;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Determine the interrupt number based on the UART port.
-    //
-    ulInt = UARTIntNumberGet(ulBase);
-
-    //
-    // Disable the interrupt.
-    //
-    IntDisable(ulInt);
-
-    //
-    // Unregister the interrupt handler.
-    //
-    IntUnregister(ulInt);
-}
-
-//*****************************************************************************
-//
-//! Enables individual UART interrupt sources.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
-//!
-//! This function enables the indicated UART interrupt sources.  Only the
-//! sources that are enabled can be reflected to the processor interrupt;
-//! disabled sources have no effect on the processor.
-//!
-//! The \e ulIntFlags parameter is the logical OR of any of the following:
-//!
-//! - \b UART_INT_OE - Overrun Error interrupt
-//! - \b UART_INT_BE - Break Error interrupt
-//! - \b UART_INT_PE - Parity Error interrupt
-//! - \b UART_INT_FE - Framing Error interrupt
-//! - \b UART_INT_RT - Receive Timeout interrupt
-//! - \b UART_INT_TX - Transmit interrupt
-//! - \b UART_INT_RX - Receive interrupt
-//! - \b UART_INT_CTS - CTS interrupt
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Enable the specified interrupts.
-    //
-    HWREG(ulBase + UART_O_IM) |= ulIntFlags;
-}
-
-//*****************************************************************************
-//
-//! Disables individual UART interrupt sources.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
-//!
-//! This function disables the indicated UART interrupt sources.  Only the
-//! sources that are enabled can be reflected to the processor interrupt;
-//! disabled sources have no effect on the processor.
-//!
-//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
-//! parameter to UARTIntEnable().
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Disable the specified interrupts.
-    //
-    HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags);
-}
-
-//*****************************************************************************
-//
-//! Gets the current interrupt status.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param bMasked is \b false if the raw interrupt status is required and
-//! \b true if the masked interrupt status is required.
-//!
-//! This function returns the interrupt status for the specified UART.  Either
-//! the raw interrupt status or the status of interrupts that are allowed to
-//! reflect to the processor can be returned.
-//!
-//! \return Returns the current interrupt status, enumerated as a bit field of
-//! values described in UARTIntEnable().
-//
-//*****************************************************************************
-unsigned long
-UARTIntStatus(unsigned long ulBase, tBoolean bMasked)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Return either the interrupt status or the raw interrupt status as
-    // requested.
-    //
-    if(bMasked)
-    {
-        return(HWREG(ulBase + UART_O_MIS));
-    }
-    else
-    {
-        return(HWREG(ulBase + UART_O_RIS));
-    }
-}
-
-//*****************************************************************************
-//
-//! Clears UART interrupt sources.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
-//!
-//! The specified UART interrupt sources are cleared, so that they no longer
-//! assert.  This function must be called in the interrupt handler to keep the
-//! interrupt from being recognized again immediately upon exit.
-//!
-//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
-//! parameter to UARTIntEnable().
-//!
-//! \note Because there is a write buffer in the Cortex-M3 processor, it may
-//! take several clock cycles before the interrupt source is actually cleared.
-//! Therefore, it is recommended that the interrupt source be cleared early in
-//! the interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (because the interrupt controller still sees
-//! the interrupt source asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Clear the requested interrupt sources.
-    //
-    HWREG(ulBase + UART_O_ICR) = ulIntFlags;
-}
-
-//*****************************************************************************
-//
-//! Enable UART DMA operation.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulDMAFlags is a bit mask of the DMA features to enable.
-//!
-//! The specified UART DMA features are enabled.  The UART can be
-//! configured to use DMA for transmit or receive, and to disable
-//! receive if an error occurs.  The \e ulDMAFlags parameter is the
-//! logical OR of any of the following values:
-//!
-//! - UART_DMA_RX - enable DMA for receive
-//! - UART_DMA_TX - enable DMA for transmit
-//! - UART_DMA_ERR_RXSTOP - disable DMA receive on UART error
-//!
-//! \note The uDMA controller must also be set up before DMA can be used
-//! with the UART.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Set the requested bits in the UART DMA control register.
-    //
-    HWREG(ulBase + UART_O_DMACTL) |= ulDMAFlags;
-}
-
-//*****************************************************************************
-//
-//! Disable UART DMA operation.
-//!
-//! \param ulBase is the base address of the UART port.
-//! \param ulDMAFlags is a bit mask of the DMA features to disable.
-//!
-//! This function is used to disable UART DMA features that were enabled
-//! by UARTDMAEnable().  The specified UART DMA features are disabled.  The
-//! \e ulDMAFlags parameter is the logical OR of any of the following values:
-//!
-//! - UART_DMA_RX - disable DMA for receive
-//! - UART_DMA_TX - disable DMA for transmit
-//! - UART_DMA_ERR_RXSTOP - do not disable DMA receive on UART error
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Clear the requested bits in the UART DMA control register.
-    //
-    HWREG(ulBase + UART_O_DMACTL) &= ~ulDMAFlags;
-}
-
-//*****************************************************************************
-//
-//! Gets current receiver errors.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function returns the current state of each of the 4 receiver error
-//! sources.  The returned errors are equivalent to the four error bits
-//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking()
-//! with the exception that the overrun error is set immediately the overrun
-//! occurs rather than when a character is next read.
-//!
-//! \return Returns a logical OR combination of the receiver error flags,
-//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK
-//! and \b UART_RXERROR_OVERRUN.
-//
-//*****************************************************************************
-unsigned long
-UARTRxErrorGet(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Return the current value of the receive status register.
-    //
-    return(HWREG(ulBase + UART_O_RSR) & 0x0000000F);
-}
-
-//*****************************************************************************
-//
-//! Clears all reported receiver errors.
-//!
-//! \param ulBase is the base address of the UART port.
-//!
-//! This function is used to clear all receiver error conditions reported via
-//! UARTRxErrorGet().  If using the overrun, framing error, parity error or
-//! break interrupts, this function must be called after clearing the interrupt
-//! to ensure that later errors of the same type trigger another interrupt.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-UARTRxErrorClear(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(UARTBaseValid(ulBase));
-
-    //
-    // Any write to the Error Clear Register will clear all bits which are
-    // currently set.
-    //
-    HWREG(ulBase + UART_O_ECR) = 0;
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
diff --git a/cc3200/hal/uart.h b/cc3200/hal/uart.h
deleted file mode 100644
index 503cd2c9e..000000000
--- a/cc3200/hal/uart.h
+++ /dev/null
@@ -1,234 +0,0 @@
-//*****************************************************************************
-//
-//  uart.h
-//
-//  Defines and Macros for the UART.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __UART_H__
-#define __UART_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
-// as the ulIntFlags parameter, and returned from UARTIntStatus.
-//
-//*****************************************************************************
-#define UART_INT_DMATX          0x20000     // DMA Tx Done interrupt Mask
-#define UART_INT_DMARX          0x10000     // DMA Rx Done interrupt Mask
-#define UART_INT_EOT            0x800       // End of transfer interrupt Mask
-#define UART_INT_OE             0x400       // Overrun Error Interrupt Mask
-#define UART_INT_BE             0x200       // Break Error Interrupt Mask
-#define UART_INT_PE             0x100       // Parity Error Interrupt Mask
-#define UART_INT_FE             0x080       // Framing Error Interrupt Mask
-#define UART_INT_RT             0x040       // Receive Timeout Interrupt Mask
-#define UART_INT_TX             0x020       // Transmit Interrupt Mask
-#define UART_INT_RX             0x010       // Receive Interrupt Mask
-#define UART_INT_CTS            0x002       // CTS Modem Interrupt Mask
-
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
-// and returned by UARTConfigGetExpClk in the pulConfig parameter.
-// Additionally, the UART_CONFIG_PAR_* subset can be passed to
-// UARTParityModeSet as the ulParity parameter, and are returned by
-// UARTParityModeGet.
-//
-//*****************************************************************************
-#define UART_CONFIG_WLEN_MASK   0x00000060  // Mask for extracting word length
-#define UART_CONFIG_WLEN_8      0x00000060  // 8 bit data
-#define UART_CONFIG_WLEN_7      0x00000040  // 7 bit data
-#define UART_CONFIG_WLEN_6      0x00000020  // 6 bit data
-#define UART_CONFIG_WLEN_5      0x00000000  // 5 bit data
-#define UART_CONFIG_STOP_MASK   0x00000008  // Mask for extracting stop bits
-#define UART_CONFIG_STOP_ONE    0x00000000  // One stop bit
-#define UART_CONFIG_STOP_TWO    0x00000008  // Two stop bits
-#define UART_CONFIG_PAR_MASK    0x00000086  // Mask for extracting parity
-#define UART_CONFIG_PAR_NONE    0x00000000  // No parity
-#define UART_CONFIG_PAR_EVEN    0x00000006  // Even parity
-#define UART_CONFIG_PAR_ODD     0x00000002  // Odd parity
-#define UART_CONFIG_PAR_ONE     0x00000082  // Parity bit is one
-#define UART_CONFIG_PAR_ZERO    0x00000086  // Parity bit is zero
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
-// returned by UARTFIFOLevelGet in the pulTxLevel.
-//
-//*****************************************************************************
-#define UART_FIFO_TX1_8         0x00000000  // Transmit interrupt at 1/8 Full
-#define UART_FIFO_TX2_8         0x00000001  // Transmit interrupt at 1/4 Full
-#define UART_FIFO_TX4_8         0x00000002  // Transmit interrupt at 1/2 Full
-#define UART_FIFO_TX6_8         0x00000003  // Transmit interrupt at 3/4 Full
-#define UART_FIFO_TX7_8         0x00000004  // Transmit interrupt at 7/8 Full
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
-// returned by UARTFIFOLevelGet in the pulRxLevel.
-//
-//*****************************************************************************
-#define UART_FIFO_RX1_8         0x00000000  // Receive interrupt at 1/8 Full
-#define UART_FIFO_RX2_8         0x00000008  // Receive interrupt at 1/4 Full
-#define UART_FIFO_RX4_8         0x00000010  // Receive interrupt at 1/2 Full
-#define UART_FIFO_RX6_8         0x00000018  // Receive interrupt at 3/4 Full
-#define UART_FIFO_RX7_8         0x00000020  // Receive interrupt at 7/8 Full
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
-//
-//*****************************************************************************
-#define UART_DMA_ERR_RXSTOP     0x00000004  // Stop DMA receive if UART error
-#define UART_DMA_TX             0x00000002  // Enable DMA for transmit
-#define UART_DMA_RX             0x00000001  // Enable DMA for receive
-
-//*****************************************************************************
-//
-// Values returned from UARTRxErrorGet().
-//
-//*****************************************************************************
-#define UART_RXERROR_OVERRUN    0x00000008
-#define UART_RXERROR_BREAK      0x00000004
-#define UART_RXERROR_PARITY     0x00000002
-#define UART_RXERROR_FRAMING    0x00000001
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTModemControlSet()and UARTModemControlClear()
-// or returned from UARTModemControlGet().
-//
-//*****************************************************************************
-#define UART_OUTPUT_RTS         0x00000800
-
-//*****************************************************************************
-//
-// Values that can be returned from UARTModemStatusGet().
-//
-//*****************************************************************************
-#define UART_INPUT_CTS          0x00000001
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTFlowControl() or returned from
-// UARTFlowControlGet().
-//
-//*****************************************************************************
-#define UART_FLOWCONTROL_TX     0x00008000
-#define UART_FLOWCONTROL_RX     0x00004000
-#define UART_FLOWCONTROL_NONE   0x00000000
-
-//*****************************************************************************
-//
-// Values that can be passed to UARTTxIntModeSet() or returned from
-// UARTTxIntModeGet().
-//
-//*****************************************************************************
-#define UART_TXINT_MODE_FIFO    0x00000000
-#define UART_TXINT_MODE_EOT     0x00000010
-
-
-//*****************************************************************************
-//
-// API Function prototypes
-//
-//*****************************************************************************
-extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
-extern unsigned long UARTParityModeGet(unsigned long ulBase);
-extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
-                             unsigned long ulRxLevel);
-extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
-                             unsigned long *pulRxLevel);
-extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
-                                unsigned long ulBaud, unsigned long ulConfig);
-extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
-                                unsigned long *pulBaud,
-                                unsigned long *pulConfig);
-extern void UARTEnable(unsigned long ulBase);
-extern void UARTDisable(unsigned long ulBase);
-extern void UARTFIFOEnable(unsigned long ulBase);
-extern void UARTFIFODisable(unsigned long ulBase);
-extern tBoolean UARTCharsAvail(unsigned long ulBase);
-extern tBoolean UARTSpaceAvail(unsigned long ulBase);
-extern long UARTCharGetNonBlocking(unsigned long ulBase);
-extern long UARTCharGet(unsigned long ulBase);
-extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
-                                       unsigned char ucData);
-extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
-extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
-extern tBoolean UARTBusy(unsigned long ulBase);
-extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
-extern void UARTIntUnregister(unsigned long ulBase);
-extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
-extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
-extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
-extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
-extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
-extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
-extern unsigned long UARTRxErrorGet(unsigned long ulBase);
-extern void UARTRxErrorClear(unsigned long ulBase);
-extern void UARTModemControlSet(unsigned long ulBase,
-                                unsigned long ulControl);
-extern void UARTModemControlClear(unsigned long ulBase,
-                                  unsigned long ulControl);
-extern unsigned long UARTModemControlGet(unsigned long ulBase);
-extern unsigned long UARTModemStatusGet(unsigned long ulBase);
-extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode);
-extern unsigned long UARTFlowControlGet(unsigned long ulBase);
-extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode);
-extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif //  __UART_H__
diff --git a/cc3200/hal/utils.c b/cc3200/hal/utils.c
deleted file mode 100644
index d0b13d7bf..000000000
--- a/cc3200/hal/utils.c
+++ /dev/null
@@ -1,104 +0,0 @@
-//*****************************************************************************
-//
-//  utils.c
-//
-//  Utility APIs
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup Utils_api
-//! @{
-//
-//*****************************************************************************
-#include "utils.h"
-
-
-//*****************************************************************************
-//
-//! Provides a small delay.
-//!
-//! \param ulCount is the number of delay loop iterations to perform.
-//!
-//! This function provides a means of generating a constant length delay.  It
-//! is written in assembly to keep the delay consistent across tool chains,
-//! avoiding the need to tune the delay based on the tool chain in use.
-//!
-//! The loop takes 3 cycles/loop.
-//!
-//! \return None.
-//
-//*****************************************************************************
-#if defined(ewarm) || defined(DOXYGEN)
-void
-UtilsDelay(unsigned long ulCount)
-{
-    __asm("    subs    r0, #1\n"
-          "    bne.n   UtilsDelay\n");
-}
-#endif
-
-#if defined(gcc)
-void __attribute__((naked))
-UtilsDelay(unsigned long ulCount)
-{
-    __asm("    subs    r0, #1\n"
-          "    bne     UtilsDelay\n"
-          "    bx      lr");
-}
-#endif
-
-//
-// For CCS implement this function in pure assembly.  This prevents the TI
-// compiler from doing funny things with the optimizer.
-//
-#if defined(ccs)
-    __asm("    .sect \".text:UtilsDelay\"\n"
-          "    .clink\n"
-          "    .thumbfunc UtilsDelay\n"
-          "    .thumb\n"
-          "    .global UtilsDelay\n"
-          "UtilsDelay:\n"
-          "    subs r0, #1\n"
-          "    bne.n UtilsDelay\n"
-          "    bx lr\n");
-#endif
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
diff --git a/cc3200/hal/utils.h b/cc3200/hal/utils.h
deleted file mode 100644
index a6fa78dac..000000000
--- a/cc3200/hal/utils.h
+++ /dev/null
@@ -1,71 +0,0 @@
-//*****************************************************************************
-//
-//  utils.h
-//
-//  Prototypes and macros for utility APIs
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __UTILS_H__
-#define __UTILS_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//*****************************************************************************
-//
-// API Function prototypes
-//
-//*****************************************************************************
-extern void UtilsDelay(unsigned long ulCount);
-
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__UTILS_H__
diff --git a/cc3200/hal/wdt.c b/cc3200/hal/wdt.c
deleted file mode 100644
index 8d8a9e9df..000000000
--- a/cc3200/hal/wdt.c
+++ /dev/null
@@ -1,491 +0,0 @@
-//*****************************************************************************
-//
-//  wdt.c
-//
-//  Driver for the Watchdog Timer Module.
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-//*****************************************************************************
-//
-//! \addtogroup WDT_Watchdog_Timer_api
-//! @{
-//
-//*****************************************************************************
-
-#include "inc/hw_ints.h"
-#include "inc/hw_memmap.h"
-#include "inc/hw_types.h"
-#include "inc/hw_wdt.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "wdt.h"
-
-//*****************************************************************************
-//
-//! Determines if the watchdog timer is enabled.
-//!
-//! \param ulBase is the base address of the watchdog timer module.
-//!
-//! This will check to see if the watchdog timer is enabled.
-//!
-//! \return Returns \b true if the watchdog timer is enabled, and \b false
-//! if it is not.
-//
-//*****************************************************************************
-tBoolean
-WatchdogRunning(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ulBase == WDT_BASE));
-
-    //
-    // See if the watchdog timer module is enabled, and return.
-    //
-    return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN);
-}
-
-//*****************************************************************************
-//
-//! Enables the watchdog timer.
-//!
-//! \param ulBase is the base address of the watchdog timer module.
-//!
-//! This will enable the watchdog timer counter and interrupt.
-//!
-//! \note This function will have no effect if the watchdog timer has
-//! been locked.
-//!
-//! \sa WatchdogLock(), WatchdogUnlock()
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-WatchdogEnable(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ulBase == WDT_BASE));
-
-    //
-    // Enable the watchdog timer module.
-    //
-    HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
-}
-
-//*****************************************************************************
-//
-//! Enables the watchdog timer lock mechanism.
-//!
-//! \param ulBase is the base address of the watchdog timer module.
-//!
-//! Locks out write access to the watchdog timer configuration registers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-WatchdogLock(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ulBase == WDT_BASE));
-
-    //
-    // Lock out watchdog register writes.  Writing anything to the WDT_O_LOCK
-    // register causes the lock to go into effect.
-    //
-    HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED;
-}
-
-//*****************************************************************************
-//
-//! Disables the watchdog timer lock mechanism.
-//!
-//! \param ulBase is the base address of the watchdog timer module.
-//!
-//! Enables write access to the watchdog timer configuration registers.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-WatchdogUnlock(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ulBase == WDT_BASE));
-
-    //
-    // Unlock watchdog register writes.
-    //
-    HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
-}
-
-//*****************************************************************************
-//
-//! Gets the state of the watchdog timer lock mechanism.
-//!
-//! \param ulBase is the base address of the watchdog timer module.
-//!
-//! Returns the lock state of the watchdog timer registers.
-//!
-//! \return Returns \b true if the watchdog timer registers are locked, and
-//! \b false if they are not locked.
-//
-//*****************************************************************************
-tBoolean
-WatchdogLockState(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ulBase == WDT_BASE));
-
-    //
-    // Get the lock state.
-    //
-    return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);
-}
-
-//*****************************************************************************
-//
-//! Sets the watchdog timer reload value.
-//!
-//! \param ulBase is the base address of the watchdog timer module.
-//! \param ulLoadVal is the load value for the watchdog timer.
-//!
-//! This function sets the value to load into the watchdog timer when the count
-//! reaches zero for the first time; if the watchdog timer is running when this
-//! function is called, then the value will be immediately loaded into the
-//! watchdog timer counter.  If the \e ulLoadVal parameter is 0, then an
-//! interrupt is immediately generated.
-//!
-//! \note This function will have no effect if the watchdog timer has
-//! been locked.
-//!
-//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet()
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ulBase == WDT_BASE));
-
-    //
-    // Set the load register.
-    //
-    HWREG(ulBase + WDT_O_LOAD) = ulLoadVal;
-}
-
-//*****************************************************************************
-//
-//! Gets the watchdog timer reload value.
-//!
-//! \param ulBase is the base address of the watchdog timer module.
-//!
-//! This function gets the value that is loaded into the watchdog timer when
-//! the count reaches zero for the first time.
-//!
-//! \sa WatchdogReloadSet()
-//!
-//! \return None.
-//
-//*****************************************************************************
-unsigned long
-WatchdogReloadGet(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ulBase == WDT_BASE));
-
-    //
-    // Get the load register.
-    //
-    return(HWREG(ulBase + WDT_O_LOAD));
-}
-
-//*****************************************************************************
-//
-//! Gets the current watchdog timer value.
-//!
-//! \param ulBase is the base address of the watchdog timer module.
-//!
-//! This function reads the current value of the watchdog timer.
-//!
-//! \return Returns the current value of the watchdog timer.
-//
-//*****************************************************************************
-unsigned long
-WatchdogValueGet(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ulBase == WDT_BASE));
-
-    //
-    // Get the current watchdog timer register value.
-    //
-    return(HWREG(ulBase + WDT_O_VALUE));
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for watchdog timer interrupt.
-//!
-//! \param ulBase is the base address of the watchdog timer module.
-//! \param pfnHandler is a pointer to the function to be called when the
-//! watchdog timer interrupt occurs.
-//!
-//! This function does the actual registering of the interrupt handler.  This
-//! will enable the global interrupt in the interrupt controller; the watchdog
-//! timer interrupt must be enabled via WatchdogEnable().  It is the interrupt
-//! handler's responsibility to clear the interrupt source via
-//! WatchdogIntClear().
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \note This function will only register the standard watchdog interrupt
-//! handler.  To register the NMI watchdog handler, use IntRegister()
-//! to register the handler for the \b FAULT_NMI interrupt.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ulBase == WDT_BASE));
-
-    //
-    // Register the interrupt handler and
-    // Enable the watchdog timer interrupt.
-    //
-    IntRegister(INT_WDT, pfnHandler);
-    IntEnable(INT_WDT);
-}
-
-//*****************************************************************************
-//
-//! Unregisters an interrupt handler for the watchdog timer interrupt.
-//!
-//! \param ulBase is the base address of the watchdog timer module.
-//!
-//! This function does the actual unregistering of the interrupt handler.  This
-//! function will clear the handler to be called when a watchdog timer
-//! interrupt occurs.  This will also mask off the interrupt in the interrupt
-//! controller so that the interrupt handler no longer is called.
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \note This function will only unregister the standard watchdog interrupt
-//! handler.  To unregister the NMI watchdog handler, use IntUnregister()
-//! to unregister the handler for the \b FAULT_NMI interrupt.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-WatchdogIntUnregister(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ulBase == WDT_BASE));
-
-    //
-    // Disable the interrupt
-    IntDisable(INT_WDT);
-
-    //
-    // Unregister the interrupt handler.
-    //
-    IntUnregister(INT_WDT);
-}
-
-//*****************************************************************************
-//
-//! Gets the current watchdog timer interrupt status.
-//!
-//! \param ulBase is the base address of the watchdog timer module.
-//! \param bMasked is \b false if the raw interrupt status is required and
-//! \b true if the masked interrupt status is required.
-//!
-//! This returns the interrupt status for the watchdog timer module.  Either
-//! the raw interrupt status or the status of interrupt that is allowed to
-//! reflect to the processor can be returned.
-//!
-//! \return Returns the current interrupt status, where a 1 indicates that the
-//! watchdog interrupt is active, and a 0 indicates that it is not active.
-//
-//*****************************************************************************
-unsigned long
-WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ulBase == WDT_BASE));
-
-    //
-    // Return either the interrupt status or the raw interrupt status as
-    // requested.
-    //
-    if(bMasked)
-    {
-        return(HWREG(ulBase + WDT_O_MIS));
-    }
-    else
-    {
-        return(HWREG(ulBase + WDT_O_RIS));
-    }
-}
-
-//*****************************************************************************
-//
-//! Clears the watchdog timer interrupt.
-//!
-//! \param ulBase is the base address of the watchdog timer module.
-//!
-//! The watchdog timer interrupt source is cleared, so that it no longer
-//! asserts.
-//!
-//! \note Because there is a write buffer in the Cortex-M3 processor, it may
-//! take several clock cycles before the interrupt source is actually cleared.
-//! Therefore, it is recommended that the interrupt source be cleared early in
-//! the interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (because the interrupt controller still sees
-//! the interrupt source asserted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-WatchdogIntClear(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ulBase == WDT_BASE));
-
-    //
-    // Clear the interrupt source.
-    //
-    HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT;
-}
-
-//*****************************************************************************
-//
-//! Enables stalling of the watchdog timer during debug events.
-//!
-//! \param ulBase is the base address of the watchdog timer module.
-//!
-//! This function allows the watchdog timer to stop counting when the processor
-//! is stopped by the debugger.  By doing so, the watchdog is prevented from
-//! expiring (typically almost immediately from a human time perspective) and
-//! resetting the system (if reset is enabled).  The watchdog will instead
-//! expired after the appropriate number of processor cycles have been executed
-//! while debugging (or at the appropriate time after the processor has been
-//! restarted).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-WatchdogStallEnable(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ulBase == WDT_BASE));
-
-    //
-    // Enable timer stalling.
-    //
-    HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL;
-}
-
-//*****************************************************************************
-//
-//! Disables stalling of the watchdog timer during debug events.
-//!
-//! \param ulBase is the base address of the watchdog timer module.
-//!
-//! This function disables the debug mode stall of the watchdog timer.  By
-//! doing so, the watchdog timer continues to count regardless of the processor
-//! debug state.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-WatchdogStallDisable(unsigned long ulBase)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT((ulBase == WDT_BASE));
-
-    //
-    // Disable timer stalling.
-    //
-    HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL);
-}
-
-//*****************************************************************************
-//
-// Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************
diff --git a/cc3200/hal/wdt.h b/cc3200/hal/wdt.h
deleted file mode 100644
index 2e52db42b..000000000
--- a/cc3200/hal/wdt.h
+++ /dev/null
@@ -1,82 +0,0 @@
-//*****************************************************************************
-//
-//  wdt.h - Prototypes for the Watchdog Timer API
-//
-//  Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the
-//    distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//*****************************************************************************
-
-#ifndef __WATCHDOG_H__
-#define __WATCHDOG_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-extern tBoolean WatchdogRunning(unsigned long ulBase);
-extern void WatchdogEnable(unsigned long ulBase);
-extern void WatchdogLock(unsigned long ulBase);
-extern void WatchdogUnlock(unsigned long ulBase);
-extern tBoolean WatchdogLockState(unsigned long ulBase);
-extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
-extern unsigned long WatchdogReloadGet(unsigned long ulBase);
-extern unsigned long WatchdogValueGet(unsigned long ulBase);
-extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
-extern void WatchdogIntUnregister(unsigned long ulBase);
-extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
-extern void WatchdogIntClear(unsigned long ulBase);
-extern void WatchdogStallEnable(unsigned long ulBase);
-extern void WatchdogStallDisable(unsigned long ulBase);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __WATCHDOG_H__