Initial; working SAIL RISC-V regs

The register definition along with read/write functions for registers are lowered to Coq. The FIRRTL annotation does not work as expected.
author: Aditya Naik 2021-08-27 13:07:37 -0400
committer: Aditya Naik 2021-08-27 13:07:37 -0400
commit: 663e24a3d8f45b4b184b3a4bc3a57bc0f3d6cd78 (patch)
tree: 62a699a6065bea9f4bcefda93d227209fec4a154 /build
17 files changed, 4990 insertions, 0 deletions
diff --git a/build/.Makefile.d b/build/.Makefile.d
new file mode 100644
index 0000000..e6650b7
--- /dev/null
+++ b/build/.Makefile.d
@@ -0,0 +1,6 @@
+riscv_types.vo riscv_types.glob riscv_types.v.beautified riscv_types.required_vo: riscv_types.v /home/aditya/.opam/default/share/sail/lib/coq/Base.vo /home/aditya/.opam/default/share/sail/lib/coq/Real.vo
+riscv_types.vio: riscv_types.v /home/aditya/.opam/default/share/sail/lib/coq/Base.vio /home/aditya/.opam/default/share/sail/lib/coq/Real.vio
+riscv_types.vos riscv_types.vok riscv_types.required_vos: riscv_types.v /home/aditya/.opam/default/share/sail/lib/coq/Base.vos /home/aditya/.opam/default/share/sail/lib/coq/Real.vos
+riscv.vo riscv.glob riscv.v.beautified riscv.required_vo: riscv.v /home/aditya/.opam/default/share/sail/lib/coq/Base.vo /home/aditya/.opam/default/share/sail/lib/coq/Real.vo riscv_types.vo
+riscv.vio: riscv.v /home/aditya/.opam/default/share/sail/lib/coq/Base.vio /home/aditya/.opam/default/share/sail/lib/coq/Real.vio riscv_types.vio
+riscv.vos riscv.vok riscv.required_vos: riscv.v /home/aditya/.opam/default/share/sail/lib/coq/Base.vos /home/aditya/.opam/default/share/sail/lib/coq/Real.vos riscv_types.vos
diff --git a/build/.lia.cache b/build/.lia.cache
new file mode 100644
index 0000000..21e5075
--- /dev/null
+++ b/build/.lia.cache
diff --git a/build/.riscv.aux b/build/.riscv.aux
new file mode 100644
index 0000000..06dda63
--- /dev/null
+++ b/build/.riscv.aux
@@ -0,0 +1,9 @@
+COQAUX1 c6db294320f7a6b05e7783002664d787 /home/aditya/dev/firrtl-proof/sail-simple-test/build/riscv.v
+515 646 context_used ""
+1345 1557 context_used ""
+1345 1557 context_used ""
+1345 1557 context_used ""
+1644 1897 context_used ""
+8826 8916 context_used ""
+8918 9026 context_used ""
+0 0 vo_compile_time "0.649"
diff --git a/build/.riscv_types.aux b/build/.riscv_types.aux
new file mode 100644
index 0000000..3dea1e8
--- /dev/null
+++ b/build/.riscv_types.aux
@@ -0,0 +1,2 @@
+COQAUX1 23addcfb4a3be3458f693a2ed5b20df5 /home/aditya/dev/firrtl-proof/sail-simple-test/build/riscv_types.v
+0 0 vo_compile_time "0.639"
diff --git a/build/Makefile b/build/Makefile
new file mode 100644
index 0000000..8bfc468
--- /dev/null
+++ b/build/Makefile
@@ -0,0 +1,870 @@
+##########################################################################
+##         #   The Coq Proof Assistant / The Coq Development Team       ##
+##  v      #         Copyright INRIA, CNRS and contributors             ##
+## <O___,, # (see version control and CREDITS file for authors & dates) ##
+##   \VV/  ###############################################################
+##    //   #    This file is distributed under the terms of the         ##
+##         #     GNU Lesser General Public License Version 2.1          ##
+##         #     (see LICENSE file for the text of the license)         ##
+##########################################################################
+## GNUMakefile for Coq 8.13.2
+
+# For debugging purposes (must stay here, don't move below)
+INITIAL_VARS := $(.VARIABLES)
+# To implement recursion we save the name of the main Makefile
+SELF := $(lastword $(MAKEFILE_LIST))
+PARENT := $(firstword $(MAKEFILE_LIST))
+
+# This file is generated by coq_makefile and contains many variable
+# definitions, like the list of .v files or the path to Coq
+include Makefile.conf
+
+# Put in place old names
+VFILES            := $(COQMF_VFILES)
+MLIFILES          := $(COQMF_MLIFILES)
+MLFILES           := $(COQMF_MLFILES)
+MLGFILES          := $(COQMF_MLGFILES)
+MLPACKFILES       := $(COQMF_MLPACKFILES)
+MLLIBFILES        := $(COQMF_MLLIBFILES)
+CMDLINE_VFILES    := $(COQMF_CMDLINE_VFILES)
+INSTALLCOQDOCROOT := $(COQMF_INSTALLCOQDOCROOT)
+OTHERFLAGS        := $(COQMF_OTHERFLAGS)
+COQ_SRC_SUBDIRS   := $(COQMF_COQ_SRC_SUBDIRS)
+OCAMLLIBS         := $(COQMF_OCAMLLIBS)
+SRC_SUBDIRS       := $(COQMF_SRC_SUBDIRS)
+COQLIBS           := $(COQMF_COQLIBS)
+COQLIBS_NOML      := $(COQMF_COQLIBS_NOML)
+CMDLINE_COQLIBS   := $(COQMF_CMDLINE_COQLIBS)
+LOCAL             := $(COQMF_LOCAL)
+COQLIB            := $(COQMF_COQLIB)
+DOCDIR            := $(COQMF_DOCDIR)
+OCAMLFIND         := $(COQMF_OCAMLFIND)
+CAMLFLAGS         := $(COQMF_CAMLFLAGS)
+HASNATDYNLINK     := $(COQMF_HASNATDYNLINK)
+OCAMLWARN         := $(COQMF_WARN)
+
+Makefile.conf: _CoqProject
+	coq_makefile -f _CoqProject riscv_types.v riscv.v -o Makefile
+
+# This file can be created by the user to hook into double colon rules or
+# add any other Makefile code he may need
+-include Makefile.local
+
+# Parameters ##################################################################
+#
+# Parameters are make variable assignments.
+# They can be passed to (each call to) make on the command line.
+# They can also be put in Makefile.local once and for all.
+# For retro-compatibility reasons they can be put in the _CoqProject, but this
+# practice is discouraged since _CoqProject better not contain make specific
+# code (be nice to user interfaces).
+
+# Print shell commands (set to non empty)
+VERBOSE ?=
+
+# Time the Coq process (set to non empty), and how (see default value)
+TIMED?=
+TIMECMD?=
+# Use command time on linux, gtime on Mac OS
+TIMEFMT?="$@ (real: %e, user: %U, sys: %S, mem: %M ko)"
+ifneq (,$(TIMED))
+ifeq (0,$(shell command time -f "" true >/dev/null 2>/dev/null; echo $$?))
+STDTIME?=command time -f $(TIMEFMT)
+else
+ifeq (0,$(shell gtime -f "" true >/dev/null 2>/dev/null; echo $$?))
+STDTIME?=gtime -f $(TIMEFMT)
+else
+STDTIME?=command time
+endif
+endif
+else
+STDTIME?=command time -f $(TIMEFMT)
+endif
+
+ifneq (,$(COQBIN))
+# add an ending /
+COQBIN:=$(COQBIN)/
+endif
+
+# Coq binaries
+COQC     ?= "$(COQBIN)coqc"
+COQTOP   ?= "$(COQBIN)coqtop"
+COQCHK   ?= "$(COQBIN)coqchk"
+COQDEP   ?= "$(COQBIN)coqdep"
+COQDOC   ?= "$(COQBIN)coqdoc"
+COQPP    ?= "$(COQBIN)coqpp"
+COQMKFILE ?= "$(COQBIN)coq_makefile"
+OCAMLLIBDEP ?= "$(COQBIN)ocamllibdep"
+
+# Timing scripts
+COQMAKE_ONE_TIME_FILE ?= "$(COQLIB)/tools/make-one-time-file.py"
+COQMAKE_BOTH_TIME_FILES ?= "$(COQLIB)/tools/make-both-time-files.py"
+COQMAKE_BOTH_SINGLE_TIMING_FILES ?= "$(COQLIB)/tools/make-both-single-timing-files.py"
+BEFORE ?=
+AFTER ?=
+
+# FIXME this should be generated by Coq (modules already linked by Coq)
+CAMLDONTLINK=str,unix,dynlink,threads,zarith
+
+# OCaml binaries
+CAMLC       ?= "$(OCAMLFIND)" ocamlc   -c
+CAMLOPTC    ?= "$(OCAMLFIND)" opt      -c
+CAMLLINK    ?= "$(OCAMLFIND)" ocamlc   -linkpkg -dontlink $(CAMLDONTLINK)
+CAMLOPTLINK ?= "$(OCAMLFIND)" opt      -linkpkg -dontlink $(CAMLDONTLINK)
+CAMLDOC     ?= "$(OCAMLFIND)" ocamldoc
+CAMLDEP     ?= "$(OCAMLFIND)" ocamldep -slash -ml-synonym .mlpack
+
+# DESTDIR is prepended to all installation paths
+DESTDIR ?=
+
+# Debug builds, typically -g to OCaml, -debug to Coq.
+CAMLDEBUG ?=
+COQDEBUG ?=
+
+# Extra packages to be linked in (as in findlib -package)
+CAMLPKGS ?=
+
+# Option for making timing files
+TIMING?=
+# Option for changing sorting of timing output file
+TIMING_SORT_BY ?= auto
+# Option for changing the fuzz parameter on the output file
+TIMING_FUZZ ?= 0
+# Option for changing whether to use real or user time for timing tables
+TIMING_REAL?=
+# Option for including the memory column(s)
+TIMING_INCLUDE_MEM?=
+# Option for sorting by the memory column
+TIMING_SORT_BY_MEM?=
+# Output file names for timed builds
+TIME_OF_BUILD_FILE               ?= time-of-build.log
+TIME_OF_BUILD_BEFORE_FILE        ?= time-of-build-before.log
+TIME_OF_BUILD_AFTER_FILE         ?= time-of-build-after.log
+TIME_OF_PRETTY_BUILD_FILE        ?= time-of-build-pretty.log
+TIME_OF_PRETTY_BOTH_BUILD_FILE   ?= time-of-build-both.log
+TIME_OF_PRETTY_BUILD_EXTRA_FILES ?= - # also output to the command line
+
+TGTS ?=
+
+# Retro compatibility (DESTDIR is standard on Unix, DSTROOT is not)
+ifdef DSTROOT
+DESTDIR := $(DSTROOT)
+endif
+
+# Substitution of the path by appending $(DESTDIR) if needed.
+# The variable $(COQMF_WINDRIVE) can be needed for Cygwin environments.
+windrive_path = $(if $(COQMF_WINDRIVE),$(subst $(COQMF_WINDRIVE),/,$(1)),$(1))
+destination_path = $(if $(DESTDIR),$(DESTDIR)/$(call windrive_path,$(1)),$(1))
+
+# Installation paths of libraries and documentation.
+COQLIBINSTALL ?= $(call destination_path,$(COQLIB)/user-contrib)
+COQDOCINSTALL ?= $(call destination_path,$(DOCDIR)/user-contrib)
+COQTOPINSTALL ?= $(call destination_path,$(COQLIB)/toploop) # FIXME: Unused variable?
+
+########## End of parameters ##################################################
+# What follows may be relevant to you only if you need to
+# extend this Makefile.  If so, look for 'Extension point' here and
+# put in Makefile.local double colon rules accordingly.
+# E.g. to perform some work after the all target completes you can write
+#
+# post-all::
+# 	echo "All done!"
+#
+# in Makefile.local
+#
+###############################################################################
+
+
+
+
+# Flags #######################################################################
+#
+# We define a bunch of variables combining the parameters.
+# To add additional flags to coq, coqchk or coqdoc, set the
+# {COQ,COQCHK,COQDOC}EXTRAFLAGS variable to whatever you want to add.
+# To overwrite the default choice and set your own flags entirely, set the
+# {COQ,COQCHK,COQDOC}FLAGS variable.
+
+SHOW := $(if $(VERBOSE),@true "",@echo "")
+HIDE := $(if $(VERBOSE),,@)
+
+TIMER=$(if $(TIMED), $(STDTIME), $(TIMECMD))
+
+OPT?=
+
+# The DYNOBJ and DYNLIB variables are used by "coqdep -dyndep var" in .v.d
+ifeq '$(OPT)' '-byte'
+USEBYTE:=true
+DYNOBJ:=.cma
+DYNLIB:=.cma
+else
+USEBYTE:=
+DYNOBJ:=.cmxs
+DYNLIB:=.cmxs
+endif
+
+# these variables are meant to be overridden if you want to add *extra* flags
+COQEXTRAFLAGS?=
+COQCHKEXTRAFLAGS?=
+COQDOCEXTRAFLAGS?=
+
+# these flags do NOT contain the libraries, to make them easier to overwrite
+COQFLAGS?=-q $(OTHERFLAGS) $(COQEXTRAFLAGS)
+COQCHKFLAGS?=-silent -o $(COQCHKEXTRAFLAGS)
+COQDOCFLAGS?=-interpolate -utf8 $(COQDOCEXTRAFLAGS)
+
+COQDOCLIBS?=$(COQLIBS_NOML)
+
+# The version of Coq being run and the version of coq_makefile that
+# generated this makefile
+COQ_VERSION:=$(shell $(COQC) --print-version | cut -d " " -f 1)
+COQMAKEFILE_VERSION:=8.13.2
+
+COQSRCLIBS?= $(foreach d,$(COQ_SRC_SUBDIRS), -I "$(COQLIB)/$(d)")
+
+CAMLFLAGS+=$(OCAMLLIBS) $(COQSRCLIBS)
+# ocamldoc fails with unknown argument otherwise
+CAMLDOCFLAGS:=$(filter-out -annot, $(filter-out -bin-annot, $(CAMLFLAGS)))
+CAMLFLAGS+=$(OCAMLWARN)
+
+ifneq (,$(TIMING))
+TIMING_ARG=-time
+ifeq (after,$(TIMING))
+TIMING_EXT=after-timing
+else
+ifeq (before,$(TIMING))
+TIMING_EXT=before-timing
+else
+TIMING_EXT=timing
+endif
+endif
+else
+TIMING_ARG=
+endif
+
+# Files #######################################################################
+#
+# We here define a bunch of variables about the files being part of the
+# Coq project in order to ease the writing of build target and build rules
+
+VDFILE := .Makefile.d
+
+ALLSRCFILES := \
+	$(MLGFILES) \
+	$(MLFILES) \
+	$(MLPACKFILES) \
+	$(MLLIBFILES) \
+	$(MLIFILES)
+
+# helpers
+vo_to_obj = $(addsuffix .o,\
+  $(filter-out Warning: Error:,\
+  $(shell $(COQTOP) -q -noinit -batch -quiet -print-mod-uid $(1))))
+strip_dotslash = $(patsubst ./%,%,$(1))
+
+# without this we get undefined variables in the expansion for the
+# targets of the [deprecated,use-mllib-or-mlpack] rule
+with_undef = $(if $(filter-out undefined, $(origin $(1))),$($(1)))
+
+VO = vo
+VOS = vos
+
+VOFILES = $(VFILES:.v=.$(VO))
+GLOBFILES = $(VFILES:.v=.glob)
+HTMLFILES = $(VFILES:.v=.html)
+GHTMLFILES = $(VFILES:.v=.g.html)
+BEAUTYFILES = $(addsuffix .beautified,$(VFILES))
+TEXFILES = $(VFILES:.v=.tex)
+GTEXFILES = $(VFILES:.v=.g.tex)
+CMOFILES = \
+	$(MLGFILES:.mlg=.cmo) \
+	$(MLFILES:.ml=.cmo) \
+	$(MLPACKFILES:.mlpack=.cmo)
+CMXFILES = $(CMOFILES:.cmo=.cmx)
+OFILES = $(CMXFILES:.cmx=.o)
+CMAFILES = $(MLLIBFILES:.mllib=.cma) $(MLPACKFILES:.mlpack=.cma)
+CMXAFILES = $(CMAFILES:.cma=.cmxa)
+CMIFILES = \
+	$(CMOFILES:.cmo=.cmi) \
+	$(MLIFILES:.mli=.cmi)
+# the /if/ is because old _CoqProject did not list a .ml(pack|lib) but just
+# a .mlg file
+CMXSFILES = \
+	$(MLPACKFILES:.mlpack=.cmxs) \
+	$(CMXAFILES:.cmxa=.cmxs) \
+	$(if $(MLPACKFILES)$(CMXAFILES),,\
+		$(MLGFILES:.mlg=.cmxs) $(MLFILES:.ml=.cmxs))
+
+# files that are packed into a plugin (no extension)
+PACKEDFILES = \
+	$(call strip_dotslash, \
+	  $(foreach lib, \
+	    $(call strip_dotslash, \
+	       $(MLPACKFILES:.mlpack=_MLPACK_DEPENDENCIES)),$(call with_undef,$(lib))))
+# files that are archived into a .cma (mllib)
+LIBEDFILES = \
+	$(call strip_dotslash, \
+	  $(foreach lib, \
+	    $(call strip_dotslash, \
+	       $(MLLIBFILES:.mllib=_MLLIB_DEPENDENCIES)),$(call with_undef,$(lib))))
+CMIFILESTOINSTALL = $(filter-out $(addsuffix .cmi,$(PACKEDFILES)),$(CMIFILES))
+CMOFILESTOINSTALL = $(filter-out $(addsuffix .cmo,$(PACKEDFILES)),$(CMOFILES))
+OBJFILES = $(call vo_to_obj,$(VOFILES))
+ALLNATIVEFILES = \
+	$(OBJFILES:.o=.cmi) \
+	$(OBJFILES:.o=.cmx) \
+	$(OBJFILES:.o=.cmxs)
+# trick: wildcard filters out non-existing files, so that `install` doesn't show
+# warnings and `clean` doesn't pass to rm a list of files that is too long for
+# the shell.
+NATIVEFILES = $(wildcard $(ALLNATIVEFILES))
+FILESTOINSTALL = \
+	$(VOFILES) \
+	$(VFILES) \
+	$(GLOBFILES) \
+	$(NATIVEFILES) \
+	$(CMIFILESTOINSTALL)
+BYTEFILESTOINSTALL = \
+	$(CMOFILESTOINSTALL) \
+	$(CMAFILES)
+ifeq '$(HASNATDYNLINK)' 'true'
+DO_NATDYNLINK = yes
+FILESTOINSTALL += $(CMXSFILES) $(CMXAFILES) $(CMOFILESTOINSTALL:.cmo=.cmx)
+else
+DO_NATDYNLINK =
+endif
+
+ALLDFILES = $(addsuffix .d,$(ALLSRCFILES)) $(VDFILE)
+
+# Compilation targets #########################################################
+
+all:
+	$(HIDE)$(MAKE) --no-print-directory -f "$(SELF)" pre-all
+	$(HIDE)$(MAKE) --no-print-directory -f "$(SELF)" real-all
+	$(HIDE)$(MAKE) --no-print-directory -f "$(SELF)" post-all
+.PHONY: all
+
+all.timing.diff:
+	$(HIDE)$(MAKE) --no-print-directory -f "$(SELF)" pre-all
+	$(HIDE)$(MAKE) --no-print-directory -f "$(SELF)" real-all.timing.diff TIME_OF_PRETTY_BUILD_EXTRA_FILES=""
+	$(HIDE)$(MAKE) --no-print-directory -f "$(SELF)" post-all
+.PHONY: all.timing.diff
+
+ifeq (0,$(TIMING_REAL))
+TIMING_REAL_ARG :=
+TIMING_USER_ARG := --user
+else
+ifeq (1,$(TIMING_REAL))
+TIMING_REAL_ARG := --real
+TIMING_USER_ARG :=
+else
+TIMING_REAL_ARG :=
+TIMING_USER_ARG :=
+endif
+endif
+
+ifeq (0,$(TIMING_INCLUDE_MEM))
+TIMING_INCLUDE_MEM_ARG := --no-include-mem
+else
+TIMING_INCLUDE_MEM_ARG :=
+endif
+
+ifeq (1,$(TIMING_SORT_BY_MEM))
+TIMING_SORT_BY_MEM_ARG := --sort-by-mem
+else
+TIMING_SORT_BY_MEM_ARG :=
+endif
+
+make-pretty-timed-before:: TIME_OF_BUILD_FILE=$(TIME_OF_BUILD_BEFORE_FILE)
+make-pretty-timed-after:: TIME_OF_BUILD_FILE=$(TIME_OF_BUILD_AFTER_FILE)
+make-pretty-timed make-pretty-timed-before make-pretty-timed-after::
+	$(HIDE)rm -f pretty-timed-success.ok
+	$(HIDE)($(MAKE) --no-print-directory -f "$(PARENT)" $(TGTS) TIMED=1 2>&1 && touch pretty-timed-success.ok) | tee -a $(TIME_OF_BUILD_FILE)
+	$(HIDE)rm pretty-timed-success.ok # must not be -f; must fail if the touch failed
+print-pretty-timed::
+	$(HIDE)$(COQMAKE_ONE_TIME_FILE) $(TIMING_INCLUDE_MEM_ARG) $(TIMING_SORT_BY_MEM_ARG) $(TIMING_REAL_ARG) $(TIME_OF_BUILD_FILE) $(TIME_OF_PRETTY_BUILD_FILE) $(TIME_OF_PRETTY_BUILD_EXTRA_FILES)
+print-pretty-timed-diff::
+	$(HIDE)$(COQMAKE_BOTH_TIME_FILES) --sort-by=$(TIMING_SORT_BY) $(TIMING_INCLUDE_MEM_ARG) $(TIMING_SORT_BY_MEM_ARG) $(TIMING_REAL_ARG) $(TIME_OF_BUILD_AFTER_FILE) $(TIME_OF_BUILD_BEFORE_FILE) $(TIME_OF_PRETTY_BOTH_BUILD_FILE) $(TIME_OF_PRETTY_BUILD_EXTRA_FILES)
+ifeq (,$(BEFORE))
+print-pretty-single-time-diff::
+	@echo 'Error: Usage: $(MAKE) print-pretty-single-time-diff AFTER=path/to/file.v.after-timing BEFORE=path/to/file.v.before-timing'
+	$(HIDE)false
+else
+ifeq (,$(AFTER))
+print-pretty-single-time-diff::
+	@echo 'Error: Usage: $(MAKE) print-pretty-single-time-diff AFTER=path/to/file.v.after-timing BEFORE=path/to/file.v.before-timing'
+	$(HIDE)false
+else
+print-pretty-single-time-diff::
+	$(HIDE)$(COQMAKE_BOTH_SINGLE_TIMING_FILES) --fuzz=$(TIMING_FUZZ) --sort-by=$(TIMING_SORT_BY) $(TIMING_USER_ARG) $(AFTER) $(BEFORE) $(TIME_OF_PRETTY_BUILD_FILE) $(TIME_OF_PRETTY_BUILD_EXTRA_FILES)
+endif
+endif
+pretty-timed:
+	$(HIDE)$(MAKE) --no-print-directory -f "$(PARENT)" make-pretty-timed
+	$(HIDE)$(MAKE) --no-print-directory -f "$(SELF)" print-pretty-timed
+.PHONY: pretty-timed make-pretty-timed make-pretty-timed-before make-pretty-timed-after print-pretty-timed print-pretty-timed-diff print-pretty-single-time-diff
+
+# Extension points for actions to be performed before/after the all target
+pre-all::
+	@# Extension point
+	$(HIDE)if [ "$(COQMAKEFILE_VERSION)" != "$(COQ_VERSION)" ]; then\
+	  echo "W: This Makefile was generated by Coq $(COQMAKEFILE_VERSION)";\
+	  echo "W: while the current Coq version is $(COQ_VERSION)";\
+	fi
+.PHONY: pre-all
+
+post-all::
+	@# Extension point
+.PHONY: post-all
+
+real-all: $(VOFILES) $(if $(USEBYTE),bytefiles,optfiles)
+.PHONY: real-all
+
+real-all.timing.diff: $(VOFILES:.vo=.v.timing.diff)
+.PHONY: real-all.timing.diff
+
+bytefiles: $(CMOFILES) $(CMAFILES)
+.PHONY: bytefiles
+
+optfiles: $(if $(DO_NATDYNLINK),$(CMXSFILES))
+.PHONY: optfiles
+
+# FIXME, see Ralf's bugreport
+# quick is deprecated, now renamed vio
+vio: $(VOFILES:.vo=.vio)
+.PHONY: vio
+quick: vio
+	$(warning "'make quick' is deprecated, use 'make vio' or consider using 'vos' files")
+.PHONY: quick
+
+vio2vo:
+	$(TIMER) $(COQC) $(COQDEBUG) $(COQFLAGS) $(COQLIBS) \
+		-schedule-vio2vo $(J) $(VOFILES:%.vo=%.vio)
+.PHONY: vio2vo
+
+# quick2vo is undocumented
+quick2vo:
+	$(HIDE)make -j $(J) vio
+	$(HIDE)VIOFILES=$$(for vofile in $(VOFILES); do \
+	  viofile="$$(echo "$$vofile" | sed "s/\.vo$$/.vio/")"; \
+	  if [ "$$vofile" -ot "$$viofile" -o ! -e "$$vofile" ]; then printf "$$viofile "; fi; \
+	done); \
+	echo "VIO2VO: $$VIOFILES"; \
+	if [ -n "$$VIOFILES" ]; then \
+	  $(TIMER) $(COQC) $(COQDEBUG) $(COQFLAGS) $(COQLIBS) -schedule-vio2vo $(J) $$VIOFILES; \
+	fi
+.PHONY: quick2vo
+
+checkproofs:
+	$(TIMER) $(COQC) $(COQDEBUG) $(COQFLAGS) $(COQLIBS) \
+		-schedule-vio-checking $(J) $(VOFILES:%.vo=%.vio)
+.PHONY: checkproofs
+
+vos: $(VOFILES:%.vo=%.vos)
+.PHONY: vos
+
+vok: $(VOFILES:%.vo=%.vok)
+.PHONY: vok
+
+validate: $(VOFILES)
+	$(TIMER) $(COQCHK) $(COQCHKFLAGS) $(COQLIBS_NOML) $^
+.PHONY: validate
+
+only: $(TGTS)
+.PHONY: only
+
+# Documentation targets #######################################################
+
+html: $(GLOBFILES) $(VFILES)
+	$(SHOW)'COQDOC -d html $(GAL)'
+	$(HIDE)mkdir -p html
+	$(HIDE)$(COQDOC) \
+		-toc $(COQDOCFLAGS) -html $(GAL) $(COQDOCLIBS) -d html $(VFILES)
+
+mlihtml: $(MLIFILES:.mli=.cmi)
+	$(SHOW)'CAMLDOC -d $@'
+	$(HIDE)mkdir $@ || rm -rf $@/*
+	$(HIDE)$(CAMLDOC) -html \
+		-d $@ -m A $(CAMLDEBUG) $(CAMLDOCFLAGS) $(MLIFILES)
+
+all-mli.tex: $(MLIFILES:.mli=.cmi)
+	$(SHOW)'CAMLDOC -latex $@'
+	$(HIDE)$(CAMLDOC) -latex \
+		-o $@ -m A $(CAMLDEBUG) $(CAMLDOCFLAGS) $(MLIFILES)
+
+all.ps: $(VFILES)
+	$(SHOW)'COQDOC -ps $(GAL)'
+	$(HIDE)$(COQDOC) \
+		-toc $(COQDOCFLAGS) -ps $(GAL) $(COQDOCLIBS) \
+		-o $@ `$(COQDEP) -sort $(VFILES)`
+
+all.pdf: $(VFILES)
+	$(SHOW)'COQDOC -pdf $(GAL)'
+	$(HIDE)$(COQDOC) \
+		-toc $(COQDOCFLAGS) -pdf $(GAL) $(COQDOCLIBS) \
+		-o $@ `$(COQDEP) -sort $(VFILES)`
+
+# FIXME: not quite right, since the output name is different
+gallinahtml: GAL=-g
+gallinahtml: html
+
+all-gal.ps: GAL=-g
+all-gal.ps: all.ps
+
+all-gal.pdf: GAL=-g
+all-gal.pdf: all.pdf
+
+# ?
+beautify: $(BEAUTYFILES)
+	for file in $^; do mv $${file%.beautified} $${file%beautified}old && mv $${file} $${file%.beautified}; done
+	@echo 'Do not do "make clean" until you are sure that everything went well!'
+	@echo 'If there were a problem, execute "for file in $$(find . -name \*.v.old -print); do mv $${file} $${file%.old}; done" in your shell/'
+.PHONY: beautify
+
+# Installation targets ########################################################
+#
+# There rules can be extended in Makefile.local
+# Extensions can't assume when they run.
+
+install:
+	$(HIDE)code=0; for f in $(FILESTOINSTALL); do\
+	 if ! [ -f "$$f" ]; then >&2 echo $$f does not exist; code=1; fi \
+	done; exit $$code
+	$(HIDE)for f in $(FILESTOINSTALL); do\
+	 df="`$(COQMKFILE) -destination-of "$$f" $(COQLIBS)`";\
+	 if [ "$$?" != "0" -o -z "$$df" ]; then\
+	   echo SKIP "$$f" since it has no logical path;\
+	 else\
+	   install -d "$(COQLIBINSTALL)/$$df" &&\
+	   install -m 0644 "$$f" "$(COQLIBINSTALL)/$$df" &&\
+	   echo INSTALL "$$f" "$(COQLIBINSTALL)/$$df";\
+	 fi;\
+	done
+	$(HIDE)$(MAKE) install-extra -f "$(SELF)"
+install-extra::
+	@# Extension point
+.PHONY: install install-extra
+
+install-byte:
+	$(HIDE)for f in $(BYTEFILESTOINSTALL); do\
+	 df="`$(COQMKFILE) -destination-of "$$f" $(COQLIBS)`";\
+	 if [ "$$?" != "0" -o -z "$$df" ]; then\
+	   echo SKIP "$$f" since it has no logical path;\
+	 else\
+	   install -d "$(COQLIBINSTALL)/$$df" &&\
+	   install -m 0644 "$$f" "$(COQLIBINSTALL)/$$df" &&\
+	   echo INSTALL "$$f" "$(COQLIBINSTALL)/$$df";\
+	 fi;\
+	done
+
+install-doc:: html mlihtml
+	@# Extension point
+	$(HIDE)install -d "$(COQDOCINSTALL)/$(INSTALLCOQDOCROOT)/html"
+	$(HIDE)for i in html/*; do \
+	 dest="$(COQDOCINSTALL)/$(INSTALLCOQDOCROOT)/$$i";\
+	 install -m 0644 "$$i" "$$dest";\
+	 echo INSTALL "$$i" "$$dest";\
+	done
+	$(HIDE)install -d \
+		"$(COQDOCINSTALL)/$(INSTALLCOQDOCROOT)/mlihtml"
+	$(HIDE)for i in mlihtml/*; do \
+	 dest="$(COQDOCINSTALL)/$(INSTALLCOQDOCROOT)/$$i";\
+	 install -m 0644 "$$i" "$$dest";\
+	 echo INSTALL "$$i" "$$dest";\
+	done
+.PHONY: install-doc
+
+uninstall::
+	@# Extension point
+	$(HIDE)for f in $(FILESTOINSTALL); do \
+	 df="`$(COQMKFILE) -destination-of "$$f" $(COQLIBS)`" &&\
+	 instf="$(COQLIBINSTALL)/$$df/`basename $$f`" &&\
+	 rm -f "$$instf" &&\
+	 echo RM "$$instf" &&\
+	 (rmdir "$(COQLIBINSTALL)/$$df/" 2>/dev/null || true); \
+	done
+.PHONY: uninstall
+
+uninstall-doc::
+	@# Extension point
+	$(SHOW)'RM $(COQDOCINSTALL)/$(INSTALLCOQDOCROOT)/html'
+	$(HIDE)rm -rf "$(COQDOCINSTALL)/$(INSTALLCOQDOCROOT)/html"
+	$(SHOW)'RM $(COQDOCINSTALL)/$(INSTALLCOQDOCROOT)/mlihtml'
+	$(HIDE)rm -rf "$(COQDOCINSTALL)/$(INSTALLCOQDOCROOT)/mlihtml"
+	$(HIDE) rmdir "$(COQDOCINSTALL)/$(INSTALLCOQDOCROOT)/" || true
+.PHONY: uninstall-doc
+
+# Cleaning ####################################################################
+#
+# There rules can be extended in Makefile.local
+# Extensions can't assume when they run.
+
+clean::
+	@# Extension point
+	$(SHOW)'CLEAN'
+	$(HIDE)rm -f $(CMOFILES)
+	$(HIDE)rm -f $(CMIFILES)
+	$(HIDE)rm -f $(CMAFILES)
+	$(HIDE)rm -f $(CMOFILES:.cmo=.cmx)
+	$(HIDE)rm -f $(CMXAFILES)
+	$(HIDE)rm -f $(CMXSFILES)
+	$(HIDE)rm -f $(CMOFILES:.cmo=.o)
+	$(HIDE)rm -f $(CMXAFILES:.cmxa=.a)
+	$(HIDE)rm -f $(MLGFILES:.mlg=.ml)
+	$(HIDE)rm -f $(ALLDFILES)
+	$(HIDE)rm -f $(NATIVEFILES)
+	$(HIDE)find . -name .coq-native -type d -empty -delete
+	$(HIDE)rm -f $(VOFILES)
+	$(HIDE)rm -f $(VOFILES:.vo=.vio)
+	$(HIDE)rm -f $(VOFILES:.vo=.vos)
+	$(HIDE)rm -f $(VOFILES:.vo=.vok)
+	$(HIDE)rm -f $(BEAUTYFILES) $(VFILES:=.old)
+	$(HIDE)rm -f all.ps all-gal.ps all.pdf all-gal.pdf all.glob all-mli.tex
+	$(HIDE)rm -f $(VFILES:.v=.glob)
+	$(HIDE)rm -f $(VFILES:.v=.tex)
+	$(HIDE)rm -f $(VFILES:.v=.g.tex)
+	$(HIDE)rm -f pretty-timed-success.ok
+	$(HIDE)rm -rf html mlihtml
+.PHONY: clean
+
+cleanall:: clean
+	@# Extension point
+	$(SHOW)'CLEAN *.aux *.timing'
+	$(HIDE)rm -f $(foreach f,$(VFILES:.v=),$(dir $(f)).$(notdir $(f)).aux)
+	$(HIDE)rm -f $(TIME_OF_BUILD_FILE) $(TIME_OF_BUILD_BEFORE_FILE) $(TIME_OF_BUILD_AFTER_FILE) $(TIME_OF_PRETTY_BUILD_FILE) $(TIME_OF_PRETTY_BOTH_BUILD_FILE)
+	$(HIDE)rm -f $(VOFILES:.vo=.v.timing)
+	$(HIDE)rm -f $(VOFILES:.vo=.v.before-timing)
+	$(HIDE)rm -f $(VOFILES:.vo=.v.after-timing)
+	$(HIDE)rm -f $(VOFILES:.vo=.v.timing.diff)
+	$(HIDE)rm -f .lia.cache .nia.cache
+.PHONY: cleanall
+
+archclean::
+	@# Extension point
+	$(SHOW)'CLEAN *.cmx *.o'
+	$(HIDE)rm -f $(NATIVEFILES)
+	$(HIDE)rm -f $(CMOFILES:%.cmo=%.cmx)
+.PHONY: archclean
+
+
+# Compilation rules ###########################################################
+
+$(MLIFILES:.mli=.cmi): %.cmi: %.mli
+	$(SHOW)'CAMLC -c $<'
+	$(HIDE)$(TIMER) $(CAMLC) $(CAMLDEBUG) $(CAMLFLAGS) $(CAMLPKGS) $<
+
+$(MLGFILES:.mlg=.ml): %.ml: %.mlg
+	$(SHOW)'COQPP $<'
+	$(HIDE)$(COQPP) $<
+
+# Stupid hack around a deficient syntax: we cannot concatenate two expansions
+$(filter %.cmo, $(MLFILES:.ml=.cmo) $(MLGFILES:.mlg=.cmo)): %.cmo: %.ml
+	$(SHOW)'CAMLC -c $<'
+	$(HIDE)$(TIMER) $(CAMLC) $(CAMLDEBUG) $(CAMLFLAGS) $(CAMLPKGS) $<
+
+# Same hack
+$(filter %.cmx, $(MLFILES:.ml=.cmx) $(MLGFILES:.mlg=.cmx)): %.cmx: %.ml
+	$(SHOW)'CAMLOPT -c $(FOR_PACK) $<'
+	$(HIDE)$(TIMER) $(CAMLOPTC) $(CAMLDEBUG) $(CAMLFLAGS) $(CAMLPKGS) $(FOR_PACK) $<
+
+
+$(MLLIBFILES:.mllib=.cmxs): %.cmxs: %.cmxa
+	$(SHOW)'CAMLOPT -shared -o $@'
+	$(HIDE)$(TIMER) $(CAMLOPTLINK) $(CAMLDEBUG) $(CAMLFLAGS) $(CAMLPKGS) \
+		-linkall -shared -o $@ $<
+
+$(MLLIBFILES:.mllib=.cma): %.cma: | %.mllib
+	$(SHOW)'CAMLC -a -o $@'
+	$(HIDE)$(TIMER) $(CAMLLINK) $(CAMLDEBUG) $(CAMLFLAGS) $(CAMLPKGS) -a -o $@ $^
+
+$(MLLIBFILES:.mllib=.cmxa): %.cmxa: | %.mllib
+	$(SHOW)'CAMLOPT -a -o $@'
+	$(HIDE)$(TIMER) $(CAMLOPTLINK) $(CAMLDEBUG) $(CAMLFLAGS) -a -o $@ $^
+
+
+$(MLPACKFILES:.mlpack=.cmxs): %.cmxs: %.cmxa
+	$(SHOW)'CAMLOPT -shared -o $@'
+	$(HIDE)$(TIMER) $(CAMLOPTLINK) $(CAMLDEBUG) $(CAMLFLAGS) $(CAMLPKGS) \
+		-shared -linkall -o $@ $<
+
+$(MLPACKFILES:.mlpack=.cmxa): %.cmxa: %.cmx
+	$(SHOW)'CAMLOPT -a -o $@'
+	$(HIDE)$(TIMER) $(CAMLOPTLINK) $(CAMLDEBUG) $(CAMLFLAGS) -a -o $@ $<
+
+$(MLPACKFILES:.mlpack=.cma): %.cma: %.cmo | %.mlpack
+	$(SHOW)'CAMLC -a -o $@'
+	$(HIDE)$(TIMER) $(CAMLLINK) $(CAMLDEBUG) $(CAMLFLAGS) $(CAMLPKGS) -a -o $@ $^
+
+$(MLPACKFILES:.mlpack=.cmo): %.cmo: | %.mlpack
+	$(SHOW)'CAMLC -pack -o $@'
+	$(HIDE)$(TIMER) $(CAMLLINK) $(CAMLDEBUG) $(CAMLFLAGS) -pack -o $@ $^
+
+$(MLPACKFILES:.mlpack=.cmx): %.cmx: | %.mlpack
+	$(SHOW)'CAMLOPT -pack -o $@'
+	$(HIDE)$(TIMER) $(CAMLOPTLINK) $(CAMLDEBUG) $(CAMLFLAGS) -pack -o $@ $^
+
+# This rule is for _CoqProject with no .mllib nor .mlpack
+$(filter-out $(MLLIBFILES:.mllib=.cmxs) $(MLPACKFILES:.mlpack=.cmxs) $(addsuffix .cmxs,$(PACKEDFILES)) $(addsuffix .cmxs,$(LIBEDFILES)),$(MLFILES:.ml=.cmxs) $(MLGFILES:.mlg=.cmxs)): %.cmxs: %.cmx
+	$(SHOW)'[deprecated,use-mllib-or-mlpack] CAMLOPT -shared -o $@'
+	$(HIDE)$(TIMER) $(CAMLOPTLINK) $(CAMLDEBUG) $(CAMLFLAGS) $(CAMLPKGS) \
+		-shared -o $@ $<
+
+ifneq (,$(TIMING))
+TIMING_EXTRA = > $<.$(TIMING_EXT)
+else
+TIMING_EXTRA =
+endif
+
+$(VOFILES): %.vo: %.v
+	$(SHOW)COQC $<
+	$(HIDE)$(TIMER) $(COQC) $(COQDEBUG) $(TIMING_ARG) $(COQFLAGS) $(COQLIBS) $< $(TIMING_EXTRA)
+
+# FIXME ?merge with .vo / .vio ?
+$(GLOBFILES): %.glob: %.v
+	$(TIMER) $(COQC) $(COQDEBUG) $(COQFLAGS) $(COQLIBS) $<
+
+$(VFILES:.v=.vio): %.vio: %.v
+	$(SHOW)COQC -vio $<
+	$(HIDE)$(TIMER) $(COQC) -vio $(COQDEBUG) $(COQFLAGS) $(COQLIBS) $<
+
+$(VFILES:.v=.vos): %.vos: %.v
+	$(SHOW)COQC -vos $<
+	$(HIDE)$(TIMER) $(COQC) -vos $(COQDEBUG) $(COQFLAGS) $(COQLIBS) $<
+
+$(VFILES:.v=.vok): %.vok: %.v
+	$(SHOW)COQC -vok $<
+	$(HIDE)$(TIMER) $(COQC) -vok $(COQDEBUG) $(COQFLAGS) $(COQLIBS) $<
+
+$(addsuffix .timing.diff,$(VFILES)): %.timing.diff : %.before-timing %.after-timing
+	$(SHOW)PYTHON TIMING-DIFF $*.{before,after}-timing
+	$(HIDE)$(MAKE) --no-print-directory -f "$(SELF)" print-pretty-single-time-diff BEFORE=$*.before-timing AFTER=$*.after-timing TIME_OF_PRETTY_BUILD_FILE="$@"
+
+$(BEAUTYFILES): %.v.beautified: %.v
+	$(SHOW)'BEAUTIFY $<'
+	$(HIDE)$(TIMER) $(COQC) $(COQDEBUG) $(COQFLAGS) $(COQLIBS) -beautify $<
+
+$(TEXFILES): %.tex: %.v
+	$(SHOW)'COQDOC -latex $<'
+	$(HIDE)$(COQDOC) $(COQDOCFLAGS) -latex $< -o $@
+
+$(GTEXFILES): %.g.tex: %.v
+	$(SHOW)'COQDOC -latex -g $<'
+	$(HIDE)$(COQDOC) $(COQDOCFLAGS) -latex -g $< -o $@
+
+$(HTMLFILES): %.html: %.v %.glob
+	$(SHOW)'COQDOC -html $<'
+	$(HIDE)$(COQDOC) $(COQDOCFLAGS) -html $< -o $@
+
+$(GHTMLFILES): %.g.html: %.v %.glob
+	$(SHOW)'COQDOC -html -g $<'
+	$(HIDE)$(COQDOC) $(COQDOCFLAGS)  -html -g $< -o $@
+
+# Dependency files ############################################################
+
+ifndef MAKECMDGOALS
+  -include $(ALLDFILES)
+else
+  ifneq ($(filter-out archclean clean cleanall printenv make-pretty-timed make-pretty-timed-before make-pretty-timed-after print-pretty-timed print-pretty-timed-diff print-pretty-single-time-diff,$(MAKECMDGOALS)),)
+   -include $(ALLDFILES)
+ endif
+endif
+
+.SECONDARY: $(ALLDFILES)
+
+redir_if_ok = > "$@" || ( RV=$$?; rm -f "$@"; exit $$RV )
+
+GENMLFILES:=$(MLGFILES:.mlg=.ml)
+$(addsuffix .d,$(ALLSRCFILES)): $(GENMLFILES)
+
+$(addsuffix .d,$(MLIFILES)): %.mli.d: %.mli
+	$(SHOW)'CAMLDEP $<'
+	$(HIDE)$(CAMLDEP) $(OCAMLLIBS) "$<" $(redir_if_ok)
+
+$(addsuffix .d,$(MLGFILES)): %.mlg.d: %.ml
+	$(SHOW)'CAMLDEP $<'
+	$(HIDE)$(CAMLDEP) $(OCAMLLIBS) "$<" $(redir_if_ok)
+
+$(addsuffix .d,$(MLFILES)): %.ml.d: %.ml
+	$(SHOW)'CAMLDEP $<'
+	$(HIDE)$(CAMLDEP) $(OCAMLLIBS) "$<" $(redir_if_ok)
+
+$(addsuffix .d,$(MLLIBFILES)): %.mllib.d: %.mllib
+	$(SHOW)'OCAMLLIBDEP $<'
+	$(HIDE)$(OCAMLLIBDEP) -c $(OCAMLLIBS) "$<" $(redir_if_ok)
+
+$(addsuffix .d,$(MLPACKFILES)): %.mlpack.d: %.mlpack
+	$(SHOW)'OCAMLLIBDEP $<'
+	$(HIDE)$(OCAMLLIBDEP) -c $(OCAMLLIBS) "$<" $(redir_if_ok)
+
+# If this makefile is created using a _CoqProject we have coqdep get
+# options from it. This avoids argument length limits for pathological
+# projects. Note that extra options might be on the command line.
+VDFILE_FLAGS:=$(if _CoqProject,-f _CoqProject,) $(CMDLINE_COQLIBS) $(CMDLINE_VFILES)
+
+$(VDFILE): _CoqProject $(VFILES)
+	$(SHOW)'COQDEP VFILES'
+	$(HIDE)$(COQDEP) -vos -dyndep var $(VDFILE_FLAGS) $(redir_if_ok)
+
+# Misc ########################################################################
+
+byte:
+	$(HIDE)$(MAKE) all "OPT:=-byte" -f "$(SELF)"
+.PHONY: byte
+
+opt:
+	$(HIDE)$(MAKE) all "OPT:=-opt" -f "$(SELF)"
+.PHONY:	opt
+
+# This is deprecated.  To extend this makefile use
+# extension points and Makefile.local
+printenv::
+	$(warning printenv is deprecated)
+	$(warning write extensions in Makefile.local or include Makefile.conf)
+	@echo 'LOCAL = $(LOCAL)'
+	@echo 'COQLIB = $(COQLIB)'
+	@echo 'DOCDIR = $(DOCDIR)'
+	@echo 'OCAMLFIND = $(OCAMLFIND)'
+	@echo 'HASNATDYNLINK = $(HASNATDYNLINK)'
+	@echo 'SRC_SUBDIRS = $(SRC_SUBDIRS)'
+	@echo 'COQ_SRC_SUBDIRS = $(COQ_SRC_SUBDIRS)'
+	@echo 'OCAMLFIND = $(OCAMLFIND)'
+	@echo 'PP = $(PP)'
+	@echo 'COQFLAGS = $(COQFLAGS)'
+	@echo 'COQLIB = $(COQLIBS)'
+	@echo 'COQLIBINSTALL = $(COQLIBINSTALL)'
+	@echo 'COQDOCINSTALL = $(COQDOCINSTALL)'
+.PHONY:	printenv
+
+# Generate a .merlin file.  If you need to append directives to this
+# file you can extend the merlin-hook target in Makefile.local
+.merlin:
+	$(SHOW)'FILL .merlin'
+	$(HIDE)echo 'FLG $(COQMF_CAMLFLAGS)' > .merlin
+	$(HIDE)echo 'B $(COQLIB)' >> .merlin
+	$(HIDE)echo 'S $(COQLIB)' >> .merlin
+	$(HIDE)$(foreach d,$(COQ_SRC_SUBDIRS), \
+		echo 'B $(COQLIB)$(d)' >> .merlin;)
+	$(HIDE)$(foreach d,$(COQ_SRC_SUBDIRS), \
+		echo 'S $(COQLIB)$(d)' >> .merlin;)
+	$(HIDE)$(foreach d,$(SRC_SUBDIRS), echo 'B $(d)' >> .merlin;)
+	$(HIDE)$(foreach d,$(SRC_SUBDIRS), echo 'S $(d)' >> .merlin;)
+	$(HIDE)$(MAKE) merlin-hook -f "$(SELF)"
+.PHONY: merlin
+
+merlin-hook::
+	@# Extension point
+.PHONY: merlin-hook
+
+# prints all variables
+debug:
+	$(foreach v,\
+		$(sort $(filter-out $(INITIAL_VARS) INITIAL_VARS,\
+	       		$(.VARIABLES))),\
+	       	$(info $(v) = $($(v))))
+.PHONY: debug
+
+.DEFAULT_GOAL := all
+
+# Local Variables:
+# mode: makefile-gmake
+# End:
diff --git a/build/Makefile.conf b/build/Makefile.conf
new file mode 100644
index 0000000..db8f321
--- /dev/null
+++ b/build/Makefile.conf
@@ -0,0 +1,55 @@
+# This configuration file was generated by running:
+# coq_makefile -f _CoqProject riscv_types.v riscv.v -o Makefile
+
+
+###############################################################################
+#                                                                             #
+# Project files.                                                              #
+#                                                                             #
+###############################################################################
+
+COQMF_VFILES = riscv_types.v riscv.v
+COQMF_MLIFILES = 
+COQMF_MLFILES = 
+COQMF_MLGFILES = 
+COQMF_MLPACKFILES = 
+COQMF_MLLIBFILES = 
+COQMF_CMDLINE_VFILES = riscv_types.v riscv.v
+
+###############################################################################
+#                                                                             #
+# Path directives (-I, -R, -Q).                                               #
+#                                                                             #
+###############################################################################
+
+COQMF_OCAMLLIBS = 
+COQMF_SRC_SUBDIRS = 
+COQMF_COQLIBS =   -R /home/aditya/.opam/default/share/sail/lib/coq/ Sail -R . '' -R ../handwritten_support ''
+COQMF_COQLIBS_NOML =  -R /home/aditya/.opam/default/share/sail/lib/coq/ Sail -R . '' -R ../handwritten_support ''
+COQMF_CMDLINE_COQLIBS =   
+
+###############################################################################
+#                                                                             #
+# Coq configuration.                                                          #
+#                                                                             #
+###############################################################################
+
+COQMF_LOCAL=0
+COQMF_COQLIB=/home/aditya/.opam/default/lib/coq/
+COQMF_DOCDIR=/home/aditya/.opam/default/doc/
+COQMF_OCAMLFIND=/home/aditya/.opam/default/bin/ocamlfind
+COQMF_CAMLFLAGS=-thread -rectypes -w +a-4-9-27-41-42-44-45-48-58-67   -safe-string -strict-sequence
+COQMF_WARN=-warn-error +a-3
+COQMF_HASNATDYNLINK=true
+COQMF_COQ_SRC_SUBDIRS=config lib clib kernel library engine pretyping interp gramlib gramlib/.pack parsing proofs tactics toplevel printing ide stm vernac plugins/btauto plugins/cc plugins/derive plugins/extraction plugins/firstorder plugins/funind plugins/ltac plugins/micromega plugins/nsatz plugins/omega plugins/ring plugins/rtauto plugins/ssr plugins/ssrmatching plugins/ssrsearch plugins/syntax
+COQMF_COQ_NATIVE_COMPILER_DEFAULT=no
+COQMF_WINDRIVE=
+
+###############################################################################
+#                                                                             #
+# Extra variables.                                                            #
+#                                                                             #
+###############################################################################
+
+COQMF_OTHERFLAGS = 
+COQMF_INSTALLCOQDOCROOT = orphan_Sail__
diff --git a/build/_CoqProject b/build/_CoqProject
new file mode 100644
index 0000000..b4438de
--- /dev/null
+++ b/build/_CoqProject
@@ -0,0 +1,3 @@
+-R /home/aditya/.opam/default/share/sail/lib/coq/ Sail
+-R . ""
+-R ../handwritten_support ""
+\ No newline at end of file
diff --git a/build/riscv.glob b/build/riscv.glob
new file mode 100644
index 0000000..7206a6e
--- /dev/null
+++ b/build/riscv.glob
@@ -0,0 +1,1313 @@
+DIGEST c6db294320f7a6b05e7783002664d787
+Friscv
+R49:57 Sail.Base <> <> lib
+R75:83 Sail.Real <> <> lib
+R101:111 riscv_types <> <> lib
+def 199:205 <> is_none
+binder 208:208 <> a:1
+R225:230 Coq.Init.Datatypes <> option ind
+R232:232 riscv <> a:1 var
+binder 219:221 <> opt:2
+R237:240 Coq.Init.Datatypes <> bool ind
+R254:256 riscv <> opt:2 var
+R265:268 Coq.Init.Datatypes <> Some constr
+R275:279 Coq.Init.Datatypes <> false constr
+R283:286 Coq.Init.Datatypes <> None constr
+R291:294 Coq.Init.Datatypes <> true constr
+def 313:319 <> is_some
+binder 322:322 <> a:4
+R339:344 Coq.Init.Datatypes <> option ind
+R346:346 riscv <> a:4 var
+binder 333:335 <> opt:5
+R351:354 Coq.Init.Datatypes <> bool ind
+R368:370 riscv <> opt:5 var
+R379:382 Coq.Init.Datatypes <> Some constr
+R389:392 Coq.Init.Datatypes <> true constr
+R396:399 Coq.Init.Datatypes <> None constr
+R404:408 Coq.Init.Datatypes <> false constr
+def 427:433 <> eq_unit
+R440:443 Coq.Init.Datatypes <> unit ind
+R451:454 Coq.Init.Datatypes <> unit ind
+R459:459 Coq.Init.Specif <> ::type_scope:'{'_x_':'_x_'&'_x_'}' not
+R465:467 Coq.Init.Specif <> ::type_scope:'{'_x_':'_x_'&'_x_'}' not
+R472:474 Coq.Init.Specif <> ::type_scope:'{'_x_':'_x_'&'_x_'}' not
+R492:492 Coq.Init.Specif <> ::type_scope:'{'_x_':'_x_'&'_x_'}' not
+R468:471 Coq.Init.Datatypes <> bool ind
+binder 460:464 <> _bool:7
+R475:483 Sail.Values <> ArithFact class
+R486:490 riscv <> _bool:7 var
+R497:504 Sail.Values <> build_ex def
+R507:510 Coq.Init.Datatypes <> true constr
+def 526:532 <> neq_int
+R539:539 Coq.Numbers.BinNums <> Z ind
+binder 535:535 <> x:8
+R547:547 Coq.Numbers.BinNums <> Z ind
+binder 543:543 <> y:9
+R552:552 Coq.Init.Specif <> ::type_scope:'{'_x_':'_x_'&'_x_'}' not
+R558:560 Coq.Init.Specif <> ::type_scope:'{'_x_':'_x_'&'_x_'}' not
+R565:567 Coq.Init.Specif <> ::type_scope:'{'_x_':'_x_'&'_x_'}' not
+R610:610 Coq.Init.Specif <> ::type_scope:'{'_x_':'_x_'&'_x_'}' not
+R561:564 Coq.Init.Datatypes <> bool ind
+binder 553:557 <> _bool:10
+R568:576 Sail.Values <> ArithFact class
+R579:586 Coq.Bool.Bool <> eqb def
+R589:592 Coq.Init.Datatypes <> negb def
+R596:599 Coq.ZArith.BinInt <> ::Z_scope:x_'=?'_x not
+R595:595 riscv <> x:8 var
+R600:600 riscv <> y:9 var
+R604:608 riscv <> _bool:10 var
+R618:625 Sail.Values <> build_ex def
+R628:631 Coq.Init.Datatypes <> negb def
+R634:638 Coq.ZArith.BinInt Z eqb def
+R640:640 riscv <> x:8 var
+R642:642 riscv <> y:9 var
+def 659:666 <> neq_bool
+R673:676 Coq.Init.Datatypes <> bool ind
+binder 669:669 <> x:11
+R684:687 Coq.Init.Datatypes <> bool ind
+binder 680:680 <> y:12
+R692:695 Coq.Init.Datatypes <> bool ind
+R700:703 Coq.Init.Datatypes <> negb def
+R706:713 Coq.Bool.Bool <> eqb def
+R715:715 riscv <> x:11 var
+R717:717 riscv <> y:12 var
+def 733:736 <> __id
+R743:743 Coq.Numbers.BinNums <> Z ind
+binder 739:739 <> x:13
+R748:748 Coq.Init.Specif <> ::type_scope:'{'_x_':'_x_'&'_x_'}' not
+R756:758 Coq.Init.Specif <> ::type_scope:'{'_x_':'_x_'&'_x_'}' not
+R760:762 Coq.Init.Specif <> ::type_scope:'{'_x_':'_x_'&'_x_'}' not
+R787:787 Coq.Init.Specif <> ::type_scope:'{'_x_':'_x_'&'_x_'}' not
+R759:759 Coq.Numbers.BinNums <> Z ind
+binder 749:755 <> _retval:14
+R763:771 Sail.Values <> ArithFact class
+R781:784 Coq.ZArith.BinInt <> ::Z_scope:x_'=?'_x not
+R774:780 riscv <> _retval:14 var
+R785:785 riscv <> x:13 var
+R792:799 Sail.Values <> build_ex def
+R802:802 riscv <> x:13 var
+def 818:825 <> fdiv_int
+R832:832 Coq.Numbers.BinNums <> Z ind
+binder 828:828 <> n:15
+R840:840 Coq.Numbers.BinNums <> Z ind
+binder 836:836 <> m:16
+R845:845 Coq.Numbers.BinNums <> Z ind
+R856:870 Coq.Bool.Sumbool <> sumbool_of_bool def
+R873:876 Coq.Init.Datatypes <> andb def
+R891:895 Coq.ZArith.BinInt Z gtb def
+R897:897 riscv <> m:16 var
+R879:883 Coq.ZArith.BinInt Z ltb def
+R885:885 riscv <> n:15 var
+R950:964 Coq.Bool.Sumbool <> sumbool_of_bool def
+R967:970 Coq.Init.Datatypes <> andb def
+R985:989 Coq.ZArith.BinInt Z ltb def
+R991:991 riscv <> m:16 var
+R973:977 Coq.ZArith.BinInt Z gtb def
+R979:979 riscv <> n:15 var
+R1041:1046 Coq.ZArith.BinInt Z quot def
+R1048:1048 riscv <> n:15 var
+R1050:1050 riscv <> m:16 var
+R1002:1006 Coq.ZArith.BinInt Z sub def
+R1009:1014 Coq.ZArith.BinInt Z quot def
+R1017:1021 Coq.ZArith.BinInt Z sub def
+R1023:1023 riscv <> n:15 var
+R1028:1028 riscv <> m:16 var
+R908:912 Coq.ZArith.BinInt Z sub def
+R915:920 Coq.ZArith.BinInt Z quot def
+R923:927 Coq.ZArith.BinInt Z add def
+R929:929 riscv <> n:15 var
+R934:934 riscv <> m:16 var
+def 1065:1072 <> fmod_int
+R1079:1079 Coq.Numbers.BinNums <> Z ind
+binder 1075:1075 <> n:17
+R1087:1087 Coq.Numbers.BinNums <> Z ind
+binder 1083:1083 <> m:18
+R1092:1092 Coq.Numbers.BinNums <> Z ind
+R1097:1101 Coq.ZArith.BinInt Z sub def
+R1103:1103 riscv <> n:17 var
+R1106:1110 Coq.ZArith.BinInt Z mul def
+R1112:1112 riscv <> m:18 var
+R1115:1122 riscv <> fdiv_int def
+R1124:1124 riscv <> n:17 var
+R1126:1126 riscv <> m:18 var
+def 1143:1157 <> concat_str_bits
+R1164:1164 Coq.Numbers.BinNums <> Z ind
+binder 1160:1160 <> n:19
+R1174:1179 Coq.Strings.String <> string ind
+binder 1168:1170 <> str:20
+R1187:1191 Sail.Values <> mword def
+R1193:1193 riscv <> n:19 var
+binder 1183:1183 <> x:21
+R1198:1203 Coq.Strings.String <> string ind
+R1211:1223 Coq.Strings.String <> append def
+R1225:1227 riscv <> str:20 var
+R1230:1243 Sail.Operators_mwords <> string_of_bits def
+R1245:1245 riscv <> x:21 var
+def 1261:1274 <> concat_str_dec
+R1283:1288 Coq.Strings.String <> string ind
+binder 1277:1279 <> str:22
+R1296:1296 Coq.Numbers.BinNums <> Z ind
+binder 1292:1292 <> x:23
+R1301:1306 Coq.Strings.String <> string ind
+R1311:1323 Coq.Strings.String <> append def
+R1325:1327 riscv <> str:22 var
+R1330:1336 Sail.String <> dec_str def
+R1338:1338 riscv <> x:23 var
+def 1356:1364 <> sail_mask
+R1372:1372 Coq.Numbers.BinNums <> Z ind
+binder 1367:1368 <> v0:24
+R1382:1382 Coq.Numbers.BinNums <> Z ind
+binder 1376:1378 <> len:25
+R1390:1394 Sail.Values <> mword def
+R1396:1397 riscv <> v0:24 var
+binder 1386:1386 <> v:26
+R1402:1410 Sail.Values <> ArithFact class
+R1413:1413 Coq.Init.Datatypes <> ::bool_scope:x_'&&'_x not
+R1423:1428 Coq.Init.Datatypes <> ::bool_scope:x_'&&'_x not
+R1437:1437 Coq.Init.Datatypes <> ::bool_scope:x_'&&'_x not
+R1417:1421 Coq.ZArith.BinInt <> ::Z_scope:x_'>=?'_x not
+R1414:1416 riscv <> len:25 var
+R1431:1435 Coq.ZArith.BinInt <> ::Z_scope:x_'>=?'_x not
+R1429:1430 riscv <> v0:24 var
+binder 1402:1438 <> H:27
+R1443:1447 Sail.Values <> mword def
+R1449:1451 riscv <> len:25 var
+R1462:1476 Coq.Bool.Sumbool <> sumbool_of_bool def
+R1479:1483 Coq.ZArith.BinInt Z leb def
+R1485:1487 riscv <> len:25 var
+R1490:1501 Sail.Values <> length_mword def
+R1503:1503 riscv <> v:26 var
+R1539:1549 Sail.Operators_mwords <> zero_extend def
+R1553:1555 riscv <> len:25 var
+R1551:1551 riscv <> v:26 var
+R1512:1526 Sail.Operators_mwords <> vector_truncate def
+R1530:1532 riscv <> len:25 var
+R1528:1528 riscv <> v:26 var
+def 1570:1578 <> sail_ones
+R1585:1585 Coq.Numbers.BinNums <> Z ind
+binder 1581:1581 <> n:28
+R1590:1598 Sail.Values <> ArithFact class
+R1602:1606 Coq.ZArith.BinInt <> ::Z_scope:x_'>=?'_x not
+R1601:1601 riscv <> n:28 var
+binder 1590:1608 <> H:29
+R1613:1617 Sail.Values <> mword def
+R1619:1619 riscv <> n:28 var
+R1624:1630 Sail.Operators_mwords <> not_vec def
+R1633:1637 Sail.Operators_mwords <> zeros def
+R1639:1639 riscv <> n:28 var
+def 1655:1664 <> slice_mask
+R1671:1671 Coq.Numbers.BinNums <> Z ind
+binder 1667:1667 <> n:30
+R1679:1679 Coq.Numbers.BinNums <> Z ind
+binder 1675:1675 <> i:31
+R1687:1687 Coq.Numbers.BinNums <> Z ind
+binder 1683:1683 <> l:32
+R1692:1700 Sail.Values <> ArithFact class
+R1704:1708 Coq.ZArith.BinInt <> ::Z_scope:x_'>=?'_x not
+R1703:1703 riscv <> n:30 var
+binder 1692:1710 <> H:33
+R1715:1719 Sail.Values <> mword def
+R1721:1721 riscv <> n:30 var
+R1732:1746 Coq.Bool.Sumbool <> sumbool_of_bool def
+R1749:1753 Coq.ZArith.BinInt Z geb def
+R1755:1755 riscv <> l:32 var
+R1757:1757 riscv <> n:30 var
+R1821:1829 riscv <> sail_mask def
+R1843:1846 riscv_types <> bits def
+R1834:1835 bbv.HexNotationWord <> :::'''b'_x not
+R1831:1831 riscv <> n:30 var
+R1811:1814 riscv_types <> bits def
+R1816:1816 riscv <> n:30 var
+binder 1805:1807 <> one:34
+R1859:1864 Sail.Operators_mwords <> shiftl def
+R1895:1895 riscv <> i:31 var
+R1867:1873 Sail.Operators_mwords <> sub_vec def
+R1890:1892 riscv <> one:34 var
+R1876:1881 Sail.Operators_mwords <> shiftl def
+R1887:1887 riscv <> l:32 var
+R1883:1885 riscv <> one:34 var
+R1765:1770 Sail.Operators_mwords <> shiftl def
+R1786:1786 riscv <> i:31 var
+R1773:1781 riscv <> sail_ones def
+R1783:1783 riscv <> n:30 var
+def 1910:1913 <> EXTS
+R1920:1920 Coq.Numbers.BinNums <> Z ind
+binder 1916:1916 <> n:35
+R1928:1928 Coq.Numbers.BinNums <> Z ind
+binder 1924:1924 <> m:36
+R1936:1940 Sail.Values <> mword def
+R1942:1942 riscv <> n:35 var
+binder 1932:1932 <> v:37
+R1947:1955 Sail.Values <> ArithFact class
+R1959:1963 Coq.ZArith.BinInt <> ::Z_scope:x_'>=?'_x not
+R1958:1958 riscv <> m:36 var
+R1964:1964 riscv <> n:35 var
+binder 1947:1965 <> H:38
+R1970:1974 Sail.Values <> mword def
+R1976:1976 riscv <> m:36 var
+R1981:1991 Sail.Operators_mwords <> sign_extend def
+R1995:1995 riscv <> m:36 var
+R1993:1993 riscv <> v:37 var
+def 2010:2013 <> EXTZ
+R2020:2020 Coq.Numbers.BinNums <> Z ind
+binder 2016:2016 <> n:39
+R2028:2028 Coq.Numbers.BinNums <> Z ind
+binder 2024:2024 <> m:40
+R2036:2040 Sail.Values <> mword def
+R2042:2042 riscv <> n:39 var
+binder 2032:2032 <> v:41
+R2047:2055 Sail.Values <> ArithFact class
+R2059:2063 Coq.ZArith.BinInt <> ::Z_scope:x_'>=?'_x not
+R2058:2058 riscv <> m:40 var
+R2064:2064 riscv <> n:39 var
+binder 2047:2065 <> H:42
+R2070:2074 Sail.Values <> mword def
+R2076:2076 riscv <> m:40 var
+R2081:2091 Sail.Operators_mwords <> zero_extend def
+R2095:2095 riscv <> m:40 var
+R2093:2093 riscv <> v:41 var
+def 2110:2117 <> zero_reg
+R2121:2127 riscv_types <> regtype def
+R2132:2135 riscv <> EXTZ def
+R2150:2154 Sail.Values <> mword def
+R2141:2142 bbv.HexNotationWord <> :::'Ox'_x not
+R2172:2179 riscv <> zero_reg def
+def 2200:2214 <> regval_from_reg
+R2221:2225 Sail.Values <> mword def
+binder 2217:2217 <> r:43
+R2233:2237 Sail.Values <> mword def
+R2245:2245 riscv <> r:43 var
+def 2260:2274 <> regval_into_reg
+R2281:2285 Sail.Values <> mword def
+binder 2277:2277 <> v:44
+R2293:2297 Sail.Values <> mword def
+R2305:2305 riscv <> v:44 var
+def 2320:2321 <> rX
+R2328:2328 Coq.Numbers.BinNums <> Z ind
+binder 2324:2324 <> r:45
+R2333:2341 Sail.Values <> ArithFact class
+R2344:2344 Coq.Init.Datatypes <> ::bool_scope:x_'&&'_x not
+R2352:2357 Coq.Init.Datatypes <> ::bool_scope:x_'&&'_x not
+R2365:2365 Coq.Init.Datatypes <> ::bool_scope:x_'&&'_x not
+R2346:2350 Coq.ZArith.BinInt <> ::Z_scope:x_'<=?'_x not
+R2351:2351 riscv <> r:45 var
+R2359:2362 Coq.ZArith.BinInt <> ::Z_scope:x_'<?'_x not
+R2358:2358 riscv <> r:45 var
+binder 2333:2366 <> H:46
+R2371:2371 riscv_types <> M def
+R2374:2378 Sail.Values <> mword def
+R2403:2403 riscv <> r:45 var
+binder 2394:2398 <> l__32:47
+R2411:2411 Sail.Prompt_monad <> :::x_'>>='_x not
+R5981:5986 Sail.Prompt_monad <> :::x_'>>='_x not
+R2415:2429 Coq.Bool.Sumbool <> sumbool_of_bool def
+R2432:2436 Coq.ZArith.BinInt Z eqb def
+R2438:2442 riscv <> l__32:47 var
+R2481:2495 Coq.Bool.Sumbool <> sumbool_of_bool def
+R2498:2502 Coq.ZArith.BinInt Z eqb def
+R2504:2508 riscv <> l__32:47 var
+R2582:2596 Coq.Bool.Sumbool <> sumbool_of_bool def
+R2599:2603 Coq.ZArith.BinInt Z eqb def
+R2605:2609 riscv <> l__32:47 var
+R2683:2697 Coq.Bool.Sumbool <> sumbool_of_bool def
+R2700:2704 Coq.ZArith.BinInt Z eqb def
+R2706:2710 riscv <> l__32:47 var
+R2784:2798 Coq.Bool.Sumbool <> sumbool_of_bool def
+R2801:2805 Coq.ZArith.BinInt Z eqb def
+R2807:2811 riscv <> l__32:47 var
+R2885:2899 Coq.Bool.Sumbool <> sumbool_of_bool def
+R2902:2906 Coq.ZArith.BinInt Z eqb def
+R2908:2912 riscv <> l__32:47 var
+R2986:3000 Coq.Bool.Sumbool <> sumbool_of_bool def
+R3003:3007 Coq.ZArith.BinInt Z eqb def
+R3009:3013 riscv <> l__32:47 var
+R3087:3101 Coq.Bool.Sumbool <> sumbool_of_bool def
+R3104:3108 Coq.ZArith.BinInt Z eqb def
+R3110:3114 riscv <> l__32:47 var
+R3188:3202 Coq.Bool.Sumbool <> sumbool_of_bool def
+R3205:3209 Coq.ZArith.BinInt Z eqb def
+R3211:3215 riscv <> l__32:47 var
+R3289:3303 Coq.Bool.Sumbool <> sumbool_of_bool def
+R3306:3310 Coq.ZArith.BinInt Z eqb def
+R3312:3316 riscv <> l__32:47 var
+R3390:3404 Coq.Bool.Sumbool <> sumbool_of_bool def
+R3407:3411 Coq.ZArith.BinInt Z eqb def
+R3413:3417 riscv <> l__32:47 var
+R3505:3519 Coq.Bool.Sumbool <> sumbool_of_bool def
+R3522:3526 Coq.ZArith.BinInt Z eqb def
+R3528:3532 riscv <> l__32:47 var
+R3620:3634 Coq.Bool.Sumbool <> sumbool_of_bool def
+R3637:3641 Coq.ZArith.BinInt Z eqb def
+R3643:3647 riscv <> l__32:47 var
+R3735:3749 Coq.Bool.Sumbool <> sumbool_of_bool def
+R3752:3756 Coq.ZArith.BinInt Z eqb def
+R3758:3762 riscv <> l__32:47 var
+R3850:3864 Coq.Bool.Sumbool <> sumbool_of_bool def
+R3867:3871 Coq.ZArith.BinInt Z eqb def
+R3873:3877 riscv <> l__32:47 var
+R3965:3979 Coq.Bool.Sumbool <> sumbool_of_bool def
+R3982:3986 Coq.ZArith.BinInt Z eqb def
+R3988:3992 riscv <> l__32:47 var
+R4080:4094 Coq.Bool.Sumbool <> sumbool_of_bool def
+R4097:4101 Coq.ZArith.BinInt Z eqb def
+R4103:4107 riscv <> l__32:47 var
+R4195:4209 Coq.Bool.Sumbool <> sumbool_of_bool def
+R4212:4216 Coq.ZArith.BinInt Z eqb def
+R4218:4222 riscv <> l__32:47 var
+R4310:4324 Coq.Bool.Sumbool <> sumbool_of_bool def
+R4327:4331 Coq.ZArith.BinInt Z eqb def
+R4333:4337 riscv <> l__32:47 var
+R4425:4439 Coq.Bool.Sumbool <> sumbool_of_bool def
+R4442:4446 Coq.ZArith.BinInt Z eqb def
+R4448:4452 riscv <> l__32:47 var
+R4540:4554 Coq.Bool.Sumbool <> sumbool_of_bool def
+R4557:4561 Coq.ZArith.BinInt Z eqb def
+R4563:4567 riscv <> l__32:47 var
+R4655:4669 Coq.Bool.Sumbool <> sumbool_of_bool def
+R4672:4676 Coq.ZArith.BinInt Z eqb def
+R4678:4682 riscv <> l__32:47 var
+R4770:4784 Coq.Bool.Sumbool <> sumbool_of_bool def
+R4787:4791 Coq.ZArith.BinInt Z eqb def
+R4793:4797 riscv <> l__32:47 var
+R4885:4899 Coq.Bool.Sumbool <> sumbool_of_bool def
+R4902:4906 Coq.ZArith.BinInt Z eqb def
+R4908:4912 riscv <> l__32:47 var
+R5000:5014 Coq.Bool.Sumbool <> sumbool_of_bool def
+R5017:5021 Coq.ZArith.BinInt Z eqb def
+R5023:5027 riscv <> l__32:47 var
+R5115:5129 Coq.Bool.Sumbool <> sumbool_of_bool def
+R5132:5136 Coq.ZArith.BinInt Z eqb def
+R5138:5142 riscv <> l__32:47 var
+R5230:5244 Coq.Bool.Sumbool <> sumbool_of_bool def
+R5247:5251 Coq.ZArith.BinInt Z eqb def
+R5253:5257 riscv <> l__32:47 var
+R5345:5359 Coq.Bool.Sumbool <> sumbool_of_bool def
+R5362:5366 Coq.ZArith.BinInt Z eqb def
+R5368:5372 riscv <> l__32:47 var
+R5460:5474 Coq.Bool.Sumbool <> sumbool_of_bool def
+R5477:5481 Coq.ZArith.BinInt Z eqb def
+R5483:5487 riscv <> l__32:47 var
+R5575:5589 Coq.Bool.Sumbool <> sumbool_of_bool def
+R5592:5596 Coq.ZArith.BinInt Z eqb def
+R5598:5602 riscv <> l__32:47 var
+R5690:5704 Coq.Bool.Sumbool <> sumbool_of_bool def
+R5707:5711 Coq.ZArith.BinInt Z eqb def
+R5713:5717 riscv <> l__32:47 var
+R5805:5819 Coq.Bool.Sumbool <> sumbool_of_bool def
+R5822:5826 Coq.ZArith.BinInt Z eqb def
+R5828:5832 riscv <> l__32:47 var
+R5960:5964 Sail.Prompt_monad <> :::x_'>>='_x not
+R5917:5927 Sail.Prompt_monad <> assert_exp' def
+R5929:5933 Coq.Init.Datatypes <> false constr
+R5974:5977 Sail.Prompt_monad <> exit def
+R5979:5980 Coq.Init.Datatypes <> tt constr
+R5895:5895 riscv_types <> M def
+R5898:5902 Sail.Values <> mword def
+R5872:5872 riscv_types <> M def
+R5875:5879 Sail.Values <> mword def
+R5851:5858 Sail.Prompt_monad <> read_reg def
+R5860:5866 riscv_types <> x31_ref def
+R5780:5780 riscv_types <> M def
+R5783:5787 Sail.Values <> mword def
+R5757:5757 riscv_types <> M def
+R5760:5764 Sail.Values <> mword def
+R5736:5743 Sail.Prompt_monad <> read_reg def
+R5745:5751 riscv_types <> x30_ref def
+R5665:5665 riscv_types <> M def
+R5668:5672 Sail.Values <> mword def
+R5642:5642 riscv_types <> M def
+R5645:5649 Sail.Values <> mword def
+R5621:5628 Sail.Prompt_monad <> read_reg def
+R5630:5636 riscv_types <> x29_ref def
+R5550:5550 riscv_types <> M def
+R5553:5557 Sail.Values <> mword def
+R5527:5527 riscv_types <> M def
+R5530:5534 Sail.Values <> mword def
+R5506:5513 Sail.Prompt_monad <> read_reg def
+R5515:5521 riscv_types <> x28_ref def
+R5435:5435 riscv_types <> M def
+R5438:5442 Sail.Values <> mword def
+R5412:5412 riscv_types <> M def
+R5415:5419 Sail.Values <> mword def
+R5391:5398 Sail.Prompt_monad <> read_reg def
+R5400:5406 riscv_types <> x27_ref def
+R5320:5320 riscv_types <> M def
+R5323:5327 Sail.Values <> mword def
+R5297:5297 riscv_types <> M def
+R5300:5304 Sail.Values <> mword def
+R5276:5283 Sail.Prompt_monad <> read_reg def
+R5285:5291 riscv_types <> x26_ref def
+R5205:5205 riscv_types <> M def
+R5208:5212 Sail.Values <> mword def
+R5182:5182 riscv_types <> M def
+R5185:5189 Sail.Values <> mword def
+R5161:5168 Sail.Prompt_monad <> read_reg def
+R5170:5176 riscv_types <> x25_ref def
+R5090:5090 riscv_types <> M def
+R5093:5097 Sail.Values <> mword def
+R5067:5067 riscv_types <> M def
+R5070:5074 Sail.Values <> mword def
+R5046:5053 Sail.Prompt_monad <> read_reg def
+R5055:5061 riscv_types <> x24_ref def
+R4975:4975 riscv_types <> M def
+R4978:4982 Sail.Values <> mword def
+R4952:4952 riscv_types <> M def
+R4955:4959 Sail.Values <> mword def
+R4931:4938 Sail.Prompt_monad <> read_reg def
+R4940:4946 riscv_types <> x23_ref def
+R4860:4860 riscv_types <> M def
+R4863:4867 Sail.Values <> mword def
+R4837:4837 riscv_types <> M def
+R4840:4844 Sail.Values <> mword def
+R4816:4823 Sail.Prompt_monad <> read_reg def
+R4825:4831 riscv_types <> x22_ref def
+R4745:4745 riscv_types <> M def
+R4748:4752 Sail.Values <> mword def
+R4722:4722 riscv_types <> M def
+R4725:4729 Sail.Values <> mword def
+R4701:4708 Sail.Prompt_monad <> read_reg def
+R4710:4716 riscv_types <> x21_ref def
+R4630:4630 riscv_types <> M def
+R4633:4637 Sail.Values <> mword def
+R4607:4607 riscv_types <> M def
+R4610:4614 Sail.Values <> mword def
+R4586:4593 Sail.Prompt_monad <> read_reg def
+R4595:4601 riscv_types <> x20_ref def
+R4515:4515 riscv_types <> M def
+R4518:4522 Sail.Values <> mword def
+R4492:4492 riscv_types <> M def
+R4495:4499 Sail.Values <> mword def
+R4471:4478 Sail.Prompt_monad <> read_reg def
+R4480:4486 riscv_types <> x19_ref def
+R4400:4400 riscv_types <> M def
+R4403:4407 Sail.Values <> mword def
+R4377:4377 riscv_types <> M def
+R4380:4384 Sail.Values <> mword def
+R4356:4363 Sail.Prompt_monad <> read_reg def
+R4365:4371 riscv_types <> x18_ref def
+R4285:4285 riscv_types <> M def
+R4288:4292 Sail.Values <> mword def
+R4262:4262 riscv_types <> M def
+R4265:4269 Sail.Values <> mword def
+R4241:4248 Sail.Prompt_monad <> read_reg def
+R4250:4256 riscv_types <> x17_ref def
+R4170:4170 riscv_types <> M def
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+R4147:4147 riscv_types <> M def
+R4150:4154 Sail.Values <> mword def
+R4126:4133 Sail.Prompt_monad <> read_reg def
+R4135:4141 riscv_types <> x16_ref def
+R4055:4055 riscv_types <> M def
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+R4032:4032 riscv_types <> M def
+R4035:4039 Sail.Values <> mword def
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+R3943:3947 Sail.Values <> mword def
+R3917:3917 riscv_types <> M def
+R3920:3924 Sail.Values <> mword def
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+R3905:3911 riscv_types <> x14_ref def
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+R3687:3687 riscv_types <> M def
+R3690:3694 Sail.Values <> mword def
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+R3575:3579 Sail.Values <> mword def
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+R3457:3457 riscv_types <> M def
+R3460:3464 Sail.Values <> mword def
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+R3348:3348 riscv_types <> M def
+R3351:3355 Sail.Values <> mword def
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+R3250:3254 Sail.Values <> mword def
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+R3236:3241 riscv_types <> x8_ref def
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+R3149:3153 Sail.Values <> mword def
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+R3048:3052 Sail.Values <> mword def
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+R2944:2944 riscv_types <> M def
+R2947:2951 Sail.Values <> mword def
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+R2933:2938 riscv_types <> x5_ref def
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+R2843:2843 riscv_types <> M def
+R2846:2850 Sail.Values <> mword def
+R2823:2830 Sail.Prompt_monad <> read_reg def
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+R2742:2742 riscv_types <> M def
+R2745:2749 Sail.Values <> mword def
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+R2644:2648 Sail.Values <> mword def
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+R2543:2547 Sail.Values <> mword def
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+R6490:6504 Coq.Bool.Sumbool <> sumbool_of_bool def
+R6507:6511 Coq.ZArith.BinInt Z eqb def
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+R6744:6748 Coq.ZArith.BinInt Z eqb def
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+R7207:7221 Coq.Bool.Sumbool <> sumbool_of_bool def
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+R7450:7464 Coq.Bool.Sumbool <> sumbool_of_bool def
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+R7531:7545 Coq.Bool.Sumbool <> sumbool_of_bool def
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+R7855:7869 Coq.Bool.Sumbool <> sumbool_of_bool def
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+R8341:8355 Coq.Bool.Sumbool <> sumbool_of_bool def
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+R8422:8436 Coq.Bool.Sumbool <> sumbool_of_bool def
+R8439:8443 Coq.ZArith.BinInt Z eqb def
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+R8503:8517 Coq.Bool.Sumbool <> sumbool_of_bool def
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+R8584:8598 Coq.Bool.Sumbool <> sumbool_of_bool def
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+R8665:8679 Coq.Bool.Sumbool <> sumbool_of_bool def
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+R8540:8548 Sail.Prompt_monad <> write_reg def
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+R8459:8467 Sail.Prompt_monad <> write_reg def
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+R8378:8386 Sail.Prompt_monad <> write_reg def
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+R8216:8224 Sail.Prompt_monad <> write_reg def
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+R8054:8062 Sail.Prompt_monad <> write_reg def
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+R7973:7981 Sail.Prompt_monad <> write_reg def
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+R7892:7900 Sail.Prompt_monad <> write_reg def
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+R7811:7819 Sail.Prompt_monad <> write_reg def
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+R7730:7738 Sail.Prompt_monad <> write_reg def
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+R7649:7657 Sail.Prompt_monad <> write_reg def
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+R7568:7576 Sail.Prompt_monad <> write_reg def
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+R7487:7495 Sail.Prompt_monad <> write_reg def
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+R7406:7414 Sail.Prompt_monad <> write_reg def
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+R7325:7333 Sail.Prompt_monad <> write_reg def
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+R7244:7252 Sail.Prompt_monad <> write_reg def
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+R7163:7171 Sail.Prompt_monad <> write_reg def
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+R7082:7090 Sail.Prompt_monad <> write_reg def
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+R7001:7009 Sail.Prompt_monad <> write_reg def
+R7019:7019 riscv <> v:52 var
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+R6921:6929 Sail.Prompt_monad <> write_reg def
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+R6842:6850 Sail.Prompt_monad <> write_reg def
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+R6763:6771 Sail.Prompt_monad <> write_reg def
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+R6684:6692 Sail.Prompt_monad <> write_reg def
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+R6605:6613 Sail.Prompt_monad <> write_reg def
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+R6526:6534 Sail.Prompt_monad <> write_reg def
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+R6447:6455 Sail.Prompt_monad <> write_reg def
+R6464:6464 riscv <> v:52 var
+R6457:6462 riscv_types <> x3_ref def
+R6390:6390 riscv_types <> M def
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+R6368:6376 Sail.Prompt_monad <> write_reg def
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+R6378:6383 riscv_types <> x2_ref def
+R6311:6311 riscv_types <> M def
+R6314:6317 Coq.Init.Datatypes <> unit ind
+R6289:6297 Sail.Prompt_monad <> write_reg def
+R6306:6306 riscv <> v:52 var
+R6299:6304 riscv_types <> x1_ref def
+R6230:6236 Sail.Prompt_monad <> returnm def
+R6238:6239 Coq.Init.Datatypes <> tt constr
+def 8837:8843 <> rX_bits
+R8850:8854 Sail.Values <> mword def
+binder 8846:8846 <> i:54
+R8861:8861 riscv_types <> M def
+R8864:8868 Sail.Values <> mword def
+R8903:8903 riscv_types <> M def
+R8906:8910 Sail.Values <> mword def
+R8878:8879 riscv <> rX def
+R8882:8887 Coq.Init.Specif <> projT1 def
+R8890:8893 Sail.Operators_mwords <> uint def
+R8895:8895 riscv <> i:54 var
+def 8929:8935 <> wX_bits
+R8942:8946 Sail.Values <> mword def
+binder 8938:8938 <> i:55
+R8959:8963 Sail.Values <> mword def
+binder 8952:8955 <> data:56
+R8971:8971 riscv_types <> M def
+R8974:8977 Coq.Init.Datatypes <> unit ind
+R9017:9017 riscv_types <> M def
+R9020:9023 Coq.Init.Datatypes <> unit ind
+R8987:8988 riscv <> wX def
+R9008:9011 riscv <> data:56 var
+R8991:8996 Coq.Init.Specif <> projT1 def
+R8999:9002 Sail.Operators_mwords <> uint def
+R9004:9004 riscv <> i:55 var
+def 9039:9050 <> reg_name_abi
+R9057:9061 Sail.Values <> mword def
+binder 9053:9053 <> r:57
+R9068:9068 riscv_types <> M def
+R9071:9076 Coq.Strings.String <> string ind
+R9097:9097 riscv <> r:57 var
+binder 9089:9092 <> b__0:58
+R11305:11305 riscv_types <> M def
+R11308:11313 Coq.Strings.String <> string ind
+R9109:9114 Sail.Operators_mwords <> eq_vec def
+R9135:9139 Sail.Values <> mword def
+R9122:9123 bbv.HexNotationWord <> :::'''b'_x not
+R9116:9119 riscv <> b__0:58 var
+R9176:9181 Sail.Operators_mwords <> eq_vec def
+R9202:9206 Sail.Values <> mword def
+R9189:9190 bbv.HexNotationWord <> :::'''b'_x not
+R9183:9186 riscv <> b__0:58 var
+R9241:9246 Sail.Operators_mwords <> eq_vec def
+R9267:9271 Sail.Values <> mword def
+R9254:9255 bbv.HexNotationWord <> :::'''b'_x not
+R9248:9251 riscv <> b__0:58 var
+R9306:9311 Sail.Operators_mwords <> eq_vec def
+R9332:9336 Sail.Values <> mword def
+R9319:9320 bbv.HexNotationWord <> :::'''b'_x not
+R9313:9316 riscv <> b__0:58 var
+R9371:9376 Sail.Operators_mwords <> eq_vec def
+R9397:9401 Sail.Values <> mword def
+R9384:9385 bbv.HexNotationWord <> :::'''b'_x not
+R9378:9381 riscv <> b__0:58 var
+R9436:9441 Sail.Operators_mwords <> eq_vec def
+R9462:9466 Sail.Values <> mword def
+R9449:9450 bbv.HexNotationWord <> :::'''b'_x not
+R9443:9446 riscv <> b__0:58 var
+R9501:9506 Sail.Operators_mwords <> eq_vec def
+R9527:9531 Sail.Values <> mword def
+R9514:9515 bbv.HexNotationWord <> :::'''b'_x not
+R9508:9511 riscv <> b__0:58 var
+R9566:9571 Sail.Operators_mwords <> eq_vec def
+R9592:9596 Sail.Values <> mword def
+R9579:9580 bbv.HexNotationWord <> :::'''b'_x not
+R9573:9576 riscv <> b__0:58 var
+R9631:9636 Sail.Operators_mwords <> eq_vec def
+R9657:9661 Sail.Values <> mword def
+R9644:9645 bbv.HexNotationWord <> :::'''b'_x not
+R9638:9641 riscv <> b__0:58 var
+R9696:9701 Sail.Operators_mwords <> eq_vec def
+R9722:9726 Sail.Values <> mword def
+R9709:9710 bbv.HexNotationWord <> :::'''b'_x not
+R9703:9706 riscv <> b__0:58 var
+R9761:9766 Sail.Operators_mwords <> eq_vec def
+R9787:9791 Sail.Values <> mword def
+R9774:9775 bbv.HexNotationWord <> :::'''b'_x not
+R9768:9771 riscv <> b__0:58 var
+R9826:9831 Sail.Operators_mwords <> eq_vec def
+R9852:9856 Sail.Values <> mword def
+R9839:9840 bbv.HexNotationWord <> :::'''b'_x not
+R9833:9836 riscv <> b__0:58 var
+R9891:9896 Sail.Operators_mwords <> eq_vec def
+R9917:9921 Sail.Values <> mword def
+R9904:9905 bbv.HexNotationWord <> :::'''b'_x not
+R9898:9901 riscv <> b__0:58 var
+R9956:9961 Sail.Operators_mwords <> eq_vec def
+R9982:9986 Sail.Values <> mword def
+R9969:9970 bbv.HexNotationWord <> :::'''b'_x not
+R9963:9966 riscv <> b__0:58 var
+R10021:10026 Sail.Operators_mwords <> eq_vec def
+R10047:10051 Sail.Values <> mword def
+R10034:10035 bbv.HexNotationWord <> :::'''b'_x not
+R10028:10031 riscv <> b__0:58 var
+R10086:10091 Sail.Operators_mwords <> eq_vec def
+R10112:10116 Sail.Values <> mword def
+R10099:10100 bbv.HexNotationWord <> :::'''b'_x not
+R10093:10096 riscv <> b__0:58 var
+R10151:10156 Sail.Operators_mwords <> eq_vec def
+R10177:10181 Sail.Values <> mword def
+R10164:10165 bbv.HexNotationWord <> :::'''b'_x not
+R10158:10161 riscv <> b__0:58 var
+R10216:10221 Sail.Operators_mwords <> eq_vec def
+R10242:10246 Sail.Values <> mword def
+R10229:10230 bbv.HexNotationWord <> :::'''b'_x not
+R10223:10226 riscv <> b__0:58 var
+R10281:10286 Sail.Operators_mwords <> eq_vec def
+R10307:10311 Sail.Values <> mword def
+R10294:10295 bbv.HexNotationWord <> :::'''b'_x not
+R10288:10291 riscv <> b__0:58 var
+R10346:10351 Sail.Operators_mwords <> eq_vec def
+R10372:10376 Sail.Values <> mword def
+R10359:10360 bbv.HexNotationWord <> :::'''b'_x not
+R10353:10356 riscv <> b__0:58 var
+R10411:10416 Sail.Operators_mwords <> eq_vec def
+R10437:10441 Sail.Values <> mword def
+R10424:10425 bbv.HexNotationWord <> :::'''b'_x not
+R10418:10421 riscv <> b__0:58 var
+R10476:10481 Sail.Operators_mwords <> eq_vec def
+R10502:10506 Sail.Values <> mword def
+R10489:10490 bbv.HexNotationWord <> :::'''b'_x not
+R10483:10486 riscv <> b__0:58 var
+R10541:10546 Sail.Operators_mwords <> eq_vec def
+R10567:10571 Sail.Values <> mword def
+R10554:10555 bbv.HexNotationWord <> :::'''b'_x not
+R10548:10551 riscv <> b__0:58 var
+R10606:10611 Sail.Operators_mwords <> eq_vec def
+R10632:10636 Sail.Values <> mword def
+R10619:10620 bbv.HexNotationWord <> :::'''b'_x not
+R10613:10616 riscv <> b__0:58 var
+R10671:10676 Sail.Operators_mwords <> eq_vec def
+R10697:10701 Sail.Values <> mword def
+R10684:10685 bbv.HexNotationWord <> :::'''b'_x not
+R10678:10681 riscv <> b__0:58 var
+R10736:10741 Sail.Operators_mwords <> eq_vec def
+R10762:10766 Sail.Values <> mword def
+R10749:10750 bbv.HexNotationWord <> :::'''b'_x not
+R10743:10746 riscv <> b__0:58 var
+R10801:10806 Sail.Operators_mwords <> eq_vec def
+R10827:10831 Sail.Values <> mword def
+R10814:10815 bbv.HexNotationWord <> :::'''b'_x not
+R10808:10811 riscv <> b__0:58 var
+R10867:10872 Sail.Operators_mwords <> eq_vec def
+R10893:10897 Sail.Values <> mword def
+R10880:10881 bbv.HexNotationWord <> :::'''b'_x not
+R10874:10877 riscv <> b__0:58 var
+R10933:10938 Sail.Operators_mwords <> eq_vec def
+R10959:10963 Sail.Values <> mword def
+R10946:10947 bbv.HexNotationWord <> :::'''b'_x not
+R10940:10943 riscv <> b__0:58 var
+R10998:11003 Sail.Operators_mwords <> eq_vec def
+R11024:11028 Sail.Values <> mword def
+R11011:11012 bbv.HexNotationWord <> :::'''b'_x not
+R11005:11008 riscv <> b__0:58 var
+R11063:11068 Sail.Operators_mwords <> eq_vec def
+R11089:11093 Sail.Values <> mword def
+R11076:11077 bbv.HexNotationWord <> :::'''b'_x not
+R11070:11073 riscv <> b__0:58 var
+R11128:11133 Sail.Operators_mwords <> eq_vec def
+R11154:11158 Sail.Values <> mword def
+R11141:11142 bbv.HexNotationWord <> :::'''b'_x not
+R11135:11138 riscv <> b__0:58 var
+R11270:11274 Sail.Prompt_monad <> :::x_'>>='_x not
+R11196:11206 Sail.Prompt_monad <> assert_exp' def
+R11208:11212 Coq.Init.Datatypes <> false constr
+R11290:11293 Sail.Prompt_monad <> exit def
+R11295:11296 Coq.Init.Datatypes <> tt constr
+R11168:11174 Sail.Prompt_monad <> returnm def
+R11103:11109 Sail.Prompt_monad <> returnm def
+R11038:11044 Sail.Prompt_monad <> returnm def
+R10973:10979 Sail.Prompt_monad <> returnm def
+R10907:10913 Sail.Prompt_monad <> returnm def
+R10841:10847 Sail.Prompt_monad <> returnm def
+R10776:10782 Sail.Prompt_monad <> returnm def
+R10711:10717 Sail.Prompt_monad <> returnm def
+R10646:10652 Sail.Prompt_monad <> returnm def
+R10581:10587 Sail.Prompt_monad <> returnm def
+R10516:10522 Sail.Prompt_monad <> returnm def
+R10451:10457 Sail.Prompt_monad <> returnm def
+R10386:10392 Sail.Prompt_monad <> returnm def
+R10321:10327 Sail.Prompt_monad <> returnm def
+R10256:10262 Sail.Prompt_monad <> returnm def
+R10191:10197 Sail.Prompt_monad <> returnm def
+R10126:10132 Sail.Prompt_monad <> returnm def
+R10061:10067 Sail.Prompt_monad <> returnm def
+R9996:10002 Sail.Prompt_monad <> returnm def
+R9931:9937 Sail.Prompt_monad <> returnm def
+R9866:9872 Sail.Prompt_monad <> returnm def
+R9801:9807 Sail.Prompt_monad <> returnm def
+R9736:9742 Sail.Prompt_monad <> returnm def
+R9671:9677 Sail.Prompt_monad <> returnm def
+R9606:9612 Sail.Prompt_monad <> returnm def
+R9541:9547 Sail.Prompt_monad <> returnm def
+R9476:9482 Sail.Prompt_monad <> returnm def
+R9411:9417 Sail.Prompt_monad <> returnm def
+R9346:9352 Sail.Prompt_monad <> returnm def
+R9281:9287 Sail.Prompt_monad <> returnm def
+R9216:9222 Sail.Prompt_monad <> returnm def
+R9149:9155 Sail.Prompt_monad <> returnm def
+def 11329:11342 <> init_base_regs
+R11346:11347 Coq.Init.Datatypes <> tt constr
+R11351:11354 Coq.Init.Datatypes <> unit ind
+binder 11346:11354 <> pat:59
+R11359:11359 riscv_types <> M def
+R11362:11365 Coq.Init.Datatypes <> unit ind
+R12382:12382 riscv_types <> M def
+R12385:12388 Coq.Init.Datatypes <> unit ind
+R12348:12351 Sail.Prompt_monad <> :::x_'>>'_x not
+R12315:12321 Sail.Prompt_monad <> :::x_'>>'_x not
+R12282:12288 Sail.Prompt_monad <> :::x_'>>'_x not
+R12249:12255 Sail.Prompt_monad <> :::x_'>>'_x not
+R12216:12222 Sail.Prompt_monad <> :::x_'>>'_x not
+R12183:12189 Sail.Prompt_monad <> :::x_'>>'_x not
+R12150:12156 Sail.Prompt_monad <> :::x_'>>'_x not
+R12117:12123 Sail.Prompt_monad <> :::x_'>>'_x not
+R12084:12090 Sail.Prompt_monad <> :::x_'>>'_x not
+R12051:12057 Sail.Prompt_monad <> :::x_'>>'_x not
+R12018:12024 Sail.Prompt_monad <> :::x_'>>'_x not
+R11985:11991 Sail.Prompt_monad <> :::x_'>>'_x not
+R11952:11958 Sail.Prompt_monad <> :::x_'>>'_x not
+R11919:11925 Sail.Prompt_monad <> :::x_'>>'_x not
+R11886:11892 Sail.Prompt_monad <> :::x_'>>'_x not
+R11853:11859 Sail.Prompt_monad <> :::x_'>>'_x not
+R11820:11826 Sail.Prompt_monad <> :::x_'>>'_x not
+R11787:11793 Sail.Prompt_monad <> :::x_'>>'_x not
+R11754:11760 Sail.Prompt_monad <> :::x_'>>'_x not
+R11721:11727 Sail.Prompt_monad <> :::x_'>>'_x not
+R11688:11694 Sail.Prompt_monad <> :::x_'>>'_x not
+R11655:11661 Sail.Prompt_monad <> :::x_'>>'_x not
+R11623:11629 Sail.Prompt_monad <> :::x_'>>'_x not
+R11591:11597 Sail.Prompt_monad <> :::x_'>>'_x not
+R11559:11565 Sail.Prompt_monad <> :::x_'>>'_x not
+R11527:11533 Sail.Prompt_monad <> :::x_'>>'_x not
+R11495:11501 Sail.Prompt_monad <> :::x_'>>'_x not
+R11463:11469 Sail.Prompt_monad <> :::x_'>>'_x not
+R11431:11437 Sail.Prompt_monad <> :::x_'>>'_x not
+R11399:11405 Sail.Prompt_monad <> :::x_'>>'_x not
+R11374:11382 Sail.Prompt_monad <> write_reg def
+R11391:11398 riscv <> zero_reg def
+R11384:11389 riscv_types <> x1_ref def
+R11406:11414 Sail.Prompt_monad <> write_reg def
+R11423:11430 riscv <> zero_reg def
+R11416:11421 riscv_types <> x2_ref def
+R11438:11446 Sail.Prompt_monad <> write_reg def
+R11455:11462 riscv <> zero_reg def
+R11448:11453 riscv_types <> x3_ref def
+R11470:11478 Sail.Prompt_monad <> write_reg def
+R11487:11494 riscv <> zero_reg def
+R11480:11485 riscv_types <> x4_ref def
+R11502:11510 Sail.Prompt_monad <> write_reg def
+R11519:11526 riscv <> zero_reg def
+R11512:11517 riscv_types <> x5_ref def
+R11534:11542 Sail.Prompt_monad <> write_reg def
+R11551:11558 riscv <> zero_reg def
+R11544:11549 riscv_types <> x6_ref def
+R11566:11574 Sail.Prompt_monad <> write_reg def
+R11583:11590 riscv <> zero_reg def
+R11576:11581 riscv_types <> x7_ref def
+R11598:11606 Sail.Prompt_monad <> write_reg def
+R11615:11622 riscv <> zero_reg def
+R11608:11613 riscv_types <> x8_ref def
+R11630:11638 Sail.Prompt_monad <> write_reg def
+R11647:11654 riscv <> zero_reg def
+R11640:11645 riscv_types <> x9_ref def
+R11662:11670 Sail.Prompt_monad <> write_reg def
+R11680:11687 riscv <> zero_reg def
+R11672:11678 riscv_types <> x10_ref def
+R11695:11703 Sail.Prompt_monad <> write_reg def
+R11713:11720 riscv <> zero_reg def
+R11705:11711 riscv_types <> x11_ref def
+R11728:11736 Sail.Prompt_monad <> write_reg def
+R11746:11753 riscv <> zero_reg def
+R11738:11744 riscv_types <> x12_ref def
+R11761:11769 Sail.Prompt_monad <> write_reg def
+R11779:11786 riscv <> zero_reg def
+R11771:11777 riscv_types <> x13_ref def
+R11794:11802 Sail.Prompt_monad <> write_reg def
+R11812:11819 riscv <> zero_reg def
+R11804:11810 riscv_types <> x14_ref def
+R11827:11835 Sail.Prompt_monad <> write_reg def
+R11845:11852 riscv <> zero_reg def
+R11837:11843 riscv_types <> x15_ref def
+R11860:11868 Sail.Prompt_monad <> write_reg def
+R11878:11885 riscv <> zero_reg def
+R11870:11876 riscv_types <> x16_ref def
+R11893:11901 Sail.Prompt_monad <> write_reg def
+R11911:11918 riscv <> zero_reg def
+R11903:11909 riscv_types <> x17_ref def
+R11926:11934 Sail.Prompt_monad <> write_reg def
+R11944:11951 riscv <> zero_reg def
+R11936:11942 riscv_types <> x18_ref def
+R11959:11967 Sail.Prompt_monad <> write_reg def
+R11977:11984 riscv <> zero_reg def
+R11969:11975 riscv_types <> x19_ref def
+R11992:12000 Sail.Prompt_monad <> write_reg def
+R12010:12017 riscv <> zero_reg def
+R12002:12008 riscv_types <> x20_ref def
+R12025:12033 Sail.Prompt_monad <> write_reg def
+R12043:12050 riscv <> zero_reg def
+R12035:12041 riscv_types <> x21_ref def
+R12058:12066 Sail.Prompt_monad <> write_reg def
+R12076:12083 riscv <> zero_reg def
+R12068:12074 riscv_types <> x22_ref def
+R12091:12099 Sail.Prompt_monad <> write_reg def
+R12109:12116 riscv <> zero_reg def
+R12101:12107 riscv_types <> x23_ref def
+R12124:12132 Sail.Prompt_monad <> write_reg def
+R12142:12149 riscv <> zero_reg def
+R12134:12140 riscv_types <> x24_ref def
+R12157:12165 Sail.Prompt_monad <> write_reg def
+R12175:12182 riscv <> zero_reg def
+R12167:12173 riscv_types <> x25_ref def
+R12190:12198 Sail.Prompt_monad <> write_reg def
+R12208:12215 riscv <> zero_reg def
+R12200:12206 riscv_types <> x26_ref def
+R12223:12231 Sail.Prompt_monad <> write_reg def
+R12241:12248 riscv <> zero_reg def
+R12233:12239 riscv_types <> x27_ref def
+R12256:12264 Sail.Prompt_monad <> write_reg def
+R12274:12281 riscv <> zero_reg def
+R12266:12272 riscv_types <> x28_ref def
+R12289:12297 Sail.Prompt_monad <> write_reg def
+R12307:12314 riscv <> zero_reg def
+R12299:12305 riscv_types <> x29_ref def
+R12322:12330 Sail.Prompt_monad <> write_reg def
+R12340:12347 riscv <> zero_reg def
+R12332:12338 riscv_types <> x30_ref def
+R12352:12360 Sail.Prompt_monad <> write_reg def
+R12370:12377 riscv <> zero_reg def
+R12362:12368 riscv_types <> x31_ref def
+def 12404:12419 <> initial_regstate
+R12423:12430 riscv_types <> regstate rec
+R12438:12440 riscv_types <> x31 proj
+R12438:12440 riscv_types <> x31 proj
+R12485:12487 riscv_types <> x30 proj
+R12532:12534 riscv_types <> x29 proj
+R12579:12581 riscv_types <> x28 proj
+R12626:12628 riscv_types <> x27 proj
+R12673:12675 riscv_types <> x26 proj
+R12720:12722 riscv_types <> x25 proj
+R12767:12769 riscv_types <> x24 proj
+R12814:12816 riscv_types <> x23 proj
+R12861:12863 riscv_types <> x22 proj
+R12908:12910 riscv_types <> x21 proj
+R12955:12957 riscv_types <> x20 proj
+R13002:13004 riscv_types <> x19 proj
+R13049:13051 riscv_types <> x18 proj
+R13096:13098 riscv_types <> x17 proj
+R13143:13145 riscv_types <> x16 proj
+R13190:13192 riscv_types <> x15 proj
+R13237:13239 riscv_types <> x14 proj
+R13284:13286 riscv_types <> x13 proj
+R13331:13333 riscv_types <> x12 proj
+R13378:13380 riscv_types <> x11 proj
+R13425:13427 riscv_types <> x10 proj
+R13472:13473 riscv_types <> x9 proj
+R13518:13519 riscv_types <> x8 proj
+R13564:13565 riscv_types <> x7 proj
+R13610:13611 riscv_types <> x6 proj
+R13656:13657 riscv_types <> x5 proj
+R13702:13703 riscv_types <> x4 proj
+R13748:13749 riscv_types <> x3 proj
+R13794:13795 riscv_types <> x2 proj
+R13840:13841 riscv_types <> x1 proj
+R13886:13893 riscv_types <> instbits proj
+R13938:13943 riscv_types <> nextPC proj
+R13988:13989 riscv_types <> PC proj
+R12470:12474 Sail.Values <> mword def
+R12446:12447 bbv.HexNotationWord <> :::'Ox'_x not
+R12517:12521 Sail.Values <> mword def
+R12493:12494 bbv.HexNotationWord <> :::'Ox'_x not
+R12564:12568 Sail.Values <> mword def
+R12540:12541 bbv.HexNotationWord <> :::'Ox'_x not
+R12611:12615 Sail.Values <> mword def
+R12587:12588 bbv.HexNotationWord <> :::'Ox'_x not
+R12658:12662 Sail.Values <> mword def
+R12634:12635 bbv.HexNotationWord <> :::'Ox'_x not
+R12705:12709 Sail.Values <> mword def
+R12681:12682 bbv.HexNotationWord <> :::'Ox'_x not
+R12752:12756 Sail.Values <> mword def
+R12728:12729 bbv.HexNotationWord <> :::'Ox'_x not
+R12799:12803 Sail.Values <> mword def
+R12775:12776 bbv.HexNotationWord <> :::'Ox'_x not
+R12846:12850 Sail.Values <> mword def
+R12822:12823 bbv.HexNotationWord <> :::'Ox'_x not
+R12893:12897 Sail.Values <> mword def
+R12869:12870 bbv.HexNotationWord <> :::'Ox'_x not
+R12940:12944 Sail.Values <> mword def
+R12916:12917 bbv.HexNotationWord <> :::'Ox'_x not
+R12987:12991 Sail.Values <> mword def
+R12963:12964 bbv.HexNotationWord <> :::'Ox'_x not
+R13034:13038 Sail.Values <> mword def
+R13010:13011 bbv.HexNotationWord <> :::'Ox'_x not
+R13081:13085 Sail.Values <> mword def
+R13057:13058 bbv.HexNotationWord <> :::'Ox'_x not
+R13128:13132 Sail.Values <> mword def
+R13104:13105 bbv.HexNotationWord <> :::'Ox'_x not
+R13175:13179 Sail.Values <> mword def
+R13151:13152 bbv.HexNotationWord <> :::'Ox'_x not
+R13222:13226 Sail.Values <> mword def
+R13198:13199 bbv.HexNotationWord <> :::'Ox'_x not
+R13269:13273 Sail.Values <> mword def
+R13245:13246 bbv.HexNotationWord <> :::'Ox'_x not
+R13316:13320 Sail.Values <> mword def
+R13292:13293 bbv.HexNotationWord <> :::'Ox'_x not
+R13363:13367 Sail.Values <> mword def
+R13339:13340 bbv.HexNotationWord <> :::'Ox'_x not
+R13410:13414 Sail.Values <> mword def
+R13386:13387 bbv.HexNotationWord <> :::'Ox'_x not
+R13457:13461 Sail.Values <> mword def
+R13433:13434 bbv.HexNotationWord <> :::'Ox'_x not
+R13503:13507 Sail.Values <> mword def
+R13479:13480 bbv.HexNotationWord <> :::'Ox'_x not
+R13549:13553 Sail.Values <> mword def
+R13525:13526 bbv.HexNotationWord <> :::'Ox'_x not
+R13595:13599 Sail.Values <> mword def
+R13571:13572 bbv.HexNotationWord <> :::'Ox'_x not
+R13641:13645 Sail.Values <> mword def
+R13617:13618 bbv.HexNotationWord <> :::'Ox'_x not
+R13687:13691 Sail.Values <> mword def
+R13663:13664 bbv.HexNotationWord <> :::'Ox'_x not
+R13733:13737 Sail.Values <> mword def
+R13709:13710 bbv.HexNotationWord <> :::'Ox'_x not
+R13779:13783 Sail.Values <> mword def
+R13755:13756 bbv.HexNotationWord <> :::'Ox'_x not
+R13825:13829 Sail.Values <> mword def
+R13801:13802 bbv.HexNotationWord <> :::'Ox'_x not
+R13871:13875 Sail.Values <> mword def
+R13847:13848 bbv.HexNotationWord <> :::'Ox'_x not
+R13923:13927 Sail.Values <> mword def
+R13899:13900 bbv.HexNotationWord <> :::'Ox'_x not
+R13973:13977 Sail.Values <> mword def
+R13949:13950 bbv.HexNotationWord <> :::'Ox'_x not
+R14019:14023 Sail.Values <> mword def
+R13995:13996 bbv.HexNotationWord <> :::'Ox'_x not
+R14045:14060 riscv <> initial_regstate def
diff --git a/build/riscv.v b/build/riscv.v
new file mode 100644
index 0000000..09457da
--- /dev/null
+++ b/build/riscv.v
@@ -0,0 +1,294 @@
+(*Generated by Sail from riscv.*)
+Require Import Sail.Base.
+Require Import Sail.Real.
+Require Import riscv_types.
+Import ListNotations.
+Open Scope string.
+Open Scope bool.
+Open Scope Z.
+
+
+Definition is_none {a : Type} (opt : option a) : bool :=
+   match opt with | Some _ => false | None => true end.
+
+Definition is_some {a : Type} (opt : option a) : bool :=
+   match opt with | Some _ => true | None => false end.
+
+Definition eq_unit (_ : unit) (_ : unit) : {_bool : bool & ArithFact (_bool)} := build_ex (true).
+
+Definition neq_int (x : Z) (y : Z) : {_bool : bool & ArithFact (Bool.eqb (negb (x =? y)) _bool)} :=
+   build_ex (negb (Z.eqb x y)).
+
+Definition neq_bool (x : bool) (y : bool) : bool := negb (Bool.eqb x y).
+
+Definition __id (x : Z) : {_retval : Z & ArithFact (_retval =? x)} := build_ex (x).
+
+Definition fdiv_int (n : Z) (m : Z) : Z :=
+   if sumbool_of_bool (andb (Z.ltb n 0) (Z.gtb m 0)) then Z.sub (Z.quot (Z.add n 1) m) 1
+   else if sumbool_of_bool (andb (Z.gtb n 0) (Z.ltb m 0)) then Z.sub (Z.quot (Z.sub n 1) m) 1
+   else Z.quot n m.
+
+Definition fmod_int (n : Z) (m : Z) : Z := Z.sub n (Z.mul m (fdiv_int n m)).
+
+Definition concat_str_bits {n : Z} (str : string) (x : mword n) : string :=
+   String.append str (string_of_bits x).
+
+Definition concat_str_dec (str : string) (x : Z) : string := String.append str (dec_str x).
+
+
+
+Definition sail_mask {v0 : Z} (len : Z) (v : mword v0) `{ArithFact ((len >=? 0) && (v0 >=? 0))}
+: mword len :=
+   if sumbool_of_bool (Z.leb len (length_mword v)) then vector_truncate v len else zero_extend v len.
+
+Definition sail_ones (n : Z) `{ArithFact (n >=? 0)} : mword n := not_vec (zeros n).
+
+Definition slice_mask (n : Z) (i : Z) (l : Z) `{ArithFact (n >=? 0)} : mword n :=
+   if sumbool_of_bool (Z.geb l n) then shiftl (sail_ones n) i
+   else
+     let one : bits n := sail_mask n ('b"1"  : bits 1) in
+     shiftl (sub_vec (shiftl one l) one) i.
+
+Definition EXTS {n : Z} (m : Z) (v : mword n) `{ArithFact (m >=? n)} : mword m := sign_extend v m.
+
+Definition EXTZ {n : Z} (m : Z) (v : mword n) `{ArithFact (m >=? n)} : mword m := zero_extend v m.
+
+Definition zero_reg : regtype := EXTZ 64 (Ox"0"  : mword 4).
+Hint Unfold zero_reg : sail.
+Definition regval_from_reg (r : mword 64) : mword 64 := r.
+
+Definition regval_into_reg (v : mword 64) : mword 64 := v.
+
+Definition rX (r : Z) `{ArithFact ((0 <=? r) && (r <? 32))} : M (mword 64) :=
+   let l__32 := r in
+   (if sumbool_of_bool (Z.eqb l__32 0) then returnm zero_reg
+    else if sumbool_of_bool (Z.eqb l__32 1) then ((read_reg x1_ref)  : M (mword 64))  : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 2) then ((read_reg x2_ref)  : M (mword 64))  : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 3) then ((read_reg x3_ref)  : M (mword 64))  : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 4) then ((read_reg x4_ref)  : M (mword 64))  : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 5) then ((read_reg x5_ref)  : M (mword 64))  : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 6) then ((read_reg x6_ref)  : M (mword 64))  : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 7) then ((read_reg x7_ref)  : M (mword 64))  : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 8) then ((read_reg x8_ref)  : M (mword 64))  : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 9) then ((read_reg x9_ref)  : M (mword 64))  : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 10) then
+      ((read_reg x10_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 11) then
+      ((read_reg x11_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 12) then
+      ((read_reg x12_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 13) then
+      ((read_reg x13_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 14) then
+      ((read_reg x14_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 15) then
+      ((read_reg x15_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 16) then
+      ((read_reg x16_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 17) then
+      ((read_reg x17_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 18) then
+      ((read_reg x18_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 19) then
+      ((read_reg x19_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 20) then
+      ((read_reg x20_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 21) then
+      ((read_reg x21_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 22) then
+      ((read_reg x22_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 23) then
+      ((read_reg x23_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 24) then
+      ((read_reg x24_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 25) then
+      ((read_reg x25_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 26) then
+      ((read_reg x26_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 27) then
+      ((read_reg x27_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 28) then
+      ((read_reg x28_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 29) then
+      ((read_reg x29_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 30) then
+      ((read_reg x30_ref)  : M (mword 64))
+       : M (mword 64)
+    else if sumbool_of_bool (Z.eqb l__32 31) then
+      ((read_reg x31_ref)  : M (mword 64))
+       : M (mword 64)
+    else assert_exp' false "invalid register number" >>= fun _ => exit tt) >>= fun v : regtype =>
+   returnm (regval_from_reg v).
+
+Definition wX (r : Z) (in_v : mword 64) `{ArithFact ((0 <=? r) && (r <? 32))} : M (unit) :=
+   let v := regval_into_reg in_v in
+   let l__0 := r in
+   (if sumbool_of_bool (Z.eqb l__0 0) then returnm tt
+    else if sumbool_of_bool (Z.eqb l__0 1) then write_reg x1_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 2) then write_reg x2_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 3) then write_reg x3_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 4) then write_reg x4_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 5) then write_reg x5_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 6) then write_reg x6_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 7) then write_reg x7_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 8) then write_reg x8_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 9) then write_reg x9_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 10) then write_reg x10_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 11) then write_reg x11_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 12) then write_reg x12_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 13) then write_reg x13_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 14) then write_reg x14_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 15) then write_reg x15_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 16) then write_reg x16_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 17) then write_reg x17_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 18) then write_reg x18_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 19) then write_reg x19_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 20) then write_reg x20_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 21) then write_reg x21_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 22) then write_reg x22_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 23) then write_reg x23_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 24) then write_reg x24_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 25) then write_reg x25_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 26) then write_reg x26_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 27) then write_reg x27_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 28) then write_reg x28_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 29) then write_reg x29_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 30) then write_reg x30_ref v  : M (unit)
+    else if sumbool_of_bool (Z.eqb l__0 31) then write_reg x31_ref v  : M (unit)
+    else assert_exp' false "invalid register number" >>= fun _ => exit tt)
+    : M (unit).
+
+Definition rX_bits (i : mword 5) : M (mword 64) := (rX (projT1 (uint i)))  : M (mword 64).
+
+Definition wX_bits (i : mword 5) (data : mword 64) : M (unit) :=
+   (wX (projT1 (uint i)) data)  : M (unit).
+
+Definition reg_name_abi (r : mword 5) : M (string) :=
+   let b__0 := r in
+   (if eq_vec b__0 ('b"00000"  : mword 5) then returnm "zero"
+    else if eq_vec b__0 ('b"00001"  : mword 5) then returnm "ra"
+    else if eq_vec b__0 ('b"00010"  : mword 5) then returnm "sp"
+    else if eq_vec b__0 ('b"00011"  : mword 5) then returnm "gp"
+    else if eq_vec b__0 ('b"00100"  : mword 5) then returnm "tp"
+    else if eq_vec b__0 ('b"00101"  : mword 5) then returnm "t0"
+    else if eq_vec b__0 ('b"00110"  : mword 5) then returnm "t1"
+    else if eq_vec b__0 ('b"00111"  : mword 5) then returnm "t2"
+    else if eq_vec b__0 ('b"01000"  : mword 5) then returnm "fp"
+    else if eq_vec b__0 ('b"01001"  : mword 5) then returnm "s1"
+    else if eq_vec b__0 ('b"01010"  : mword 5) then returnm "a0"
+    else if eq_vec b__0 ('b"01011"  : mword 5) then returnm "a1"
+    else if eq_vec b__0 ('b"01100"  : mword 5) then returnm "a2"
+    else if eq_vec b__0 ('b"01101"  : mword 5) then returnm "a3"
+    else if eq_vec b__0 ('b"01110"  : mword 5) then returnm "a4"
+    else if eq_vec b__0 ('b"01111"  : mword 5) then returnm "a5"
+    else if eq_vec b__0 ('b"10000"  : mword 5) then returnm "a6"
+    else if eq_vec b__0 ('b"10001"  : mword 5) then returnm "a7"
+    else if eq_vec b__0 ('b"10010"  : mword 5) then returnm "s2"
+    else if eq_vec b__0 ('b"10011"  : mword 5) then returnm "s3"
+    else if eq_vec b__0 ('b"10100"  : mword 5) then returnm "s4"
+    else if eq_vec b__0 ('b"10101"  : mword 5) then returnm "s5"
+    else if eq_vec b__0 ('b"10110"  : mword 5) then returnm "s6"
+    else if eq_vec b__0 ('b"10111"  : mword 5) then returnm "s7"
+    else if eq_vec b__0 ('b"11000"  : mword 5) then returnm "s8"
+    else if eq_vec b__0 ('b"11001"  : mword 5) then returnm "s9"
+    else if eq_vec b__0 ('b"11010"  : mword 5) then returnm "s10"
+    else if eq_vec b__0 ('b"11011"  : mword 5) then returnm "s11"
+    else if eq_vec b__0 ('b"11100"  : mword 5) then returnm "t3"
+    else if eq_vec b__0 ('b"11101"  : mword 5) then returnm "t4"
+    else if eq_vec b__0 ('b"11110"  : mword 5) then returnm "t5"
+    else if eq_vec b__0 ('b"11111"  : mword 5) then returnm "t6"
+    else
+      assert_exp' false "Pattern match failure at riscv_regs.sail 160:2 - 193:3" >>= fun _ =>
+      exit tt)
+    : M (string).
+
+Definition init_base_regs '(tt : unit) : M (unit) :=
+   write_reg x1_ref zero_reg >>
+   write_reg x2_ref zero_reg >>
+   write_reg x3_ref zero_reg >>
+   write_reg x4_ref zero_reg >>
+   write_reg x5_ref zero_reg >>
+   write_reg x6_ref zero_reg >>
+   write_reg x7_ref zero_reg >>
+   write_reg x8_ref zero_reg >>
+   write_reg x9_ref zero_reg >>
+   write_reg x10_ref zero_reg >>
+   write_reg x11_ref zero_reg >>
+   write_reg x12_ref zero_reg >>
+   write_reg x13_ref zero_reg >>
+   write_reg x14_ref zero_reg >>
+   write_reg x15_ref zero_reg >>
+   write_reg x16_ref zero_reg >>
+   write_reg x17_ref zero_reg >>
+   write_reg x18_ref zero_reg >>
+   write_reg x19_ref zero_reg >>
+   write_reg x20_ref zero_reg >>
+   write_reg x21_ref zero_reg >>
+   write_reg x22_ref zero_reg >>
+   write_reg x23_ref zero_reg >>
+   write_reg x24_ref zero_reg >>
+   write_reg x25_ref zero_reg >>
+   write_reg x26_ref zero_reg >>
+   write_reg x27_ref zero_reg >>
+   write_reg x28_ref zero_reg >>
+   write_reg x29_ref zero_reg >>
+   write_reg x30_ref zero_reg >> write_reg x31_ref zero_reg  : M (unit).
+
+Definition initial_regstate : regstate :=
+{| x31 := (Ox"0000000000000000"  : mword 64); 
+   x30 := (Ox"0000000000000000"  : mword 64); 
+   x29 := (Ox"0000000000000000"  : mword 64); 
+   x28 := (Ox"0000000000000000"  : mword 64); 
+   x27 := (Ox"0000000000000000"  : mword 64); 
+   x26 := (Ox"0000000000000000"  : mword 64); 
+   x25 := (Ox"0000000000000000"  : mword 64); 
+   x24 := (Ox"0000000000000000"  : mword 64); 
+   x23 := (Ox"0000000000000000"  : mword 64); 
+   x22 := (Ox"0000000000000000"  : mword 64); 
+   x21 := (Ox"0000000000000000"  : mword 64); 
+   x20 := (Ox"0000000000000000"  : mword 64); 
+   x19 := (Ox"0000000000000000"  : mword 64); 
+   x18 := (Ox"0000000000000000"  : mword 64); 
+   x17 := (Ox"0000000000000000"  : mword 64); 
+   x16 := (Ox"0000000000000000"  : mword 64); 
+   x15 := (Ox"0000000000000000"  : mword 64); 
+   x14 := (Ox"0000000000000000"  : mword 64); 
+   x13 := (Ox"0000000000000000"  : mword 64); 
+   x12 := (Ox"0000000000000000"  : mword 64); 
+   x11 := (Ox"0000000000000000"  : mword 64); 
+   x10 := (Ox"0000000000000000"  : mword 64); 
+   x9 := (Ox"0000000000000000"  : mword 64); 
+   x8 := (Ox"0000000000000000"  : mword 64); 
+   x7 := (Ox"0000000000000000"  : mword 64); 
+   x6 := (Ox"0000000000000000"  : mword 64); 
+   x5 := (Ox"0000000000000000"  : mword 64); 
+   x4 := (Ox"0000000000000000"  : mword 64); 
+   x3 := (Ox"0000000000000000"  : mword 64); 
+   x2 := (Ox"0000000000000000"  : mword 64); 
+   x1 := (Ox"0000000000000000"  : mword 64); 
+   instbits := (Ox"0000000000000000"  : mword 64); 
+   nextPC := (Ox"0000000000000000"  : mword 64); 
+   PC := (Ox"0000000000000000"  : mword 64) |}.
+Hint Unfold initial_regstate : sail.
+
+
diff --git a/build/riscv.vo b/build/riscv.vo
new file mode 100644
index 0000000..2bbe4d2
--- /dev/null
+++ b/build/riscv.vo
diff --git a/build/riscv.vok b/build/riscv.vok
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/build/riscv.vok
diff --git a/build/riscv.vos b/build/riscv.vos
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/build/riscv.vos
diff --git a/build/riscv_types.glob b/build/riscv_types.glob
new file mode 100644
index 0000000..75c986b
--- /dev/null
+++ b/build/riscv_types.glob
@@ -0,0 +1,1839 @@
+DIGEST 23addcfb4a3be3458f693a2ed5b20df5
+Friscv_types
+R49:57 Sail.Base <> <> lib
+R75:83 Sail.Real <> <> lib
+def 170:173 <> bits
+R180:180 Coq.Numbers.BinNums <> Z ind
+binder 176:176 <> n:1
+R193:197 Sail.Values <> mword def
+R199:199 riscv_types <> n:1 var
+def 214:217 <> xlen
+R222:222 Coq.Numbers.BinNums <> Z ind
+R243:246 riscv_types <> xlen def
+def 268:277 <> xlen_bytes
+R282:282 Coq.Numbers.BinNums <> Z ind
+R302:311 riscv_types <> xlen_bytes def
+def 333:340 <> xlenbits
+R353:356 riscv_types <> bits def
+def 374:380 <> regtype
+R393:400 riscv_types <> xlenbits def
+def 415:419 <> regno
+R426:426 Coq.Numbers.BinNums <> Z ind
+binder 422:422 <> n:2
+R430:438 Sail.Values <> ArithFact class
+R441:441 Coq.Init.Datatypes <> ::bool_scope:x_'&&'_x not
+R449:454 Coq.Init.Datatypes <> ::bool_scope:x_'&&'_x not
+R462:462 Coq.Init.Datatypes <> ::bool_scope:x_'&&'_x not
+R443:447 Coq.ZArith.BinInt <> ::Z_scope:x_'<=?'_x not
+R448:448 riscv_types <> n:2 var
+R456:459 Coq.ZArith.BinInt <> ::Z_scope:x_'<?'_x not
+R455:455 riscv_types <> n:2 var
+binder 430:463 <> H:3
+R476:476 Coq.Numbers.BinNums <> Z ind
+def 491:496 <> regidx
+R509:512 riscv_types <> bits def
+def 529:535 <> cregidx
+R548:551 riscv_types <> bits def
+def 568:572 <> csreg
+R585:588 riscv_types <> bits def
+ind 605:618 <> register_value
+constr 628:640 <> Regval_vector
+constr 686:696 <> Regval_list
+constr 742:754 <> Regval_option
+constr 802:811 <> Regval_bit
+constr 842:864 <> Regval_bitvector_64_dec
+R663:666 Coq.Init.Logic <> ::type_scope:x_'->'_x not
+R644:647 Coq.Init.Datatypes <> list ind
+R649:662 riscv_types <> register_value:4 ind
+R667:680 riscv_types <> register_value:4 ind
+R719:722 Coq.Init.Logic <> ::type_scope:x_'->'_x not
+R700:703 Coq.Init.Datatypes <> list ind
+R705:718 riscv_types <> register_value:4 ind
+R723:736 riscv_types <> register_value:4 ind
+R779:782 Coq.Init.Logic <> ::type_scope:x_'->'_x not
+R758:763 Coq.Init.Datatypes <> option ind
+R765:778 riscv_types <> register_value:4 ind
+R783:796 riscv_types <> register_value:4 ind
+R819:822 Coq.Init.Logic <> ::type_scope:x_'->'_x not
+R815:818 Sail.Values <> bitU ind
+R823:836 riscv_types <> register_value:4 ind
+R876:879 Coq.Init.Logic <> ::type_scope:x_'->'_x not
+R868:872 Sail.Values <> mword def
+R880:893 riscv_types <> register_value:4 ind
+R907:920 riscv_types <> register_value ind
+R907:920 riscv_types <> register_value ind
+rec 949:956 <> regstate
+proj 966:968 <> x31
+proj 986:988 <> x30
+proj 1006:1008 <> x29
+proj 1026:1028 <> x28
+proj 1046:1048 <> x27
+proj 1066:1068 <> x26
+proj 1086:1088 <> x25
+proj 1106:1108 <> x24
+proj 1126:1128 <> x23
+proj 1146:1148 <> x22
+proj 1166:1168 <> x21
+proj 1186:1188 <> x20
+proj 1206:1208 <> x19
+proj 1226:1228 <> x18
+proj 1246:1248 <> x17
+proj 1266:1268 <> x16
+proj 1286:1288 <> x15
+proj 1306:1308 <> x14
+proj 1326:1328 <> x13
+proj 1346:1348 <> x12
+proj 1366:1368 <> x11
+proj 1386:1388 <> x10
+proj 1406:1407 <> x9
+proj 1425:1426 <> x8
+proj 1444:1445 <> x7
+proj 1463:1464 <> x6
+proj 1482:1483 <> x5
+proj 1501:1502 <> x4
+proj 1520:1521 <> x3
+proj 1539:1540 <> x2
+proj 1558:1559 <> x1
+proj 1577:1584 <> instbits
+proj 1602:1607 <> nextPC
+proj 1625:1626 <> PC
+R972:976 Sail.Values <> mword def
+R992:996 Sail.Values <> mword def
+R1012:1016 Sail.Values <> mword def
+R1032:1036 Sail.Values <> mword def
+R1052:1056 Sail.Values <> mword def
+R1072:1076 Sail.Values <> mword def
+R1092:1096 Sail.Values <> mword def
+R1112:1116 Sail.Values <> mword def
+R1132:1136 Sail.Values <> mword def
+R1152:1156 Sail.Values <> mword def
+R1172:1176 Sail.Values <> mword def
+R1192:1196 Sail.Values <> mword def
+R1212:1216 Sail.Values <> mword def
+R1232:1236 Sail.Values <> mword def
+R1252:1256 Sail.Values <> mword def
+R1272:1276 Sail.Values <> mword def
+R1292:1296 Sail.Values <> mword def
+R1312:1316 Sail.Values <> mword def
+R1332:1336 Sail.Values <> mword def
+R1352:1356 Sail.Values <> mword def
+R1372:1376 Sail.Values <> mword def
+R1392:1396 Sail.Values <> mword def
+R1411:1415 Sail.Values <> mword def
+R1430:1434 Sail.Values <> mword def
+R1449:1453 Sail.Values <> mword def
+R1468:1472 Sail.Values <> mword def
+R1487:1491 Sail.Values <> mword def
+R1506:1510 Sail.Values <> mword def
+R1525:1529 Sail.Values <> mword def
+R1544:1548 Sail.Values <> mword def
+R1563:1567 Sail.Values <> mword def
+R1588:1592 Sail.Values <> mword def
+R1611:1615 Sail.Values <> mword def
+R1630:1634 Sail.Values <> mword def
+R1654:1661 riscv_types <> regstate rec
+R1654:1661 riscv_types <> regstate rec
+R1738:1751 riscv_types <> Build_regstate constr
+R1885:1898 riscv_types <> Build_regstate constr
+not 1692:1692 <> :::'{['_x_'with'_'x31'_':='_x_']}'
+R2091:2104 riscv_types <> Build_regstate constr
+R2238:2251 riscv_types <> Build_regstate constr
+not 2045:2045 <> :::'{['_x_'with'_'x30'_':='_x_']}'
+R2444:2457 riscv_types <> Build_regstate constr
+R2591:2604 riscv_types <> Build_regstate constr
+not 2398:2398 <> :::'{['_x_'with'_'x29'_':='_x_']}'
+R2797:2810 riscv_types <> Build_regstate constr
+R2944:2957 riscv_types <> Build_regstate constr
+not 2751:2751 <> :::'{['_x_'with'_'x28'_':='_x_']}'
+R3150:3163 riscv_types <> Build_regstate constr
+R3297:3310 riscv_types <> Build_regstate constr
+not 3104:3104 <> :::'{['_x_'with'_'x27'_':='_x_']}'
+R3503:3516 riscv_types <> Build_regstate constr
+R3650:3663 riscv_types <> Build_regstate constr
+not 3457:3457 <> :::'{['_x_'with'_'x26'_':='_x_']}'
+R3856:3869 riscv_types <> Build_regstate constr
+R4003:4016 riscv_types <> Build_regstate constr
+not 3810:3810 <> :::'{['_x_'with'_'x25'_':='_x_']}'
+R4209:4222 riscv_types <> Build_regstate constr
+R4356:4369 riscv_types <> Build_regstate constr
+not 4163:4163 <> :::'{['_x_'with'_'x24'_':='_x_']}'
+R4562:4575 riscv_types <> Build_regstate constr
+R4709:4722 riscv_types <> Build_regstate constr
+not 4516:4516 <> :::'{['_x_'with'_'x23'_':='_x_']}'
+R4915:4928 riscv_types <> Build_regstate constr
+R5062:5075 riscv_types <> Build_regstate constr
+not 4869:4869 <> :::'{['_x_'with'_'x22'_':='_x_']}'
+R5268:5281 riscv_types <> Build_regstate constr
+R5414:5427 riscv_types <> Build_regstate constr
+not 5222:5222 <> :::'{['_x_'with'_'x21'_':='_x_']}'
+R5619:5632 riscv_types <> Build_regstate constr
+R5765:5778 riscv_types <> Build_regstate constr
+not 5573:5573 <> :::'{['_x_'with'_'x20'_':='_x_']}'
+R5970:5983 riscv_types <> Build_regstate constr
+R6116:6129 riscv_types <> Build_regstate constr
+not 5924:5924 <> :::'{['_x_'with'_'x19'_':='_x_']}'
+R6321:6334 riscv_types <> Build_regstate constr
+R6467:6480 riscv_types <> Build_regstate constr
+not 6275:6275 <> :::'{['_x_'with'_'x18'_':='_x_']}'
+R6672:6685 riscv_types <> Build_regstate constr
+R6818:6831 riscv_types <> Build_regstate constr
+not 6626:6626 <> :::'{['_x_'with'_'x17'_':='_x_']}'
+R7023:7036 riscv_types <> Build_regstate constr
+R7169:7182 riscv_types <> Build_regstate constr
+not 6977:6977 <> :::'{['_x_'with'_'x16'_':='_x_']}'
+R7374:7387 riscv_types <> Build_regstate constr
+R7520:7533 riscv_types <> Build_regstate constr
+not 7328:7328 <> :::'{['_x_'with'_'x15'_':='_x_']}'
+R7725:7738 riscv_types <> Build_regstate constr
+R7871:7884 riscv_types <> Build_regstate constr
+not 7679:7679 <> :::'{['_x_'with'_'x14'_':='_x_']}'
+R8076:8089 riscv_types <> Build_regstate constr
+R8222:8235 riscv_types <> Build_regstate constr
+not 8030:8030 <> :::'{['_x_'with'_'x13'_':='_x_']}'
+R8427:8440 riscv_types <> Build_regstate constr
+R8573:8586 riscv_types <> Build_regstate constr
+not 8381:8381 <> :::'{['_x_'with'_'x12'_':='_x_']}'
+R8778:8791 riscv_types <> Build_regstate constr
+R8924:8937 riscv_types <> Build_regstate constr
+not 8732:8732 <> :::'{['_x_'with'_'x11'_':='_x_']}'
+R9129:9142 riscv_types <> Build_regstate constr
+R9275:9288 riscv_types <> Build_regstate constr
+not 9083:9083 <> :::'{['_x_'with'_'x10'_':='_x_']}'
+R9479:9492 riscv_types <> Build_regstate constr
+R9625:9638 riscv_types <> Build_regstate constr
+not 9434:9434 <> :::'{['_x_'with'_'x9'_':='_x_']}'
+R9829:9842 riscv_types <> Build_regstate constr
+R9975:9988 riscv_types <> Build_regstate constr
+not 9784:9784 <> :::'{['_x_'with'_'x8'_':='_x_']}'
+R10179:10192 riscv_types <> Build_regstate constr
+R10325:10338 riscv_types <> Build_regstate constr
+not 10134:10134 <> :::'{['_x_'with'_'x7'_':='_x_']}'
+R10529:10542 riscv_types <> Build_regstate constr
+R10675:10688 riscv_types <> Build_regstate constr
+not 10484:10484 <> :::'{['_x_'with'_'x6'_':='_x_']}'
+R10879:10892 riscv_types <> Build_regstate constr
+R11025:11038 riscv_types <> Build_regstate constr
+not 10834:10834 <> :::'{['_x_'with'_'x5'_':='_x_']}'
+R11229:11242 riscv_types <> Build_regstate constr
+R11375:11388 riscv_types <> Build_regstate constr
+not 11184:11184 <> :::'{['_x_'with'_'x4'_':='_x_']}'
+R11579:11592 riscv_types <> Build_regstate constr
+R11725:11738 riscv_types <> Build_regstate constr
+not 11534:11534 <> :::'{['_x_'with'_'x3'_':='_x_']}'
+R11929:11942 riscv_types <> Build_regstate constr
+R12075:12088 riscv_types <> Build_regstate constr
+not 11884:11884 <> :::'{['_x_'with'_'x2'_':='_x_']}'
+R12279:12292 riscv_types <> Build_regstate constr
+R12425:12438 riscv_types <> Build_regstate constr
+not 12234:12234 <> :::'{['_x_'with'_'x1'_':='_x_']}'
+R12635:12648 riscv_types <> Build_regstate constr
+R12781:12794 riscv_types <> Build_regstate constr
+not 12584:12584 <> :::'{['_x_'with'_'instbits'_':='_x_']}'
+R12989:13002 riscv_types <> Build_regstate constr
+R13135:13148 riscv_types <> Build_regstate constr
+not 12940:12940 <> :::'{['_x_'with'_'nextPC'_':='_x_']}'
+R13339:13352 riscv_types <> Build_regstate constr
+R13485:13498 riscv_types <> Build_regstate constr
+not 13294:13294 <> :::'{['_x_'with'_'PC'_':='_x_']}'
+def 13649:13661 <> bit_of_regval
+R13676:13689 riscv_types <> register_value ind
+binder 13664:13672 <> merge_var:41
+R13694:13699 Coq.Init.Datatypes <> option ind
+R13701:13704 Sail.Values <> bitU ind
+R13718:13726 riscv_types <> merge_var:41 var
+R13735:13744 riscv_types <> Regval_bit constr
+R13751:13754 Coq.Init.Datatypes <> Some constr
+R13765:13768 Coq.Init.Datatypes <> None constr
+def 13787:13799 <> regval_of_bit
+R13806:13809 Sail.Values <> bitU ind
+binder 13802:13802 <> v:43
+R13814:13827 riscv_types <> register_value ind
+R13832:13841 riscv_types <> Regval_bit constr
+R13843:13843 riscv_types <> v:43 var
+def 13858:13883 <> bitvector_64_dec_of_regval
+R13898:13911 riscv_types <> register_value ind
+binder 13886:13894 <> merge_var:44
+R13918:13923 Coq.Init.Datatypes <> option ind
+R13926:13930 Sail.Values <> mword def
+R13948:13956 riscv_types <> merge_var:44 var
+R13965:13987 riscv_types <> Regval_bitvector_64_dec constr
+R13994:13997 Coq.Init.Datatypes <> Some constr
+R14008:14011 Coq.Init.Datatypes <> None constr
+def 14031:14056 <> regval_of_bitvector_64_dec
+R14063:14067 Sail.Values <> mword def
+binder 14059:14059 <> v:46
+R14075:14088 riscv_types <> register_value ind
+R14095:14117 riscv_types <> Regval_bitvector_64_dec constr
+R14119:14119 riscv_types <> v:46 var
+def 14135:14150 <> vector_of_regval
+binder 14153:14153 <> a:47
+binder 14156:14156 <> n:48
+R14185:14188 Coq.Init.Logic <> ::type_scope:x_'->'_x not
+R14171:14184 riscv_types <> register_value ind
+R14189:14194 Coq.Init.Datatypes <> option ind
+R14196:14196 riscv_types <> a:47 var
+binder 14159:14167 <> of_regval:49
+R14216:14229 riscv_types <> register_value ind
+binder 14211:14212 <> rv:50
+R14234:14239 Coq.Init.Datatypes <> option ind
+R14242:14244 Sail.Values <> vec def
+R14246:14246 riscv_types <> a:47 var
+R14248:14248 riscv_types <> n:48 var
+R14262:14263 riscv_types <> rv:50 var
+R14274:14286 riscv_types <> Regval_vector constr
+R14301:14304 Coq.ZArith.BinInt <> ::Z_scope:x_'=?'_x not
+R14300:14300 riscv_types <> n:48 var
+R14305:14315 Sail.Values <> length_list def
+R14399:14402 Coq.Init.Datatypes <> None constr
+R14330:14337 Sail.Values <> map_bind def
+R14356:14364 Sail.Values <> just_list def
+R14367:14374 Coq.Lists.List <> map def
+R14376:14384 riscv_types <> of_regval:49 var
+R14340:14350 Sail.Values <> vec_of_list def
+R14352:14352 riscv_types <> n:48 var
+R14413:14416 Coq.Init.Datatypes <> None constr
+def 14435:14450 <> regval_of_vector
+binder 14453:14453 <> a:52
+binder 14455:14458 <> size:53
+R14475:14478 Coq.Init.Logic <> ::type_scope:x_'->'_x not
+R14474:14474 riscv_types <> a:52 var
+R14479:14492 riscv_types <> register_value ind
+binder 14462:14470 <> regval_of:54
+R14501:14503 Sail.Values <> vec def
+R14505:14505 riscv_types <> a:52 var
+R14507:14510 riscv_types <> size:53 var
+binder 14496:14497 <> xs:55
+R14515:14528 riscv_types <> register_value ind
+R14533:14545 riscv_types <> Regval_vector constr
+R14548:14555 Coq.Lists.List <> map def
+R14568:14578 Sail.Values <> list_of_vec def
+R14580:14581 riscv_types <> xs:55 var
+R14557:14565 riscv_types <> regval_of:54 var
+def 14598:14611 <> list_of_regval
+binder 14614:14614 <> a:56
+R14644:14647 Coq.Init.Logic <> ::type_scope:x_'->'_x not
+R14630:14643 riscv_types <> register_value ind
+R14648:14653 Coq.Init.Datatypes <> option ind
+R14655:14655 riscv_types <> a:56 var
+binder 14618:14626 <> of_regval:57
+R14675:14688 riscv_types <> register_value ind
+binder 14670:14671 <> rv:58
+R14693:14698 Coq.Init.Datatypes <> option ind
+R14701:14704 Coq.Init.Datatypes <> list ind
+R14706:14706 riscv_types <> a:56 var
+R14720:14721 riscv_types <> rv:58 var
+R14732:14742 riscv_types <> Regval_list constr
+R14749:14757 Sail.Values <> just_list def
+R14760:14767 Coq.Lists.List <> map def
+R14769:14777 riscv_types <> of_regval:57 var
+R14791:14794 Coq.Init.Datatypes <> None constr
+def 14813:14826 <> regval_of_list
+binder 14829:14829 <> a:60
+R14846:14849 Coq.Init.Logic <> ::type_scope:x_'->'_x not
+R14845:14845 riscv_types <> a:60 var
+R14850:14863 riscv_types <> register_value ind
+binder 14833:14841 <> regval_of:61
+R14883:14886 Coq.Init.Datatypes <> list ind
+R14888:14888 riscv_types <> a:60 var
+binder 14878:14879 <> xs:62
+R14893:14906 riscv_types <> register_value ind
+R14913:14923 riscv_types <> Regval_list constr
+R14926:14933 Coq.Lists.List <> map def
+R14945:14946 riscv_types <> xs:62 var
+R14935:14943 riscv_types <> regval_of:61 var
+def 14962:14977 <> option_of_regval
+binder 14980:14980 <> a:63
+R15010:15013 Coq.Init.Logic <> ::type_scope:x_'->'_x not
+R14996:15009 riscv_types <> register_value ind
+R15014:15019 Coq.Init.Datatypes <> option ind
+R15021:15021 riscv_types <> a:63 var
+binder 14984:14992 <> of_regval:64
+R15041:15054 riscv_types <> register_value ind
+binder 15036:15037 <> rv:65
+R15059:15064 Coq.Init.Datatypes <> option ind
+R15067:15072 Coq.Init.Datatypes <> option ind
+R15074:15074 riscv_types <> a:63 var
+R15088:15089 riscv_types <> rv:65 var
+R15100:15112 riscv_types <> Regval_option constr
+R15119:15128 Coq.Init.Datatypes <> option_map def
+R15130:15138 riscv_types <> of_regval:64 var
+R15151:15154 Coq.Init.Datatypes <> None constr
+def 15173:15188 <> regval_of_option
+binder 15191:15191 <> a:67
+R15208:15211 Coq.Init.Logic <> ::type_scope:x_'->'_x not
+R15207:15207 riscv_types <> a:67 var
+R15212:15225 riscv_types <> register_value ind
+binder 15195:15203 <> regval_of:68
+R15244:15249 Coq.Init.Datatypes <> option ind
+R15251:15251 riscv_types <> a:67 var
+binder 15240:15240 <> v:69
+R15257:15269 riscv_types <> Regval_option constr
+R15272:15281 Coq.Init.Datatypes <> option_map def
+R15293:15293 riscv_types <> v:69 var
+R15283:15291 riscv_types <> regval_of:68 var
+def 15310:15316 <> x31_ref
+R15326:15329 Sail.Values <> name proj
+R15326:15329 Sail.Values <> name proj
+R15343:15351 Sail.Values <> read_from proj
+R15378:15385 Sail.Values <> write_to proj
+R15430:15438 Sail.Values <> of_regval proj
+R15486:15494 Sail.Values <> regval_of proj
+binder 15361:15361 <> s:70
+R15369:15371 riscv_types <> x31 proj
+R15366:15366 riscv_types <> s:70 var
+binder 15395:15395 <> v:71
+binder 15397:15397 <> s:72
+R15403:15405 riscv_types <> :::'{['_x_'with'_'x31'_':='_x_']}' not
+R15407:15419 riscv_types <> :::'{['_x_'with'_'x31'_':='_x_']}' not
+R15421:15423 riscv_types <> :::'{['_x_'with'_'x31'_':='_x_']}' not
+R15406:15406 riscv_types <> s:72 var
+R15420:15420 riscv_types <> v:71 var
+binder 15448:15448 <> v:73
+R15453:15478 riscv_types <> bitvector_64_dec_of_regval def
+R15480:15480 riscv_types <> v:73 var
+binder 15504:15504 <> v:74
+R15509:15534 riscv_types <> regval_of_bitvector_64_dec def
+R15536:15536 riscv_types <> v:74 var
+def 15555:15561 <> x30_ref
+R15571:15574 Sail.Values <> name proj
+R15571:15574 Sail.Values <> name proj
+R15588:15596 Sail.Values <> read_from proj
+R15623:15630 Sail.Values <> write_to proj
+R15675:15683 Sail.Values <> of_regval proj
+R15731:15739 Sail.Values <> regval_of proj
+binder 15606:15606 <> s:75
+R15614:15616 riscv_types <> x30 proj
+R15611:15611 riscv_types <> s:75 var
+binder 15640:15640 <> v:76
+binder 15642:15642 <> s:77
+R15648:15650 riscv_types <> :::'{['_x_'with'_'x30'_':='_x_']}' not
+R15652:15664 riscv_types <> :::'{['_x_'with'_'x30'_':='_x_']}' not
+R15666:15668 riscv_types <> :::'{['_x_'with'_'x30'_':='_x_']}' not
+R15651:15651 riscv_types <> s:77 var
+R15665:15665 riscv_types <> v:76 var
+binder 15693:15693 <> v:78
+R15698:15723 riscv_types <> bitvector_64_dec_of_regval def
+R15725:15725 riscv_types <> v:78 var
+binder 15749:15749 <> v:79
+R15754:15779 riscv_types <> regval_of_bitvector_64_dec def
+R15781:15781 riscv_types <> v:79 var
+def 15800:15806 <> x29_ref
+R15816:15819 Sail.Values <> name proj
+R15816:15819 Sail.Values <> name proj
+R15833:15841 Sail.Values <> read_from proj
+R15868:15875 Sail.Values <> write_to proj
+R15920:15928 Sail.Values <> of_regval proj
+R15976:15984 Sail.Values <> regval_of proj
+binder 15851:15851 <> s:80
+R15859:15861 riscv_types <> x29 proj
+R15856:15856 riscv_types <> s:80 var
+binder 15885:15885 <> v:81
+binder 15887:15887 <> s:82
+R15893:15895 riscv_types <> :::'{['_x_'with'_'x29'_':='_x_']}' not
+R15897:15909 riscv_types <> :::'{['_x_'with'_'x29'_':='_x_']}' not
+R15911:15913 riscv_types <> :::'{['_x_'with'_'x29'_':='_x_']}' not
+R15896:15896 riscv_types <> s:82 var
+R15910:15910 riscv_types <> v:81 var
+binder 15938:15938 <> v:83
+R15943:15968 riscv_types <> bitvector_64_dec_of_regval def
+R15970:15970 riscv_types <> v:83 var
+binder 15994:15994 <> v:84
+R15999:16024 riscv_types <> regval_of_bitvector_64_dec def
+R16026:16026 riscv_types <> v:84 var
+def 16045:16051 <> x28_ref
+R16061:16064 Sail.Values <> name proj
+R16061:16064 Sail.Values <> name proj
+R16078:16086 Sail.Values <> read_from proj
+R16113:16120 Sail.Values <> write_to proj
+R16165:16173 Sail.Values <> of_regval proj
+R16221:16229 Sail.Values <> regval_of proj
+binder 16096:16096 <> s:85
+R16104:16106 riscv_types <> x28 proj
+R16101:16101 riscv_types <> s:85 var
+binder 16130:16130 <> v:86
+binder 16132:16132 <> s:87
+R16138:16140 riscv_types <> :::'{['_x_'with'_'x28'_':='_x_']}' not
+R16142:16154 riscv_types <> :::'{['_x_'with'_'x28'_':='_x_']}' not
+R16156:16158 riscv_types <> :::'{['_x_'with'_'x28'_':='_x_']}' not
+R16141:16141 riscv_types <> s:87 var
+R16155:16155 riscv_types <> v:86 var
+binder 16183:16183 <> v:88
+R16188:16213 riscv_types <> bitvector_64_dec_of_regval def
+R16215:16215 riscv_types <> v:88 var
+binder 16239:16239 <> v:89
+R16244:16269 riscv_types <> regval_of_bitvector_64_dec def
+R16271:16271 riscv_types <> v:89 var
+def 16290:16296 <> x27_ref
+R16306:16309 Sail.Values <> name proj
+R16306:16309 Sail.Values <> name proj
+R16323:16331 Sail.Values <> read_from proj
+R16358:16365 Sail.Values <> write_to proj
+R16410:16418 Sail.Values <> of_regval proj
+R16466:16474 Sail.Values <> regval_of proj
+binder 16341:16341 <> s:90
+R16349:16351 riscv_types <> x27 proj
+R16346:16346 riscv_types <> s:90 var
+binder 16375:16375 <> v:91
+binder 16377:16377 <> s:92
+R16383:16385 riscv_types <> :::'{['_x_'with'_'x27'_':='_x_']}' not
+R16387:16399 riscv_types <> :::'{['_x_'with'_'x27'_':='_x_']}' not
+R16401:16403 riscv_types <> :::'{['_x_'with'_'x27'_':='_x_']}' not
+R16386:16386 riscv_types <> s:92 var
+R16400:16400 riscv_types <> v:91 var
+binder 16428:16428 <> v:93
+R16433:16458 riscv_types <> bitvector_64_dec_of_regval def
+R16460:16460 riscv_types <> v:93 var
+binder 16484:16484 <> v:94
+R16489:16514 riscv_types <> regval_of_bitvector_64_dec def
+R16516:16516 riscv_types <> v:94 var
+def 16535:16541 <> x26_ref
+R16551:16554 Sail.Values <> name proj
+R16551:16554 Sail.Values <> name proj
+R16568:16576 Sail.Values <> read_from proj
+R16603:16610 Sail.Values <> write_to proj
+R16655:16663 Sail.Values <> of_regval proj
+R16711:16719 Sail.Values <> regval_of proj
+binder 16586:16586 <> s:95
+R16594:16596 riscv_types <> x26 proj
+R16591:16591 riscv_types <> s:95 var
+binder 16620:16620 <> v:96
+binder 16622:16622 <> s:97
+R16628:16630 riscv_types <> :::'{['_x_'with'_'x26'_':='_x_']}' not
+R16632:16644 riscv_types <> :::'{['_x_'with'_'x26'_':='_x_']}' not
+R16646:16648 riscv_types <> :::'{['_x_'with'_'x26'_':='_x_']}' not
+R16631:16631 riscv_types <> s:97 var
+R16645:16645 riscv_types <> v:96 var
+binder 16673:16673 <> v:98
+R16678:16703 riscv_types <> bitvector_64_dec_of_regval def
+R16705:16705 riscv_types <> v:98 var
+binder 16729:16729 <> v:99
+R16734:16759 riscv_types <> regval_of_bitvector_64_dec def
+R16761:16761 riscv_types <> v:99 var
+def 16780:16786 <> x25_ref
+R16796:16799 Sail.Values <> name proj
+R16796:16799 Sail.Values <> name proj
+R16813:16821 Sail.Values <> read_from proj
+R16848:16855 Sail.Values <> write_to proj
+R16900:16908 Sail.Values <> of_regval proj
+R16956:16964 Sail.Values <> regval_of proj
+binder 16831:16831 <> s:100
+R16839:16841 riscv_types <> x25 proj
+R16836:16836 riscv_types <> s:100 var
+binder 16865:16865 <> v:101
+binder 16867:16867 <> s:102
+R16873:16875 riscv_types <> :::'{['_x_'with'_'x25'_':='_x_']}' not
+R16877:16889 riscv_types <> :::'{['_x_'with'_'x25'_':='_x_']}' not
+R16891:16893 riscv_types <> :::'{['_x_'with'_'x25'_':='_x_']}' not
+R16876:16876 riscv_types <> s:102 var
+R16890:16890 riscv_types <> v:101 var
+binder 16918:16918 <> v:103
+R16923:16948 riscv_types <> bitvector_64_dec_of_regval def
+R16950:16950 riscv_types <> v:103 var
+binder 16974:16974 <> v:104
+R16979:17004 riscv_types <> regval_of_bitvector_64_dec def
+R17006:17006 riscv_types <> v:104 var
+def 17025:17031 <> x24_ref
+R17041:17044 Sail.Values <> name proj
+R17041:17044 Sail.Values <> name proj
+R17058:17066 Sail.Values <> read_from proj
+R17093:17100 Sail.Values <> write_to proj
+R17145:17153 Sail.Values <> of_regval proj
+R17201:17209 Sail.Values <> regval_of proj
+binder 17076:17076 <> s:105
+R17084:17086 riscv_types <> x24 proj
+R17081:17081 riscv_types <> s:105 var
+binder 17110:17110 <> v:106
+binder 17112:17112 <> s:107
+R17118:17120 riscv_types <> :::'{['_x_'with'_'x24'_':='_x_']}' not
+R17122:17134 riscv_types <> :::'{['_x_'with'_'x24'_':='_x_']}' not
+R17136:17138 riscv_types <> :::'{['_x_'with'_'x24'_':='_x_']}' not
+R17121:17121 riscv_types <> s:107 var
+R17135:17135 riscv_types <> v:106 var
+binder 17163:17163 <> v:108
+R17168:17193 riscv_types <> bitvector_64_dec_of_regval def
+R17195:17195 riscv_types <> v:108 var
+binder 17219:17219 <> v:109
+R17224:17249 riscv_types <> regval_of_bitvector_64_dec def
+R17251:17251 riscv_types <> v:109 var
+def 17270:17276 <> x23_ref
+R17286:17289 Sail.Values <> name proj
+R17286:17289 Sail.Values <> name proj
+R17303:17311 Sail.Values <> read_from proj
+R17338:17345 Sail.Values <> write_to proj
+R17390:17398 Sail.Values <> of_regval proj
+R17446:17454 Sail.Values <> regval_of proj
+binder 17321:17321 <> s:110
+R17329:17331 riscv_types <> x23 proj
+R17326:17326 riscv_types <> s:110 var
+binder 17355:17355 <> v:111
+binder 17357:17357 <> s:112
+R17363:17365 riscv_types <> :::'{['_x_'with'_'x23'_':='_x_']}' not
+R17367:17379 riscv_types <> :::'{['_x_'with'_'x23'_':='_x_']}' not
+R17381:17383 riscv_types <> :::'{['_x_'with'_'x23'_':='_x_']}' not
+R17366:17366 riscv_types <> s:112 var
+R17380:17380 riscv_types <> v:111 var
+binder 17408:17408 <> v:113
+R17413:17438 riscv_types <> bitvector_64_dec_of_regval def
+R17440:17440 riscv_types <> v:113 var
+binder 17464:17464 <> v:114
+R17469:17494 riscv_types <> regval_of_bitvector_64_dec def
+R17496:17496 riscv_types <> v:114 var
+def 17515:17521 <> x22_ref
+R17531:17534 Sail.Values <> name proj
+R17531:17534 Sail.Values <> name proj
+R17548:17556 Sail.Values <> read_from proj
+R17583:17590 Sail.Values <> write_to proj
+R17635:17643 Sail.Values <> of_regval proj
+R17691:17699 Sail.Values <> regval_of proj
+binder 17566:17566 <> s:115
+R17574:17576 riscv_types <> x22 proj
+R17571:17571 riscv_types <> s:115 var
+binder 17600:17600 <> v:116
+binder 17602:17602 <> s:117
+R17608:17610 riscv_types <> :::'{['_x_'with'_'x22'_':='_x_']}' not
+R17612:17624 riscv_types <> :::'{['_x_'with'_'x22'_':='_x_']}' not
+R17626:17628 riscv_types <> :::'{['_x_'with'_'x22'_':='_x_']}' not
+R17611:17611 riscv_types <> s:117 var
+R17625:17625 riscv_types <> v:116 var
+binder 17653:17653 <> v:118
+R17658:17683 riscv_types <> bitvector_64_dec_of_regval def
+R17685:17685 riscv_types <> v:118 var
+binder 17709:17709 <> v:119
+R17714:17739 riscv_types <> regval_of_bitvector_64_dec def
+R17741:17741 riscv_types <> v:119 var
+def 17760:17766 <> x21_ref
+R17776:17779 Sail.Values <> name proj
+R17776:17779 Sail.Values <> name proj
+R17793:17801 Sail.Values <> read_from proj
+R17828:17835 Sail.Values <> write_to proj
+R17880:17888 Sail.Values <> of_regval proj
+R17936:17944 Sail.Values <> regval_of proj
+binder 17811:17811 <> s:120
+R17819:17821 riscv_types <> x21 proj
+R17816:17816 riscv_types <> s:120 var
+binder 17845:17845 <> v:121
+binder 17847:17847 <> s:122
+R17853:17855 riscv_types <> :::'{['_x_'with'_'x21'_':='_x_']}' not
+R17857:17869 riscv_types <> :::'{['_x_'with'_'x21'_':='_x_']}' not
+R17871:17873 riscv_types <> :::'{['_x_'with'_'x21'_':='_x_']}' not
+R17856:17856 riscv_types <> s:122 var
+R17870:17870 riscv_types <> v:121 var
+binder 17898:17898 <> v:123
+R17903:17928 riscv_types <> bitvector_64_dec_of_regval def
+R17930:17930 riscv_types <> v:123 var
+binder 17954:17954 <> v:124
+R17959:17984 riscv_types <> regval_of_bitvector_64_dec def
+R17986:17986 riscv_types <> v:124 var
+def 18005:18011 <> x20_ref
+R18021:18024 Sail.Values <> name proj
+R18021:18024 Sail.Values <> name proj
+R18038:18046 Sail.Values <> read_from proj
+R18073:18080 Sail.Values <> write_to proj
+R18125:18133 Sail.Values <> of_regval proj
+R18181:18189 Sail.Values <> regval_of proj
+binder 18056:18056 <> s:125
+R18064:18066 riscv_types <> x20 proj
+R18061:18061 riscv_types <> s:125 var
+binder 18090:18090 <> v:126
+binder 18092:18092 <> s:127
+R18098:18100 riscv_types <> :::'{['_x_'with'_'x20'_':='_x_']}' not
+R18102:18114 riscv_types <> :::'{['_x_'with'_'x20'_':='_x_']}' not
+R18116:18118 riscv_types <> :::'{['_x_'with'_'x20'_':='_x_']}' not
+R18101:18101 riscv_types <> s:127 var
+R18115:18115 riscv_types <> v:126 var
+binder 18143:18143 <> v:128
+R18148:18173 riscv_types <> bitvector_64_dec_of_regval def
+R18175:18175 riscv_types <> v:128 var
+binder 18199:18199 <> v:129
+R18204:18229 riscv_types <> regval_of_bitvector_64_dec def
+R18231:18231 riscv_types <> v:129 var
+def 18250:18256 <> x19_ref
+R18266:18269 Sail.Values <> name proj
+R18266:18269 Sail.Values <> name proj
+R18283:18291 Sail.Values <> read_from proj
+R18318:18325 Sail.Values <> write_to proj
+R18370:18378 Sail.Values <> of_regval proj
+R18426:18434 Sail.Values <> regval_of proj
+binder 18301:18301 <> s:130
+R18309:18311 riscv_types <> x19 proj
+R18306:18306 riscv_types <> s:130 var
+binder 18335:18335 <> v:131
+binder 18337:18337 <> s:132
+R18343:18345 riscv_types <> :::'{['_x_'with'_'x19'_':='_x_']}' not
+R18347:18359 riscv_types <> :::'{['_x_'with'_'x19'_':='_x_']}' not
+R18361:18363 riscv_types <> :::'{['_x_'with'_'x19'_':='_x_']}' not
+R18346:18346 riscv_types <> s:132 var
+R18360:18360 riscv_types <> v:131 var
+binder 18388:18388 <> v:133
+R18393:18418 riscv_types <> bitvector_64_dec_of_regval def
+R18420:18420 riscv_types <> v:133 var
+binder 18444:18444 <> v:134
+R18449:18474 riscv_types <> regval_of_bitvector_64_dec def
+R18476:18476 riscv_types <> v:134 var
+def 18495:18501 <> x18_ref
+R18511:18514 Sail.Values <> name proj
+R18511:18514 Sail.Values <> name proj
+R18528:18536 Sail.Values <> read_from proj
+R18563:18570 Sail.Values <> write_to proj
+R18615:18623 Sail.Values <> of_regval proj
+R18671:18679 Sail.Values <> regval_of proj
+binder 18546:18546 <> s:135
+R18554:18556 riscv_types <> x18 proj
+R18551:18551 riscv_types <> s:135 var
+binder 18580:18580 <> v:136
+binder 18582:18582 <> s:137
+R18588:18590 riscv_types <> :::'{['_x_'with'_'x18'_':='_x_']}' not
+R18592:18604 riscv_types <> :::'{['_x_'with'_'x18'_':='_x_']}' not
+R18606:18608 riscv_types <> :::'{['_x_'with'_'x18'_':='_x_']}' not
+R18591:18591 riscv_types <> s:137 var
+R18605:18605 riscv_types <> v:136 var
+binder 18633:18633 <> v:138
+R18638:18663 riscv_types <> bitvector_64_dec_of_regval def
+R18665:18665 riscv_types <> v:138 var
+binder 18689:18689 <> v:139
+R18694:18719 riscv_types <> regval_of_bitvector_64_dec def
+R18721:18721 riscv_types <> v:139 var
+def 18740:18746 <> x17_ref
+R18756:18759 Sail.Values <> name proj
+R18756:18759 Sail.Values <> name proj
+R18773:18781 Sail.Values <> read_from proj
+R18808:18815 Sail.Values <> write_to proj
+R18860:18868 Sail.Values <> of_regval proj
+R18916:18924 Sail.Values <> regval_of proj
+binder 18791:18791 <> s:140
+R18799:18801 riscv_types <> x17 proj
+R18796:18796 riscv_types <> s:140 var
+binder 18825:18825 <> v:141
+binder 18827:18827 <> s:142
+R18833:18835 riscv_types <> :::'{['_x_'with'_'x17'_':='_x_']}' not
+R18837:18849 riscv_types <> :::'{['_x_'with'_'x17'_':='_x_']}' not
+R18851:18853 riscv_types <> :::'{['_x_'with'_'x17'_':='_x_']}' not
+R18836:18836 riscv_types <> s:142 var
+R18850:18850 riscv_types <> v:141 var
+binder 18878:18878 <> v:143
+R18883:18908 riscv_types <> bitvector_64_dec_of_regval def
+R18910:18910 riscv_types <> v:143 var
+binder 18934:18934 <> v:144
+R18939:18964 riscv_types <> regval_of_bitvector_64_dec def
+R18966:18966 riscv_types <> v:144 var
+def 18985:18991 <> x16_ref
+R19001:19004 Sail.Values <> name proj
+R19001:19004 Sail.Values <> name proj
+R19018:19026 Sail.Values <> read_from proj
+R19053:19060 Sail.Values <> write_to proj
+R19105:19113 Sail.Values <> of_regval proj
+R19161:19169 Sail.Values <> regval_of proj
+binder 19036:19036 <> s:145
+R19044:19046 riscv_types <> x16 proj
+R19041:19041 riscv_types <> s:145 var
+binder 19070:19070 <> v:146
+binder 19072:19072 <> s:147
+R19078:19080 riscv_types <> :::'{['_x_'with'_'x16'_':='_x_']}' not
+R19082:19094 riscv_types <> :::'{['_x_'with'_'x16'_':='_x_']}' not
+R19096:19098 riscv_types <> :::'{['_x_'with'_'x16'_':='_x_']}' not
+R19081:19081 riscv_types <> s:147 var
+R19095:19095 riscv_types <> v:146 var
+binder 19123:19123 <> v:148
+R19128:19153 riscv_types <> bitvector_64_dec_of_regval def
+R19155:19155 riscv_types <> v:148 var
+binder 19179:19179 <> v:149
+R19184:19209 riscv_types <> regval_of_bitvector_64_dec def
+R19211:19211 riscv_types <> v:149 var
+def 19230:19236 <> x15_ref
+R19246:19249 Sail.Values <> name proj
+R19246:19249 Sail.Values <> name proj
+R19263:19271 Sail.Values <> read_from proj
+R19298:19305 Sail.Values <> write_to proj
+R19350:19358 Sail.Values <> of_regval proj
+R19406:19414 Sail.Values <> regval_of proj
+binder 19281:19281 <> s:150
+R19289:19291 riscv_types <> x15 proj
+R19286:19286 riscv_types <> s:150 var
+binder 19315:19315 <> v:151
+binder 19317:19317 <> s:152
+R19323:19325 riscv_types <> :::'{['_x_'with'_'x15'_':='_x_']}' not
+R19327:19339 riscv_types <> :::'{['_x_'with'_'x15'_':='_x_']}' not
+R19341:19343 riscv_types <> :::'{['_x_'with'_'x15'_':='_x_']}' not
+R19326:19326 riscv_types <> s:152 var
+R19340:19340 riscv_types <> v:151 var
+binder 19368:19368 <> v:153
+R19373:19398 riscv_types <> bitvector_64_dec_of_regval def
+R19400:19400 riscv_types <> v:153 var
+binder 19424:19424 <> v:154
+R19429:19454 riscv_types <> regval_of_bitvector_64_dec def
+R19456:19456 riscv_types <> v:154 var
+def 19475:19481 <> x14_ref
+R19491:19494 Sail.Values <> name proj
+R19491:19494 Sail.Values <> name proj
+R19508:19516 Sail.Values <> read_from proj
+R19543:19550 Sail.Values <> write_to proj
+R19595:19603 Sail.Values <> of_regval proj
+R19651:19659 Sail.Values <> regval_of proj
+binder 19526:19526 <> s:155
+R19534:19536 riscv_types <> x14 proj
+R19531:19531 riscv_types <> s:155 var
+binder 19560:19560 <> v:156
+binder 19562:19562 <> s:157
+R19568:19570 riscv_types <> :::'{['_x_'with'_'x14'_':='_x_']}' not
+R19572:19584 riscv_types <> :::'{['_x_'with'_'x14'_':='_x_']}' not
+R19586:19588 riscv_types <> :::'{['_x_'with'_'x14'_':='_x_']}' not
+R19571:19571 riscv_types <> s:157 var
+R19585:19585 riscv_types <> v:156 var
+binder 19613:19613 <> v:158
+R19618:19643 riscv_types <> bitvector_64_dec_of_regval def
+R19645:19645 riscv_types <> v:158 var
+binder 19669:19669 <> v:159
+R19674:19699 riscv_types <> regval_of_bitvector_64_dec def
+R19701:19701 riscv_types <> v:159 var
+def 19720:19726 <> x13_ref
+R19736:19739 Sail.Values <> name proj
+R19736:19739 Sail.Values <> name proj
+R19753:19761 Sail.Values <> read_from proj
+R19788:19795 Sail.Values <> write_to proj
+R19840:19848 Sail.Values <> of_regval proj
+R19896:19904 Sail.Values <> regval_of proj
+binder 19771:19771 <> s:160
+R19779:19781 riscv_types <> x13 proj
+R19776:19776 riscv_types <> s:160 var
+binder 19805:19805 <> v:161
+binder 19807:19807 <> s:162
+R19813:19815 riscv_types <> :::'{['_x_'with'_'x13'_':='_x_']}' not
+R19817:19829 riscv_types <> :::'{['_x_'with'_'x13'_':='_x_']}' not
+R19831:19833 riscv_types <> :::'{['_x_'with'_'x13'_':='_x_']}' not
+R19816:19816 riscv_types <> s:162 var
+R19830:19830 riscv_types <> v:161 var
+binder 19858:19858 <> v:163
+R19863:19888 riscv_types <> bitvector_64_dec_of_regval def
+R19890:19890 riscv_types <> v:163 var
+binder 19914:19914 <> v:164
+R19919:19944 riscv_types <> regval_of_bitvector_64_dec def
+R19946:19946 riscv_types <> v:164 var
+def 19965:19971 <> x12_ref
+R19981:19984 Sail.Values <> name proj
+R19981:19984 Sail.Values <> name proj
+R19998:20006 Sail.Values <> read_from proj
+R20033:20040 Sail.Values <> write_to proj
+R20085:20093 Sail.Values <> of_regval proj
+R20141:20149 Sail.Values <> regval_of proj
+binder 20016:20016 <> s:165
+R20024:20026 riscv_types <> x12 proj
+R20021:20021 riscv_types <> s:165 var
+binder 20050:20050 <> v:166
+binder 20052:20052 <> s:167
+R20058:20060 riscv_types <> :::'{['_x_'with'_'x12'_':='_x_']}' not
+R20062:20074 riscv_types <> :::'{['_x_'with'_'x12'_':='_x_']}' not
+R20076:20078 riscv_types <> :::'{['_x_'with'_'x12'_':='_x_']}' not
+R20061:20061 riscv_types <> s:167 var
+R20075:20075 riscv_types <> v:166 var
+binder 20103:20103 <> v:168
+R20108:20133 riscv_types <> bitvector_64_dec_of_regval def
+R20135:20135 riscv_types <> v:168 var
+binder 20159:20159 <> v:169
+R20164:20189 riscv_types <> regval_of_bitvector_64_dec def
+R20191:20191 riscv_types <> v:169 var
+def 20210:20216 <> x11_ref
+R20226:20229 Sail.Values <> name proj
+R20226:20229 Sail.Values <> name proj
+R20243:20251 Sail.Values <> read_from proj
+R20278:20285 Sail.Values <> write_to proj
+R20330:20338 Sail.Values <> of_regval proj
+R20386:20394 Sail.Values <> regval_of proj
+binder 20261:20261 <> s:170
+R20269:20271 riscv_types <> x11 proj
+R20266:20266 riscv_types <> s:170 var
+binder 20295:20295 <> v:171
+binder 20297:20297 <> s:172
+R20303:20305 riscv_types <> :::'{['_x_'with'_'x11'_':='_x_']}' not
+R20307:20319 riscv_types <> :::'{['_x_'with'_'x11'_':='_x_']}' not
+R20321:20323 riscv_types <> :::'{['_x_'with'_'x11'_':='_x_']}' not
+R20306:20306 riscv_types <> s:172 var
+R20320:20320 riscv_types <> v:171 var
+binder 20348:20348 <> v:173
+R20353:20378 riscv_types <> bitvector_64_dec_of_regval def
+R20380:20380 riscv_types <> v:173 var
+binder 20404:20404 <> v:174
+R20409:20434 riscv_types <> regval_of_bitvector_64_dec def
+R20436:20436 riscv_types <> v:174 var
+def 20455:20461 <> x10_ref
+R20471:20474 Sail.Values <> name proj
+R20471:20474 Sail.Values <> name proj
+R20488:20496 Sail.Values <> read_from proj
+R20523:20530 Sail.Values <> write_to proj
+R20575:20583 Sail.Values <> of_regval proj
+R20631:20639 Sail.Values <> regval_of proj
+binder 20506:20506 <> s:175
+R20514:20516 riscv_types <> x10 proj
+R20511:20511 riscv_types <> s:175 var
+binder 20540:20540 <> v:176
+binder 20542:20542 <> s:177
+R20548:20550 riscv_types <> :::'{['_x_'with'_'x10'_':='_x_']}' not
+R20552:20564 riscv_types <> :::'{['_x_'with'_'x10'_':='_x_']}' not
+R20566:20568 riscv_types <> :::'{['_x_'with'_'x10'_':='_x_']}' not
+R20551:20551 riscv_types <> s:177 var
+R20565:20565 riscv_types <> v:176 var
+binder 20593:20593 <> v:178
+R20598:20623 riscv_types <> bitvector_64_dec_of_regval def
+R20625:20625 riscv_types <> v:178 var
+binder 20649:20649 <> v:179
+R20654:20679 riscv_types <> regval_of_bitvector_64_dec def
+R20681:20681 riscv_types <> v:179 var
+def 20700:20705 <> x9_ref
+R20715:20718 Sail.Values <> name proj
+R20715:20718 Sail.Values <> name proj
+R20731:20739 Sail.Values <> read_from proj
+R20765:20772 Sail.Values <> write_to proj
+R20816:20824 Sail.Values <> of_regval proj
+R20872:20880 Sail.Values <> regval_of proj
+binder 20749:20749 <> s:180
+R20757:20758 riscv_types <> x9 proj
+R20754:20754 riscv_types <> s:180 var
+binder 20782:20782 <> v:181
+binder 20784:20784 <> s:182
+R20790:20792 riscv_types <> :::'{['_x_'with'_'x9'_':='_x_']}' not
+R20794:20805 riscv_types <> :::'{['_x_'with'_'x9'_':='_x_']}' not
+R20807:20809 riscv_types <> :::'{['_x_'with'_'x9'_':='_x_']}' not
+R20793:20793 riscv_types <> s:182 var
+R20806:20806 riscv_types <> v:181 var
+binder 20834:20834 <> v:183
+R20839:20864 riscv_types <> bitvector_64_dec_of_regval def
+R20866:20866 riscv_types <> v:183 var
+binder 20890:20890 <> v:184
+R20895:20920 riscv_types <> regval_of_bitvector_64_dec def
+R20922:20922 riscv_types <> v:184 var
+def 20941:20946 <> x8_ref
+R20956:20959 Sail.Values <> name proj
+R20956:20959 Sail.Values <> name proj
+R20972:20980 Sail.Values <> read_from proj
+R21006:21013 Sail.Values <> write_to proj
+R21057:21065 Sail.Values <> of_regval proj
+R21113:21121 Sail.Values <> regval_of proj
+binder 20990:20990 <> s:185
+R20998:20999 riscv_types <> x8 proj
+R20995:20995 riscv_types <> s:185 var
+binder 21023:21023 <> v:186
+binder 21025:21025 <> s:187
+R21031:21033 riscv_types <> :::'{['_x_'with'_'x8'_':='_x_']}' not
+R21035:21046 riscv_types <> :::'{['_x_'with'_'x8'_':='_x_']}' not
+R21048:21050 riscv_types <> :::'{['_x_'with'_'x8'_':='_x_']}' not
+R21034:21034 riscv_types <> s:187 var
+R21047:21047 riscv_types <> v:186 var
+binder 21075:21075 <> v:188
+R21080:21105 riscv_types <> bitvector_64_dec_of_regval def
+R21107:21107 riscv_types <> v:188 var
+binder 21131:21131 <> v:189
+R21136:21161 riscv_types <> regval_of_bitvector_64_dec def
+R21163:21163 riscv_types <> v:189 var
+def 21182:21187 <> x7_ref
+R21197:21200 Sail.Values <> name proj
+R21197:21200 Sail.Values <> name proj
+R21213:21221 Sail.Values <> read_from proj
+R21247:21254 Sail.Values <> write_to proj
+R21298:21306 Sail.Values <> of_regval proj
+R21354:21362 Sail.Values <> regval_of proj
+binder 21231:21231 <> s:190
+R21239:21240 riscv_types <> x7 proj
+R21236:21236 riscv_types <> s:190 var
+binder 21264:21264 <> v:191
+binder 21266:21266 <> s:192
+R21272:21274 riscv_types <> :::'{['_x_'with'_'x7'_':='_x_']}' not
+R21276:21287 riscv_types <> :::'{['_x_'with'_'x7'_':='_x_']}' not
+R21289:21291 riscv_types <> :::'{['_x_'with'_'x7'_':='_x_']}' not
+R21275:21275 riscv_types <> s:192 var
+R21288:21288 riscv_types <> v:191 var
+binder 21316:21316 <> v:193
+R21321:21346 riscv_types <> bitvector_64_dec_of_regval def
+R21348:21348 riscv_types <> v:193 var
+binder 21372:21372 <> v:194
+R21377:21402 riscv_types <> regval_of_bitvector_64_dec def
+R21404:21404 riscv_types <> v:194 var
+def 21423:21428 <> x6_ref
+R21438:21441 Sail.Values <> name proj
+R21438:21441 Sail.Values <> name proj
+R21454:21462 Sail.Values <> read_from proj
+R21488:21495 Sail.Values <> write_to proj
+R21539:21547 Sail.Values <> of_regval proj
+R21595:21603 Sail.Values <> regval_of proj
+binder 21472:21472 <> s:195
+R21480:21481 riscv_types <> x6 proj
+R21477:21477 riscv_types <> s:195 var
+binder 21505:21505 <> v:196
+binder 21507:21507 <> s:197
+R21513:21515 riscv_types <> :::'{['_x_'with'_'x6'_':='_x_']}' not
+R21517:21528 riscv_types <> :::'{['_x_'with'_'x6'_':='_x_']}' not
+R21530:21532 riscv_types <> :::'{['_x_'with'_'x6'_':='_x_']}' not
+R21516:21516 riscv_types <> s:197 var
+R21529:21529 riscv_types <> v:196 var
+binder 21557:21557 <> v:198
+R21562:21587 riscv_types <> bitvector_64_dec_of_regval def
+R21589:21589 riscv_types <> v:198 var
+binder 21613:21613 <> v:199
+R21618:21643 riscv_types <> regval_of_bitvector_64_dec def
+R21645:21645 riscv_types <> v:199 var
+def 21664:21669 <> x5_ref
+R21679:21682 Sail.Values <> name proj
+R21679:21682 Sail.Values <> name proj
+R21695:21703 Sail.Values <> read_from proj
+R21729:21736 Sail.Values <> write_to proj
+R21780:21788 Sail.Values <> of_regval proj
+R21836:21844 Sail.Values <> regval_of proj
+binder 21713:21713 <> s:200
+R21721:21722 riscv_types <> x5 proj
+R21718:21718 riscv_types <> s:200 var
+binder 21746:21746 <> v:201
+binder 21748:21748 <> s:202
+R21754:21756 riscv_types <> :::'{['_x_'with'_'x5'_':='_x_']}' not
+R21758:21769 riscv_types <> :::'{['_x_'with'_'x5'_':='_x_']}' not
+R21771:21773 riscv_types <> :::'{['_x_'with'_'x5'_':='_x_']}' not
+R21757:21757 riscv_types <> s:202 var
+R21770:21770 riscv_types <> v:201 var
+binder 21798:21798 <> v:203
+R21803:21828 riscv_types <> bitvector_64_dec_of_regval def
+R21830:21830 riscv_types <> v:203 var
+binder 21854:21854 <> v:204
+R21859:21884 riscv_types <> regval_of_bitvector_64_dec def
+R21886:21886 riscv_types <> v:204 var
+def 21905:21910 <> x4_ref
+R21920:21923 Sail.Values <> name proj
+R21920:21923 Sail.Values <> name proj
+R21936:21944 Sail.Values <> read_from proj
+R21970:21977 Sail.Values <> write_to proj
+R22021:22029 Sail.Values <> of_regval proj
+R22077:22085 Sail.Values <> regval_of proj
+binder 21954:21954 <> s:205
+R21962:21963 riscv_types <> x4 proj
+R21959:21959 riscv_types <> s:205 var
+binder 21987:21987 <> v:206
+binder 21989:21989 <> s:207
+R21995:21997 riscv_types <> :::'{['_x_'with'_'x4'_':='_x_']}' not
+R21999:22010 riscv_types <> :::'{['_x_'with'_'x4'_':='_x_']}' not
+R22012:22014 riscv_types <> :::'{['_x_'with'_'x4'_':='_x_']}' not
+R21998:21998 riscv_types <> s:207 var
+R22011:22011 riscv_types <> v:206 var
+binder 22039:22039 <> v:208
+R22044:22069 riscv_types <> bitvector_64_dec_of_regval def
+R22071:22071 riscv_types <> v:208 var
+binder 22095:22095 <> v:209
+R22100:22125 riscv_types <> regval_of_bitvector_64_dec def
+R22127:22127 riscv_types <> v:209 var
+def 22146:22151 <> x3_ref
+R22161:22164 Sail.Values <> name proj
+R22161:22164 Sail.Values <> name proj
+R22177:22185 Sail.Values <> read_from proj
+R22211:22218 Sail.Values <> write_to proj
+R22262:22270 Sail.Values <> of_regval proj
+R22318:22326 Sail.Values <> regval_of proj
+binder 22195:22195 <> s:210
+R22203:22204 riscv_types <> x3 proj
+R22200:22200 riscv_types <> s:210 var
+binder 22228:22228 <> v:211
+binder 22230:22230 <> s:212
+R22236:22238 riscv_types <> :::'{['_x_'with'_'x3'_':='_x_']}' not
+R22240:22251 riscv_types <> :::'{['_x_'with'_'x3'_':='_x_']}' not
+R22253:22255 riscv_types <> :::'{['_x_'with'_'x3'_':='_x_']}' not
+R22239:22239 riscv_types <> s:212 var
+R22252:22252 riscv_types <> v:211 var
+binder 22280:22280 <> v:213
+R22285:22310 riscv_types <> bitvector_64_dec_of_regval def
+R22312:22312 riscv_types <> v:213 var
+binder 22336:22336 <> v:214
+R22341:22366 riscv_types <> regval_of_bitvector_64_dec def
+R22368:22368 riscv_types <> v:214 var
+def 22387:22392 <> x2_ref
+R22402:22405 Sail.Values <> name proj
+R22402:22405 Sail.Values <> name proj
+R22418:22426 Sail.Values <> read_from proj
+R22452:22459 Sail.Values <> write_to proj
+R22503:22511 Sail.Values <> of_regval proj
+R22559:22567 Sail.Values <> regval_of proj
+binder 22436:22436 <> s:215
+R22444:22445 riscv_types <> x2 proj
+R22441:22441 riscv_types <> s:215 var
+binder 22469:22469 <> v:216
+binder 22471:22471 <> s:217
+R22477:22479 riscv_types <> :::'{['_x_'with'_'x2'_':='_x_']}' not
+R22481:22492 riscv_types <> :::'{['_x_'with'_'x2'_':='_x_']}' not
+R22494:22496 riscv_types <> :::'{['_x_'with'_'x2'_':='_x_']}' not
+R22480:22480 riscv_types <> s:217 var
+R22493:22493 riscv_types <> v:216 var
+binder 22521:22521 <> v:218
+R22526:22551 riscv_types <> bitvector_64_dec_of_regval def
+R22553:22553 riscv_types <> v:218 var
+binder 22577:22577 <> v:219
+R22582:22607 riscv_types <> regval_of_bitvector_64_dec def
+R22609:22609 riscv_types <> v:219 var
+def 22628:22633 <> x1_ref
+R22643:22646 Sail.Values <> name proj
+R22643:22646 Sail.Values <> name proj
+R22659:22667 Sail.Values <> read_from proj
+R22693:22700 Sail.Values <> write_to proj
+R22744:22752 Sail.Values <> of_regval proj
+R22800:22808 Sail.Values <> regval_of proj
+binder 22677:22677 <> s:220
+R22685:22686 riscv_types <> x1 proj
+R22682:22682 riscv_types <> s:220 var
+binder 22710:22710 <> v:221
+binder 22712:22712 <> s:222
+R22718:22720 riscv_types <> :::'{['_x_'with'_'x1'_':='_x_']}' not
+R22722:22733 riscv_types <> :::'{['_x_'with'_'x1'_':='_x_']}' not
+R22735:22737 riscv_types <> :::'{['_x_'with'_'x1'_':='_x_']}' not
+R22721:22721 riscv_types <> s:222 var
+R22734:22734 riscv_types <> v:221 var
+binder 22762:22762 <> v:223
+R22767:22792 riscv_types <> bitvector_64_dec_of_regval def
+R22794:22794 riscv_types <> v:223 var
+binder 22818:22818 <> v:224
+R22823:22848 riscv_types <> regval_of_bitvector_64_dec def
+R22850:22850 riscv_types <> v:224 var
+def 22869:22880 <> instbits_ref
+R22890:22893 Sail.Values <> name proj
+R22890:22893 Sail.Values <> name proj
+R22912:22920 Sail.Values <> read_from proj
+R22952:22959 Sail.Values <> write_to proj
+R23009:23017 Sail.Values <> of_regval proj
+R23065:23073 Sail.Values <> regval_of proj
+binder 22930:22930 <> s:225
+R22938:22945 riscv_types <> instbits proj
+R22935:22935 riscv_types <> s:225 var
+binder 22969:22969 <> v:226
+binder 22971:22971 <> s:227
+R22977:22979 riscv_types <> :::'{['_x_'with'_'instbits'_':='_x_']}' not
+R22981:22998 riscv_types <> :::'{['_x_'with'_'instbits'_':='_x_']}' not
+R23000:23002 riscv_types <> :::'{['_x_'with'_'instbits'_':='_x_']}' not
+R22980:22980 riscv_types <> s:227 var
+R22999:22999 riscv_types <> v:226 var
+binder 23027:23027 <> v:228
+R23032:23057 riscv_types <> bitvector_64_dec_of_regval def
+R23059:23059 riscv_types <> v:228 var
+binder 23083:23083 <> v:229
+R23088:23113 riscv_types <> regval_of_bitvector_64_dec def
+R23115:23115 riscv_types <> v:229 var
+def 23134:23143 <> nextPC_ref
+R23153:23156 Sail.Values <> name proj
+R23153:23156 Sail.Values <> name proj
+R23173:23181 Sail.Values <> read_from proj
+R23211:23218 Sail.Values <> write_to proj
+R23266:23274 Sail.Values <> of_regval proj
+R23322:23330 Sail.Values <> regval_of proj
+binder 23191:23191 <> s:230
+R23199:23204 riscv_types <> nextPC proj
+R23196:23196 riscv_types <> s:230 var
+binder 23228:23228 <> v:231
+binder 23230:23230 <> s:232
+R23236:23238 riscv_types <> :::'{['_x_'with'_'nextPC'_':='_x_']}' not
+R23240:23255 riscv_types <> :::'{['_x_'with'_'nextPC'_':='_x_']}' not
+R23257:23259 riscv_types <> :::'{['_x_'with'_'nextPC'_':='_x_']}' not
+R23239:23239 riscv_types <> s:232 var
+R23256:23256 riscv_types <> v:231 var
+binder 23284:23284 <> v:233
+R23289:23314 riscv_types <> bitvector_64_dec_of_regval def
+R23316:23316 riscv_types <> v:233 var
+binder 23340:23340 <> v:234
+R23345:23370 riscv_types <> regval_of_bitvector_64_dec def
+R23372:23372 riscv_types <> v:234 var
+def 23391:23396 <> PC_ref
+R23406:23409 Sail.Values <> name proj
+R23406:23409 Sail.Values <> name proj
+R23422:23430 Sail.Values <> read_from proj
+R23456:23463 Sail.Values <> write_to proj
+R23507:23515 Sail.Values <> of_regval proj
+R23563:23571 Sail.Values <> regval_of proj
+binder 23440:23440 <> s:235
+R23448:23449 riscv_types <> PC proj
+R23445:23445 riscv_types <> s:235 var
+binder 23473:23473 <> v:236
+binder 23475:23475 <> s:237
+R23481:23483 riscv_types <> :::'{['_x_'with'_'PC'_':='_x_']}' not
+R23485:23496 riscv_types <> :::'{['_x_'with'_'PC'_':='_x_']}' not
+R23498:23500 riscv_types <> :::'{['_x_'with'_'PC'_':='_x_']}' not
+R23484:23484 riscv_types <> s:237 var
+R23497:23497 riscv_types <> v:236 var
+binder 23525:23525 <> v:238
+R23530:23555 riscv_types <> bitvector_64_dec_of_regval def
+R23557:23557 riscv_types <> v:238 var
+binder 23581:23581 <> v:239
+R23586:23611 riscv_types <> regval_of_bitvector_64_dec def
+R23613:23613 riscv_types <> v:239 var
+def 23657:23666 <> get_regval
+R23680:23685 Coq.Strings.String <> string ind
+binder 23669:23676 <> reg_name:240
+R23693:23700 riscv_types <> regstate rec
+binder 23689:23689 <> s:241
+R23705:23710 Coq.Init.Datatypes <> option ind
+R23712:23725 riscv_types <> register_value ind
+R23735:23744 Coq.Strings.String <> string_dec def
+R23746:23753 riscv_types <> reg_name:240 var
+R23827:23836 Coq.Strings.String <> string_dec def
+R23838:23845 riscv_types <> reg_name:240 var
+R23919:23928 Coq.Strings.String <> string_dec def
+R23930:23937 riscv_types <> reg_name:240 var
+R24011:24020 Coq.Strings.String <> string_dec def
+R24022:24029 riscv_types <> reg_name:240 var
+R24103:24112 Coq.Strings.String <> string_dec def
+R24114:24121 riscv_types <> reg_name:240 var
+R24195:24204 Coq.Strings.String <> string_dec def
+R24206:24213 riscv_types <> reg_name:240 var
+R24287:24296 Coq.Strings.String <> string_dec def
+R24298:24305 riscv_types <> reg_name:240 var
+R24379:24388 Coq.Strings.String <> string_dec def
+R24390:24397 riscv_types <> reg_name:240 var
+R24471:24480 Coq.Strings.String <> string_dec def
+R24482:24489 riscv_types <> reg_name:240 var
+R24563:24572 Coq.Strings.String <> string_dec def
+R24574:24581 riscv_types <> reg_name:240 var
+R24655:24664 Coq.Strings.String <> string_dec def
+R24666:24673 riscv_types <> reg_name:240 var
+R24747:24756 Coq.Strings.String <> string_dec def
+R24758:24765 riscv_types <> reg_name:240 var
+R24839:24848 Coq.Strings.String <> string_dec def
+R24850:24857 riscv_types <> reg_name:240 var
+R24931:24940 Coq.Strings.String <> string_dec def
+R24942:24949 riscv_types <> reg_name:240 var
+R25023:25032 Coq.Strings.String <> string_dec def
+R25034:25041 riscv_types <> reg_name:240 var
+R25115:25124 Coq.Strings.String <> string_dec def
+R25126:25133 riscv_types <> reg_name:240 var
+R25207:25216 Coq.Strings.String <> string_dec def
+R25218:25225 riscv_types <> reg_name:240 var
+R25299:25308 Coq.Strings.String <> string_dec def
+R25310:25317 riscv_types <> reg_name:240 var
+R25391:25400 Coq.Strings.String <> string_dec def
+R25402:25409 riscv_types <> reg_name:240 var
+R25483:25492 Coq.Strings.String <> string_dec def
+R25494:25501 riscv_types <> reg_name:240 var
+R25575:25584 Coq.Strings.String <> string_dec def
+R25586:25593 riscv_types <> reg_name:240 var
+R25667:25676 Coq.Strings.String <> string_dec def
+R25678:25685 riscv_types <> reg_name:240 var
+R25759:25768 Coq.Strings.String <> string_dec def
+R25770:25777 riscv_types <> reg_name:240 var
+R25848:25857 Coq.Strings.String <> string_dec def
+R25859:25866 riscv_types <> reg_name:240 var
+R25937:25946 Coq.Strings.String <> string_dec def
+R25948:25955 riscv_types <> reg_name:240 var
+R26026:26035 Coq.Strings.String <> string_dec def
+R26037:26044 riscv_types <> reg_name:240 var
+R26115:26124 Coq.Strings.String <> string_dec def
+R26126:26133 riscv_types <> reg_name:240 var
+R26204:26213 Coq.Strings.String <> string_dec def
+R26215:26222 riscv_types <> reg_name:240 var
+R26293:26302 Coq.Strings.String <> string_dec def
+R26304:26311 riscv_types <> reg_name:240 var
+R26382:26391 Coq.Strings.String <> string_dec def
+R26393:26400 riscv_types <> reg_name:240 var
+R26471:26480 Coq.Strings.String <> string_dec def
+R26482:26489 riscv_types <> reg_name:240 var
+R26560:26569 Coq.Strings.String <> string_dec def
+R26571:26578 riscv_types <> reg_name:240 var
+R26667:26676 Coq.Strings.String <> string_dec def
+R26678:26685 riscv_types <> reg_name:240 var
+R26768:26777 Coq.Strings.String <> string_dec def
+R26779:26786 riscv_types <> reg_name:240 var
+R26854:26857 Coq.Init.Datatypes <> None constr
+R26798:26801 Coq.Init.Datatypes <> Some constr
+R26812:26820 Sail.Values <> regval_of proj
+R26832:26840 Sail.Values <> read_from proj
+R26843:26843 riscv_types <> s:241 var
+R26824:26829 riscv_types <> PC_ref def
+R26804:26809 riscv_types <> PC_ref def
+R26701:26704 Coq.Init.Datatypes <> Some constr
+R26719:26727 Sail.Values <> regval_of proj
+R26743:26751 Sail.Values <> read_from proj
+R26754:26754 riscv_types <> s:241 var
+R26731:26740 riscv_types <> nextPC_ref def
+R26707:26716 riscv_types <> nextPC_ref def
+R26596:26599 Coq.Init.Datatypes <> Some constr
+R26616:26624 Sail.Values <> regval_of proj
+R26642:26650 Sail.Values <> read_from proj
+R26653:26653 riscv_types <> s:241 var
+R26628:26639 riscv_types <> instbits_ref def
+R26602:26613 riscv_types <> instbits_ref def
+R26501:26504 Coq.Init.Datatypes <> Some constr
+R26515:26523 Sail.Values <> regval_of proj
+R26535:26543 Sail.Values <> read_from proj
+R26546:26546 riscv_types <> s:241 var
+R26527:26532 riscv_types <> x1_ref def
+R26507:26512 riscv_types <> x1_ref def
+R26412:26415 Coq.Init.Datatypes <> Some constr
+R26426:26434 Sail.Values <> regval_of proj
+R26446:26454 Sail.Values <> read_from proj
+R26457:26457 riscv_types <> s:241 var
+R26438:26443 riscv_types <> x2_ref def
+R26418:26423 riscv_types <> x2_ref def
+R26323:26326 Coq.Init.Datatypes <> Some constr
+R26337:26345 Sail.Values <> regval_of proj
+R26357:26365 Sail.Values <> read_from proj
+R26368:26368 riscv_types <> s:241 var
+R26349:26354 riscv_types <> x3_ref def
+R26329:26334 riscv_types <> x3_ref def
+R26234:26237 Coq.Init.Datatypes <> Some constr
+R26248:26256 Sail.Values <> regval_of proj
+R26268:26276 Sail.Values <> read_from proj
+R26279:26279 riscv_types <> s:241 var
+R26260:26265 riscv_types <> x4_ref def
+R26240:26245 riscv_types <> x4_ref def
+R26145:26148 Coq.Init.Datatypes <> Some constr
+R26159:26167 Sail.Values <> regval_of proj
+R26179:26187 Sail.Values <> read_from proj
+R26190:26190 riscv_types <> s:241 var
+R26171:26176 riscv_types <> x5_ref def
+R26151:26156 riscv_types <> x5_ref def
+R26056:26059 Coq.Init.Datatypes <> Some constr
+R26070:26078 Sail.Values <> regval_of proj
+R26090:26098 Sail.Values <> read_from proj
+R26101:26101 riscv_types <> s:241 var
+R26082:26087 riscv_types <> x6_ref def
+R26062:26067 riscv_types <> x6_ref def
+R25967:25970 Coq.Init.Datatypes <> Some constr
+R25981:25989 Sail.Values <> regval_of proj
+R26001:26009 Sail.Values <> read_from proj
+R26012:26012 riscv_types <> s:241 var
+R25993:25998 riscv_types <> x7_ref def
+R25973:25978 riscv_types <> x7_ref def
+R25878:25881 Coq.Init.Datatypes <> Some constr
+R25892:25900 Sail.Values <> regval_of proj
+R25912:25920 Sail.Values <> read_from proj
+R25923:25923 riscv_types <> s:241 var
+R25904:25909 riscv_types <> x8_ref def
+R25884:25889 riscv_types <> x8_ref def
+R25789:25792 Coq.Init.Datatypes <> Some constr
+R25803:25811 Sail.Values <> regval_of proj
+R25823:25831 Sail.Values <> read_from proj
+R25834:25834 riscv_types <> s:241 var
+R25815:25820 riscv_types <> x9_ref def
+R25795:25800 riscv_types <> x9_ref def
+R25698:25701 Coq.Init.Datatypes <> Some constr
+R25713:25721 Sail.Values <> regval_of proj
+R25734:25742 Sail.Values <> read_from proj
+R25745:25745 riscv_types <> s:241 var
+R25725:25731 riscv_types <> x10_ref def
+R25704:25710 riscv_types <> x10_ref def
+R25606:25609 Coq.Init.Datatypes <> Some constr
+R25621:25629 Sail.Values <> regval_of proj
+R25642:25650 Sail.Values <> read_from proj
+R25653:25653 riscv_types <> s:241 var
+R25633:25639 riscv_types <> x11_ref def
+R25612:25618 riscv_types <> x11_ref def
+R25514:25517 Coq.Init.Datatypes <> Some constr
+R25529:25537 Sail.Values <> regval_of proj
+R25550:25558 Sail.Values <> read_from proj
+R25561:25561 riscv_types <> s:241 var
+R25541:25547 riscv_types <> x12_ref def
+R25520:25526 riscv_types <> x12_ref def
+R25422:25425 Coq.Init.Datatypes <> Some constr
+R25437:25445 Sail.Values <> regval_of proj
+R25458:25466 Sail.Values <> read_from proj
+R25469:25469 riscv_types <> s:241 var
+R25449:25455 riscv_types <> x13_ref def
+R25428:25434 riscv_types <> x13_ref def
+R25330:25333 Coq.Init.Datatypes <> Some constr
+R25345:25353 Sail.Values <> regval_of proj
+R25366:25374 Sail.Values <> read_from proj
+R25377:25377 riscv_types <> s:241 var
+R25357:25363 riscv_types <> x14_ref def
+R25336:25342 riscv_types <> x14_ref def
+R25238:25241 Coq.Init.Datatypes <> Some constr
+R25253:25261 Sail.Values <> regval_of proj
+R25274:25282 Sail.Values <> read_from proj
+R25285:25285 riscv_types <> s:241 var
+R25265:25271 riscv_types <> x15_ref def
+R25244:25250 riscv_types <> x15_ref def
+R25146:25149 Coq.Init.Datatypes <> Some constr
+R25161:25169 Sail.Values <> regval_of proj
+R25182:25190 Sail.Values <> read_from proj
+R25193:25193 riscv_types <> s:241 var
+R25173:25179 riscv_types <> x16_ref def
+R25152:25158 riscv_types <> x16_ref def
+R25054:25057 Coq.Init.Datatypes <> Some constr
+R25069:25077 Sail.Values <> regval_of proj
+R25090:25098 Sail.Values <> read_from proj
+R25101:25101 riscv_types <> s:241 var
+R25081:25087 riscv_types <> x17_ref def
+R25060:25066 riscv_types <> x17_ref def
+R24962:24965 Coq.Init.Datatypes <> Some constr
+R24977:24985 Sail.Values <> regval_of proj
+R24998:25006 Sail.Values <> read_from proj
+R25009:25009 riscv_types <> s:241 var
+R24989:24995 riscv_types <> x18_ref def
+R24968:24974 riscv_types <> x18_ref def
+R24870:24873 Coq.Init.Datatypes <> Some constr
+R24885:24893 Sail.Values <> regval_of proj
+R24906:24914 Sail.Values <> read_from proj
+R24917:24917 riscv_types <> s:241 var
+R24897:24903 riscv_types <> x19_ref def
+R24876:24882 riscv_types <> x19_ref def
+R24778:24781 Coq.Init.Datatypes <> Some constr
+R24793:24801 Sail.Values <> regval_of proj
+R24814:24822 Sail.Values <> read_from proj
+R24825:24825 riscv_types <> s:241 var
+R24805:24811 riscv_types <> x20_ref def
+R24784:24790 riscv_types <> x20_ref def
+R24686:24689 Coq.Init.Datatypes <> Some constr
+R24701:24709 Sail.Values <> regval_of proj
+R24722:24730 Sail.Values <> read_from proj
+R24733:24733 riscv_types <> s:241 var
+R24713:24719 riscv_types <> x21_ref def
+R24692:24698 riscv_types <> x21_ref def
+R24594:24597 Coq.Init.Datatypes <> Some constr
+R24609:24617 Sail.Values <> regval_of proj
+R24630:24638 Sail.Values <> read_from proj
+R24641:24641 riscv_types <> s:241 var
+R24621:24627 riscv_types <> x22_ref def
+R24600:24606 riscv_types <> x22_ref def
+R24502:24505 Coq.Init.Datatypes <> Some constr
+R24517:24525 Sail.Values <> regval_of proj
+R24538:24546 Sail.Values <> read_from proj
+R24549:24549 riscv_types <> s:241 var
+R24529:24535 riscv_types <> x23_ref def
+R24508:24514 riscv_types <> x23_ref def
+R24410:24413 Coq.Init.Datatypes <> Some constr
+R24425:24433 Sail.Values <> regval_of proj
+R24446:24454 Sail.Values <> read_from proj
+R24457:24457 riscv_types <> s:241 var
+R24437:24443 riscv_types <> x24_ref def
+R24416:24422 riscv_types <> x24_ref def
+R24318:24321 Coq.Init.Datatypes <> Some constr
+R24333:24341 Sail.Values <> regval_of proj
+R24354:24362 Sail.Values <> read_from proj
+R24365:24365 riscv_types <> s:241 var
+R24345:24351 riscv_types <> x25_ref def
+R24324:24330 riscv_types <> x25_ref def
+R24226:24229 Coq.Init.Datatypes <> Some constr
+R24241:24249 Sail.Values <> regval_of proj
+R24262:24270 Sail.Values <> read_from proj
+R24273:24273 riscv_types <> s:241 var
+R24253:24259 riscv_types <> x26_ref def
+R24232:24238 riscv_types <> x26_ref def
+R24134:24137 Coq.Init.Datatypes <> Some constr
+R24149:24157 Sail.Values <> regval_of proj
+R24170:24178 Sail.Values <> read_from proj
+R24181:24181 riscv_types <> s:241 var
+R24161:24167 riscv_types <> x27_ref def
+R24140:24146 riscv_types <> x27_ref def
+R24042:24045 Coq.Init.Datatypes <> Some constr
+R24057:24065 Sail.Values <> regval_of proj
+R24078:24086 Sail.Values <> read_from proj
+R24089:24089 riscv_types <> s:241 var
+R24069:24075 riscv_types <> x28_ref def
+R24048:24054 riscv_types <> x28_ref def
+R23950:23953 Coq.Init.Datatypes <> Some constr
+R23965:23973 Sail.Values <> regval_of proj
+R23986:23994 Sail.Values <> read_from proj
+R23997:23997 riscv_types <> s:241 var
+R23977:23983 riscv_types <> x29_ref def
+R23956:23962 riscv_types <> x29_ref def
+R23858:23861 Coq.Init.Datatypes <> Some constr
+R23873:23881 Sail.Values <> regval_of proj
+R23894:23902 Sail.Values <> read_from proj
+R23905:23905 riscv_types <> s:241 var
+R23885:23891 riscv_types <> x30_ref def
+R23864:23870 riscv_types <> x30_ref def
+R23766:23769 Coq.Init.Datatypes <> Some constr
+R23781:23789 Sail.Values <> regval_of proj
+R23802:23810 Sail.Values <> read_from proj
+R23813:23813 riscv_types <> s:241 var
+R23793:23799 riscv_types <> x31_ref def
+R23772:23778 riscv_types <> x31_ref def
+def 26872:26881 <> set_regval
+R26895:26900 Coq.Strings.String <> string ind
+binder 26884:26891 <> reg_name:242
+R26908:26921 riscv_types <> register_value ind
+binder 26904:26904 <> v:243
+R26929:26936 riscv_types <> regstate rec
+binder 26925:26925 <> s:244
+R26941:26946 Coq.Init.Datatypes <> option ind
+R26948:26955 riscv_types <> regstate rec
+R26965:26974 Coq.Strings.String <> string_dec def
+R26976:26983 riscv_types <> reg_name:242 var
+R27075:27084 Coq.Strings.String <> string_dec def
+R27086:27093 riscv_types <> reg_name:242 var
+R27185:27194 Coq.Strings.String <> string_dec def
+R27196:27203 riscv_types <> reg_name:242 var
+R27295:27304 Coq.Strings.String <> string_dec def
+R27306:27313 riscv_types <> reg_name:242 var
+R27405:27414 Coq.Strings.String <> string_dec def
+R27416:27423 riscv_types <> reg_name:242 var
+R27515:27524 Coq.Strings.String <> string_dec def
+R27526:27533 riscv_types <> reg_name:242 var
+R27625:27634 Coq.Strings.String <> string_dec def
+R27636:27643 riscv_types <> reg_name:242 var
+R27735:27744 Coq.Strings.String <> string_dec def
+R27746:27753 riscv_types <> reg_name:242 var
+R27845:27854 Coq.Strings.String <> string_dec def
+R27856:27863 riscv_types <> reg_name:242 var
+R27955:27964 Coq.Strings.String <> string_dec def
+R27966:27973 riscv_types <> reg_name:242 var
+R28065:28074 Coq.Strings.String <> string_dec def
+R28076:28083 riscv_types <> reg_name:242 var
+R28175:28184 Coq.Strings.String <> string_dec def
+R28186:28193 riscv_types <> reg_name:242 var
+R28285:28294 Coq.Strings.String <> string_dec def
+R28296:28303 riscv_types <> reg_name:242 var
+R28395:28404 Coq.Strings.String <> string_dec def
+R28406:28413 riscv_types <> reg_name:242 var
+R28505:28514 Coq.Strings.String <> string_dec def
+R28516:28523 riscv_types <> reg_name:242 var
+R28615:28624 Coq.Strings.String <> string_dec def
+R28626:28633 riscv_types <> reg_name:242 var
+R28725:28734 Coq.Strings.String <> string_dec def
+R28736:28743 riscv_types <> reg_name:242 var
+R28835:28844 Coq.Strings.String <> string_dec def
+R28846:28853 riscv_types <> reg_name:242 var
+R28945:28954 Coq.Strings.String <> string_dec def
+R28956:28963 riscv_types <> reg_name:242 var
+R29055:29064 Coq.Strings.String <> string_dec def
+R29066:29073 riscv_types <> reg_name:242 var
+R29165:29174 Coq.Strings.String <> string_dec def
+R29176:29183 riscv_types <> reg_name:242 var
+R29275:29284 Coq.Strings.String <> string_dec def
+R29286:29293 riscv_types <> reg_name:242 var
+R29385:29394 Coq.Strings.String <> string_dec def
+R29396:29403 riscv_types <> reg_name:242 var
+R29492:29501 Coq.Strings.String <> string_dec def
+R29503:29510 riscv_types <> reg_name:242 var
+R29599:29608 Coq.Strings.String <> string_dec def
+R29610:29617 riscv_types <> reg_name:242 var
+R29706:29715 Coq.Strings.String <> string_dec def
+R29717:29724 riscv_types <> reg_name:242 var
+R29813:29822 Coq.Strings.String <> string_dec def
+R29824:29831 riscv_types <> reg_name:242 var
+R29920:29929 Coq.Strings.String <> string_dec def
+R29931:29938 riscv_types <> reg_name:242 var
+R30027:30036 Coq.Strings.String <> string_dec def
+R30038:30045 riscv_types <> reg_name:242 var
+R30134:30143 Coq.Strings.String <> string_dec def
+R30145:30152 riscv_types <> reg_name:242 var
+R30241:30250 Coq.Strings.String <> string_dec def
+R30252:30259 riscv_types <> reg_name:242 var
+R30348:30357 Coq.Strings.String <> string_dec def
+R30359:30366 riscv_types <> reg_name:242 var
+R30473:30482 Coq.Strings.String <> string_dec def
+R30484:30491 riscv_types <> reg_name:242 var
+R30592:30601 Coq.Strings.String <> string_dec def
+R30603:30610 riscv_types <> reg_name:242 var
+R30696:30699 Coq.Init.Datatypes <> None constr
+R30622:30631 Coq.Init.Datatypes <> option_map def
+R30675:30683 Sail.Values <> of_regval proj
+R30686:30686 riscv_types <> v:243 var
+R30667:30672 riscv_types <> PC_ref def
+binder 30638:30638 <> v:245
+R30651:30658 Sail.Values <> write_to proj
+R30663:30663 riscv_types <> s:244 var
+R30661:30661 riscv_types <> v:245 var
+R30643:30648 riscv_types <> PC_ref def
+R30507:30516 Coq.Init.Datatypes <> option_map def
+R30568:30576 Sail.Values <> of_regval proj
+R30579:30579 riscv_types <> v:243 var
+R30556:30565 riscv_types <> nextPC_ref def
+binder 30523:30523 <> v:246
+R30540:30547 Sail.Values <> write_to proj
+R30552:30552 riscv_types <> s:244 var
+R30550:30550 riscv_types <> v:246 var
+R30528:30537 riscv_types <> nextPC_ref def
+R30384:30393 Coq.Init.Datatypes <> option_map def
+R30449:30457 Sail.Values <> of_regval proj
+R30460:30460 riscv_types <> v:243 var
+R30435:30446 riscv_types <> instbits_ref def
+binder 30400:30400 <> v:247
+R30419:30426 Sail.Values <> write_to proj
+R30431:30431 riscv_types <> s:244 var
+R30429:30429 riscv_types <> v:247 var
+R30405:30416 riscv_types <> instbits_ref def
+R30271:30280 Coq.Init.Datatypes <> option_map def
+R30324:30332 Sail.Values <> of_regval proj
+R30335:30335 riscv_types <> v:243 var
+R30316:30321 riscv_types <> x1_ref def
+binder 30287:30287 <> v:248
+R30300:30307 Sail.Values <> write_to proj
+R30312:30312 riscv_types <> s:244 var
+R30310:30310 riscv_types <> v:248 var
+R30292:30297 riscv_types <> x1_ref def
+R30164:30173 Coq.Init.Datatypes <> option_map def
+R30217:30225 Sail.Values <> of_regval proj
+R30228:30228 riscv_types <> v:243 var
+R30209:30214 riscv_types <> x2_ref def
+binder 30180:30180 <> v:249
+R30193:30200 Sail.Values <> write_to proj
+R30205:30205 riscv_types <> s:244 var
+R30203:30203 riscv_types <> v:249 var
+R30185:30190 riscv_types <> x2_ref def
+R30057:30066 Coq.Init.Datatypes <> option_map def
+R30110:30118 Sail.Values <> of_regval proj
+R30121:30121 riscv_types <> v:243 var
+R30102:30107 riscv_types <> x3_ref def
+binder 30073:30073 <> v:250
+R30086:30093 Sail.Values <> write_to proj
+R30098:30098 riscv_types <> s:244 var
+R30096:30096 riscv_types <> v:250 var
+R30078:30083 riscv_types <> x3_ref def
+R29950:29959 Coq.Init.Datatypes <> option_map def
+R30003:30011 Sail.Values <> of_regval proj
+R30014:30014 riscv_types <> v:243 var
+R29995:30000 riscv_types <> x4_ref def
+binder 29966:29966 <> v:251
+R29979:29986 Sail.Values <> write_to proj
+R29991:29991 riscv_types <> s:244 var
+R29989:29989 riscv_types <> v:251 var
+R29971:29976 riscv_types <> x4_ref def
+R29843:29852 Coq.Init.Datatypes <> option_map def
+R29896:29904 Sail.Values <> of_regval proj
+R29907:29907 riscv_types <> v:243 var
+R29888:29893 riscv_types <> x5_ref def
+binder 29859:29859 <> v:252
+R29872:29879 Sail.Values <> write_to proj
+R29884:29884 riscv_types <> s:244 var
+R29882:29882 riscv_types <> v:252 var
+R29864:29869 riscv_types <> x5_ref def
+R29736:29745 Coq.Init.Datatypes <> option_map def
+R29789:29797 Sail.Values <> of_regval proj
+R29800:29800 riscv_types <> v:243 var
+R29781:29786 riscv_types <> x6_ref def
+binder 29752:29752 <> v:253
+R29765:29772 Sail.Values <> write_to proj
+R29777:29777 riscv_types <> s:244 var
+R29775:29775 riscv_types <> v:253 var
+R29757:29762 riscv_types <> x6_ref def
+R29629:29638 Coq.Init.Datatypes <> option_map def
+R29682:29690 Sail.Values <> of_regval proj
+R29693:29693 riscv_types <> v:243 var
+R29674:29679 riscv_types <> x7_ref def
+binder 29645:29645 <> v:254
+R29658:29665 Sail.Values <> write_to proj
+R29670:29670 riscv_types <> s:244 var
+R29668:29668 riscv_types <> v:254 var
+R29650:29655 riscv_types <> x7_ref def
+R29522:29531 Coq.Init.Datatypes <> option_map def
+R29575:29583 Sail.Values <> of_regval proj
+R29586:29586 riscv_types <> v:243 var
+R29567:29572 riscv_types <> x8_ref def
+binder 29538:29538 <> v:255
+R29551:29558 Sail.Values <> write_to proj
+R29563:29563 riscv_types <> s:244 var
+R29561:29561 riscv_types <> v:255 var
+R29543:29548 riscv_types <> x8_ref def
+R29415:29424 Coq.Init.Datatypes <> option_map def
+R29468:29476 Sail.Values <> of_regval proj
+R29479:29479 riscv_types <> v:243 var
+R29460:29465 riscv_types <> x9_ref def
+binder 29431:29431 <> v:256
+R29444:29451 Sail.Values <> write_to proj
+R29456:29456 riscv_types <> s:244 var
+R29454:29454 riscv_types <> v:256 var
+R29436:29441 riscv_types <> x9_ref def
+R29306:29315 Coq.Init.Datatypes <> option_map def
+R29361:29369 Sail.Values <> of_regval proj
+R29372:29372 riscv_types <> v:243 var
+R29352:29358 riscv_types <> x10_ref def
+binder 29322:29322 <> v:257
+R29336:29343 Sail.Values <> write_to proj
+R29348:29348 riscv_types <> s:244 var
+R29346:29346 riscv_types <> v:257 var
+R29327:29333 riscv_types <> x10_ref def
+R29196:29205 Coq.Init.Datatypes <> option_map def
+R29251:29259 Sail.Values <> of_regval proj
+R29262:29262 riscv_types <> v:243 var
+R29242:29248 riscv_types <> x11_ref def
+binder 29212:29212 <> v:258
+R29226:29233 Sail.Values <> write_to proj
+R29238:29238 riscv_types <> s:244 var
+R29236:29236 riscv_types <> v:258 var
+R29217:29223 riscv_types <> x11_ref def
+R29086:29095 Coq.Init.Datatypes <> option_map def
+R29141:29149 Sail.Values <> of_regval proj
+R29152:29152 riscv_types <> v:243 var
+R29132:29138 riscv_types <> x12_ref def
+binder 29102:29102 <> v:259
+R29116:29123 Sail.Values <> write_to proj
+R29128:29128 riscv_types <> s:244 var
+R29126:29126 riscv_types <> v:259 var
+R29107:29113 riscv_types <> x12_ref def
+R28976:28985 Coq.Init.Datatypes <> option_map def
+R29031:29039 Sail.Values <> of_regval proj
+R29042:29042 riscv_types <> v:243 var
+R29022:29028 riscv_types <> x13_ref def
+binder 28992:28992 <> v:260
+R29006:29013 Sail.Values <> write_to proj
+R29018:29018 riscv_types <> s:244 var
+R29016:29016 riscv_types <> v:260 var
+R28997:29003 riscv_types <> x13_ref def
+R28866:28875 Coq.Init.Datatypes <> option_map def
+R28921:28929 Sail.Values <> of_regval proj
+R28932:28932 riscv_types <> v:243 var
+R28912:28918 riscv_types <> x14_ref def
+binder 28882:28882 <> v:261
+R28896:28903 Sail.Values <> write_to proj
+R28908:28908 riscv_types <> s:244 var
+R28906:28906 riscv_types <> v:261 var
+R28887:28893 riscv_types <> x14_ref def
+R28756:28765 Coq.Init.Datatypes <> option_map def
+R28811:28819 Sail.Values <> of_regval proj
+R28822:28822 riscv_types <> v:243 var
+R28802:28808 riscv_types <> x15_ref def
+binder 28772:28772 <> v:262
+R28786:28793 Sail.Values <> write_to proj
+R28798:28798 riscv_types <> s:244 var
+R28796:28796 riscv_types <> v:262 var
+R28777:28783 riscv_types <> x15_ref def
+R28646:28655 Coq.Init.Datatypes <> option_map def
+R28701:28709 Sail.Values <> of_regval proj
+R28712:28712 riscv_types <> v:243 var
+R28692:28698 riscv_types <> x16_ref def
+binder 28662:28662 <> v:263
+R28676:28683 Sail.Values <> write_to proj
+R28688:28688 riscv_types <> s:244 var
+R28686:28686 riscv_types <> v:263 var
+R28667:28673 riscv_types <> x16_ref def
+R28536:28545 Coq.Init.Datatypes <> option_map def
+R28591:28599 Sail.Values <> of_regval proj
+R28602:28602 riscv_types <> v:243 var
+R28582:28588 riscv_types <> x17_ref def
+binder 28552:28552 <> v:264
+R28566:28573 Sail.Values <> write_to proj
+R28578:28578 riscv_types <> s:244 var
+R28576:28576 riscv_types <> v:264 var
+R28557:28563 riscv_types <> x17_ref def
+R28426:28435 Coq.Init.Datatypes <> option_map def
+R28481:28489 Sail.Values <> of_regval proj
+R28492:28492 riscv_types <> v:243 var
+R28472:28478 riscv_types <> x18_ref def
+binder 28442:28442 <> v:265
+R28456:28463 Sail.Values <> write_to proj
+R28468:28468 riscv_types <> s:244 var
+R28466:28466 riscv_types <> v:265 var
+R28447:28453 riscv_types <> x18_ref def
+R28316:28325 Coq.Init.Datatypes <> option_map def
+R28371:28379 Sail.Values <> of_regval proj
+R28382:28382 riscv_types <> v:243 var
+R28362:28368 riscv_types <> x19_ref def
+binder 28332:28332 <> v:266
+R28346:28353 Sail.Values <> write_to proj
+R28358:28358 riscv_types <> s:244 var
+R28356:28356 riscv_types <> v:266 var
+R28337:28343 riscv_types <> x19_ref def
+R28206:28215 Coq.Init.Datatypes <> option_map def
+R28261:28269 Sail.Values <> of_regval proj
+R28272:28272 riscv_types <> v:243 var
+R28252:28258 riscv_types <> x20_ref def
+binder 28222:28222 <> v:267
+R28236:28243 Sail.Values <> write_to proj
+R28248:28248 riscv_types <> s:244 var
+R28246:28246 riscv_types <> v:267 var
+R28227:28233 riscv_types <> x20_ref def
+R28096:28105 Coq.Init.Datatypes <> option_map def
+R28151:28159 Sail.Values <> of_regval proj
+R28162:28162 riscv_types <> v:243 var
+R28142:28148 riscv_types <> x21_ref def
+binder 28112:28112 <> v:268
+R28126:28133 Sail.Values <> write_to proj
+R28138:28138 riscv_types <> s:244 var
+R28136:28136 riscv_types <> v:268 var
+R28117:28123 riscv_types <> x21_ref def
+R27986:27995 Coq.Init.Datatypes <> option_map def
+R28041:28049 Sail.Values <> of_regval proj
+R28052:28052 riscv_types <> v:243 var
+R28032:28038 riscv_types <> x22_ref def
+binder 28002:28002 <> v:269
+R28016:28023 Sail.Values <> write_to proj
+R28028:28028 riscv_types <> s:244 var
+R28026:28026 riscv_types <> v:269 var
+R28007:28013 riscv_types <> x22_ref def
+R27876:27885 Coq.Init.Datatypes <> option_map def
+R27931:27939 Sail.Values <> of_regval proj
+R27942:27942 riscv_types <> v:243 var
+R27922:27928 riscv_types <> x23_ref def
+binder 27892:27892 <> v:270
+R27906:27913 Sail.Values <> write_to proj
+R27918:27918 riscv_types <> s:244 var
+R27916:27916 riscv_types <> v:270 var
+R27897:27903 riscv_types <> x23_ref def
+R27766:27775 Coq.Init.Datatypes <> option_map def
+R27821:27829 Sail.Values <> of_regval proj
+R27832:27832 riscv_types <> v:243 var
+R27812:27818 riscv_types <> x24_ref def
+binder 27782:27782 <> v:271
+R27796:27803 Sail.Values <> write_to proj
+R27808:27808 riscv_types <> s:244 var
+R27806:27806 riscv_types <> v:271 var
+R27787:27793 riscv_types <> x24_ref def
+R27656:27665 Coq.Init.Datatypes <> option_map def
+R27711:27719 Sail.Values <> of_regval proj
+R27722:27722 riscv_types <> v:243 var
+R27702:27708 riscv_types <> x25_ref def
+binder 27672:27672 <> v:272
+R27686:27693 Sail.Values <> write_to proj
+R27698:27698 riscv_types <> s:244 var
+R27696:27696 riscv_types <> v:272 var
+R27677:27683 riscv_types <> x25_ref def
+R27546:27555 Coq.Init.Datatypes <> option_map def
+R27601:27609 Sail.Values <> of_regval proj
+R27612:27612 riscv_types <> v:243 var
+R27592:27598 riscv_types <> x26_ref def
+binder 27562:27562 <> v:273
+R27576:27583 Sail.Values <> write_to proj
+R27588:27588 riscv_types <> s:244 var
+R27586:27586 riscv_types <> v:273 var
+R27567:27573 riscv_types <> x26_ref def
+R27436:27445 Coq.Init.Datatypes <> option_map def
+R27491:27499 Sail.Values <> of_regval proj
+R27502:27502 riscv_types <> v:243 var
+R27482:27488 riscv_types <> x27_ref def
+binder 27452:27452 <> v:274
+R27466:27473 Sail.Values <> write_to proj
+R27478:27478 riscv_types <> s:244 var
+R27476:27476 riscv_types <> v:274 var
+R27457:27463 riscv_types <> x27_ref def
+R27326:27335 Coq.Init.Datatypes <> option_map def
+R27381:27389 Sail.Values <> of_regval proj
+R27392:27392 riscv_types <> v:243 var
+R27372:27378 riscv_types <> x28_ref def
+binder 27342:27342 <> v:275
+R27356:27363 Sail.Values <> write_to proj
+R27368:27368 riscv_types <> s:244 var
+R27366:27366 riscv_types <> v:275 var
+R27347:27353 riscv_types <> x28_ref def
+R27216:27225 Coq.Init.Datatypes <> option_map def
+R27271:27279 Sail.Values <> of_regval proj
+R27282:27282 riscv_types <> v:243 var
+R27262:27268 riscv_types <> x29_ref def
+binder 27232:27232 <> v:276
+R27246:27253 Sail.Values <> write_to proj
+R27258:27258 riscv_types <> s:244 var
+R27256:27256 riscv_types <> v:276 var
+R27237:27243 riscv_types <> x29_ref def
+R27106:27115 Coq.Init.Datatypes <> option_map def
+R27161:27169 Sail.Values <> of_regval proj
+R27172:27172 riscv_types <> v:243 var
+R27152:27158 riscv_types <> x30_ref def
+binder 27122:27122 <> v:277
+R27136:27143 Sail.Values <> write_to proj
+R27148:27148 riscv_types <> s:244 var
+R27146:27146 riscv_types <> v:277 var
+R27127:27133 riscv_types <> x30_ref def
+R26996:27005 Coq.Init.Datatypes <> option_map def
+R27051:27059 Sail.Values <> of_regval proj
+R27062:27062 riscv_types <> v:243 var
+R27042:27048 riscv_types <> x31_ref def
+binder 27012:27012 <> v:278
+R27026:27033 Sail.Values <> write_to proj
+R27038:27038 riscv_types <> s:244 var
+R27036:27036 riscv_types <> v:278 var
+R27017:27023 riscv_types <> x31_ref def
+def 30714:30731 <> register_accessors
+R30736:30736 Coq.Init.Datatypes <> ::core_scope:'('_x_','_x_','_'..'_','_x_')' not
+R30747:30748 Coq.Init.Datatypes <> ::core_scope:'('_x_','_x_','_'..'_','_x_')' not
+R30759:30759 Coq.Init.Datatypes <> ::core_scope:'('_x_','_x_','_'..'_','_x_')' not
+R30737:30746 riscv_types <> get_regval def
+R30749:30758 riscv_types <> set_regval def
+def 30775:30776 <> MR
+binder 30778:30778 <> a:279
+binder 30780:30780 <> r:280
+R30785:30790 Sail.Prompt_monad <> monadR def
+R30792:30805 riscv_types <> register_value ind
+R30807:30807 riscv_types <> a:279 var
+R30809:30809 riscv_types <> r:280 var
+R30811:30814 Coq.Init.Datatypes <> unit ind
+def 30828:30828 <> M
+binder 30830:30830 <> a:281
+R30835:30839 Sail.Prompt_monad <> monad ind
+R30841:30854 riscv_types <> register_value ind
+R30856:30856 riscv_types <> a:281 var
+R30858:30861 Coq.Init.Datatypes <> unit ind
diff --git a/build/riscv_types.v b/build/riscv_types.v
new file mode 100644
index 0000000..2b32fd2
--- /dev/null
+++ b/build/riscv_types.v
@@ -0,0 +1,599 @@
+(*Generated by Sail from riscv.*)
+Require Import Sail.Base.
+Require Import Sail.Real.
+Import ListNotations.
+Open Scope string.
+Open Scope bool.
+Open Scope Z.
+
+Definition bits (n : Z) : Type := mword n.
+
+Definition xlen  : Z := 64.
+Hint Unfold xlen : sail.
+
+Definition xlen_bytes  : Z := 8.
+Hint Unfold xlen_bytes : sail.
+
+Definition xlenbits  : Type := bits 64.
+
+Definition regtype  : Type := xlenbits.
+
+Definition regno (n : Z)`{ArithFact ((0 <=? n) && (n <? 32))} : Type := Z.
+
+Definition regidx  : Type := bits 5.
+
+Definition cregidx  : Type := bits 3.
+
+Definition csreg  : Type := bits 12.
+
+Inductive register_value  :=
+  | Regval_vector : list register_value -> register_value
+  | Regval_list : list register_value -> register_value
+  | Regval_option : option register_value -> register_value
+  | Regval_bit : bitU -> register_value
+  | Regval_bitvector_64_dec : mword 64 -> register_value.
+
+Arguments register_value : clear implicits.
+
+Record regstate  :=
+  { x31 : mword 64;
+    x30 : mword 64;
+    x29 : mword 64;
+    x28 : mword 64;
+    x27 : mword 64;
+    x26 : mword 64;
+    x25 : mword 64;
+    x24 : mword 64;
+    x23 : mword 64;
+    x22 : mword 64;
+    x21 : mword 64;
+    x20 : mword 64;
+    x19 : mword 64;
+    x18 : mword 64;
+    x17 : mword 64;
+    x16 : mword 64;
+    x15 : mword 64;
+    x14 : mword 64;
+    x13 : mword 64;
+    x12 : mword 64;
+    x11 : mword 64;
+    x10 : mword 64;
+    x9 : mword 64;
+    x8 : mword 64;
+    x7 : mword 64;
+    x6 : mword 64;
+    x5 : mword 64;
+    x4 : mword 64;
+    x3 : mword 64;
+    x2 : mword 64;
+    x1 : mword 64;
+    instbits : mword 64;
+    nextPC : mword 64;
+    PC : mword 64; }.
+
+Arguments regstate : clear implicits.
+
+Notation "{[ r 'with' 'x31' := e ]}" :=
+  match r with Build_regstate _ f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate e f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x30' := e ]}" :=
+  match r with Build_regstate f0 _ f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 e f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x29' := e ]}" :=
+  match r with Build_regstate f0 f1 _ f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 e f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x28' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 _ f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 e f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x27' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 _ f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 e f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x26' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 _ f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 e f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x25' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 _ f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 e f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x24' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 _ f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 e f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x23' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 _ f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 e f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x22' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 _ f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 e f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x21' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 _ f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 e f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x20' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 _ f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 e f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x19' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 _ f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 e f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x18' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 _ f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 e f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x17' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 _ f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 e f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x16' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 _ f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 e f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x15' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 _ f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 e f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x14' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 _ f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 e f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x13' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 _ f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 e f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x12' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 _ f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 e f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x11' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 _ f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 e f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x10' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 _ f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 e f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x9' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 _ f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 e f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x8' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 _ f24 f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 e f24 f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x7' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 _ f25 f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 e f25 f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x6' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 _ f26 f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 e f26 f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x5' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 _ f27 f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 e f27 f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x4' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 _ f28 f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 e f28 f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x3' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 _ f29 f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 e f29 f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x2' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 _ f30 f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 e f30 f31 f32 f33
+      end.
+Notation "{[ r 'with' 'x1' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 _ f31 f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 e f31 f32 f33
+      end.
+Notation "{[ r 'with' 'instbits' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 _ f32 f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 e f32 f33
+      end.
+Notation "{[ r 'with' 'nextPC' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 _ f33 =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 e f33
+      end.
+Notation "{[ r 'with' 'PC' := e ]}" :=
+  match r with Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 _ =>
+    Build_regstate f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f25 f26 f27 f28 f29 f30 f31 f32 e
+      end.
+
+
+
+Definition bit_of_regval (merge_var : register_value) : option bitU :=
+   match merge_var with | Regval_bit v => Some v | _ => None end.
+
+Definition regval_of_bit (v : bitU) : register_value := Regval_bit v.
+
+Definition bitvector_64_dec_of_regval (merge_var : register_value) :
+  option (mword 64) :=
+   match merge_var with | Regval_bitvector_64_dec v => Some v | _ => None end.
+
+
+Definition regval_of_bitvector_64_dec (v : mword 64) : register_value :=
+  Regval_bitvector_64_dec v.
+
+
+Definition vector_of_regval {a} n (of_regval : register_value -> option a)
+           (rv : register_value) : option (vec a n) :=
+  match rv with
+  | Regval_vector v =>
+    if n =? length_list v then
+      map_bind (vec_of_list n) (just_list (List.map of_regval v))
+    else None
+  | _ => None
+end.
+
+Definition regval_of_vector {a size} (regval_of : a -> register_value) (xs : vec a size) : register_value := Regval_vector (List.map regval_of (list_of_vec xs)).
+
+Definition list_of_regval {a} (of_regval : register_value -> option a)
+           (rv : register_value) : option (list a) :=
+  match rv with
+  | Regval_list v => just_list (List.map of_regval v)
+  | _ => None
+end.
+
+Definition regval_of_list {a} (regval_of : a -> register_value)
+           (xs : list a) : register_value :=
+  Regval_list (List.map regval_of xs).
+
+Definition option_of_regval {a} (of_regval : register_value -> option a)
+           (rv : register_value) : option (option a) :=
+  match rv with
+  | Regval_option v => option_map of_regval v
+  | _ => None
+end.
+
+Definition regval_of_option {a} (regval_of : a -> register_value)
+           (v : option a) := Regval_option (option_map regval_of v).
+
+
+Definition x31_ref := {|
+  name := "x31";
+  read_from := (fun s => s.(x31));
+  write_to := (fun v s => ({[ s with x31 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x30_ref := {|
+  name := "x30";
+  read_from := (fun s => s.(x30));
+  write_to := (fun v s => ({[ s with x30 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x29_ref := {|
+  name := "x29";
+  read_from := (fun s => s.(x29));
+  write_to := (fun v s => ({[ s with x29 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x28_ref := {|
+  name := "x28";
+  read_from := (fun s => s.(x28));
+  write_to := (fun v s => ({[ s with x28 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x27_ref := {|
+  name := "x27";
+  read_from := (fun s => s.(x27));
+  write_to := (fun v s => ({[ s with x27 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x26_ref := {|
+  name := "x26";
+  read_from := (fun s => s.(x26));
+  write_to := (fun v s => ({[ s with x26 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x25_ref := {|
+  name := "x25";
+  read_from := (fun s => s.(x25));
+  write_to := (fun v s => ({[ s with x25 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x24_ref := {|
+  name := "x24";
+  read_from := (fun s => s.(x24));
+  write_to := (fun v s => ({[ s with x24 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x23_ref := {|
+  name := "x23";
+  read_from := (fun s => s.(x23));
+  write_to := (fun v s => ({[ s with x23 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x22_ref := {|
+  name := "x22";
+  read_from := (fun s => s.(x22));
+  write_to := (fun v s => ({[ s with x22 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x21_ref := {|
+  name := "x21";
+  read_from := (fun s => s.(x21));
+  write_to := (fun v s => ({[ s with x21 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x20_ref := {|
+  name := "x20";
+  read_from := (fun s => s.(x20));
+  write_to := (fun v s => ({[ s with x20 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x19_ref := {|
+  name := "x19";
+  read_from := (fun s => s.(x19));
+  write_to := (fun v s => ({[ s with x19 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x18_ref := {|
+  name := "x18";
+  read_from := (fun s => s.(x18));
+  write_to := (fun v s => ({[ s with x18 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x17_ref := {|
+  name := "x17";
+  read_from := (fun s => s.(x17));
+  write_to := (fun v s => ({[ s with x17 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x16_ref := {|
+  name := "x16";
+  read_from := (fun s => s.(x16));
+  write_to := (fun v s => ({[ s with x16 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x15_ref := {|
+  name := "x15";
+  read_from := (fun s => s.(x15));
+  write_to := (fun v s => ({[ s with x15 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x14_ref := {|
+  name := "x14";
+  read_from := (fun s => s.(x14));
+  write_to := (fun v s => ({[ s with x14 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x13_ref := {|
+  name := "x13";
+  read_from := (fun s => s.(x13));
+  write_to := (fun v s => ({[ s with x13 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x12_ref := {|
+  name := "x12";
+  read_from := (fun s => s.(x12));
+  write_to := (fun v s => ({[ s with x12 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x11_ref := {|
+  name := "x11";
+  read_from := (fun s => s.(x11));
+  write_to := (fun v s => ({[ s with x11 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x10_ref := {|
+  name := "x10";
+  read_from := (fun s => s.(x10));
+  write_to := (fun v s => ({[ s with x10 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x9_ref := {|
+  name := "x9";
+  read_from := (fun s => s.(x9));
+  write_to := (fun v s => ({[ s with x9 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x8_ref := {|
+  name := "x8";
+  read_from := (fun s => s.(x8));
+  write_to := (fun v s => ({[ s with x8 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x7_ref := {|
+  name := "x7";
+  read_from := (fun s => s.(x7));
+  write_to := (fun v s => ({[ s with x7 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x6_ref := {|
+  name := "x6";
+  read_from := (fun s => s.(x6));
+  write_to := (fun v s => ({[ s with x6 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x5_ref := {|
+  name := "x5";
+  read_from := (fun s => s.(x5));
+  write_to := (fun v s => ({[ s with x5 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x4_ref := {|
+  name := "x4";
+  read_from := (fun s => s.(x4));
+  write_to := (fun v s => ({[ s with x4 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x3_ref := {|
+  name := "x3";
+  read_from := (fun s => s.(x3));
+  write_to := (fun v s => ({[ s with x3 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x2_ref := {|
+  name := "x2";
+  read_from := (fun s => s.(x2));
+  write_to := (fun v s => ({[ s with x2 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x1_ref := {|
+  name := "x1";
+  read_from := (fun s => s.(x1));
+  write_to := (fun v s => ({[ s with x1 := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition instbits_ref := {|
+  name := "instbits";
+  read_from := (fun s => s.(instbits));
+  write_to := (fun v s => ({[ s with instbits := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+(* These should get generated from anno.json... *)
+Definition Xtype (X: Type) :=
+  match X with
+  | x1_ref => true
+  | x2_ref => true
+  | x3_ref => true
+  | x4_ref => true
+  (* ... *)
+  end.
+Inductive typing_result (A : Type) :=
+| Checked (a : A)
+| TypeError (t : type_error).
+
+Check Xtype(x1_ref).
+Check Xtype(x2_ref).
+Check Xtype(x3_ref).
+Check Xtype(x4_ref).
+
+Definition nextPC_ref := {|
+  name := "nextPC";
+  read_from := (fun s => s.(nextPC));
+  write_to := (fun v s => ({[ s with nextPC := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition PC_ref := {|
+  name := "PC";
+  read_from := (fun s => s.(PC));
+  write_to := (fun v s => ({[ s with PC := v ]}));
+  of_regval := (fun v => bitvector_64_dec_of_regval v);
+  regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+
+Local Open Scope string.
+Definition get_regval (reg_name : string) (s : regstate) : option register_value :=
+  if string_dec reg_name "x31" then Some (x31_ref.(regval_of) (x31_ref.(read_from) s)) else
+  if string_dec reg_name "x30" then Some (x30_ref.(regval_of) (x30_ref.(read_from) s)) else
+  if string_dec reg_name "x29" then Some (x29_ref.(regval_of) (x29_ref.(read_from) s)) else
+  if string_dec reg_name "x28" then Some (x28_ref.(regval_of) (x28_ref.(read_from) s)) else
+  if string_dec reg_name "x27" then Some (x27_ref.(regval_of) (x27_ref.(read_from) s)) else
+  if string_dec reg_name "x26" then Some (x26_ref.(regval_of) (x26_ref.(read_from) s)) else
+  if string_dec reg_name "x25" then Some (x25_ref.(regval_of) (x25_ref.(read_from) s)) else
+  if string_dec reg_name "x24" then Some (x24_ref.(regval_of) (x24_ref.(read_from) s)) else
+  if string_dec reg_name "x23" then Some (x23_ref.(regval_of) (x23_ref.(read_from) s)) else
+  if string_dec reg_name "x22" then Some (x22_ref.(regval_of) (x22_ref.(read_from) s)) else
+  if string_dec reg_name "x21" then Some (x21_ref.(regval_of) (x21_ref.(read_from) s)) else
+  if string_dec reg_name "x20" then Some (x20_ref.(regval_of) (x20_ref.(read_from) s)) else
+  if string_dec reg_name "x19" then Some (x19_ref.(regval_of) (x19_ref.(read_from) s)) else
+  if string_dec reg_name "x18" then Some (x18_ref.(regval_of) (x18_ref.(read_from) s)) else
+  if string_dec reg_name "x17" then Some (x17_ref.(regval_of) (x17_ref.(read_from) s)) else
+  if string_dec reg_name "x16" then Some (x16_ref.(regval_of) (x16_ref.(read_from) s)) else
+  if string_dec reg_name "x15" then Some (x15_ref.(regval_of) (x15_ref.(read_from) s)) else
+  if string_dec reg_name "x14" then Some (x14_ref.(regval_of) (x14_ref.(read_from) s)) else
+  if string_dec reg_name "x13" then Some (x13_ref.(regval_of) (x13_ref.(read_from) s)) else
+  if string_dec reg_name "x12" then Some (x12_ref.(regval_of) (x12_ref.(read_from) s)) else
+  if string_dec reg_name "x11" then Some (x11_ref.(regval_of) (x11_ref.(read_from) s)) else
+  if string_dec reg_name "x10" then Some (x10_ref.(regval_of) (x10_ref.(read_from) s)) else
+  if string_dec reg_name "x9" then Some (x9_ref.(regval_of) (x9_ref.(read_from) s)) else
+  if string_dec reg_name "x8" then Some (x8_ref.(regval_of) (x8_ref.(read_from) s)) else
+  if string_dec reg_name "x7" then Some (x7_ref.(regval_of) (x7_ref.(read_from) s)) else
+  if string_dec reg_name "x6" then Some (x6_ref.(regval_of) (x6_ref.(read_from) s)) else
+  if string_dec reg_name "x5" then Some (x5_ref.(regval_of) (x5_ref.(read_from) s)) else
+  if string_dec reg_name "x4" then Some (x4_ref.(regval_of) (x4_ref.(read_from) s)) else
+  if string_dec reg_name "x3" then Some (x3_ref.(regval_of) (x3_ref.(read_from) s)) else
+  if string_dec reg_name "x2" then Some (x2_ref.(regval_of) (x2_ref.(read_from) s)) else
+  if string_dec reg_name "x1" then Some (x1_ref.(regval_of) (x1_ref.(read_from) s)) else
+  if string_dec reg_name "instbits" then Some (instbits_ref.(regval_of) (instbits_ref.(read_from) s)) else
+  if string_dec reg_name "nextPC" then Some (nextPC_ref.(regval_of) (nextPC_ref.(read_from) s)) else
+  if string_dec reg_name "PC" then Some (PC_ref.(regval_of) (PC_ref.(read_from) s)) else
+  None.
+
+Definition set_regval (reg_name : string) (v : register_value) (s : regstate) : option regstate :=
+  if string_dec reg_name "x31" then option_map (fun v => x31_ref.(write_to) v s) (x31_ref.(of_regval) v) else
+  if string_dec reg_name "x30" then option_map (fun v => x30_ref.(write_to) v s) (x30_ref.(of_regval) v) else
+  if string_dec reg_name "x29" then option_map (fun v => x29_ref.(write_to) v s) (x29_ref.(of_regval) v) else
+  if string_dec reg_name "x28" then option_map (fun v => x28_ref.(write_to) v s) (x28_ref.(of_regval) v) else
+  if string_dec reg_name "x27" then option_map (fun v => x27_ref.(write_to) v s) (x27_ref.(of_regval) v) else
+  if string_dec reg_name "x26" then option_map (fun v => x26_ref.(write_to) v s) (x26_ref.(of_regval) v) else
+  if string_dec reg_name "x25" then option_map (fun v => x25_ref.(write_to) v s) (x25_ref.(of_regval) v) else
+  if string_dec reg_name "x24" then option_map (fun v => x24_ref.(write_to) v s) (x24_ref.(of_regval) v) else
+  if string_dec reg_name "x23" then option_map (fun v => x23_ref.(write_to) v s) (x23_ref.(of_regval) v) else
+  if string_dec reg_name "x22" then option_map (fun v => x22_ref.(write_to) v s) (x22_ref.(of_regval) v) else
+  if string_dec reg_name "x21" then option_map (fun v => x21_ref.(write_to) v s) (x21_ref.(of_regval) v) else
+  if string_dec reg_name "x20" then option_map (fun v => x20_ref.(write_to) v s) (x20_ref.(of_regval) v) else
+  if string_dec reg_name "x19" then option_map (fun v => x19_ref.(write_to) v s) (x19_ref.(of_regval) v) else
+  if string_dec reg_name "x18" then option_map (fun v => x18_ref.(write_to) v s) (x18_ref.(of_regval) v) else
+  if string_dec reg_name "x17" then option_map (fun v => x17_ref.(write_to) v s) (x17_ref.(of_regval) v) else
+  if string_dec reg_name "x16" then option_map (fun v => x16_ref.(write_to) v s) (x16_ref.(of_regval) v) else
+  if string_dec reg_name "x15" then option_map (fun v => x15_ref.(write_to) v s) (x15_ref.(of_regval) v) else
+  if string_dec reg_name "x14" then option_map (fun v => x14_ref.(write_to) v s) (x14_ref.(of_regval) v) else
+  if string_dec reg_name "x13" then option_map (fun v => x13_ref.(write_to) v s) (x13_ref.(of_regval) v) else
+  if string_dec reg_name "x12" then option_map (fun v => x12_ref.(write_to) v s) (x12_ref.(of_regval) v) else
+  if string_dec reg_name "x11" then option_map (fun v => x11_ref.(write_to) v s) (x11_ref.(of_regval) v) else
+  if string_dec reg_name "x10" then option_map (fun v => x10_ref.(write_to) v s) (x10_ref.(of_regval) v) else
+  if string_dec reg_name "x9" then option_map (fun v => x9_ref.(write_to) v s) (x9_ref.(of_regval) v) else
+  if string_dec reg_name "x8" then option_map (fun v => x8_ref.(write_to) v s) (x8_ref.(of_regval) v) else
+  if string_dec reg_name "x7" then option_map (fun v => x7_ref.(write_to) v s) (x7_ref.(of_regval) v) else
+  if string_dec reg_name "x6" then option_map (fun v => x6_ref.(write_to) v s) (x6_ref.(of_regval) v) else
+  if string_dec reg_name "x5" then option_map (fun v => x5_ref.(write_to) v s) (x5_ref.(of_regval) v) else
+  if string_dec reg_name "x4" then option_map (fun v => x4_ref.(write_to) v s) (x4_ref.(of_regval) v) else
+  if string_dec reg_name "x3" then option_map (fun v => x3_ref.(write_to) v s) (x3_ref.(of_regval) v) else
+  if string_dec reg_name "x2" then option_map (fun v => x2_ref.(write_to) v s) (x2_ref.(of_regval) v) else
+  if string_dec reg_name "x1" then option_map (fun v => x1_ref.(write_to) v s) (x1_ref.(of_regval) v) else
+  if string_dec reg_name "instbits" then option_map (fun v => instbits_ref.(write_to) v s) (instbits_ref.(of_regval) v) else
+  if string_dec reg_name "nextPC" then option_map (fun v => nextPC_ref.(write_to) v s) (nextPC_ref.(of_regval) v) else
+  if string_dec reg_name "PC" then option_map (fun v => PC_ref.(write_to) v s) (PC_ref.(of_regval) v) else
+  None.
+
+Definition register_accessors := (get_regval, set_regval).
+
+
+Definition MR a r := monadR register_value a r unit.
+Definition M a := monad register_value a unit.
diff --git a/build/riscv_types.vo b/build/riscv_types.vo
new file mode 100644
index 0000000..641a150
--- /dev/null
+++ b/build/riscv_types.vo
diff --git a/build/riscv_types.vok b/build/riscv_types.vok
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/build/riscv_types.vok
diff --git a/build/riscv_types.vos b/build/riscv_types.vos
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/build/riscv_types.vos
author	Aditya Naik	2021-08-27 13:07:37 -0400
committer	Aditya Naik	2021-08-27 13:07:37 -0400
commit	663e24a3d8f45b4b184b3a4bc3a57bc0f3d6cd78 (patch)
tree	62a699a6065bea9f4bcefda93d227209fec4a154 /build