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-rw-r--r--build/.Makefile.d6
1 files changed, 6 insertions, 0 deletions
diff --git a/build/.Makefile.d b/build/.Makefile.d
new file mode 100644
index 0000000..e6650b7
--- /dev/null
+++ b/build/.Makefile.d
@@ -0,0 +1,6 @@
+riscv_types.vo riscv_types.glob riscv_types.v.beautified riscv_types.required_vo: riscv_types.v /home/aditya/.opam/default/share/sail/lib/coq/Base.vo /home/aditya/.opam/default/share/sail/lib/coq/Real.vo
+riscv_types.vio: riscv_types.v /home/aditya/.opam/default/share/sail/lib/coq/Base.vio /home/aditya/.opam/default/share/sail/lib/coq/Real.vio
+riscv_types.vos riscv_types.vok riscv_types.required_vos: riscv_types.v /home/aditya/.opam/default/share/sail/lib/coq/Base.vos /home/aditya/.opam/default/share/sail/lib/coq/Real.vos
+riscv.vo riscv.glob riscv.v.beautified riscv.required_vo: riscv.v /home/aditya/.opam/default/share/sail/lib/coq/Base.vo /home/aditya/.opam/default/share/sail/lib/coq/Real.vo riscv_types.vo
+riscv.vio: riscv.v /home/aditya/.opam/default/share/sail/lib/coq/Base.vio /home/aditya/.opam/default/share/sail/lib/coq/Real.vio riscv_types.vio
+riscv.vos riscv.vok riscv.required_vos: riscv.v /home/aditya/.opam/default/share/sail/lib/coq/Base.vos /home/aditya/.opam/default/share/sail/lib/coq/Real.vos riscv_types.vos