diff options
| author | Aditya Naik | 2021-08-27 13:07:37 -0400 |
|---|---|---|
| committer | Aditya Naik | 2021-08-27 13:07:37 -0400 |
| commit | 663e24a3d8f45b4b184b3a4bc3a57bc0f3d6cd78 (patch) | |
| tree | 62a699a6065bea9f4bcefda93d227209fec4a154 /build/riscv.vok | |
Initial; working SAIL RISC-V regs
The register definition along with read/write functions for registers
are lowered to Coq. The FIRRTL annotation does not work as expected.
Diffstat (limited to 'build/riscv.vok')
| -rw-r--r-- | build/riscv.vok | 0 |
1 files changed, 0 insertions, 0 deletions
diff --git a/build/riscv.vok b/build/riscv.vok new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/build/riscv.vok |