diff options
| author | Aditya Naik | 2021-08-27 13:07:37 -0400 |
|---|---|---|
| committer | Aditya Naik | 2021-08-27 13:07:37 -0400 |
| commit | 663e24a3d8f45b4b184b3a4bc3a57bc0f3d6cd78 (patch) | |
| tree | 62a699a6065bea9f4bcefda93d227209fec4a154 /build/.riscv_types.aux | |
Initial; working SAIL RISC-V regs
The register definition along with read/write functions for registers
are lowered to Coq. The FIRRTL annotation does not work as expected.
Diffstat (limited to 'build/.riscv_types.aux')
| -rw-r--r-- | build/.riscv_types.aux | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/build/.riscv_types.aux b/build/.riscv_types.aux new file mode 100644 index 0000000..3dea1e8 --- /dev/null +++ b/build/.riscv_types.aux @@ -0,0 +1,2 @@ +COQAUX1 23addcfb4a3be3458f693a2ed5b20df5 /home/aditya/dev/firrtl-proof/sail-simple-test/build/riscv_types.v +0 0 vo_compile_time "0.639" |