blob: b40fc7587289489eeea115ef274ea6ce377c9e2b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
|
package chisel3
import scala.collection.immutable.ListMap
import scala.collection.mutable.{ArrayBuffer, HashMap}
import scala.language.experimental.macros
import chisel3.internal._
import chisel3.internal.Builder._
import chisel3.internal.firrtl._
import chisel3.experimental.BaseModule
case class AbstractInterface[T](params: T)
case class Interface(ifaceContainer: AbstractInterface[_]*)
class Op[A, B, C](func: A => B => C) {
val f: A => B => C = func
}
class BaseAbstractModule
case class PortName(s: String)
/**
A module that uses types from its metaconnects to type its IOs.
*/
class AbstractModule(iface: Seq[AbstractInterface[_]])(body: Seq[AbstractInterface[_]] => () => Module) {
// iface.foreach(x => {
// println(x)
// })
// println(iface)
val comp: () => Module = body(iface)
def generateComponent(): Option[chisel3.internal.firrtl.Component] = ???
// def initializeInParent(parentCompileOptions: chisel3.CompileOptions): Unit = ???
}
|
