1 files changed, 7 insertions, 3 deletions
diff --git a/core/src/main/scala/chisel3/AbstractModule.scala b/core/src/main/scala/chisel3/AbstractModule.scala
index 61cad9c2..b40fc758 100644
--- a/core/src/main/scala/chisel3/AbstractModule.scala
+++ b/core/src/main/scala/chisel3/AbstractModule.scala
@@ -17,14 +17,18 @@ class Op[A, B, C](func: A => B => C) {
   val f: A => B => C = func
 }
 
+class BaseAbstractModule
+
+case class PortName(s: String)
 /**
   A module that uses types from its metaconnects to type its IOs. 
   */
-class AbstractModule(iface: Seq[AbstractInterface[_]]) extends BaseModule {
+class AbstractModule(iface: Seq[AbstractInterface[_]])(body: Seq[AbstractInterface[_]] => () => Module) {
   // iface.foreach(x => {
-  //   // println(x, x.ioNode)
+  //   println(x)
   // })
   // println(iface)
+  val comp: () => Module = body(iface)
   def generateComponent(): Option[chisel3.internal.firrtl.Component] = ???
-  def initializeInParent(parentCompileOptions: chisel3.CompileOptions): Unit = ???
+  // def initializeInParent(parentCompileOptions: chisel3.CompileOptions): Unit = ???
 }