package chisel3

import scala.collection.immutable.ListMap
import scala.collection.mutable.{ArrayBuffer, HashMap}
import scala.language.experimental.macros

import chisel3.internal._
import chisel3.internal.Builder._
import chisel3.internal.firrtl._
import chisel3.experimental.BaseModule

case class AbstractInterface[T](params: T)

case class Interface(ifaceContainer: AbstractInterface[_]*)

class Op[A, B, C](func: A => B => C) {
  val f: A => B => C = func
}

class BaseAbstractModule

case class PortName(s: String)
/**
  A module that uses types from its metaconnects to type its IOs. 
  */
class AbstractModule(iface: Seq[AbstractInterface[_]])(body: Seq[AbstractInterface[_]] => () => Module) {
  // iface.foreach(x => {
  //   println(x)
  // })
  // println(iface)
  val comp: () => Module = body(iface)
  def generateComponent(): Option[chisel3.internal.firrtl.Component] = ???
  // def initializeInParent(parentCompileOptions: chisel3.CompileOptions): Unit = ???
}