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AgeCommit message (Expand)Author
2019-05-09Add Lfsr testsSchuyler Eldridge
2019-05-09Add chisel3.util.random lib w/ LFSR generatorSchuyler Eldridge
2019-05-08Genericize LFSR testing infrastructureSchuyler Eldridge
2019-05-05Expand upon ScalaDoc in Driveredwardcwang
2019-05-01Make asTypeOf work for bundles with zero-width fields. (#1079)Paul Rigge
2019-04-26Bundle literals implementation (#1057)Richard Lin
2019-04-24Add back Int forms of Mem do_apply methods (#1082)Jack Koenig
2019-04-23Change size of memories from Int to BigInt (#1076)Jack Koenig
2019-04-19Fix wrong directionality for Vec(Flipped())Edward Wang
2019-04-15Avoid silently truncating BigInt to IntAndrew Waterman
2019-04-12Implement connectFromBits in ChiselEnum (#1052)Jack Koenig
2019-04-01Detect bundle aliasing (#1050)Richard Lin
2019-03-29Ignore empty aggregates elements when binding aggregate direction (#946)Jack Koenig
2019-03-25Allow naming annotation to work outside builder context (#1051)Richard Lin
2019-03-25Check field referential equality in autoclonetype (#1047)Richard Lin
2019-03-23move doNotDedup to experimental (#1008)Sequencer
2019-03-22Fix enum annotations (#936)Hasan Genc
2019-03-21Remove @chiselName from MixedVec (#1045)Richard Lin
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
2019-03-15Merge branch 'master' into popcountedwardcwang
2019-03-15Use TransitName for improved Pipe naming (#1024)Schuyler Eldridge
2019-03-15Add width constraint to PopCount test (which currently fails)Andrew Waterman
2019-03-15Add PopCount testAndrew Waterman
2019-03-14Decouple implementation details from LoadMemoryAnnotation. (#1034)Jim Lawson
2019-03-11ScalaDocs improvement for utils Math, MixedVec (#1019)Richard Lin
2019-02-25Docs for ListLookup (#1028)Richard Lin
2019-02-19Add HasBlackBoxPath to BlackBoxUtils.scala (#903)Albert Chen
2019-02-19ScalaDoc for Mux (examples added) (#1014)Martin Schoeberl
2019-02-19Add TransitNameSpecSchuyler Eldridge
2019-02-19Add Scaladoc for chisel3.util.TransitNameSchuyler Eldridge
2019-02-19Mainline Chisel multi-clock functionality (#1013)edwardcwang
2019-02-19Util doc lsfr (#1021)Chick Markley
2019-02-19Documentation for Reg utilities (#1018)Martin Schoeberl
2019-02-19ScalaDoc for OneHot (#1016)Martin Schoeberl
2019-02-18Add requirement that Pipe latency >= 0Schuyler Eldridge
2019-02-18Add Scaladoc for chisel3.util.PipeSchuyler Eldridge
2019-02-18Add Scaldoc for chisel3.util.ValidSchuyler Eldridge
2019-02-01Queue TestsBrendan Sweeney
2019-01-25WireDefault instead of WireInit, keep WireInit around (#986)Martin Schoeberl
2019-01-23Bump copyright year (#997)Jim Lawson
2019-01-22Define Data .toString (#985)Richard Lin
2019-01-22Changes to BoringUtils Scaladoc, paramater nameSchuyler Eldridge
2019-01-22Fix BoringUtilsSpec to require no dedupSchuyler Eldridge
2019-01-22Fix BoringUtils deduplication bugSchuyler Eldridge
2019-01-22Add Rocket Chip-style clonemodule as CloneModuleAsRecord to experimental (#943)Albert Magyar
2019-01-21Support DontCare in Mux and cloneSupertype (#995)Richard Lin
2019-01-21Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) M...Richard Lin
2019-01-11Add test for chiselNaming of Seq[Data]Andrew Waterman
2019-01-09Avoid procedural wire assignment in test resourceSchuyler Eldridge
2019-01-07Fix build error due to scala bug #11125 (#967)Nick Hynes
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