chiselX - Chisel with SFC compatibility

Age	Commit message (Collapse)	Author
2016-07-20	Compile ok.	Jim Lawson
	Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x)
2016-07-19	Fix LitBinding and MultiAssign tests.	Jim Lawson

2016-07-19	Incorporate connection logic.	Jim Lawson
	Compiles but fails tests.
2016-07-19	Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3	Jim Lawson

2016-07-18	Update Chisel -> chisel3 references.	Jim Lawson

2016-07-18	Rename "Chisel" to "chisel3" (only git mv).	Jim Lawson

2016-07-11	bitpat should keep the width of uint (#232)	Donggyu

2016-07-07	Don't check GCD result before sending it a request	Andrew Waterman

2016-07-07	Improve QoR for Log2	Andrew Waterman
	For reasonable circuit delay, need to divide & conquer.
2016-07-07	Improve Fill code generation	Andrew Waterman

2016-07-07	Correct erroneous Log2 documentation	Andrew Waterman

2016-07-07	Avoid needlessly creating Vecs	Andrew Waterman

2016-06-28	Merge branch 'master' into renamechisel3	Jim Lawson

2016-06-27	Guard firrtl stop, fixing pipelined reset	Andrew Waterman

2016-06-24	Merge branch 'master' into renamechisel3	Jim Lawson

2016-06-23	Expose FIRRTL stop construct	Andrew Waterman

2016-06-22	Merge branch 'master' into renamechisel3	Jim Lawson

2016-06-21	Most of the remaining tests with Module, IO wrapping.	Jim Lawson

2016-06-21	New Module, IO, Input/Output wrapping.	Jim Lawson

2016-06-20	make sure MuxCase and MuxLookup can take all subclasses of Data (#222)	Howard Mao

2016-06-20	Rename "package", "import", and explicit references to "chisel3".	Jim Lawson

2016-06-20	Rename chisel3 package.	Jim Lawson

2016-06-08	Move deprecated debug into compatibility	ducky

2016-06-08	Package split chisel core	ducky

2016-06-08	Move chisel/... to chisel/core/..., make chisel/compatibility ↵	ducky
	package/folder, move more things into utils
2016-06-08	Move utils into utils	ducky

2016-06-08	Add implicit xToLiteral, add Element, use internal package object	ducky

2016-06-08	Rename Chisel -> chisel in tests	ducky

2016-06-08	Rename packages to lowercase chisel, add compatibility layer	ducky

2016-06-06	Changed deprecation warning for Data#toBits to recommend asUInt instead ↵	chick
	because the sole remaining use of toBits in chiselTests was to compare to Vectors declared differently but with same underlying bits. Making at toBits was problematic because it did not support === method. Changed Vec and Bundle to both support toUInt() Note: If toBits is actually needed now, one can use toInt().toBits()
2016-06-01	Fix a fairly serious bug whereby Vec's could incorrectly compare as equal (#204)	Wesley W. Terpstra
	* chiselTests: include an example of two empty Vectors killing FIRRTL * Aggregate: fix a bug whereby Vec[T] was using equals/hashCode of Seq In Chisel, two vectors are NOT equal just if their contents are equal. For example, two empty vectors should not be considered equal. This patch makes Vec use the HasId._id for equality like other Chisel types. Without this fix, Bundle.namedElts.seen: HashSet[Data]() will eliminate one of the named vectors and emit bad IR.
2016-05-31	Remove unsafe implicit conversions from BitPat	ducky

2016-05-31	Move BitPat out of core/frontend, add implicit conversion	Ducky

2016-05-26	Fix type constraint on PriorityMux	Andrew Waterman

2016-05-20	Merge pull request #186 from ucb-bar/sloc_impl	Richard Lin
	Source locators
2016-05-20	Implementation of source locators	ducky

2016-05-20	Update BackendCompilationUtilities.verilogToCpp to specify top-module	jackkoenig
	This prevents Verilator from erroring when it cannot determine the top-module. It also changes the PRINTF_COND guard to correctly use the top-level reset instead of just the top of the Chisel-generated code.
2016-05-12	remove Tester.scala because chiselMain is now implemented in the ↵	Danny
	chisel-testers repo
2016-05-11	RegNext and RegInit should match Reg(next=) and Reg(init=)	Andrew Waterman

2016-05-10	Move emit out of IR	ducky

2016-05-09	remove vpi source files	Donggyu Kim

2016-05-09	fix width inference in enum	Donggyu Kim

2016-05-09	get -> getOrElse	Donggyu Kim

2016-05-05	Move Chisel API into separate chiselFrontend compilation unit in preparation ↵	ducky
	for source locator macros
2016-05-04	Multiple assign tester	ducky
	Closes #90
2016-05-04	Remove dependences from Chisel core on Chisel utils	Andrew Waterman
	Partially resolves #164
2016-05-04	Support writing literals like 1.U or -1.S	Andrew Waterman

2016-05-04	clock\|reset to _clock\|_reset, added explanatory comment	Stephen Twigg
	@aswaterman closes #156
2016-05-04	Change BlackBox.io.setRef into comment	Stephen Twigg
	Setting the io ref there wasn't doing anything meaningful
2016-05-04	Rewrite BlackBox IO contract, replace _clock\|_reset	Stephen Twigg
	The old blackbox behavior still emitted extmodules that have a clk, reset pin and prepended all io's with io_ (ultimately). Most verilog modules do not follow this distinction (or use a slightly different name for clock and so on). Thus, instead BlackBox has been rewritten to not assume a clk or reset pin. Instead, the io Bundle specified is flattened directly into the Module.ports declaration. The tests have been rewritten to compensate for this. Also, added a test that uses the clock pin. As a secondary change, the _clock and _reset module parameters were bad for two reasons. One, they used null as a default, which is a scala best practices violation. Two, they were just not good names. Instead the primary constructor has been rewritten to take an Option[Clock] called override_clock and an Option[Bool] called override_reset, which default to None. (Note how the getOrElse call down below is much more natural now.) However, users may not want to specify the Some(their_clock) so I also added secondary constructors that take parameters named clock and reset and wrap them into Some calls into the primary constructor. This is a better UX because now you can just stipulate clock=blah in instantiation of that module in symmetry with using the clock in the definition of the module by invoking clock. PS: We could also back out of allowing any overrides via the Module constructor and just require the instantiating Module to do submodule.clock := newclock, etc.