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AgeCommit message (Expand)Author
2016-01-25Emit FIRRTL muxes for aggregatesAndrew Waterman
2016-01-24Disallow weak connect for VecAndrew Waterman
2016-01-23Implement first draft of new FIRRTL changesAndrew Waterman
2016-01-23Change implicit clock name to clk to match Chisel2Andrew Waterman
2016-01-23Don't use deprecated constructsAndrew Waterman
2016-01-23Move firrtl subpackage to inside internal subpackage.jackkoenig
2016-01-17Remove unused WhenElse IR nodeAndrew Waterman
2016-01-17Improve code generation for WhenAndrew Waterman
2016-01-17Merge pull request #89 from ucb-bar/whenAndrew Waterman
2016-01-17Add =/= operator to BitPatAndrew Waterman
2016-01-16Disallow Muxing between bundles whose fields have different widthsAndrew Waterman
2016-01-16Allow Wire() to be called from parameterized functionsAndrew Waterman
2016-01-16Add When test and fix when / elsewhen / otherwise behaviorducky
2016-01-15flatten should return Seq[Bits], not Seq[UInt]Andrew Waterman
2016-01-12elaboration-time asserts should call Predef.assertAndrew Waterman
2016-01-12Catch yet another missing-cloneType caseAndrew Waterman
2016-01-11Add a dummy chiselMainPalmer Dabbelt
2015-12-31Add assert(Boolean), assert(Boolean, String)Palmer Dabbelt
2015-12-30Add '=/=' to bits, which does the same as '!='Palmer Dabbelt
2015-12-15Meaningful error when resource copy failsducky
2015-12-15Print test stdout/stderr to consoleducky
2015-12-14Modify TestDriver to take resource paths instead of Filesducky
2015-12-11Fix Counter docducky
2015-12-11Refactor tests to use stop() and assert() instead of io.error/io.doneducky
2015-12-11Add stop() in BasicTester as a replacement for io.doneducky
2015-12-11Add support for printf and asserts, add testbench for asserts and printfducky
2015-12-11Merge pull request #64 from ucb-bar/optionablebundleAdam Izraelevitz
2015-12-10Add Option support in Bundleducky
2015-12-09Refactor testharness generation to create directories and have minimal APIducky
2015-12-09Optional additional Verilog sources to include in executeducky
2015-12-09Extend TesterDriver to optionally take in additional Verilog sourcesducky
2015-12-06Split internal and FIRRTL packagesducky
2015-12-06More design rationale for Vecducky
2015-11-06Merge pull request #59 from ucb-bar/testing-improvementsJim Lawson
2015-11-06added elaboration tests for remaining old Chisel3 examplesHenry Cook
2015-11-06Fixed bug that created Vec(Reg(...)) instead of Reg(Vec(...))azidar
2015-11-06Fix counter testsHenry Cook
2015-11-06return -1 on simulation timeoutHenry Cook
2015-11-04Merge pull request #57 from ucb-bar/stylechiselJim Lawson
2015-11-04Merge pull request #56 from ucb-bar/stylefixJim Lawson
2015-11-04Fix new style errorsducky
2015-11-04Style fixes for test code, so we can go back down to zero style errors for testsducky
2015-11-04Fix Tbl.ioHenry Cook
2015-11-04Use elaborate for elaboration tests, not executeHenry Cook
2015-11-04Supply smaller values for generatorDrivenConfig to reduce test time.Henry Cook
2015-11-04Remove Parameters library and refactor Driver.Henry Cook
2015-11-03Add documentation on some non-intuitive partsducky
2015-11-02Remove implementation details from scaladoc.ducky
2015-11-02Add Scalastyle rule to check lines ending with a ;, fix some instancesducky
2015-11-02Scalastyle ignore ## and printlns in Error.scaladucky
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