diff options
| author | Andrew Waterman | 2016-01-17 14:53:27 -0800 |
|---|---|---|
| committer | Andrew Waterman | 2016-01-17 14:53:27 -0800 |
| commit | 57c1770a964c44b4211453ab6f7f41289f21cd50 (patch) | |
| tree | 03ec6b3e1b71d5b3ad2653417861f88b4687668d /src | |
| parent | 34ee838ebc7c9e08fc1699c9b20386fcb37a5830 (diff) | |
Remove unused WhenElse IR node
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/Chisel/firrtl/Emitter.scala | 3 | ||||
| -rw-r--r-- | src/main/scala/Chisel/firrtl/IR.scala | 1 |
2 files changed, 0 insertions, 4 deletions
diff --git a/src/main/scala/Chisel/firrtl/Emitter.scala b/src/main/scala/Chisel/firrtl/Emitter.scala index 1d0f4ddc..a6fd15aa 100644 --- a/src/main/scala/Chisel/firrtl/Emitter.scala +++ b/src/main/scala/Chisel/firrtl/Emitter.scala @@ -29,9 +29,6 @@ private class Emitter(circuit: Circuit) { case w: WhenBegin => indent() s"when ${w.pred.fullName(ctx)} :" - case _: WhenElse => - indent() - "else :" case _: WhenEnd => unindent() "skip" diff --git a/src/main/scala/Chisel/firrtl/IR.scala b/src/main/scala/Chisel/firrtl/IR.scala index 8cc31b54..6f3eb4d1 100644 --- a/src/main/scala/Chisel/firrtl/IR.scala +++ b/src/main/scala/Chisel/firrtl/IR.scala @@ -146,7 +146,6 @@ case class DefAccessor[T <: Data](id: T, source: Node, direction: Direction, ind case class DefInstance(id: Module, ports: Seq[Port]) extends Definition case class DefPoison[T <: Data](id: T) extends Definition case class WhenBegin(pred: Arg) extends Command -case class WhenElse() extends Command case class WhenEnd() extends Command case class Connect(loc: Node, exp: Arg) extends Command case class BulkConnect(loc1: Node, loc2: Node) extends Command |