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authorducky2015-11-04 12:42:38 -0800
committerPalmer Dabbelt2015-12-06 22:10:22 -0800
commite3e70ac9eb2446ad850ebddc1f42816b4537f7af (patch)
treecfca00c83ae2101afec3652ddd9ea006d0e0de01 /src
parent85f3006d7eac44ff21111d0f7ece1015164c0fe0 (diff)
More design rationale for Vec
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/Chisel/Aggregate.scala6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/Aggregate.scala b/src/main/scala/Chisel/Aggregate.scala
index e6ac6b85..8a0f20af 100644
--- a/src/main/scala/Chisel/Aggregate.scala
+++ b/src/main/scala/Chisel/Aggregate.scala
@@ -88,10 +88,14 @@ object Vec {
* @tparam T type of elements
* @note when multiple conflicting assignments are performed on a Vec element,
* the last one takes effect (unlike Mem, where the result is undefined)
+ * @note Vecs, unlike classes in Scala's collection library, are propagated
+ * intact to FIRRTL as a vector type, which may make debugging easier
*/
sealed class Vec[T <: Data] private (gen: => T, val length: Int)
extends Aggregate(gen.dir) with VecLike[T] {
- // REVIEW TODO: should this take a Seq instead of a gen()?
+ // Note: the constructor takes a gen() function instead of a Seq to enforce
+ // that all elements must be the same and because it makes FIRRTL generation
+ // simpler.
private val self = IndexedSeq.fill(length)(gen)