| Age | Commit message (Expand) | Author |
|---|
| 2016-07-20 | More literal/width rangling. | Jim Lawson |
| 2016-07-20 | Distinguish between ?Int.Lit and ?Int.width | Jim Lawson |
| 2016-07-20 | Compile ok. | Jim Lawson |
| 2016-07-19 | Fix LitBinding and MultiAssign tests. | Jim Lawson |
| 2016-07-19 | Incorporate connection logic. | Jim Lawson |
| 2016-07-19 | Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3 | Jim Lawson |
| 2016-07-18 | Update Chisel -> chisel3 references. | Jim Lawson |
| 2016-07-18 | Rename "Chisel" to "chisel3" (only git mv). | Jim Lawson |
| 2016-06-21 | Most of the remaining tests with Module, IO wrapping. | Jim Lawson |
| 2016-06-21 | New Module, IO, Input/Output wrapping. | Jim Lawson |
| 2016-06-01 | Fix a fairly serious bug whereby Vec's could incorrectly compare as equal (#204) | Wesley W. Terpstra |
| 2016-05-31 | Remove unsafe implicit conversions from BitPat | ducky |
| 2016-05-31 | Move BitPat out of core/frontend, add implicit conversion | Ducky |
| 2016-05-26 | Fix type constraint on PriorityMux | Andrew Waterman |
| 2016-05-20 | Merge pull request #186 from ucb-bar/sloc_impl | Richard Lin |
| 2016-05-20 | Implementation of source locators | ducky |
| 2016-05-20 | Update BackendCompilationUtilities.verilogToCpp to specify top-module | jackkoenig |
| 2016-05-12 | remove Tester.scala because chiselMain is now implemented in the chisel-teste... | Danny |
| 2016-05-11 | RegNext and RegInit should match Reg(next=) and Reg(init=) | Andrew Waterman |
| 2016-05-10 | Move emit out of IR | ducky |
| 2016-05-09 | remove vpi source files | Donggyu Kim |
| 2016-05-09 | fix width inference in enum | Donggyu Kim |
| 2016-05-09 | get -> getOrElse | Donggyu Kim |
| 2016-05-05 | Move Chisel API into separate chiselFrontend compilation unit in preparation ... | ducky |
| 2016-05-04 | Multiple assign tester | ducky |
| 2016-05-04 | Remove dependences from Chisel core on Chisel utils | Andrew Waterman |
| 2016-05-04 | Support writing literals like 1.U or -1.S | Andrew Waterman |
| 2016-05-04 | clock|reset to _clock|_reset, added explanatory comment | Stephen Twigg |
| 2016-05-04 | Change BlackBox.io.setRef into comment | Stephen Twigg |
| 2016-05-04 | Rewrite BlackBox IO contract, replace _clock|_reset | Stephen Twigg |
| 2016-05-04 | Add HasId=Module|Data.suggestName, TransitName util | Stephen Twigg |
| 2016-05-02 | more kind assert on chiselMain | Donggyu Kim |
| 2016-04-26 | Replace deprecated usage in tests. Issue #149 | Jim Lawson |
| 2016-04-26 | Scalastyle fixes and "ignores". - No functional changes. | Jim Lawson |
| 2016-04-18 | Add whenever method to TblSpec forall to weed out invalid test values. | Jim Lawson |
| 2016-04-18 | Only elaborate once in chiselMain.run() | Palmer Dabbelt |
| 2016-04-15 | Test FIRRTL string literals more aggressively | Andrew Waterman |
| 2016-04-14 | Disallow Counters with negative n | Andrew Waterman |
| 2016-04-14 | Use mkString to clarify and speed up DefPrim emission | Andrew Waterman |
| 2016-04-14 | Don't eagerly evaluate assertion failure strings | Andrew Waterman |
| 2016-04-14 | Improve performance of hashing HasId (e.g. Data) | Andrew Waterman |
| 2016-04-14 | Eliminate RefMap | Andrew Waterman |
| 2016-04-14 | Reject log2Up on negative inputs | Andrew Waterman |
| 2016-04-13 | Remove underscores from constant creation | Colin Schmidt |
| 2016-04-05 | Make Wire(init = x) behave the same as Wire(t = x) := x | Andrew Waterman |
| 2016-04-01 | Clearly delineate pipe/flow behavior in Queue | Andrew Waterman |
| 2016-04-01 | Reduce FIRRTL node count for Counter | Andrew Waterman |
| 2016-04-01 | Improve Arbiter implementation and QoR | Andrew Waterman |
| 2016-04-01 | Make ArbiterCtrl private; make O(n), not O(n^2) | Andrew Waterman |
| 2016-04-01 | Return Seq, not Vec, from PriorityEncoderOH | Andrew Waterman |
