Eliminate RefMap

It's an unconvincing means to pretend there isn't mutable state when
there really is.  It's more confusing and less performant than just
calling a spade a spade.

3 files changed, 9 insertions, 30 deletions

diff --git a/src/main/scala/Chisel/Module.scala b/src/main/scala/Chisel/Module.scala
index 463c2f81..22c1f9c3 100644
--- a/src/main/scala/Chisel/Module.scala
+++ b/src/main/scala/Chisel/Module.scala
@@ -53,8 +53,6 @@ abstract class Module(_clock: Clock = null, _reset: Bool = null) extends HasId {
   val reset = Bool(INPUT)
 
   private[Chisel] def addId(d: HasId) { _ids += d }
-  private[Chisel] def ref = Builder.globalRefMap(this)
-  private[Chisel] def lref = ref
 
   private def ports = (clock, "clk") :: (reset, "reset") :: (io, "io") :: Nil
 
diff --git a/src/main/scala/Chisel/internal/Builder.scala b/src/main/scala/Chisel/internal/Builder.scala
index 7e72b5e1..e040b375 100644
--- a/src/main/scala/Chisel/internal/Builder.scala
+++ b/src/main/scala/Chisel/internal/Builder.scala
@@ -45,38 +45,20 @@ private[Chisel] trait HasId {
   private[Chisel] val _parent = Builder.dynamicContext.currentModule
   _parent.foreach(_.addId(this))
 
-  private[Chisel] val _refMap = Builder.globalRefMap
   private[Chisel] val _id = Builder.idGen.next
-  private[Chisel] def setRef(imm: Arg) = _refMap.setRef(this, imm)
-  private[Chisel] def setRef(name: String) = _refMap.setRef(this, name)
-  private[Chisel] def setRef(parent: HasId, name: String) = _refMap.setField(parent, this, name)
-  private[Chisel] def setRef(parent: HasId, index: Int) = _refMap.setIndex(parent, this, ILit(index))
-  private[Chisel] def setRef(parent: HasId, index: UInt) = _refMap.setIndex(parent, this, index.ref)
-  private[Chisel] def getRef = _refMap(this)
-}
-
-class RefMap {
-  private val _refmap = new HashMap[Long,Arg]()
-
-  private[Chisel] def setRef(id: HasId, ref: Arg): Unit =
-    _refmap(id._id) = ref
-
-  private[Chisel] def setRef(id: HasId, name: String): Unit =
-    if (!_refmap.contains(id._id)) setRef(id, Ref(name))
-
-  private[Chisel] def setField(parentid: HasId, id: HasId, name: String): Unit =
-    _refmap(id._id) = Slot(Node(parentid), name)
-
-  private[Chisel] def setIndex(parentid: HasId, id: HasId, index: Arg): Unit =
-    _refmap(id._id) = Index(Node(parentid), index)
 
-  def apply(id: HasId): Arg = _refmap(id._id)
+  private var _ref: Option[Arg] = None
+  private[Chisel] def setRef(imm: Arg): Unit = _ref = Some(imm)
+  private[Chisel] def setRef(name: => String): Unit = if (_ref.isEmpty) setRef(Ref(name))
+  private[Chisel] def setRef(parent: HasId, name: String): Unit = setRef(Slot(Node(parent), name))
+  private[Chisel] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index)))
+  private[Chisel] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref))
+  private[Chisel] def getRef: Arg = _ref.get
 }
 
 private[Chisel] class DynamicContext {
   val idGen = new IdGen
   val globalNamespace = new Namespace(None, Set())
-  val globalRefMap = new RefMap
   val components = ArrayBuffer[Component]()
   var currentModule: Option[Module] = None
   val errors = new ErrorLog
@@ -89,7 +71,6 @@ private[Chisel] object Builder {
   def dynamicContext: DynamicContext = dynamicContextVar.value.get
   def idGen: IdGen = dynamicContext.idGen
   def globalNamespace: Namespace = dynamicContext.globalNamespace
-  def globalRefMap: RefMap = dynamicContext.globalRefMap
   def components: ArrayBuffer[Component] = dynamicContext.components
 
   def pushCommand[T <: Command](c: T): T = {
@@ -109,7 +90,7 @@ private[Chisel] object Builder {
       errors.checkpoint()
       errors.info("Done elaborating.")
 
-      Circuit(components.last.name, components, globalRefMap)
+      Circuit(components.last.name, components)
     }
   }
 }
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala
index 8a937419..beb32e6c 100644
--- a/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/src/main/scala/Chisel/internal/firrtl/IR.scala
@@ -181,6 +181,6 @@ case class Printf(clk: Arg, formatIn: String, ids: Seq[Arg]) extends Command {
   }
 }
 
-case class Circuit(name: String, components: Seq[Component], refMap: RefMap) {
+case class Circuit(name: String, components: Seq[Component]) {
   def emit: String = new Emitter(this).toString
 }