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AgeCommit message (Expand)Author
2016-09-21Expose FIRRTL asClock constructAndrew Waterman
2016-09-07Fix bug in Printable FullName of submodule portjackkoenig
2016-09-07Add Printable (#270)Jack Koenig
2016-08-24Per Chisel meeting.chick
2016-08-21AnnotatingExample:chick
2016-08-21Add AnnotationSpec file which provides an example of a way to implement gener...chick
2016-08-21Add annotating example to test new signal name apichick
2016-08-15Make "def width" a private API; expose isWidthKnown instead (#257)Andrew Waterman
2016-07-20Generate better names for nodes (#190)Jack Koenig
2016-07-07Don't check GCD result before sending it a requestAndrew Waterman
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-08Move utils into utilsducky
2016-06-08Rename Chisel -> chisel in testsducky
2016-06-01Fix a fairly serious bug whereby Vec's could incorrectly compare as equal (#204)Wesley W. Terpstra
2016-05-20Update BackendCompilationUtilities.verilogToCpp to specify top-modulejackkoenig
2016-05-04Multiple assign testerducky
2016-05-04Rewrite BlackBox IO contract, replace _clock|_resetStephen Twigg
2016-04-26Replace deprecated usage in tests. Issue #149Jim Lawson
2016-04-18Add whenever method to TblSpec forall to weed out invalid test values.Jim Lawson
2016-04-15Test FIRRTL string literals more aggressivelyAndrew Waterman
2016-04-14Disallow Counters with negative nAndrew Waterman
2016-03-18Add test for assertions in modules with pipedlined resetjackkoenig
2016-03-18Only randomize directory names during testingjackkoenig
2016-02-25Fixed comment punctuation and made it clearer that using an init() method for...chick
2016-02-24Remove the assignment statements in EnqIO and DeqIO Bundle constructors.chick
2016-02-24Create a test that breaks because of assignment statements in DeqIO and EnqIO...chick
2016-02-22Fixed improper apostrophe in it's in TesterDriverSpec commentschick
2016-02-10TesterDriverSpec is simpler and cleaner, extraneous circuit has been removed.chick
2016-02-10The TesterDriverSpec has been made stronger by altering circuit in finish methodchick
2016-02-10Added some comments describing potential use of the finish method hookchick
2016-02-09fixed test for finish method being put in the wrong placechick
2016-02-09Added support for finish method of BasicTester to be overridden in a subclass...chick
2016-02-08Added a simple tests that DeqIO and EnqIO get their directions right and are ...chick
2016-01-30Add BlackBox support and test, refactor execute => assertTesterPassesducky
2016-01-28Fixed NoneOptionBundleTester to actually instantiate a module without an inpu...azidar
2016-01-28Merge branch 'master' into modrefactorAndrew Waterman
2016-01-28Merge branch 'master' into scalastyleAndrew Waterman
2016-01-27Add unit test for module deduplicationducky
2016-01-16Add When test and fix when / elsewhen / otherwise behaviorducky
2016-01-06Don't silence legitimate warnings - these println()s should be controlled by ...Jim Lawson
2016-01-05Scalastyle fixes - whitespace or comments only.Jim Lawson
2015-12-11Refactor tests to use stop() and assert() instead of io.error/io.doneducky
2015-12-11Add stop() in BasicTester as a replacement for io.doneducky
2015-12-11Add support for printf and asserts, add testbench for asserts and printfducky
2015-12-11Merge pull request #64 from ucb-bar/optionablebundleAdam Izraelevitz
2015-12-10Add Option support in Bundleducky
2015-12-09Refactor testharness generation to create directories and have minimal APIducky
2015-12-09Extend TesterDriver to optionally take in additional Verilog sourcesducky
2015-12-06Split internal and FIRRTL packagesducky
2015-11-06Merge pull request #59 from ucb-bar/testing-improvementsJim Lawson
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