summaryrefslogtreecommitdiff
path: root/src/test
diff options
context:
space:
mode:
authorchick2016-02-10 14:29:49 -0800
committerchick2016-02-10 14:29:49 -0800
commita9355ba3784e3c5ae611f096a48b4ee5c78464ad (patch)
tree1b1431d32877d3fb3241c661ebf92f1dc80f1ce9 /src/test
parentc9d9a313b39fa1d43f794c85ec31d8deb847dc9c (diff)
TesterDriverSpec is simpler and cleaner, extraneous circuit has been removed.
Cleanup comment for finish method in BasicTester, and finishWrapper in TesterDriver.
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/chiselTests/TesterDriverSpec.scala48
1 files changed, 18 insertions, 30 deletions
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index d7cb0305..dfdd07cc 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -5,51 +5,39 @@ package chiselTests
import Chisel._
import Chisel.testers.BasicTester
-/** Extend basic tester with a finish method. TesterDriver will call the
- * finish method after the Tester's constructor has completed
- * -
- * In this example we use last connect semantics to alter the circuit after
- * the constructor has completed
+/** Extend BasicTester with a simple circuit and finish method. TesterDriver will call the
+ * finish method after the FinishTester's constructor has completed, which will alter the
+ * circuit after the constructor has finished.
*/
class FinishTester extends BasicTester {
val test_wire_width = 2
val test_wire_override_value = 3
+ val counter = Counter(1)
+
+ when(counter.inc()) {
+ stop()
+ }
+
val test_wire = Wire(UInt(1, width = test_wire_width))
- test_wire := UInt(1, width = test_wire_width)
- // though we just test_wire to 1, the assert below will be true because
- // the finish will override it
+ // though we just set test_wire to 1, the assert below will pass because
+ // the finish will change it's value
assert(test_wire === UInt(test_wire_override_value))
+ /** In finish we use last connect semantics to alter the test_wire in the circuit
+ * with a new value
+ */
override def finish(): Unit = {
- test_wire := UInt(test_wire_override_value, width = test_wire_width)
- }
-}
-
-class DummyCircuit extends Module {
- val io = new Bundle {
- val in = UInt(INPUT, width = 1)
- val out = UInt(OUTPUT, width = 1)
+ test_wire := UInt(test_wire_override_value)
}
-
- io.out := io.in
-}
-
-class DummyTester extends FinishTester {
- val dut = Module(new DummyCircuit)
-
- dut.io.in := UInt(1)
- Chisel.assert(dut.io.out === UInt(1))
-
- stop()
}
class TesterDriverSpec extends ChiselFlatSpec {
- "TesterDriver calls a BasicTester subclass's finish method which" should
- "allow modifications of test circuit after tester constructor is done" in {
+ "TesterDriver calls BasicTester's finish method which" should
+ "allow modifications of test circuit after the tester's constructor is done" in {
assertTesterPasses {
- new DummyTester
+ new FinishTester
}
}
}