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2021-06-24create and extend annotatable BaseSim class for verification nodes (#1968)Deborah Soung
* prototype annotating verif constructs * switch to final class * name emissions * moving BaseSim to experimental * adding name tests * fixing quotation escapes * emitting names, but everything has a default name * only name things with provided/suggested names * name every BaseSim node * removing msg, unused imports * fixing file exist calls
2021-06-23Replace hard coded line separators with system specific onesBoyang Han
2021-06-21Bump scalatest to 3.2.9 (#1965)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-06-16getVerilog in Chisel3 (#1921)Martin Schoeberl
2021-06-16implement test for qmcJiuyang Liu
2021-06-16Add test cases.Jiuyang Liu
2021-06-16switch to EndToEndSMTBaseSpecJiuyang Liu
2021-06-16Add minimized form of test casesBoyang Han
2021-06-16use z3 formal check minimized circuit and reference model.Jiuyang Liu
2021-06-16test decode cache.Jiuyang Liu
2021-06-16TruthTable can merge same inputs now.Jiuyang Liu
2021-06-16implement TruthTable to represent a decode table.Jiuyang Liu
2021-06-10Stop Emitting BlackBoxResourceAnno (#1954)Schuyler Eldridge
* Change HasBlackBoxResource to Resolve Resources Change HasBlackBoxResource to resolve resources immediately and emit BlackBoxInlineAnno instead of a BlackBoxResourceAnno. This removes the need for a FIRRTL compiler to grok the Java Resource API in order to handle BlackBoxResourceAnno. Emit BlackBoxInlineAnno from HasExtModuleResource instead of BlackBoxResourceAnno. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-05-25throw exception if BitPat width is 0 (#1920)Jiuyang Liu
* spot a bug when BitPat width is 0 * fix #1919 Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-20Implement PLA (#1912)Jiuyang Liu
* implement pla * implement test for pla * implement inverter matrix of PLA generator * fix for review. Co-authored-by: Boyang Han <yqszxx@gmail.com>
2021-05-20implement model checking API for chiseltest (#1910)Jiuyang Liu
* add os-lib to dependency. * implement EndToEndSMTBaseSpec * rename to SMTModelCheckingSpec * add documentation. * fix for review.
2021-05-09Fix ShiftRegister with 0 delay. (#1903)Jiuyang Liu
* Add test to check ShiftRegister(s) with delay is 0. This should break ShiftRegister(x, 0) since last is not exist in a empty Seq. Originally, test only test 1 to 4, which missed a potential bug from #1723. * Fix ShiftRegister with 0 delay. if ShiftRegisters is empty, java will complain: ``` java.util.NoSuchElementException scala.collection.LinearSeqOptimized.last(LinearSeqOptimized.scala:150) ``` This fix this issue and return `in` directly when ShiftRegister size is 0. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-06add ShiftRegisters to expose register inside ShiftRegister. (#1723)Jiuyang Liu
* add ShiftRegisters to expose register inside ShiftRegister. * use Seq.iter for oneline implementation.
2021-05-05Remove chisel3.stage.phases.DriverCompatibility (#1772)Schuyler Eldridge
2021-04-30add helper function to convert chirrtl to firrtl. (#1854)Jiuyang Liu
* add convert(chirrtl: cir.Circuit): fir.Circuit to convert chirrtl to firrtl. * add scaladoc. * add test. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-29Scala 2.13 support (#1751)Jack Koenig
2021-04-29verification: guard statements with module reset (#1891)Kevin Laeufer
2021-04-27Introduce VecLiterals (#1834)Chick Markley
This PR provides for support for Vec literals. They can be one of two forms Inferred: ``` Vec.Lit(0x1.U, 0x2.U) ``` or explicit: ``` Vec(2, UInt(4.W)).Lit(0 -> 0x1.U, 1 -> 0x2.U) ``` - Explicit form allows for partial, or sparse, literals. - Vec literals can be used as Register initializers - Arbitrary nesting (consistent with type constraints is allowed)
2021-04-21fixing context bug (#1874)Deborah Soung
2021-03-23Make plugin autoclonetype always on (#1826)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-18Add toString method to BitPat (#1819)Boyang Han
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-17Fix incorrect usage of emitFirrtl in test (#1817)Schuyler Eldridge
Change a test to use emitChirrtl instead of emitFirrtl. This test isn't supposed to be running the Scala FIRRTL Compiler, but the latter method causes this to happen. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-03-15allowReflectiveAutoCloneType must work outside of Builder context (#1811)Jack Koenig
2021-03-12[plugin] Disable BundleComponent by default, add option to enableJack Koenig
2021-03-12[plugin] Implement autoclonetype in the compiler pluginJack Koenig
2021-03-11Import memory files inline for Verilog generation (#1805)Carlos Eduardo
This annotation adds memory import with inline generation for the emmiter. Supports both readmemh and readmemb statements based on argument.
2021-02-26Expose AnnotationSeq to Module. (#1731)Jiuyang Liu
2021-02-11Fix stack trace trimming across Driver/ChiselStage (#1771)Schuyler Eldridge
* Handle MemTypeBinding in Analog Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Fix stack trace trimming across ChiselStage Fix bug in stack trace trimming behavior. Now, the following is what happens: 1. The Builder, if catching accumulated errors, will now throw a ChiselException with a Scala-trimmed Stack trace. Previously, this would throw the full excpetion. 2. The Elaborate phase handles stack trace trimming. By default, any Throwable thrown during elaboration will have its stack trace *mutably* trimmed and is rethrown. A logger.error is printed stating that there was an error during elaboration and how the user can turn on the full stack trace. If the --full-stacktrace option is on, then the Throwable is not caught and only the first logger.error (saying that elaboration failed) will be printed. 3. ChiselStage (the class), ChiselStage$ (the object), and ChiselMain all inherit the behavior of (2). Mutable stack trace trimming behavior is moved into an implicit class (previously this was defined on ChiselException only) so this can be applied to any Throwable. No StageErrors are now thrown anymore. However, StageErrors may still be caught by ChiselMain (since it is a StageMain). Testing is added for ChiselMain, ChiselStage, and ChiselStage$ to test all this behavior. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-02-09Make it possible to GC Data instancesJack Koenig
No longer create a pointer from parent to every HasId, only do it by default for BaseModules and MemBases. Add pointer from parent to Data upon binding the Data. * Add MemTypeBinding for port types of Mems This binding is similar to the SampleElementBinding for Vecs in that these Data are not truly hardware, but are represented in the FIRRTL IR and thus need some representation. * Call _onModuleClose on unbound Records This maintains some corner-case behavior that is nevertheless relied upon. It ensures that refs are set for the elements of Records, even if they are not bound to any real hardware.
2021-02-09Add no-plugin-tests for testing Chisel without the compiler pluginJack Koenig
This is a new SBT build unit that symlinks in some files from the normal chisel project tests, but builds them without the compiler plugin.
2021-02-08Parametrized Mem- & SyncReadMem-based implementation of the Queue class (#1740)Vladimir Milovanović
* Added SyncReadMem-based implementation of the Queue class * Rework of the parametrized Queue class SyncReadMem-based implementation * Modification of the parametrized Queue class SyncReadMem-based implementation * Limiting the visibility of the read address for SyncReadMem-based Queue Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-02-03Remove Deprecated APIs (#1730)Jiuyang Liu
2021-02-01Update reported width from div/rem to match FIRRTL results (#1748)Albert Magyar
* Update reported width from div/rem to match FIRRTL results * Add tests for width of % and / on UInt and SInt * Add loop-based test for known UInt/SInt op result widths Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-01-21Remove val ioJack Koenig
Chisel projects no longer need -Xsource:2.11 when compiling with Scala 2.12. Autowrapping of "val io" for compatibility mode Modules is now implemented using reflection instead of calling the virtual method. Also move Chisel.BlackBox to new chisel3.internal.LegacyBlackBox
2021-01-21Rename MultiIOModule to ModuleJack Koenig
2021-01-19Add when.cond for getting the current when condition (#1694)Jack Koenig
This is useful for libraries to guard operations implemented via annotations or BlackBoxes by the current when predicate
2021-01-11Make `toTarget` fail if called on a Literal (or would otherwise not ↵Megan Wachs
serialize properly) (#1714) * Add (failing) Test for Data toTarget calls Add scaladoc and clean up test * Builder: don't let .toTarget pass if it won't be able to deserialize properly later * Update src/test/scala/chiselTests/ReferenceTargetSpec.scala * Rename and simplify tests for literal toTarget
2020-12-07(encore) Builder: use LazyLogging.logger.warn to print elaboration message ↵Jiuyang Liu
(#1670) * Builder: use LazyLogging.logger.warn to print elaboration message * add deprecation for chisel3.internal.ErrorLog.info. * add test to check elaboration message still exist. Co-authored-by: Kevin Laeufer <kevin.laeufer@sifive.com>
2020-12-01Fix RegInit of Bundle lits (#1688)Jack Koenig
Implemented by folding Element.ref into Data.ref. Element.ref had special handling for literals, but because Bundles can also be literals, there were code paths that tried to get the ref of a Bundle literal which was non-existent. Now, all literals are handled together. Because FIRRTL does not have support for Bundle literals, Bundle literal refs are implemented by materializing a Wire.
2020-11-16Improve source locators for switch statements. (#1669)Daniel Kasza
* Improve source locators for switch statements.
2020-11-11Ignore tests using System.setSecurityManager (#1661)Jack Koenig
The SecurityManager is global so is not thread-safe. This is the source of flaky tests in FIRRTL CI. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-11Refine autonaming to have more intuitive behavior (#1660)Jack Koenig
* Refine autonaming to have more intuitive behavior Last name in an Expression wins, while the first Statement to name wins. This is done via checking the _id of HasIds during autonaming and only applying a name if the HasId was created in the scope of autonaming. There is no change to .autoSeed or .suggestName behavior. Behavior of chisel3-plugins from before this change is maintained. * Update docs with naming plugin changes
2020-11-05For HasId.setRef, have first set win (with force override) (#1655)Jack Koenig
This is a refinement of the assertion added in #1616 then removed in #1654. Because Records now set the refs of children upon binding, later, unbound Records could incorrectly override the refs. The first set should win.
2020-11-03Remove Data.setRef assertion (#1654)Jack Koenig
It causes issues for some legal (if awkward) patterns. A larger refactor of when refs are set could reinstate this check.
2020-11-02Bugfix - adding external modules was broken (#1649)Adam Izraelevitz
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