diff options
| author | Schuyler Eldridge | 2021-03-17 14:00:27 -0400 |
|---|---|---|
| committer | GitHub | 2021-03-17 18:00:27 +0000 |
| commit | 492a71d6d4d3acef39f29345835637bca028a089 (patch) | |
| tree | 4d2ca303110e37a6aea1d6e287b96ceb5e22bdc6 /src/test | |
| parent | 96436ae018b3631decb8384ce404ada0daa5d645 (diff) | |
Fix incorrect usage of emitFirrtl in test (#1817)
Change a test to use emitChirrtl instead of emitFirrtl. This test
isn't supposed to be running the Scala FIRRTL Compiler, but the latter
method causes this to happen.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/chiselTests/experimental/verification/VerificationSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/experimental/verification/VerificationSpec.scala b/src/test/scala/chiselTests/experimental/verification/VerificationSpec.scala index 52293abb..fe642156 100644 --- a/src/test/scala/chiselTests/experimental/verification/VerificationSpec.scala +++ b/src/test/scala/chiselTests/experimental/verification/VerificationSpec.scala @@ -28,7 +28,7 @@ class VerificationSpec extends ChiselPropSpec { } property("basic equality check should work") { - val fir = ChiselStage.emitFirrtl(new VerificationModule) + val fir = ChiselStage.emitChirrtl(new VerificationModule) val lines = fir.split("\n").map(_.trim) assertContains(lines, "cover(clock, _T, UInt<1>(\"h1\"), \"\") @[VerificationSpec.scala 16:15]") assertContains(lines, "assume(clock, _T_2, UInt<1>(\"h1\"), \"\") @[VerificationSpec.scala 18:18]") |