diff options
| author | Jack Koenig | 2020-11-10 19:29:46 -0800 |
|---|---|---|
| committer | GitHub | 2020-11-11 03:29:46 +0000 |
| commit | 9f1d6cbb79ac9b9f9e2cad5f294ca5d195aeac14 (patch) | |
| tree | c39a0e2d89ccf16e6cdaa4ec2277bbb6352db707 /src/test | |
| parent | 1260f7c89f1b95bdb00e56e49edb73dc2eac3a0e (diff) | |
Ignore tests using System.setSecurityManager (#1661)
The SecurityManager is global so is not thread-safe. This is the source
of flaky tests in FIRRTL CI.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/chiselTests/ChiselSpec.scala | 1 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/stage/ChiselStageSpec.scala | 12 |
2 files changed, 7 insertions, 6 deletions
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala index 2f8f978a..843b3192 100644 --- a/src/test/scala/chiselTests/ChiselSpec.scala +++ b/src/test/scala/chiselTests/ChiselSpec.scala @@ -281,6 +281,7 @@ trait Utils { * or doesn't try to write at all. */ def catchWrites[T](thunk: => T): Either[String, T] = { + throw new Exception("Do not use, not thread-safe") try { System.setSecurityManager(new ExceptOnWrite()) Right(thunk) diff --git a/src/test/scala/chiselTests/stage/ChiselStageSpec.scala b/src/test/scala/chiselTests/stage/ChiselStageSpec.scala index e640def8..fb5698a6 100644 --- a/src/test/scala/chiselTests/stage/ChiselStageSpec.scala +++ b/src/test/scala/chiselTests/stage/ChiselStageSpec.scala @@ -72,21 +72,21 @@ class ChiselStageSpec extends AnyFlatSpec with Matchers with Utils { behavior of "ChiselStage$.elaborate" - it should "generate a Chisel circuit from a Chisel module" in { + ignore should "generate a Chisel circuit from a Chisel module" in { info("no files were written") catchWrites { ChiselStage.elaborate(new Foo) } shouldBe a[Right[_, _]] } behavior of "ChiselStage$.convert" - it should "generate a CHIRRTL circuit from a Chisel module" in { + ignore should "generate a CHIRRTL circuit from a Chisel module" in { info("no files were written") catchWrites { ChiselStage.convert(new Foo) } shouldBe a[Right[_, _]] } behavior of "ChiselStage$.emitChirrtl" - it should "generate a CHIRRTL string from a Chisel module" in { + ignore should "generate a CHIRRTL string from a Chisel module" in { val wrapped = catchWrites { ChiselStage.emitChirrtl(new Foo) } info("no files were written") @@ -98,7 +98,7 @@ class ChiselStageSpec extends AnyFlatSpec with Matchers with Utils { behavior of "ChiselStage$.emitFirrtl" - it should "generate a FIRRTL string from a Chisel module" in { + ignore should "generate a FIRRTL string from a Chisel module" in { val wrapped = catchWrites { ChiselStage.emitFirrtl(new Foo) } info("no files were written") @@ -110,7 +110,7 @@ class ChiselStageSpec extends AnyFlatSpec with Matchers with Utils { behavior of "ChiselStage$.emitVerilog" - it should "generate a Verilog string from a Chisel module" in { + ignore should "generate a Verilog string from a Chisel module" in { val wrapped = catchWrites { ChiselStage.emitVerilog(new Foo) } info("no files were written") @@ -122,7 +122,7 @@ class ChiselStageSpec extends AnyFlatSpec with Matchers with Utils { behavior of "ChiselStage$.emitSystemVerilog" - it should "generate a SystemvVerilog string from a Chisel module" in { + ignore should "generate a SystemvVerilog string from a Chisel module" in { val wrapped = catchWrites { ChiselStage.emitSystemVerilog(new Foo) } info("no files were written") wrapped shouldBe a[Right[_, _]] |