| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-03-18 | Split #974 into two PRs - scalastyle updates (#1037) | Jim Lawson |
| 2019-01-25 | WireDefault instead of WireInit, keep WireInit around (#986) | Martin Schoeberl |
| 2019-01-22 | Define Data .toString (#985) | Richard Lin |
| 2018-07-02 | Direct to FIRRTL (#829) | Jack Koenig |
| 2017-08-17 | More of the bindings refactor (#635) | Richard Lin |
| 2017-04-13 | Module Hierarchy Refactor (#469) | Richard Lin |
| 2016-11-21 | Restyle a lot of test code, mainly with regex | ducky |
| 2016-09-07 | Fix bug in Printable FullName of submodule port | jackkoenig |
| 2016-09-07 | Add Printable (#270) | Jack Koenig |
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index : chiselX | |
| Chisel with SFC compatibility |
| summaryrefslogtreecommitdiff |