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AgeCommit message (Expand)Author
2017-04-26Deprecate fromBits and clock/reset constructors (#583)Richard Lin
2017-04-26Dropimportnotstrict492 - More updates to get things through rocket-chip. (#592)Jim Lawson
2017-04-25Remove explicit import of NotStrict - fixes #492 (#494)Jim Lawson
2017-04-13Module Hierarchy Refactor (#469)Richard Lin
2017-04-07Change Enum to emit minimum widths of 1 (#574)Jack Koenig
2017-03-17Add single arg constructor back to compatibility reg (#553)Richard Lin
2017-03-08Deprecate old Reg with nulls constructor (#455)Richard Lin
2017-03-08Move log2Up and log2Down to compatibility wrapperAndrew Waterman
2017-03-08Improve UIntToOH behavior on incorrect inputs; avoid log2UpAndrew Waterman
2017-03-08In OHToUInt, use log2Ceil instead of log2UpAndrew Waterman
2017-03-08Use zero-width wire for 1-entry enumAndrew Waterman
2017-03-08In Counter, use log2Ceil instead of log2UpAndrew Waterman
2017-03-08Fix the widths of QueueIO.count and ArbiterIO.chosen for entries=0Andrew Waterman
2017-03-08Improve Reverse's exception behavior; avoid log2UpAndrew Waterman
2017-03-08Correct Fill's exception behavior; avoid log2UpAndrew Waterman
2017-02-16Add support for clock and reset scoping (#509)Jack Koenig
2017-02-08Add Analog typeJack Koenig
2017-02-07Name all the thingsducky
2017-02-07Rename SeqMem to SyncReadMem. (#490)Jim Lawson
2017-02-01Move backend compilation utilities (#400)Jim Lawson
2017-01-31Fix spelling of ChiselExecutionSuccessJack
2017-01-31Move blackbox verilog implementations within reach of verilator (#453)Chick Markley
2017-01-30Add shift register with reset (#439)Stevo
2017-01-27Deprecate firrtlToVerilog in favor of compileFirrtlToVerilog (#367)Jack Koenig
2017-01-27Make uselessly public fields in utils privatejackkoenig
2017-01-27Provide package-level text to reduce ScalaDoc white space. (#432)Jim Lawson
2017-01-26doesn't lose old firrtl options annotations + transforms (#458)Angie Wang
2017-01-25Better name propagation by macros (#327)Richard Lin
2017-01-20Add Record as new superclass of Bundle (#366)Jack Koenig
2017-01-20Mark Annotation and FixedPoint as experimental (#444)Chick Markley
2017-01-11Merge branch 'master' into fixedPointFromBitsAdam Izraelevitz
2017-01-10Make stop() immediately end simulation for Verilator tests (#434)Jack Koenig
2016-12-15Merge branch 'master' into fixedPointFromBitsgrebe
2016-12-14Final steps for annotations getting from chisel to firrtl (#405)Chick Markley
2016-12-14Change noenq in ReadyValid to use an uninitialized Wire instead of zero (#364)Jack Koenig
2016-12-13CheckpointPaul Rigge
2016-12-07Support for creating chisel annotations that are consumed by firrtl (#393)Chick Markley
2016-12-06utils scaladoc examples for BitPat through CircuitMath (#398)Richard Lin
2016-11-29Add feature warnings to build, fix feature warnings, fix some documentation (...Richard Lin
2016-11-23Simplify Enum API (#385)Richard Lin
2016-11-21Remove deduplication from Chisel (#347)Donggyu
2016-11-21Deboilerplate the implicit conversions, add support for long.Uducky
2016-11-21Fix Log2ducky
2016-11-21Fix regex exampleducky
2016-11-21Stop confusing scaladocducky
2016-11-21better styleducky
2016-11-21Restyle UInt->BitPatComparableducky
2016-11-21Refactor some codeducky
2016-11-21All remaining automatable regex re-stylesducky
2016-11-21Restyle a lot of test code, mainly with regexducky
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