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authorRichard Lin2016-12-06 17:16:40 -0800
committerGitHub2016-12-06 17:16:40 -0800
commit9aba55e7452981058d069b3096544d45e730dba9 (patch)
treeec5314ad92aac0847d2b0b27484707b23f088900 /src/main
parenta1e8ae80888b6b4d7bac057c6486b3442334cdc6 (diff)
utils scaladoc examples for BitPat through CircuitMath (#398)
Add examples for utils, move examples from individual apply methods to class overview scaladoc
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/chisel3/util/BitPat.scala19
-rw-r--r--src/main/scala/chisel3/util/Bitwise.scala46
-rw-r--r--src/main/scala/chisel3/util/Cat.scala13
-rw-r--r--src/main/scala/chisel3/util/CircuitMath.scala17
4 files changed, 77 insertions, 18 deletions
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 9c9909cd..add40f79 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -35,7 +35,7 @@ object BitPat {
}
/** Creates a [[BitPat]] literal from a string.
- *
+ *
* @param n the literal value as a string, in binary, prefixed with 'b'
* @note legal characters are '0', '1', and '?', as well as '_' and white
* space (which are ignored)
@@ -45,7 +45,12 @@ object BitPat {
new BitPat(bits, mask, width)
}
- /** Creates a [[BitPat]] of all don't cares of the specified bitwidth. */
+ /** Creates a [[BitPat]] of all don't cares of the specified bitwidth.
+ *
+ * @example {{{
+ * val myDontCare = BitPat.dontCare(4) // equivalent to BitPat("b????")
+ * }}}
+ */
def dontCare(width: Int): BitPat = BitPat("b" + ("?" * width))
@deprecated("Use BitPat.dontCare", "chisel3")
@@ -73,10 +78,14 @@ object BitPat {
}
}
-// TODO: Break out of Core? (this doesn't involve FIRRTL generation)
/** Bit patterns are literals with masks, used to represent values with don't
- * cares. Equality comparisons will ignore don't care bits (for example,
- * BitPat(0b10?1) === 0b1001.asUInt and 0b1011.asUInt.
+ * care bits. Equality comparisons will ignore don't care bits.
+ *
+ * @example {{{
+ * "b10101".U === BitPat("b101??") // evaluates to true.B
+ * "b10111".U === BitPat("b101??") // evaluates to true.B
+ * "b10001".U === BitPat("b101??") // evaluates to false.B
+ * }}}
*/
sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) {
def getWidth: Int = width
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index 22326972..950fa65f 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -8,11 +8,21 @@ package chisel3.util
import chisel3._
import chisel3.core.SeqUtils
+/** Creates repetitions of each bit of the input in order.
+ *
+ * @example {{{
+ * FillInterleaved(2, "b1 0 0 0".U) // equivalent to "b11 00 00 00".U
+ * FillInterleaved(2, "b1 0 0 1".U) // equivalent to "b11 00 00 11".U
+ * FillInterleaved(2, myUIntWire) // dynamic interleaved fill
+ *
+ * FillInterleaved(2, Seq(true.B, false.B, false.B, false.B)) // equivalent to "b11 00 00 00".U
+ * FillInterleaved(2, Seq(true.B, false.B, false.B, true.B)) // equivalent to "b11 00 00 11".U
+ * }}}
+ */
object FillInterleaved {
/** Creates n repetitions of each bit of x in order.
*
* Output data-equivalent to in(size(in)-1) (n times) ## ... ## in(1) (n times) ## in(0) (n times)
- * For example, FillInterleaved(2, "b1000") === UInt("b11 00 00 00")
*/
def apply(n: Int, in: UInt): UInt = apply(n, in.toBools)
@@ -23,14 +33,31 @@ object FillInterleaved {
def apply(n: Int, in: Seq[Bool]): UInt = Cat(in.map(Fill(n, _)).reverse)
}
-/** Returns the number of bits set (i.e value is 1) in the input signal.
+/** Returns the number of bits set (value is 1 or true) in the input signal.
+ *
+ * @example {{{
+ * PopCount(Seq(true.B, false.B, true.B, true.B)) // evaluates to 3.U
+ * PopCount(Seq(false.B, false.B, true.B, false.B)) // evaluates to 1.U
+ *
+ * PopCount("b1011".U) // evaluates to 3.U
+ * PopCount("b0010".U) // evaluates to 1.U
+ * PopCount(myUIntWire) // dynamic count
+ * }}}
*/
-object PopCount
-{
+object PopCount {
def apply(in: Iterable[Bool]): UInt = SeqUtils.count(in.toSeq)
+
def apply(in: Bits): UInt = apply((0 until in.getWidth).map(in(_)))
}
+/** Create repetitions of the input using a tree fanout topology.
+ *
+ * @example {{{
+ * Fill(2, "b1000".U) // equivalent to "b1000 1000".U
+ * Fill(2, "b1001".U) // equivalent to "b1001 1001".U
+ * Fill(2, myUIntWire) // dynamic fill
+ * }}}
+ */
object Fill {
/** Create n repetitions of x using a tree fanout topology.
*
@@ -53,6 +80,14 @@ object Fill {
}
}
+/** Returns the input in bit-reversed order. Useful for little/big-endian conversion.
+ *
+ * @example {{{
+ * Reverse("b1101".U) // equivalent to "b1011".U
+ * Reverse("b1101".U(8.W)) // equivalent to "b10110000".U
+ * Reverse(myUIntWire) // dynamic reverse
+ * }}}
+ */
object Reverse {
private def doit(in: UInt, length: Int): UInt = {
if (length == 1) {
@@ -73,7 +108,6 @@ object Reverse {
Cat(doit(in(half-1,0), half), doit(in(length-1,half), length-half))
}
}
- /** Returns the input in bit-reversed order. Useful for little/big-endian conversion.
- */
+
def apply(in: UInt): UInt = doit(in, in.getWidth)
}
diff --git a/src/main/scala/chisel3/util/Cat.scala b/src/main/scala/chisel3/util/Cat.scala
index ba12a7d4..78801541 100644
--- a/src/main/scala/chisel3/util/Cat.scala
+++ b/src/main/scala/chisel3/util/Cat.scala
@@ -5,8 +5,19 @@ package chisel3.util
import chisel3._
import chisel3.core.SeqUtils
+/** Concatenates elements of the input, in order, together.
+ *
+ * @example {{{
+ * Cat("b101".U, "b11".U) // equivalent to "b101 11".U
+ * Cat(myUIntWire0, myUIntWire1)
+ *
+ * Cat(Seq("b101".U, "b11".U)) // equivalent to "b101 11".U
+ * Cat(mySeqOfBits)
+ * }}}
+ */
object Cat {
- /** Concatenates the argument data elements, in argument order, together.
+ /** Concatenates the argument data elements, in argument order, together. The first argument
+ * forms the most significant bits, while the last argument forms the least significant bits.
*/
def apply[T <: Bits](a: T, r: T*): UInt = apply(a :: r.toList)
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index a422b5fe..b5f491ef 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -7,10 +7,19 @@ package chisel3.util
import chisel3._
+/** Returns the base-2 integer logarithm of an UInt.
+ *
+ * @note The result is truncated, so e.g. Log2(13.U) === 3.U
+ *
+ * @example {{{
+ * Log2(8.U) // evaluates to 3.U
+ * Log2(13.U) // evaluates to 3.U (truncation)
+ * Log2(myUIntWire)
+ * }}}
+ *
+ */
object Log2 {
/** Returns the base-2 integer logarithm of the least-significant `width` bits of an UInt.
- *
- * @note The result is truncated, so e.g. Log2(13.U) === 3.U
*/
def apply(x: Bits, width: Int): UInt = {
if (width < 2) {
@@ -28,10 +37,6 @@ object Log2 {
}
}
- /** Returns the base-2 integer logarithm of an UInt.
- *
- * @note The result is truncated, so e.g. Log2(13.U) === 3.U
- */
def apply(x: Bits): UInt = apply(x, x.getWidth)
private def divideAndConquerThreshold = 4