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2021-05-10implement equal to BitPat. (#1867)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-09Fix ShiftRegister with 0 delay. (#1903)Jiuyang Liu
* Add test to check ShiftRegister(s) with delay is 0. This should break ShiftRegister(x, 0) since last is not exist in a empty Seq. Originally, test only test 1 to 4, which missed a potential bug from #1723. * Fix ShiftRegister with 0 delay. if ShiftRegisters is empty, java will complain: ``` java.util.NoSuchElementException scala.collection.LinearSeqOptimized.last(LinearSeqOptimized.scala:150) ``` This fix this issue and return `in` directly when ShiftRegister size is 0. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-06add ShiftRegisters to expose register inside ShiftRegister. (#1723)Jiuyang Liu
* add ShiftRegisters to expose register inside ShiftRegister. * use Seq.iter for oneline implementation.
2021-05-05Remove chisel3.stage.phases.DriverCompatibility (#1772)Schuyler Eldridge
2021-04-30add helper function to convert chirrtl to firrtl. (#1854)Jiuyang Liu
* add convert(chirrtl: cir.Circuit): fir.Circuit to convert chirrtl to firrtl. * add scaladoc. * add test. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-29Scala 2.13 support (#1751)Jack Koenig
2021-04-21fixing context bug (#1874)Deborah Soung
2021-03-18Add toString method to BitPat (#1819)Boyang Han
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-18Don't toggle top.cpp clock and reset on same cycle (#1820)Schuyler Eldridge
Change top.cpp to deassert reset one time unit before the clock asserts. This avoids a Verilator simultation issue in top.cpp where the eval() function is only called once per simultation loop. If the clock and reset are both changed and eval() is only called once, then any combinational update due to a change in reset is not visible to the sequential logic. This avoids issues where the downstream compilation utilities move synchronous reset logic outside of an always block that describes a synchronous reset flip flop. Reset now deasserts on time unit 10 and the clock ticks on time unit 11. h/t @albert-magyar Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-03-11Import memory files inline for Verilog generation (#1805)Carlos Eduardo
This annotation adds memory import with inline generation for the emmiter. Supports both readmemh and readmemb statements based on argument.
2021-03-01Fix conversions between DecoupledIO and IrrevocableIO (#1781)Jerry Zhao
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-02-26Expose AnnotationSeq to Module. (#1731)Jiuyang Liu
2021-02-11Fix stack trace trimming across Driver/ChiselStage (#1771)Schuyler Eldridge
* Handle MemTypeBinding in Analog Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Fix stack trace trimming across ChiselStage Fix bug in stack trace trimming behavior. Now, the following is what happens: 1. The Builder, if catching accumulated errors, will now throw a ChiselException with a Scala-trimmed Stack trace. Previously, this would throw the full excpetion. 2. The Elaborate phase handles stack trace trimming. By default, any Throwable thrown during elaboration will have its stack trace *mutably* trimmed and is rethrown. A logger.error is printed stating that there was an error during elaboration and how the user can turn on the full stack trace. If the --full-stacktrace option is on, then the Throwable is not caught and only the first logger.error (saying that elaboration failed) will be printed. 3. ChiselStage (the class), ChiselStage$ (the object), and ChiselMain all inherit the behavior of (2). Mutable stack trace trimming behavior is moved into an implicit class (previously this was defined on ChiselException only) so this can be applied to any Throwable. No StageErrors are now thrown anymore. However, StageErrors may still be caught by ChiselMain (since it is a StageMain). Testing is added for ChiselMain, ChiselStage, and ChiselStage$ to test all this behavior. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-02-08Parametrized Mem- & SyncReadMem-based implementation of the Queue class (#1740)Vladimir Milovanović
* Added SyncReadMem-based implementation of the Queue class * Rework of the parametrized Queue class SyncReadMem-based implementation * Modification of the parametrized Queue class SyncReadMem-based implementation * Limiting the visibility of the read address for SyncReadMem-based Queue Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-02-03Remove Deprecated APIs (#1730)Jiuyang Liu
2021-01-27Fix some typo and using foreach instead of map in BoringUtils (#1755)SoyaOhnishi
If a method passed to higher function does not return any value, it is prefer to use `foreach` instead of `map`. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-01-21Fold Chisel.CompatibilityModule into chisel3.internal.LegacyModuleJack Koenig
2021-01-21Remove val ioJack Koenig
Chisel projects no longer need -Xsource:2.11 when compiling with Scala 2.12. Autowrapping of "val io" for compatibility mode Modules is now implemented using reflection instead of calling the virtual method. Also move Chisel.BlackBox to new chisel3.internal.LegacyBlackBox
2021-01-21Rename MultiIOModule to ModuleJack Koenig
2020-11-16Improve source locators for switch statements. (#1669)Daniel Kasza
* Improve source locators for switch statements.
2020-11-02Bugfix - adding external modules was broken (#1649)Adam Izraelevitz
2020-10-26Bugfix - module name collision for injecting aspect (#1635)Adam Izraelevitz
* Bugfix - module name collision for injecting aspect * Fixed mechanism to avoid module name collisions * Added comments for reviewer feedback Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-10-26Added Force Name API (#1634)Adam Izraelevitz
* Added forcename transform and tests * Added documentation and additional error checking * Added mdoc. Added RunFirrtlTransform trait * Removed TODO comment * Addressed reviewer feedback * Removed trailing comma Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-10-21Make `-e` option work with ChiselStage methods (#1630)Schuyler Eldridge
* Fix `-e` option causing ChiselStage.emit* to error Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Add test of `-e` ChiselStage behavior Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * fixup! Add test of `-e` ChiselStage behavior
2020-10-19Enable Cat of Zero Element Vec (#1623)Schuyler Eldridge
* Return 0.U for asUInt of a zero-element Seq Add a condition to SeqUtils.asUInt to have it return an unspecified width 0.U when applied to an empty sequence. This enables the ability to do a Cat of a zero-element sequence. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Test elaboration of Cat on zero-element Seq Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2020-10-13ExtModule's lacked support built in support for providing (#1154)Chick Markley
* ExtModule's lacked support built in support for providing the verilog source. This changes creates traits that can be used with ExtModule to provide the support currently found in BlackBox - Add support for ExtModule helpers - HasExtModuleResource to use addResource - HasExtModuleInline to use setInline - HasExtModulePath to use addPath - Add tests of the above support. - Note: These tests use Stage instead of Driver - Added ScalaDoc for HasBlackBoxInline#setInline * Fix the danged trailing commas. * Change to use `.transform` as the correct API for `ChiselStage`
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
Change source and other relevant files to use SPDX license LICENSE file moved from src/ to ./ Changed license file to refer to this per recommendation using_spdx_license_list_short_identifiers WARNING: Tests fail with as of yet undiagnosed error ``` [error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15 [error] Failed tests: [error] chiselTests.QueueSpec [error] examples.VendingMachineGeneratorSpec [error] chiselTests.HarnessSpec [error] chiselTests.ConnectSpec [error] chiselTests.aop.SelectSpec [error] chiselTests.PopCountSpec [error] chiselTests.CloneModuleSpec [error] (Test / test) sbt.TestsFailedException: Tests unsuccessful [error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM sbt:chisel3> ```
2020-09-22Support using switch without importing SwitchContext (#1595)Jack Koenig
2020-09-15make parameters for util modules public (#1452)Albert Chen
Co-authored-by: Megan Wachs <megan@sifive.com>
2020-09-09Add new annotation for Chisel Circuit serialization (#1580)Jack Koenig
ChiselCircuitAnnotation no longer extends CustomFileEmission, rather it is Unserializable. Also the --chisel-output-file is added to the ChiselCli. New phase AddSerializationAnnotations constructs a CircuitSerializationAnnotation from ChiselCircuitAnnotation and ChiselOutputFileAnnotation. Both .fir and .pb file formats are supported. Default format is .fir unless a --chisel-output-file is specified with a .pb extension.
2020-09-09Fix load memory from file to work with binary (#1583)HappyQuark
* fix loadMemoryFromFile to work with binary Passed in hexOrBinary parameter to ChiselLoadMemoryAnnotation * Added test for binary format support in loadMemoryFromFile * Added test for binary format support in loadMemoryFromFile
2020-08-27Restore and deprecate Chisel.Driver (#1571)Jack Koenig
It shouldn't be removed until we also remove the underlying chisel3.Driver.
2020-08-26Add ChiselPhase, Stop writing files in ChiselStage$ methods, Expand ↵Schuyler Eldridge
ChiselStage$ helpers (#1566) * Add ChiselPhase * Use ChiselPhase in ChiselStage, remove targets Switch from a one-off PhaseManager inside ChiselStage to actually using the newly added ChiselPhase. This removes the targets method (and API) from ChiselStage. * Stop writing to files in ChiselStage$ methods Change the ChiselStage companion object methods, elaborate and convert, to not write files. Under the hood, these are switched from using ChiselStage (which, like all phases, will write files) to using ChiselPhase. * Test that ChiselStage$ methods write no files Modify existing ChiselStage object method tests to check that no files are written. * Expand ChiselStage$ API with more helpers This adds additional methods to the ChiselStage object for going directly from a Chisel module to a string including: CHIRRTL, high FIRRTL IR, Verilog, and SystemVerilog. Differing from their ChiselStage class counterparts, these take no arguments other than the module and write no files. * Add tests of new ChiselStage$ helper methods * Use ChiselStage object in tests Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-08-20Remove use of PreservesAll, cleanup dependencies (#1558)Schuyler Eldridge
Remove usages of the deprecated trait PreservesAll and use an explicit false invalidates. Additionally, all phases are converted to be more canonical in there specification of dependencies by: 1. Overriding all default dependency implementations 2. Using def instead of val Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-08-13Move treadle dependency to the tests (#1554)Jack Koenig
Use inheritance to make TesterDriver Backend API extensible, then define a TreadleBackend in the test project
2020-08-13Allow counters to be reset manually (#1527)Josh Bassett
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-08-12Switch to HowToSerialize for Emission (#1405)Schuyler Eldridge
* Fix emit{Firrtl,Verilog} for CustomFileEmission Change ChiselStage helper methods for emitting FIRRTL (emitFirrtl) and Verilog (emitVerilog) to look for Circuit and Verilog annotations instead of DeletedAnnotations. This is needed after migrating to the CustomFileEmission mixin in FIRRTL where FIRRTL will no longer delete emitter annotations. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Use CustomFileEmission for ChiselCircuitAnnotation Removes the explicit chisel3.phases.Emitter and instead does emission with a CustomFileEmission mixin to ChiselCircuitAnnotation. This then prevents the need for passing around DeletedAnnotations. As a consequence, I removed an unnecessary run of a second Converter in the Driver. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Fix tests for use of CustomFileEmission trait Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Fixes for newer CustomFileEmission API Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-08-11Restore Counter.n API (#1546)Jack Koenig
Includes special case support for Counter(0) which has identical behavior to Counter(1) except for the value of n.
2020-08-06Update OneHot.scala (#1539)Leigang Kou
comment fix only.
2020-07-31Add emitSystemVerilog method to ChiselStage (#1534)Tom Alcorn
2020-07-30Allow a counter to be instantiated using a Scala range (#1515)Josh Bassett
* Add positive range generator * Allow the Counter module to be instantiated with a Scala range * Use head/last to determine counter width Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> * Let counter overflow naturally when appropriate We only need to explicitly wrap counters that don't start at zero, or end on a power of two. Otherwise we just let the counter overflow naturally to avoid wasting an extra mux. * Require counter range to be non-empty Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-29Improved Chisel Naming via Compiler Plugins + Prefixing (#1448)Adam Izraelevitz
Added prefixing and a compiler plugin to improve naming. Only works for Scala 2.12 and above. Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-07-28Select: update to work with records (#1525)Albert Chen
2020-07-25Using TreadleTesterPhase now requires new (#1520)Chick Markley
Treadle tester phase requires new to fix problems found when running tests in parallel.
2020-07-22Basic model checking API (#1499)Tom Alcorn
* Add `check(...)` affordance * Add assert (renamed from check and fixed) * Add verification statements * Move formal to experimental.verification * Make test use ChiselStage `generateFirrtl` has been cut from Chisel * Fix newly introduced style warnings * Fix some old style warnings for good measure * Revert "Fix some old style warnings for good measure" This reverts commit 31d51726c2faa4c277230104bd469ff7ffefc890. * Cut scalastyle comments * Cut formal delimiter comments
2020-07-21Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-06-29- A few final fixes after the rebasechick
2020-06-29This adds a mechanism for the unittests to be run with the TreadleBackendchick
This mechanism is not enabled and should not change the behavior of existing tests A following PR will deliver a switch that will allow changing the backend. The reasons for this PR - Treadle tests run much faster, enabling quicker debugging and CI cycles - This will help ensure fidelity of Treadle to the Verilator backend A few tests are marked as verilator only due to black box limitations Change treadle to a direct dependency I tried to make it a test only dependency but the TesterDriver sits in src/main requiring that regular compile have access to treadle Oops, made treadle the default A number of changes in response to @ducky64 review - made backend check clearer and add error handling for multiple backends specified - Fixed duplicate TargetDirAnnotation uses in Treadle backend - Cleaned up BlackBox test formatting - Undid unnecessary debugging changes from Counter - Undid .gitignore change, that should be on another PR A number of changes in response to @ducky64 review - Undid debugging changes made to BitWiseOps
2020-06-24Add missing finishWrapper call in TesterDriver (#1496)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-06-22Code simplification in internal Chisel._ methodSchuyler Eldridge
Co-authored-by: Chick Markley <chick@qrhino.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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