diff options
| author | Schuyler Eldridge | 2020-10-21 19:57:38 -0400 |
|---|---|---|
| committer | GitHub | 2020-10-21 23:57:38 +0000 |
| commit | 26deb7703389b78a9b2a61f7e191f3f0e2a6623b (patch) | |
| tree | 366896d06e5f9e38e18ec2774b98219be8d82a42 /src/main | |
| parent | fef0b68a465875ab74b2b1339b29254c762d3c53 (diff) | |
Make `-e` option work with ChiselStage methods (#1630)
* Fix `-e` option causing ChiselStage.emit* to error
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Add test of `-e` ChiselStage behavior
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* fixup! Add test of `-e` ChiselStage behavior
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/chisel3/stage/ChiselStage.scala | 24 |
1 files changed, 14 insertions, 10 deletions
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala index 1ab8b766..aae7ad8d 100644 --- a/src/main/scala/chisel3/stage/ChiselStage.scala +++ b/src/main/scala/chisel3/stage/ChiselStage.scala @@ -6,7 +6,9 @@ import firrtl.{ ir => fir, AnnotationSeq, EmittedFirrtlCircuitAnnotation, + EmittedFirrtlModuleAnnotation, EmittedVerilogCircuitAnnotation, + EmittedVerilogModuleAnnotation, HighFirrtlEmitter, VerilogEmitter, SystemVerilogEmitter @@ -93,11 +95,11 @@ class ChiselStage extends Stage { annotations: AnnotationSeq = Seq.empty): String = { execute(Array("-X", "high") ++ args, ChiselGeneratorAnnotation(() => gen) +: annotations) - .collectFirst { + .collect { case EmittedFirrtlCircuitAnnotation(a) => a - } - .get - .value + case EmittedFirrtlModuleAnnotation(a) => a + }.map(_.value) + .mkString("") } @@ -115,9 +117,10 @@ class ChiselStage extends Stage { execute(Array("-X", "verilog") ++ args, ChiselGeneratorAnnotation(() => gen) +: annotations) .collectFirst { case EmittedVerilogCircuitAnnotation(a) => a - } - .get - .value + case EmittedVerilogModuleAnnotation(a) => a + }.map(_.value) + .mkString("") + } /** Convert a Chisel module to SystemVerilog @@ -134,9 +137,10 @@ class ChiselStage extends Stage { execute(Array("-X", "sverilog") ++ args, ChiselGeneratorAnnotation(() => gen) +: annotations) .collectFirst { case EmittedVerilogCircuitAnnotation(a) => a - } - .get - .value + case EmittedVerilogModuleAnnotation(a) => a + }.map(_.value) + .mkString("") + } } |